1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2022 Intel Corporation. 3 4 #include <linux/acpi.h> 5 #include <linux/clk.h> 6 #include <linux/delay.h> 7 #include <linux/i2c.h> 8 #include <linux/module.h> 9 #include <linux/pm_runtime.h> 10 #include <linux/regulator/consumer.h> 11 #include <linux/reset.h> 12 #include <media/v4l2-ctrls.h> 13 #include <media/v4l2-device.h> 14 #include <media/v4l2-fwnode.h> 15 16 #define OV08D10_SCLK 144000000ULL 17 #define OV08D10_ROWCLK 36000 18 #define OV08D10_DATA_LANES 2 19 #define OV08D10_RGB_DEPTH 10 20 21 #define OV08D10_REG_PAGE 0xfd 22 #define OV08D10_REG_GLOBAL_EFFECTIVE 0x01 23 #define OV08D10_REG_CHIP_ID_0 0x00 24 #define OV08D10_REG_CHIP_ID_1 0x01 25 #define OV08D10_ID_MASK GENMASK(15, 0) 26 #define OV08D10_CHIP_ID 0x5608 27 28 #define OV08D10_REG_MODE_SELECT 0xa0 29 #define OV08D10_MODE_STANDBY 0x00 30 #define OV08D10_MODE_STREAMING 0x01 31 32 /* vertical-timings from sensor */ 33 #define OV08D10_REG_VTS_H 0x05 34 #define OV08D10_REG_VTS_L 0x06 35 #define OV08D10_VTS_MAX 0x7fff 36 37 /* Exposure controls from sensor */ 38 #define OV08D10_REG_EXPOSURE_H 0x02 39 #define OV08D10_REG_EXPOSURE_M 0x03 40 #define OV08D10_REG_EXPOSURE_L 0x04 41 #define OV08D10_EXPOSURE_MIN 6 42 #define OV08D10_EXPOSURE_MAX_MARGIN 6 43 #define OV08D10_EXPOSURE_STEP 1 44 45 /* Analog gain controls from sensor */ 46 #define OV08D10_REG_ANALOG_GAIN 0x24 47 #define OV08D10_ANAL_GAIN_MIN 128 48 #define OV08D10_ANAL_GAIN_MAX 2047 49 #define OV08D10_ANAL_GAIN_STEP 1 50 51 /* Digital gain controls from sensor */ 52 #define OV08D10_REG_MWB_DGAIN_C 0x21 53 #define OV08D10_REG_MWB_DGAIN_F 0x22 54 #define OV08D10_DGTL_GAIN_MIN 0 55 #define OV08D10_DGTL_GAIN_MAX 4095 56 #define OV08D10_DGTL_GAIN_STEP 1 57 #define OV08D10_DGTL_GAIN_DEFAULT 1024 58 59 /* Test Pattern Control */ 60 #define OV08D10_REG_TEST_PATTERN 0x12 61 #define OV08D10_TEST_PATTERN_ENABLE 0x01 62 #define OV08D10_TEST_PATTERN_DISABLE 0x00 63 64 /* Flip Mirror Controls from sensor */ 65 #define OV08D10_REG_FLIP_OPT 0x32 66 #define OV08D10_REG_FLIP_MASK 0x3 67 68 #define to_ov08d10(_sd) container_of(_sd, struct ov08d10, sd) 69 70 struct ov08d10_reg { 71 u8 address; 72 u8 val; 73 }; 74 75 struct ov08d10_reg_list { 76 u32 num_of_regs; 77 const struct ov08d10_reg *regs; 78 }; 79 80 static const u32 ov08d10_xvclk_freqs[] = { 81 19200000, 82 24000000 83 }; 84 85 struct ov08d10_link_freq_config { 86 const struct ov08d10_reg_list reg_list[ARRAY_SIZE(ov08d10_xvclk_freqs)]; 87 }; 88 89 struct ov08d10_mode { 90 /* Frame width in pixels */ 91 u32 width; 92 93 /* Frame height in pixels */ 94 u32 height; 95 96 /* Horizontal timing size */ 97 u32 hts; 98 99 /* Default vertical timing size */ 100 u32 vts_def; 101 102 /* Min vertical timing size */ 103 u32 vts_min; 104 105 /* Link frequency needed for this resolution */ 106 u32 link_freq_index; 107 108 /* Sensor register settings for this resolution */ 109 const struct ov08d10_reg_list reg_list; 110 111 /* Number of data lanes */ 112 u8 data_lanes; 113 }; 114 115 /* 3280x2460, 3264x2448 need 720Mbps/lane, 2 lanes - 19.2 MHz */ 116 static const struct ov08d10_reg mipi_data_rate_720mbps_19_2[] = { 117 {0xfd, 0x00}, 118 {0x11, 0x2a}, 119 {0x14, 0x43}, 120 {0x1a, 0x04}, 121 {0x1b, 0xe1}, 122 {0x1e, 0x13}, 123 {0xb7, 0x02} 124 }; 125 126 /* 1632x1224 needs 360Mbps/lane, 2 lanes - 19.2 MHz */ 127 static const struct ov08d10_reg mipi_data_rate_360mbps_19_2[] = { 128 {0xfd, 0x00}, 129 {0x1a, 0x04}, 130 {0x1b, 0xe1}, 131 {0x1d, 0x00}, 132 {0x1c, 0x19}, 133 {0x11, 0x2a}, 134 {0x14, 0x54}, 135 {0x1e, 0x13}, 136 {0xb7, 0x02} 137 }; 138 139 /* 3280x2460, 3264x2448 need 720Mbps/lane, 2 lanes - 24 MHz */ 140 static const struct ov08d10_reg mipi_data_rate_720mbps_24_0[] = { 141 {0xfd, 0x00}, 142 {0x11, 0x2a}, 143 {0x14, 0x43}, 144 {0x1a, 0x04}, 145 {0x1b, 0xb4}, 146 {0x1e, 0x13}, 147 {0xb7, 0x02} 148 }; 149 150 /* 1632x1224 needs 360Mbps/lane, 2 lanes - 24 MHz */ 151 static const struct ov08d10_reg mipi_data_rate_360mbps_24_0[] = { 152 {0xfd, 0x00}, 153 {0x1a, 0x04}, 154 {0x1b, 0xb4}, 155 {0x1d, 0x00}, 156 {0x1c, 0x19}, 157 {0x11, 0x2a}, 158 {0x14, 0x54}, 159 {0x1e, 0x13}, 160 {0xb7, 0x02} 161 }; 162 163 static const struct ov08d10_reg lane_2_mode_3280x2460[] = { 164 /* 3280x2460 resolution */ 165 {0xfd, 0x01}, 166 {0x12, 0x00}, 167 {0x03, 0x12}, 168 {0x04, 0x58}, 169 {0x07, 0x05}, 170 {0x21, 0x02}, 171 {0x24, 0x30}, 172 {0x33, 0x03}, 173 {0x01, 0x03}, 174 {0x19, 0x10}, 175 {0x42, 0x55}, 176 {0x43, 0x00}, 177 {0x47, 0x07}, 178 {0x48, 0x08}, 179 {0xb2, 0x7f}, 180 {0xb3, 0x7b}, 181 {0xbd, 0x08}, 182 {0xd2, 0x57}, 183 {0xd3, 0x10}, 184 {0xd4, 0x08}, 185 {0xd5, 0x08}, 186 {0xd6, 0x06}, 187 {0xb1, 0x00}, 188 {0xb4, 0x00}, 189 {0xb7, 0x0a}, 190 {0xbc, 0x44}, 191 {0xbf, 0x48}, 192 {0xc1, 0x10}, 193 {0xc3, 0x24}, 194 {0xc8, 0x03}, 195 {0xc9, 0xf8}, 196 {0xe1, 0x33}, 197 {0xe2, 0xbb}, 198 {0x51, 0x0c}, 199 {0x52, 0x0a}, 200 {0x57, 0x8c}, 201 {0x59, 0x09}, 202 {0x5a, 0x08}, 203 {0x5e, 0x10}, 204 {0x60, 0x02}, 205 {0x6d, 0x5c}, 206 {0x76, 0x16}, 207 {0x7c, 0x11}, 208 {0x90, 0x28}, 209 {0x91, 0x16}, 210 {0x92, 0x1c}, 211 {0x93, 0x24}, 212 {0x95, 0x48}, 213 {0x9c, 0x06}, 214 {0xca, 0x0c}, 215 {0xce, 0x0d}, 216 {0xfd, 0x01}, 217 {0xc0, 0x00}, 218 {0xdd, 0x18}, 219 {0xde, 0x19}, 220 {0xdf, 0x32}, 221 {0xe0, 0x70}, 222 {0xfd, 0x01}, 223 {0xc2, 0x05}, 224 {0xd7, 0x88}, 225 {0xd8, 0x77}, 226 {0xd9, 0x00}, 227 {0xfd, 0x07}, 228 {0x00, 0xf8}, 229 {0x01, 0x2b}, 230 {0x05, 0x40}, 231 {0x08, 0x06}, 232 {0x09, 0x11}, 233 {0x28, 0x6f}, 234 {0x2a, 0x20}, 235 {0x2b, 0x05}, 236 {0x5e, 0x10}, 237 {0x52, 0x00}, 238 {0x53, 0x7c}, 239 {0x54, 0x00}, 240 {0x55, 0x7c}, 241 {0x56, 0x00}, 242 {0x57, 0x7c}, 243 {0x58, 0x00}, 244 {0x59, 0x7c}, 245 {0xfd, 0x02}, 246 {0x9a, 0x30}, 247 {0xa8, 0x02}, 248 {0xfd, 0x02}, 249 {0xa1, 0x00}, 250 {0xa2, 0x09}, 251 {0xa3, 0x9c}, 252 {0xa5, 0x00}, 253 {0xa6, 0x0c}, 254 {0xa7, 0xd0}, 255 {0xfd, 0x00}, 256 {0x24, 0x01}, 257 {0xc0, 0x16}, 258 {0xc1, 0x08}, 259 {0xc2, 0x30}, 260 {0x8e, 0x0c}, 261 {0x8f, 0xd0}, 262 {0x90, 0x09}, 263 {0x91, 0x9c}, 264 {0xfd, 0x05}, 265 {0x04, 0x40}, 266 {0x07, 0x00}, 267 {0x0d, 0x01}, 268 {0x0f, 0x01}, 269 {0x10, 0x00}, 270 {0x11, 0x00}, 271 {0x12, 0x0c}, 272 {0x13, 0xcf}, 273 {0x14, 0x00}, 274 {0x15, 0x00}, 275 {0xfd, 0x00}, 276 {0x20, 0x0f}, 277 {0xe7, 0x03}, 278 {0xe7, 0x00} 279 }; 280 281 static const struct ov08d10_reg lane_2_mode_3264x2448[] = { 282 /* 3264x2448 resolution */ 283 {0xfd, 0x01}, 284 {0x12, 0x00}, 285 {0x03, 0x12}, 286 {0x04, 0x58}, 287 {0x07, 0x05}, 288 {0x21, 0x02}, 289 {0x24, 0x30}, 290 {0x33, 0x03}, 291 {0x01, 0x03}, 292 {0x19, 0x10}, 293 {0x42, 0x55}, 294 {0x43, 0x00}, 295 {0x47, 0x07}, 296 {0x48, 0x08}, 297 {0xb2, 0x7f}, 298 {0xb3, 0x7b}, 299 {0xbd, 0x08}, 300 {0xd2, 0x57}, 301 {0xd3, 0x10}, 302 {0xd4, 0x08}, 303 {0xd5, 0x08}, 304 {0xd6, 0x06}, 305 {0xb1, 0x00}, 306 {0xb4, 0x00}, 307 {0xb7, 0x0a}, 308 {0xbc, 0x44}, 309 {0xbf, 0x48}, 310 {0xc1, 0x10}, 311 {0xc3, 0x24}, 312 {0xc8, 0x03}, 313 {0xc9, 0xf8}, 314 {0xe1, 0x33}, 315 {0xe2, 0xbb}, 316 {0x51, 0x0c}, 317 {0x52, 0x0a}, 318 {0x57, 0x8c}, 319 {0x59, 0x09}, 320 {0x5a, 0x08}, 321 {0x5e, 0x10}, 322 {0x60, 0x02}, 323 {0x6d, 0x5c}, 324 {0x76, 0x16}, 325 {0x7c, 0x11}, 326 {0x90, 0x28}, 327 {0x91, 0x16}, 328 {0x92, 0x1c}, 329 {0x93, 0x24}, 330 {0x95, 0x48}, 331 {0x9c, 0x06}, 332 {0xca, 0x0c}, 333 {0xce, 0x0d}, 334 {0xfd, 0x01}, 335 {0xc0, 0x00}, 336 {0xdd, 0x18}, 337 {0xde, 0x19}, 338 {0xdf, 0x32}, 339 {0xe0, 0x70}, 340 {0xfd, 0x01}, 341 {0xc2, 0x05}, 342 {0xd7, 0x88}, 343 {0xd8, 0x77}, 344 {0xd9, 0x00}, 345 {0xfd, 0x07}, 346 {0x00, 0xf8}, 347 {0x01, 0x2b}, 348 {0x05, 0x40}, 349 {0x08, 0x06}, 350 {0x09, 0x11}, 351 {0x28, 0x6f}, 352 {0x2a, 0x20}, 353 {0x2b, 0x05}, 354 {0x5e, 0x10}, 355 {0x52, 0x00}, 356 {0x53, 0x7c}, 357 {0x54, 0x00}, 358 {0x55, 0x7c}, 359 {0x56, 0x00}, 360 {0x57, 0x7c}, 361 {0x58, 0x00}, 362 {0x59, 0x7c}, 363 {0xfd, 0x02}, 364 {0x9a, 0x30}, 365 {0xa8, 0x02}, 366 {0xfd, 0x02}, 367 {0xa1, 0x08}, 368 {0xa2, 0x09}, 369 {0xa3, 0x90}, 370 {0xa5, 0x08}, 371 {0xa6, 0x0c}, 372 {0xa7, 0xc0}, 373 {0xfd, 0x00}, 374 {0x24, 0x01}, 375 {0xc0, 0x16}, 376 {0xc1, 0x08}, 377 {0xc2, 0x30}, 378 {0x8e, 0x0c}, 379 {0x8f, 0xc0}, 380 {0x90, 0x09}, 381 {0x91, 0x90}, 382 {0xfd, 0x05}, 383 {0x04, 0x40}, 384 {0x07, 0x00}, 385 {0x0d, 0x01}, 386 {0x0f, 0x01}, 387 {0x10, 0x00}, 388 {0x11, 0x00}, 389 {0x12, 0x0c}, 390 {0x13, 0xcf}, 391 {0x14, 0x00}, 392 {0x15, 0x00}, 393 {0xfd, 0x00}, 394 {0x20, 0x0f}, 395 {0xe7, 0x03}, 396 {0xe7, 0x00} 397 }; 398 399 static const struct ov08d10_reg lane_2_mode_1632x1224[] = { 400 /* 1640x1232 resolution */ 401 {0xfd, 0x01}, 402 {0x1a, 0x0a}, 403 {0x1b, 0x08}, 404 {0x2a, 0x01}, 405 {0x2b, 0x9a}, 406 {0xfd, 0x01}, 407 {0x12, 0x00}, 408 {0x03, 0x05}, 409 {0x04, 0xe2}, 410 {0x07, 0x05}, 411 {0x21, 0x02}, 412 {0x24, 0x30}, 413 {0x31, 0x06}, 414 {0x33, 0x03}, 415 {0x01, 0x03}, 416 {0x19, 0x10}, 417 {0x42, 0x55}, 418 {0x43, 0x00}, 419 {0x47, 0x07}, 420 {0x48, 0x08}, 421 {0xb2, 0x7f}, 422 {0xb3, 0x7b}, 423 {0xbd, 0x08}, 424 {0xd2, 0x57}, 425 {0xd3, 0x10}, 426 {0xd4, 0x08}, 427 {0xd5, 0x08}, 428 {0xd6, 0x06}, 429 {0xb1, 0x00}, 430 {0xb4, 0x00}, 431 {0xb7, 0x0a}, 432 {0xbc, 0x44}, 433 {0xbf, 0x48}, 434 {0xc1, 0x10}, 435 {0xc3, 0x24}, 436 {0xc8, 0x03}, 437 {0xc9, 0xf8}, 438 {0xe1, 0x33}, 439 {0xe2, 0xbb}, 440 {0x51, 0x0c}, 441 {0x52, 0x0a}, 442 {0x57, 0x8c}, 443 {0x59, 0x09}, 444 {0x5a, 0x08}, 445 {0x5e, 0x10}, 446 {0x60, 0x02}, 447 {0x6d, 0x5c}, 448 {0x76, 0x16}, 449 {0x7c, 0x1a}, 450 {0x90, 0x28}, 451 {0x91, 0x16}, 452 {0x92, 0x1c}, 453 {0x93, 0x24}, 454 {0x95, 0x48}, 455 {0x9c, 0x06}, 456 {0xca, 0x0c}, 457 {0xce, 0x0d}, 458 {0xfd, 0x01}, 459 {0xc0, 0x00}, 460 {0xdd, 0x18}, 461 {0xde, 0x19}, 462 {0xdf, 0x32}, 463 {0xe0, 0x70}, 464 {0xfd, 0x01}, 465 {0xc2, 0x05}, 466 {0xd7, 0x88}, 467 {0xd8, 0x77}, 468 {0xd9, 0x00}, 469 {0xfd, 0x07}, 470 {0x00, 0xf8}, 471 {0x01, 0x2b}, 472 {0x05, 0x40}, 473 {0x08, 0x03}, 474 {0x09, 0x08}, 475 {0x28, 0x6f}, 476 {0x2a, 0x20}, 477 {0x2b, 0x05}, 478 {0x2c, 0x01}, 479 {0x50, 0x02}, 480 {0x51, 0x03}, 481 {0x5e, 0x00}, 482 {0x52, 0x00}, 483 {0x53, 0x7c}, 484 {0x54, 0x00}, 485 {0x55, 0x7c}, 486 {0x56, 0x00}, 487 {0x57, 0x7c}, 488 {0x58, 0x00}, 489 {0x59, 0x7c}, 490 {0xfd, 0x02}, 491 {0x9a, 0x30}, 492 {0xa8, 0x02}, 493 {0xfd, 0x02}, 494 {0xa9, 0x04}, 495 {0xaa, 0xd0}, 496 {0xab, 0x06}, 497 {0xac, 0x68}, 498 {0xa1, 0x04}, 499 {0xa2, 0x04}, 500 {0xa3, 0xc8}, 501 {0xa5, 0x04}, 502 {0xa6, 0x06}, 503 {0xa7, 0x60}, 504 {0xfd, 0x05}, 505 {0x06, 0x80}, 506 {0x18, 0x06}, 507 {0x19, 0x68}, 508 {0xfd, 0x00}, 509 {0x24, 0x01}, 510 {0xc0, 0x16}, 511 {0xc1, 0x08}, 512 {0xc2, 0x30}, 513 {0x8e, 0x06}, 514 {0x8f, 0x60}, 515 {0x90, 0x04}, 516 {0x91, 0xc8}, 517 {0x93, 0x0e}, 518 {0x94, 0x77}, 519 {0x95, 0x77}, 520 {0x96, 0x10}, 521 {0x98, 0x88}, 522 {0x9c, 0x1a}, 523 {0xfd, 0x05}, 524 {0x04, 0x40}, 525 {0x07, 0x99}, 526 {0x0d, 0x03}, 527 {0x0f, 0x03}, 528 {0x10, 0x00}, 529 {0x11, 0x00}, 530 {0x12, 0x0c}, 531 {0x13, 0xcf}, 532 {0x14, 0x00}, 533 {0x15, 0x00}, 534 {0xfd, 0x00}, 535 {0x20, 0x0f}, 536 {0xe7, 0x03}, 537 {0xe7, 0x00}, 538 }; 539 540 static const char * const ov08d10_test_pattern_menu[] = { 541 "Disabled", 542 "Standard Color Bar", 543 }; 544 545 static const char *const ov08d10_supply_names[] = { 546 "dovdd", /* Digital I/O power */ 547 "avdd", /* Analog power */ 548 "dvdd", /* Digital core power */ 549 }; 550 551 struct ov08d10 { 552 struct device *dev; 553 struct clk *clk; 554 struct reset_control *reset; 555 struct regulator_bulk_data supplies[ARRAY_SIZE(ov08d10_supply_names)]; 556 u8 xvclk_index; 557 558 struct v4l2_subdev sd; 559 struct media_pad pad; 560 struct v4l2_ctrl_handler ctrl_handler; 561 562 /* V4L2 Controls */ 563 struct v4l2_ctrl *link_freq; 564 struct v4l2_ctrl *pixel_rate; 565 struct v4l2_ctrl *vblank; 566 struct v4l2_ctrl *hblank; 567 struct v4l2_ctrl *vflip; 568 struct v4l2_ctrl *hflip; 569 struct v4l2_ctrl *exposure; 570 571 /* Current mode */ 572 const struct ov08d10_mode *cur_mode; 573 574 /* To serialize asynchronous callbacks */ 575 struct mutex mutex; 576 577 /* lanes index */ 578 u8 nlanes; 579 580 const struct ov08d10_lane_cfg *priv_lane; 581 u8 modes_size; 582 }; 583 584 struct ov08d10_lane_cfg { 585 const s64 link_freq_menu[2]; 586 const struct ov08d10_link_freq_config link_freq_configs[2]; 587 const struct ov08d10_mode sp_modes[3]; 588 }; 589 590 static const struct ov08d10_lane_cfg lane_cfg_2 = { 591 { 592 720000000, 593 360000000, 594 }, 595 {{ 596 .reg_list = { 597 { 598 .num_of_regs = 599 ARRAY_SIZE(mipi_data_rate_720mbps_19_2), 600 .regs = mipi_data_rate_720mbps_19_2, 601 }, 602 { 603 .num_of_regs = 604 ARRAY_SIZE(mipi_data_rate_720mbps_24_0), 605 .regs = mipi_data_rate_720mbps_24_0, 606 }} 607 }, 608 { 609 .reg_list = { 610 { 611 .num_of_regs = 612 ARRAY_SIZE(mipi_data_rate_360mbps_19_2), 613 .regs = mipi_data_rate_360mbps_19_2, 614 }, 615 { 616 .num_of_regs = 617 ARRAY_SIZE(mipi_data_rate_360mbps_24_0), 618 .regs = mipi_data_rate_360mbps_24_0, 619 }} 620 }}, 621 {{ 622 .width = 3280, 623 .height = 2460, 624 .hts = 1840, 625 .vts_def = 2504, 626 .vts_min = 2504, 627 .reg_list = { 628 .num_of_regs = ARRAY_SIZE(lane_2_mode_3280x2460), 629 .regs = lane_2_mode_3280x2460, 630 }, 631 .link_freq_index = 0, 632 .data_lanes = 2, 633 }, 634 { 635 .width = 3264, 636 .height = 2448, 637 .hts = 1840, 638 .vts_def = 2504, 639 .vts_min = 2504, 640 .reg_list = { 641 .num_of_regs = ARRAY_SIZE(lane_2_mode_3264x2448), 642 .regs = lane_2_mode_3264x2448, 643 }, 644 .link_freq_index = 0, 645 .data_lanes = 2, 646 }, 647 { 648 .width = 1632, 649 .height = 1224, 650 .hts = 1912, 651 .vts_def = 3736, 652 .vts_min = 3736, 653 .reg_list = { 654 .num_of_regs = ARRAY_SIZE(lane_2_mode_1632x1224), 655 .regs = lane_2_mode_1632x1224, 656 }, 657 .link_freq_index = 1, 658 .data_lanes = 2, 659 }} 660 }; 661 662 static u32 ov08d10_get_format_code(struct ov08d10 *ov08d10) 663 { 664 static const u32 codes[2][2] = { 665 { MEDIA_BUS_FMT_SBGGR10_1X10, MEDIA_BUS_FMT_SGBRG10_1X10 }, 666 { MEDIA_BUS_FMT_SGRBG10_1X10, MEDIA_BUS_FMT_SRGGB10_1X10 }, 667 }; 668 669 return codes[ov08d10->vflip->val][ov08d10->hflip->val]; 670 } 671 672 static unsigned int ov08d10_modes_num(const struct ov08d10 *ov08d10) 673 { 674 unsigned int i, count = 0; 675 676 for (i = 0; i < ARRAY_SIZE(ov08d10->priv_lane->sp_modes); i++) { 677 if (ov08d10->priv_lane->sp_modes[i].width == 0) 678 break; 679 count++; 680 } 681 682 return count; 683 } 684 685 static u64 to_rate(const s64 *link_freq_menu, 686 u32 f_index, u8 nlanes) 687 { 688 u64 pixel_rate = link_freq_menu[f_index] * 2 * nlanes; 689 690 do_div(pixel_rate, OV08D10_RGB_DEPTH); 691 692 return pixel_rate; 693 } 694 695 static u64 to_pixels_per_line(const s64 *link_freq_menu, u32 hts, 696 u32 f_index, u8 nlanes) 697 { 698 u64 ppl = hts * to_rate(link_freq_menu, f_index, nlanes); 699 700 do_div(ppl, OV08D10_SCLK); 701 702 return ppl; 703 } 704 705 static int ov08d10_write_reg_list(struct ov08d10 *ov08d10, 706 const struct ov08d10_reg_list *r_list) 707 { 708 struct i2c_client *client = v4l2_get_subdevdata(&ov08d10->sd); 709 unsigned int i; 710 int ret; 711 712 for (i = 0; i < r_list->num_of_regs; i++) { 713 ret = i2c_smbus_write_byte_data(client, r_list->regs[i].address, 714 r_list->regs[i].val); 715 if (ret) { 716 dev_err_ratelimited(ov08d10->dev, 717 "failed to write reg 0x%2.2x. error = %d\n", 718 r_list->regs[i].address, ret); 719 return ret; 720 } 721 } 722 723 return 0; 724 } 725 726 static int ov08d10_update_analog_gain(struct ov08d10 *ov08d10, u32 a_gain) 727 { 728 struct i2c_client *client = v4l2_get_subdevdata(&ov08d10->sd); 729 u8 val; 730 int ret; 731 732 val = ((a_gain >> 3) & 0xFF); 733 /* CIS control registers */ 734 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x01); 735 if (ret < 0) 736 return ret; 737 738 /* update AGAIN */ 739 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_ANALOG_GAIN, val); 740 if (ret < 0) 741 return ret; 742 743 return i2c_smbus_write_byte_data(client, 744 OV08D10_REG_GLOBAL_EFFECTIVE, 0x01); 745 } 746 747 static int ov08d10_update_digital_gain(struct ov08d10 *ov08d10, u32 d_gain) 748 { 749 struct i2c_client *client = v4l2_get_subdevdata(&ov08d10->sd); 750 u8 val; 751 int ret; 752 753 d_gain = (d_gain >> 1); 754 /* CIS control registers */ 755 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x01); 756 if (ret < 0) 757 return ret; 758 759 val = ((d_gain >> 8) & 0x3F); 760 /* update DGAIN */ 761 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_MWB_DGAIN_C, val); 762 if (ret < 0) 763 return ret; 764 765 val = d_gain & 0xFF; 766 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_MWB_DGAIN_F, val); 767 if (ret < 0) 768 return ret; 769 770 return i2c_smbus_write_byte_data(client, 771 OV08D10_REG_GLOBAL_EFFECTIVE, 0x01); 772 } 773 774 static int ov08d10_set_exposure(struct ov08d10 *ov08d10, u32 exposure) 775 { 776 struct i2c_client *client = v4l2_get_subdevdata(&ov08d10->sd); 777 u8 val; 778 u8 hts_h, hts_l; 779 u32 hts, cur_vts, exp_cal; 780 int ret; 781 782 cur_vts = ov08d10->cur_mode->vts_def; 783 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x01); 784 if (ret < 0) 785 return ret; 786 787 hts_h = i2c_smbus_read_byte_data(client, 0x37); 788 hts_l = i2c_smbus_read_byte_data(client, 0x38); 789 hts = ((hts_h << 8) | (hts_l)); 790 exp_cal = 66 * OV08D10_ROWCLK / hts; 791 exposure = exposure * exp_cal / (cur_vts - OV08D10_EXPOSURE_MAX_MARGIN); 792 /* CIS control registers */ 793 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x01); 794 if (ret < 0) 795 return ret; 796 797 /* update exposure */ 798 val = ((exposure >> 16) & 0xFF); 799 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_EXPOSURE_H, val); 800 if (ret < 0) 801 return ret; 802 803 val = ((exposure >> 8) & 0xFF); 804 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_EXPOSURE_M, val); 805 if (ret < 0) 806 return ret; 807 808 val = exposure & 0xFF; 809 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_EXPOSURE_L, val); 810 if (ret < 0) 811 return ret; 812 813 return i2c_smbus_write_byte_data(client, 814 OV08D10_REG_GLOBAL_EFFECTIVE, 0x01); 815 } 816 817 static int ov08d10_set_vblank(struct ov08d10 *ov08d10, u32 vblank) 818 { 819 struct i2c_client *client = v4l2_get_subdevdata(&ov08d10->sd); 820 u8 val; 821 int ret; 822 823 /* CIS control registers */ 824 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x01); 825 if (ret < 0) 826 return ret; 827 828 val = ((vblank >> 8) & 0xFF); 829 /* update vblank */ 830 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_VTS_H, val); 831 if (ret < 0) 832 return ret; 833 834 val = vblank & 0xFF; 835 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_VTS_L, val); 836 if (ret < 0) 837 return ret; 838 839 return i2c_smbus_write_byte_data(client, 840 OV08D10_REG_GLOBAL_EFFECTIVE, 0x01); 841 } 842 843 static int ov08d10_test_pattern(struct ov08d10 *ov08d10, u32 pattern) 844 { 845 struct i2c_client *client = v4l2_get_subdevdata(&ov08d10->sd); 846 u8 val; 847 int ret; 848 849 if (pattern) 850 val = OV08D10_TEST_PATTERN_ENABLE; 851 else 852 val = OV08D10_TEST_PATTERN_DISABLE; 853 854 /* CIS control registers */ 855 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x01); 856 if (ret < 0) 857 return ret; 858 859 ret = i2c_smbus_write_byte_data(client, 860 OV08D10_REG_TEST_PATTERN, val); 861 if (ret < 0) 862 return ret; 863 864 return i2c_smbus_write_byte_data(client, 865 OV08D10_REG_GLOBAL_EFFECTIVE, 0x01); 866 } 867 868 static int ov08d10_set_ctrl_flip(struct ov08d10 *ov08d10, u32 ctrl_val) 869 { 870 struct i2c_client *client = v4l2_get_subdevdata(&ov08d10->sd); 871 u8 val; 872 int ret; 873 874 /* System control registers */ 875 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x01); 876 if (ret < 0) 877 return ret; 878 879 ret = i2c_smbus_read_byte_data(client, OV08D10_REG_FLIP_OPT); 880 if (ret < 0) 881 return ret; 882 883 val = ret | (ctrl_val & OV08D10_REG_FLIP_MASK); 884 885 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x01); 886 if (ret < 0) 887 return ret; 888 889 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_FLIP_OPT, val); 890 891 if (ret < 0) 892 return ret; 893 894 return i2c_smbus_write_byte_data(client, 895 OV08D10_REG_GLOBAL_EFFECTIVE, 0x01); 896 } 897 898 static int ov08d10_set_ctrl(struct v4l2_ctrl *ctrl) 899 { 900 struct ov08d10 *ov08d10 = container_of(ctrl->handler, 901 struct ov08d10, ctrl_handler); 902 s64 exposure_max; 903 int ret; 904 905 /* Propagate change of current control to all related controls */ 906 if (ctrl->id == V4L2_CID_VBLANK) { 907 /* Update max exposure while meeting expected vblanking */ 908 exposure_max = ov08d10->cur_mode->height + ctrl->val - 909 OV08D10_EXPOSURE_MAX_MARGIN; 910 __v4l2_ctrl_modify_range(ov08d10->exposure, 911 ov08d10->exposure->minimum, 912 exposure_max, ov08d10->exposure->step, 913 exposure_max); 914 } 915 916 /* V4L2 control values will be applied only when power is already up */ 917 if (!pm_runtime_get_if_in_use(ov08d10->dev)) 918 return 0; 919 920 switch (ctrl->id) { 921 case V4L2_CID_ANALOGUE_GAIN: 922 ret = ov08d10_update_analog_gain(ov08d10, ctrl->val); 923 break; 924 925 case V4L2_CID_DIGITAL_GAIN: 926 ret = ov08d10_update_digital_gain(ov08d10, ctrl->val); 927 break; 928 929 case V4L2_CID_EXPOSURE: 930 ret = ov08d10_set_exposure(ov08d10, ctrl->val); 931 break; 932 933 case V4L2_CID_VBLANK: 934 ret = ov08d10_set_vblank(ov08d10, ctrl->val); 935 break; 936 937 case V4L2_CID_TEST_PATTERN: 938 ret = ov08d10_test_pattern(ov08d10, ctrl->val); 939 break; 940 941 case V4L2_CID_HFLIP: 942 case V4L2_CID_VFLIP: 943 ret = ov08d10_set_ctrl_flip(ov08d10, 944 ov08d10->hflip->val | 945 ov08d10->vflip->val << 1); 946 break; 947 948 default: 949 ret = -EINVAL; 950 break; 951 } 952 953 pm_runtime_put(ov08d10->dev); 954 955 return ret; 956 } 957 958 static const struct v4l2_ctrl_ops ov08d10_ctrl_ops = { 959 .s_ctrl = ov08d10_set_ctrl, 960 }; 961 962 static int ov08d10_init_controls(struct ov08d10 *ov08d10) 963 { 964 struct v4l2_ctrl_handler *ctrl_hdlr; 965 u8 link_freq_size; 966 s64 exposure_max; 967 s64 vblank_def; 968 s64 vblank_min; 969 s64 h_blank; 970 s64 pixel_rate_max; 971 const struct ov08d10_mode *mode; 972 int ret; 973 974 ctrl_hdlr = &ov08d10->ctrl_handler; 975 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8); 976 if (ret) 977 return ret; 978 979 ctrl_hdlr->lock = &ov08d10->mutex; 980 link_freq_size = ARRAY_SIZE(ov08d10->priv_lane->link_freq_menu); 981 ov08d10->link_freq = 982 v4l2_ctrl_new_int_menu(ctrl_hdlr, &ov08d10_ctrl_ops, 983 V4L2_CID_LINK_FREQ, 984 link_freq_size - 1, 985 0, 986 ov08d10->priv_lane->link_freq_menu); 987 if (ov08d10->link_freq) 988 ov08d10->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 989 990 pixel_rate_max = to_rate(ov08d10->priv_lane->link_freq_menu, 0, 991 ov08d10->cur_mode->data_lanes); 992 ov08d10->pixel_rate = 993 v4l2_ctrl_new_std(ctrl_hdlr, &ov08d10_ctrl_ops, 994 V4L2_CID_PIXEL_RATE, 0, pixel_rate_max, 1, 995 pixel_rate_max); 996 997 mode = ov08d10->cur_mode; 998 vblank_def = mode->vts_def - mode->height; 999 vblank_min = mode->vts_min - mode->height; 1000 ov08d10->vblank = 1001 v4l2_ctrl_new_std(ctrl_hdlr, &ov08d10_ctrl_ops, 1002 V4L2_CID_VBLANK, vblank_min, 1003 OV08D10_VTS_MAX - mode->height, 1, 1004 vblank_def); 1005 1006 h_blank = to_pixels_per_line(ov08d10->priv_lane->link_freq_menu, 1007 mode->hts, mode->link_freq_index, 1008 mode->data_lanes) - 1009 mode->width; 1010 ov08d10->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov08d10_ctrl_ops, 1011 V4L2_CID_HBLANK, h_blank, h_blank, 1012 1, h_blank); 1013 if (ov08d10->hblank) 1014 ov08d10->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1015 1016 v4l2_ctrl_new_std(ctrl_hdlr, &ov08d10_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 1017 OV08D10_ANAL_GAIN_MIN, OV08D10_ANAL_GAIN_MAX, 1018 OV08D10_ANAL_GAIN_STEP, OV08D10_ANAL_GAIN_MIN); 1019 1020 v4l2_ctrl_new_std(ctrl_hdlr, &ov08d10_ctrl_ops, V4L2_CID_DIGITAL_GAIN, 1021 OV08D10_DGTL_GAIN_MIN, OV08D10_DGTL_GAIN_MAX, 1022 OV08D10_DGTL_GAIN_STEP, OV08D10_DGTL_GAIN_DEFAULT); 1023 1024 exposure_max = mode->vts_def - OV08D10_EXPOSURE_MAX_MARGIN; 1025 ov08d10->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov08d10_ctrl_ops, 1026 V4L2_CID_EXPOSURE, 1027 OV08D10_EXPOSURE_MIN, 1028 exposure_max, 1029 OV08D10_EXPOSURE_STEP, 1030 exposure_max); 1031 1032 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov08d10_ctrl_ops, 1033 V4L2_CID_TEST_PATTERN, 1034 ARRAY_SIZE(ov08d10_test_pattern_menu) - 1, 1035 0, 0, ov08d10_test_pattern_menu); 1036 1037 ov08d10->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &ov08d10_ctrl_ops, 1038 V4L2_CID_HFLIP, 0, 1, 1, 0); 1039 if (ov08d10->hflip) 1040 ov08d10->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; 1041 ov08d10->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &ov08d10_ctrl_ops, 1042 V4L2_CID_VFLIP, 0, 1, 1, 0); 1043 if (ov08d10->vflip) 1044 ov08d10->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; 1045 1046 if (ctrl_hdlr->error) 1047 return ctrl_hdlr->error; 1048 1049 ov08d10->sd.ctrl_handler = ctrl_hdlr; 1050 1051 return 0; 1052 } 1053 1054 static void ov08d10_update_pad_format(struct ov08d10 *ov08d10, 1055 const struct ov08d10_mode *mode, 1056 struct v4l2_mbus_framefmt *fmt) 1057 { 1058 fmt->width = mode->width; 1059 fmt->height = mode->height; 1060 fmt->code = ov08d10_get_format_code(ov08d10); 1061 fmt->field = V4L2_FIELD_NONE; 1062 } 1063 1064 static int ov08d10_start_streaming(struct ov08d10 *ov08d10) 1065 { 1066 struct i2c_client *client = v4l2_get_subdevdata(&ov08d10->sd); 1067 const struct ov08d10_reg_list *reg_list; 1068 int link_freq_index, ret; 1069 1070 link_freq_index = ov08d10->cur_mode->link_freq_index; 1071 reg_list = 1072 &ov08d10->priv_lane->link_freq_configs[link_freq_index] 1073 .reg_list[ov08d10->xvclk_index]; 1074 1075 /* soft reset */ 1076 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x00); 1077 if (ret < 0) { 1078 dev_err(ov08d10->dev, "failed to reset sensor\n"); 1079 return ret; 1080 } 1081 ret = i2c_smbus_write_byte_data(client, 0x20, 0x0e); 1082 if (ret < 0) { 1083 dev_err(ov08d10->dev, "failed to reset sensor\n"); 1084 return ret; 1085 } 1086 usleep_range(3000, 4000); 1087 ret = i2c_smbus_write_byte_data(client, 0x20, 0x0b); 1088 if (ret < 0) { 1089 dev_err(ov08d10->dev, "failed to reset sensor\n"); 1090 return ret; 1091 } 1092 1093 /* update sensor setting */ 1094 ret = ov08d10_write_reg_list(ov08d10, reg_list); 1095 if (ret) { 1096 dev_err(ov08d10->dev, "failed to set plls\n"); 1097 return ret; 1098 } 1099 1100 reg_list = &ov08d10->cur_mode->reg_list; 1101 ret = ov08d10_write_reg_list(ov08d10, reg_list); 1102 if (ret) { 1103 dev_err(ov08d10->dev, "failed to set mode\n"); 1104 return ret; 1105 } 1106 1107 ret = __v4l2_ctrl_handler_setup(ov08d10->sd.ctrl_handler); 1108 if (ret) 1109 return ret; 1110 1111 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x00); 1112 if (ret < 0) 1113 return ret; 1114 1115 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_MODE_SELECT, 1116 OV08D10_MODE_STREAMING); 1117 if (ret < 0) 1118 return ret; 1119 1120 return i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x01); 1121 } 1122 1123 static void ov08d10_stop_streaming(struct ov08d10 *ov08d10) 1124 { 1125 struct i2c_client *client = v4l2_get_subdevdata(&ov08d10->sd); 1126 int ret; 1127 1128 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x00); 1129 if (ret < 0) { 1130 dev_err(ov08d10->dev, "failed to stop streaming\n"); 1131 return; 1132 } 1133 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_MODE_SELECT, 1134 OV08D10_MODE_STANDBY); 1135 if (ret < 0) { 1136 dev_err(ov08d10->dev, "failed to stop streaming\n"); 1137 return; 1138 } 1139 1140 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x01); 1141 if (ret < 0) { 1142 dev_err(ov08d10->dev, "failed to stop streaming\n"); 1143 return; 1144 } 1145 } 1146 1147 static int ov08d10_set_stream(struct v4l2_subdev *sd, int enable) 1148 { 1149 struct ov08d10 *ov08d10 = to_ov08d10(sd); 1150 int ret = 0; 1151 1152 mutex_lock(&ov08d10->mutex); 1153 if (enable) { 1154 ret = pm_runtime_resume_and_get(ov08d10->dev); 1155 if (ret < 0) { 1156 mutex_unlock(&ov08d10->mutex); 1157 return ret; 1158 } 1159 1160 ret = ov08d10_start_streaming(ov08d10); 1161 if (ret) { 1162 enable = 0; 1163 ov08d10_stop_streaming(ov08d10); 1164 pm_runtime_put(ov08d10->dev); 1165 } 1166 } else { 1167 ov08d10_stop_streaming(ov08d10); 1168 pm_runtime_put(ov08d10->dev); 1169 } 1170 1171 /* vflip and hflip cannot change during streaming */ 1172 __v4l2_ctrl_grab(ov08d10->vflip, enable); 1173 __v4l2_ctrl_grab(ov08d10->hflip, enable); 1174 1175 mutex_unlock(&ov08d10->mutex); 1176 1177 return ret; 1178 } 1179 1180 static int ov08d10_set_format(struct v4l2_subdev *sd, 1181 struct v4l2_subdev_state *sd_state, 1182 struct v4l2_subdev_format *fmt) 1183 { 1184 struct ov08d10 *ov08d10 = to_ov08d10(sd); 1185 const struct ov08d10_mode *mode; 1186 s32 vblank_def, h_blank; 1187 s64 pixel_rate; 1188 1189 mode = v4l2_find_nearest_size(ov08d10->priv_lane->sp_modes, 1190 ov08d10->modes_size, 1191 width, height, fmt->format.width, 1192 fmt->format.height); 1193 1194 mutex_lock(&ov08d10->mutex); 1195 ov08d10_update_pad_format(ov08d10, mode, &fmt->format); 1196 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 1197 *v4l2_subdev_state_get_format(sd_state, fmt->pad) = 1198 fmt->format; 1199 } else { 1200 ov08d10->cur_mode = mode; 1201 __v4l2_ctrl_s_ctrl(ov08d10->link_freq, mode->link_freq_index); 1202 pixel_rate = to_rate(ov08d10->priv_lane->link_freq_menu, 1203 mode->link_freq_index, 1204 ov08d10->cur_mode->data_lanes); 1205 __v4l2_ctrl_s_ctrl_int64(ov08d10->pixel_rate, pixel_rate); 1206 1207 /* Update limits and set FPS to default */ 1208 vblank_def = mode->vts_def - mode->height; 1209 __v4l2_ctrl_modify_range(ov08d10->vblank, 1210 mode->vts_min - mode->height, 1211 OV08D10_VTS_MAX - mode->height, 1, 1212 vblank_def); 1213 __v4l2_ctrl_s_ctrl(ov08d10->vblank, vblank_def); 1214 h_blank = to_pixels_per_line(ov08d10->priv_lane->link_freq_menu, 1215 mode->hts, 1216 mode->link_freq_index, 1217 ov08d10->cur_mode->data_lanes) 1218 - mode->width; 1219 __v4l2_ctrl_modify_range(ov08d10->hblank, h_blank, h_blank, 1, 1220 h_blank); 1221 } 1222 1223 mutex_unlock(&ov08d10->mutex); 1224 1225 return 0; 1226 } 1227 1228 static int ov08d10_get_format(struct v4l2_subdev *sd, 1229 struct v4l2_subdev_state *sd_state, 1230 struct v4l2_subdev_format *fmt) 1231 { 1232 struct ov08d10 *ov08d10 = to_ov08d10(sd); 1233 1234 mutex_lock(&ov08d10->mutex); 1235 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) 1236 fmt->format = *v4l2_subdev_state_get_format(sd_state, 1237 fmt->pad); 1238 else 1239 ov08d10_update_pad_format(ov08d10, ov08d10->cur_mode, 1240 &fmt->format); 1241 1242 mutex_unlock(&ov08d10->mutex); 1243 1244 return 0; 1245 } 1246 1247 static int ov08d10_enum_mbus_code(struct v4l2_subdev *sd, 1248 struct v4l2_subdev_state *sd_state, 1249 struct v4l2_subdev_mbus_code_enum *code) 1250 { 1251 struct ov08d10 *ov08d10 = to_ov08d10(sd); 1252 1253 if (code->index > 0) 1254 return -EINVAL; 1255 1256 mutex_lock(&ov08d10->mutex); 1257 code->code = ov08d10_get_format_code(ov08d10); 1258 mutex_unlock(&ov08d10->mutex); 1259 1260 return 0; 1261 } 1262 1263 static int ov08d10_enum_frame_size(struct v4l2_subdev *sd, 1264 struct v4l2_subdev_state *sd_state, 1265 struct v4l2_subdev_frame_size_enum *fse) 1266 { 1267 struct ov08d10 *ov08d10 = to_ov08d10(sd); 1268 1269 if (fse->index >= ov08d10->modes_size) 1270 return -EINVAL; 1271 1272 mutex_lock(&ov08d10->mutex); 1273 if (fse->code != ov08d10_get_format_code(ov08d10)) { 1274 mutex_unlock(&ov08d10->mutex); 1275 return -EINVAL; 1276 } 1277 mutex_unlock(&ov08d10->mutex); 1278 1279 fse->min_width = ov08d10->priv_lane->sp_modes[fse->index].width; 1280 fse->max_width = fse->min_width; 1281 fse->min_height = ov08d10->priv_lane->sp_modes[fse->index].height; 1282 fse->max_height = fse->min_height; 1283 1284 return 0; 1285 } 1286 1287 static int ov08d10_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) 1288 { 1289 struct ov08d10 *ov08d10 = to_ov08d10(sd); 1290 1291 mutex_lock(&ov08d10->mutex); 1292 ov08d10_update_pad_format(ov08d10, &ov08d10->priv_lane->sp_modes[0], 1293 v4l2_subdev_state_get_format(fh->state, 0)); 1294 mutex_unlock(&ov08d10->mutex); 1295 1296 return 0; 1297 } 1298 1299 static const struct v4l2_subdev_video_ops ov08d10_video_ops = { 1300 .s_stream = ov08d10_set_stream, 1301 }; 1302 1303 static const struct v4l2_subdev_pad_ops ov08d10_pad_ops = { 1304 .set_fmt = ov08d10_set_format, 1305 .get_fmt = ov08d10_get_format, 1306 .enum_mbus_code = ov08d10_enum_mbus_code, 1307 .enum_frame_size = ov08d10_enum_frame_size, 1308 }; 1309 1310 static const struct v4l2_subdev_ops ov08d10_subdev_ops = { 1311 .video = &ov08d10_video_ops, 1312 .pad = &ov08d10_pad_ops, 1313 }; 1314 1315 static const struct v4l2_subdev_internal_ops ov08d10_internal_ops = { 1316 .open = ov08d10_open, 1317 }; 1318 1319 static int ov08d10_power_off(struct device *dev) 1320 { 1321 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1322 struct ov08d10 *ov08d10 = to_ov08d10(sd); 1323 1324 reset_control_assert(ov08d10->reset); 1325 1326 regulator_bulk_disable(ARRAY_SIZE(ov08d10->supplies), 1327 ov08d10->supplies); 1328 1329 clk_disable_unprepare(ov08d10->clk); 1330 1331 return 0; 1332 } 1333 1334 static int ov08d10_power_on(struct device *dev) 1335 { 1336 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1337 struct ov08d10 *ov08d10 = to_ov08d10(sd); 1338 int ret; 1339 1340 ret = regulator_bulk_enable(ARRAY_SIZE(ov08d10->supplies), 1341 ov08d10->supplies); 1342 if (ret < 0) { 1343 dev_err(dev, "failed to enable regulators: %d\n", ret); 1344 return ret; 1345 } 1346 1347 ret = clk_prepare_enable(ov08d10->clk); 1348 if (ret < 0) { 1349 regulator_bulk_disable(ARRAY_SIZE(ov08d10->supplies), 1350 ov08d10->supplies); 1351 1352 dev_err(dev, "failed to enable imaging clock: %d\n", ret); 1353 return ret; 1354 } 1355 1356 if (ov08d10->reset) { 1357 /* Delay from DVDD stable to sensor XSHUTDN pull up: 5ms */ 1358 fsleep(5 * USEC_PER_MSEC); 1359 1360 reset_control_deassert(ov08d10->reset); 1361 1362 /* Delay from XSHUTDN pull up to SCCB start: 8ms */ 1363 fsleep(8 * USEC_PER_MSEC); 1364 } 1365 1366 return 0; 1367 } 1368 1369 static int ov08d10_identify_module(struct ov08d10 *ov08d10) 1370 { 1371 struct i2c_client *client = v4l2_get_subdevdata(&ov08d10->sd); 1372 u32 val; 1373 u16 chip_id; 1374 int ret; 1375 1376 /* System control registers */ 1377 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x00); 1378 if (ret < 0) 1379 return ret; 1380 1381 /* Validate the chip ID */ 1382 ret = i2c_smbus_read_byte_data(client, OV08D10_REG_CHIP_ID_0); 1383 if (ret < 0) 1384 return ret; 1385 1386 val = ret << 8; 1387 1388 ret = i2c_smbus_read_byte_data(client, OV08D10_REG_CHIP_ID_1); 1389 if (ret < 0) 1390 return ret; 1391 1392 chip_id = val | ret; 1393 1394 if ((chip_id & OV08D10_ID_MASK) != OV08D10_CHIP_ID) { 1395 dev_err(ov08d10->dev, "unexpected sensor id(0x%04x)\n", 1396 chip_id); 1397 return -EINVAL; 1398 } 1399 1400 return 0; 1401 } 1402 1403 static int ov08d10_get_hwcfg(struct ov08d10 *ov08d10) 1404 { 1405 struct device *dev = ov08d10->dev; 1406 struct fwnode_handle *ep; 1407 struct fwnode_handle *fwnode = dev_fwnode(dev); 1408 struct v4l2_fwnode_endpoint bus_cfg = { 1409 .bus_type = V4L2_MBUS_CSI2_DPHY 1410 }; 1411 unsigned int i, j; 1412 int ret; 1413 1414 if (!fwnode) 1415 return -ENXIO; 1416 1417 ep = fwnode_graph_get_next_endpoint(fwnode, NULL); 1418 if (!ep) 1419 return -ENXIO; 1420 1421 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); 1422 fwnode_handle_put(ep); 1423 if (ret) 1424 return ret; 1425 1426 /* Get number of data lanes */ 1427 if (bus_cfg.bus.mipi_csi2.num_data_lanes != 2) { 1428 dev_err(dev, "number of CSI2 data lanes %d is not supported\n", 1429 bus_cfg.bus.mipi_csi2.num_data_lanes); 1430 ret = -EINVAL; 1431 goto check_hwcfg_error; 1432 } 1433 1434 dev_dbg(dev, "Using %u data lanes\n", ov08d10->cur_mode->data_lanes); 1435 1436 ov08d10->priv_lane = &lane_cfg_2; 1437 ov08d10->modes_size = ov08d10_modes_num(ov08d10); 1438 1439 if (!bus_cfg.nr_of_link_frequencies) { 1440 dev_err(dev, "no link frequencies defined\n"); 1441 ret = -EINVAL; 1442 goto check_hwcfg_error; 1443 } 1444 1445 for (i = 0; i < ARRAY_SIZE(ov08d10->priv_lane->link_freq_menu); i++) { 1446 for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) { 1447 if (ov08d10->priv_lane->link_freq_menu[i] == 1448 bus_cfg.link_frequencies[j]) 1449 break; 1450 } 1451 1452 if (j == bus_cfg.nr_of_link_frequencies) { 1453 dev_err(dev, "no link frequency %lld supported\n", 1454 ov08d10->priv_lane->link_freq_menu[i]); 1455 ret = -EINVAL; 1456 goto check_hwcfg_error; 1457 } 1458 } 1459 1460 check_hwcfg_error: 1461 v4l2_fwnode_endpoint_free(&bus_cfg); 1462 1463 return ret; 1464 } 1465 1466 static void ov08d10_remove(struct i2c_client *client) 1467 { 1468 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1469 struct ov08d10 *ov08d10 = to_ov08d10(sd); 1470 1471 v4l2_async_unregister_subdev(sd); 1472 media_entity_cleanup(&sd->entity); 1473 v4l2_ctrl_handler_free(sd->ctrl_handler); 1474 pm_runtime_disable(ov08d10->dev); 1475 if (!pm_runtime_status_suspended(ov08d10->dev)) { 1476 ov08d10_power_off(ov08d10->dev); 1477 pm_runtime_set_suspended(ov08d10->dev); 1478 } 1479 mutex_destroy(&ov08d10->mutex); 1480 } 1481 1482 static int ov08d10_probe(struct i2c_client *client) 1483 { 1484 struct ov08d10 *ov08d10; 1485 unsigned long freq; 1486 unsigned int i; 1487 int ret; 1488 1489 ov08d10 = devm_kzalloc(&client->dev, sizeof(*ov08d10), GFP_KERNEL); 1490 if (!ov08d10) 1491 return -ENOMEM; 1492 1493 ov08d10->dev = &client->dev; 1494 1495 ov08d10->clk = devm_v4l2_sensor_clk_get(ov08d10->dev, NULL); 1496 if (IS_ERR(ov08d10->clk)) 1497 return dev_err_probe(ov08d10->dev, PTR_ERR(ov08d10->clk), 1498 "failed to get clock\n"); 1499 1500 freq = clk_get_rate(ov08d10->clk); 1501 for (i = 0; i < ARRAY_SIZE(ov08d10_xvclk_freqs); i++) { 1502 if (freq == ov08d10_xvclk_freqs[i]) 1503 break; 1504 } 1505 if (i >= ARRAY_SIZE(ov08d10_xvclk_freqs)) 1506 return dev_err_probe(ov08d10->dev, -EINVAL, 1507 "external clock rate %lu is not supported\n", 1508 freq); 1509 ov08d10->xvclk_index = i; 1510 1511 ret = ov08d10_get_hwcfg(ov08d10); 1512 if (ret) { 1513 dev_err(ov08d10->dev, "failed to get HW configuration: %d\n", 1514 ret); 1515 return ret; 1516 } 1517 1518 ov08d10->reset = devm_reset_control_get_optional_exclusive(ov08d10->dev, NULL); 1519 if (IS_ERR(ov08d10->reset)) 1520 return dev_err_probe(ov08d10->dev, PTR_ERR(ov08d10->reset), 1521 "failed to get reset\n"); 1522 reset_control_assert(ov08d10->reset); 1523 1524 for (i = 0; i < ARRAY_SIZE(ov08d10_supply_names); i++) 1525 ov08d10->supplies[i].supply = ov08d10_supply_names[i]; 1526 1527 ret = devm_regulator_bulk_get(ov08d10->dev, 1528 ARRAY_SIZE(ov08d10->supplies), 1529 ov08d10->supplies); 1530 if (ret) 1531 return dev_err_probe(ov08d10->dev, ret, 1532 "failed to get regulators\n"); 1533 1534 v4l2_i2c_subdev_init(&ov08d10->sd, client, &ov08d10_subdev_ops); 1535 1536 ret = ov08d10_power_on(ov08d10->dev); 1537 if (ret) 1538 return dev_err_probe(ov08d10->dev, ret, "failed to power on\n"); 1539 1540 ret = ov08d10_identify_module(ov08d10); 1541 if (ret) { 1542 dev_err(ov08d10->dev, "failed to find sensor: %d\n", ret); 1543 goto probe_error_power_off; 1544 } 1545 1546 mutex_init(&ov08d10->mutex); 1547 ov08d10->cur_mode = &ov08d10->priv_lane->sp_modes[0]; 1548 ret = ov08d10_init_controls(ov08d10); 1549 if (ret) { 1550 dev_err(ov08d10->dev, "failed to init controls: %d\n", ret); 1551 goto probe_error_v4l2_ctrl_handler_free; 1552 } 1553 1554 ov08d10->sd.internal_ops = &ov08d10_internal_ops; 1555 ov08d10->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1556 ov08d10->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1557 ov08d10->pad.flags = MEDIA_PAD_FL_SOURCE; 1558 ret = media_entity_pads_init(&ov08d10->sd.entity, 1, &ov08d10->pad); 1559 if (ret) { 1560 dev_err(ov08d10->dev, "failed to init entity pads: %d\n", ret); 1561 goto probe_error_v4l2_ctrl_handler_free; 1562 } 1563 1564 pm_runtime_set_active(ov08d10->dev); 1565 pm_runtime_enable(ov08d10->dev); 1566 1567 ret = v4l2_async_register_subdev_sensor(&ov08d10->sd); 1568 if (ret < 0) { 1569 dev_err(ov08d10->dev, "failed to register V4L2 subdev: %d\n", 1570 ret); 1571 goto probe_error_media_entity_cleanup; 1572 } 1573 1574 pm_runtime_idle(ov08d10->dev); 1575 1576 return 0; 1577 1578 probe_error_media_entity_cleanup: 1579 pm_runtime_disable(ov08d10->dev); 1580 pm_runtime_set_suspended(ov08d10->dev); 1581 media_entity_cleanup(&ov08d10->sd.entity); 1582 1583 probe_error_v4l2_ctrl_handler_free: 1584 v4l2_ctrl_handler_free(ov08d10->sd.ctrl_handler); 1585 mutex_destroy(&ov08d10->mutex); 1586 1587 probe_error_power_off: 1588 ov08d10_power_off(ov08d10->dev); 1589 1590 return ret; 1591 } 1592 1593 static DEFINE_RUNTIME_DEV_PM_OPS(ov08d10_pm_ops, 1594 ov08d10_power_off, ov08d10_power_on, NULL); 1595 1596 #ifdef CONFIG_ACPI 1597 static const struct acpi_device_id ov08d10_acpi_ids[] = { 1598 { "OVTI08D1" }, 1599 { /* sentinel */ } 1600 }; 1601 1602 MODULE_DEVICE_TABLE(acpi, ov08d10_acpi_ids); 1603 #endif 1604 1605 static const struct of_device_id ov08d10_of_match[] = { 1606 { .compatible = "ovti,ov08d10" }, 1607 { /* sentinel */ } 1608 }; 1609 MODULE_DEVICE_TABLE(of, ov08d10_of_match); 1610 1611 static struct i2c_driver ov08d10_i2c_driver = { 1612 .driver = { 1613 .name = "ov08d10", 1614 .pm = pm_ptr(&ov08d10_pm_ops), 1615 .acpi_match_table = ACPI_PTR(ov08d10_acpi_ids), 1616 .of_match_table = ov08d10_of_match, 1617 }, 1618 .probe = ov08d10_probe, 1619 .remove = ov08d10_remove, 1620 }; 1621 1622 module_i2c_driver(ov08d10_i2c_driver); 1623 1624 MODULE_AUTHOR("Su, Jimmy <jimmy.su@intel.com>"); 1625 MODULE_DESCRIPTION("OmniVision ov08d10 sensor driver"); 1626 MODULE_LICENSE("GPL v2"); 1627