1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2022 Intel Corporation. 3 4 #include <linux/acpi.h> 5 #include <linux/clk.h> 6 #include <linux/delay.h> 7 #include <linux/gpio/consumer.h> 8 #include <linux/i2c.h> 9 #include <linux/module.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/regmap.h> 12 #include <media/v4l2-cci.h> 13 #include <media/v4l2-ctrls.h> 14 #include <media/v4l2-device.h> 15 #include <media/v4l2-fwnode.h> 16 17 #define OV02C10_LINK_FREQ_400MHZ 400000000ULL 18 #define OV02C10_MCLK 19200000 19 #define OV02C10_RGB_DEPTH 10 20 21 #define OV02C10_REG_CHIP_ID CCI_REG16(0x300a) 22 #define OV02C10_CHIP_ID 0x5602 23 24 #define OV02C10_REG_STREAM_CONTROL CCI_REG8(0x0100) 25 26 #define OV02C10_REG_HTS CCI_REG16(0x380c) 27 28 /* vertical-timings from sensor */ 29 #define OV02C10_REG_VTS CCI_REG16(0x380e) 30 #define OV02C10_VTS_MAX 0xffff 31 32 /* Exposure controls from sensor */ 33 #define OV02C10_REG_EXPOSURE CCI_REG16(0x3501) 34 #define OV02C10_EXPOSURE_MIN 4 35 #define OV02C10_EXPOSURE_MAX_MARGIN 8 36 #define OV02C10_EXPOSURE_STEP 1 37 38 /* Analog gain controls from sensor */ 39 #define OV02C10_REG_ANALOG_GAIN CCI_REG16(0x3508) 40 #define OV02C10_ANAL_GAIN_MIN 0x10 41 #define OV02C10_ANAL_GAIN_MAX 0xf8 42 #define OV02C10_ANAL_GAIN_STEP 1 43 #define OV02C10_ANAL_GAIN_DEFAULT 0x10 44 45 /* Digital gain controls from sensor */ 46 #define OV02C10_REG_DIGITAL_GAIN CCI_REG24(0x350a) 47 #define OV02C10_DGTL_GAIN_MIN 0x0400 48 #define OV02C10_DGTL_GAIN_MAX 0x3fff 49 #define OV02C10_DGTL_GAIN_STEP 1 50 #define OV02C10_DGTL_GAIN_DEFAULT 0x0400 51 52 /* Rotate */ 53 #define OV02C10_ROTATE_CONTROL CCI_REG8(0x3820) 54 #define OV02C10_ISP_X_WIN_CONTROL CCI_REG16(0x3810) 55 #define OV02C10_ISP_Y_WIN_CONTROL CCI_REG16(0x3812) 56 #define OV02C10_CONFIG_ROTATE 0x18 57 58 /* Test Pattern Control */ 59 #define OV02C10_REG_TEST_PATTERN CCI_REG8(0x4503) 60 #define OV02C10_TEST_PATTERN_ENABLE BIT(7) 61 62 struct ov02c10_mode { 63 /* Frame width in pixels */ 64 u32 width; 65 66 /* Frame height in pixels */ 67 u32 height; 68 69 /* Horizontal timining size */ 70 u32 hts; 71 72 /* Min vertical timining size */ 73 u32 vts_min; 74 75 /* Sensor register settings for this resolution */ 76 const struct reg_sequence *reg_sequence; 77 const int sequence_length; 78 /* Sensor register settings for 1 or 2 lane config */ 79 const struct reg_sequence *lane_settings[2]; 80 const int lane_settings_length[2]; 81 }; 82 83 static const struct reg_sequence sensor_1928x1092_30fps_setting[] = { 84 {0x0301, 0x08}, 85 {0x0303, 0x06}, 86 {0x0304, 0x01}, 87 {0x0305, 0xe0}, 88 {0x0313, 0x40}, 89 {0x031c, 0x4f}, 90 {0x3020, 0x97}, 91 {0x3022, 0x01}, 92 {0x3026, 0xb4}, 93 {0x303b, 0x00}, 94 {0x303c, 0x4f}, 95 {0x303d, 0xe6}, 96 {0x303e, 0x00}, 97 {0x303f, 0x03}, 98 {0x3021, 0x23}, 99 {0x3501, 0x04}, 100 {0x3502, 0x6c}, 101 {0x3504, 0x0c}, 102 {0x3507, 0x00}, 103 {0x3508, 0x08}, 104 {0x3509, 0x00}, 105 {0x350a, 0x01}, 106 {0x350b, 0x00}, 107 {0x350c, 0x41}, 108 {0x3600, 0x84}, 109 {0x3603, 0x08}, 110 {0x3610, 0x57}, 111 {0x3611, 0x1b}, 112 {0x3613, 0x78}, 113 {0x3623, 0x00}, 114 {0x3632, 0xa0}, 115 {0x3642, 0xe8}, 116 {0x364c, 0x70}, 117 {0x365f, 0x0f}, 118 {0x3708, 0x30}, 119 {0x3714, 0x24}, 120 {0x3725, 0x02}, 121 {0x3737, 0x08}, 122 {0x3739, 0x28}, 123 {0x3749, 0x32}, 124 {0x374a, 0x32}, 125 {0x374b, 0x32}, 126 {0x374c, 0x32}, 127 {0x374d, 0x81}, 128 {0x374e, 0x81}, 129 {0x374f, 0x81}, 130 {0x3752, 0x36}, 131 {0x3753, 0x36}, 132 {0x3754, 0x36}, 133 {0x3761, 0x00}, 134 {0x376c, 0x81}, 135 {0x3774, 0x18}, 136 {0x3776, 0x08}, 137 {0x377c, 0x81}, 138 {0x377d, 0x81}, 139 {0x377e, 0x81}, 140 {0x37a0, 0x44}, 141 {0x37a6, 0x44}, 142 {0x37aa, 0x0d}, 143 {0x37ae, 0x00}, 144 {0x37cb, 0x03}, 145 {0x37cc, 0x01}, 146 {0x37d8, 0x02}, 147 {0x37d9, 0x10}, 148 {0x37e1, 0x10}, 149 {0x37e2, 0x18}, 150 {0x37e3, 0x08}, 151 {0x37e4, 0x08}, 152 {0x37e5, 0x02}, 153 {0x37e6, 0x08}, 154 155 /* 1928x1092 */ 156 {0x3800, 0x00}, 157 {0x3801, 0x00}, 158 {0x3802, 0x00}, 159 {0x3803, 0x00}, 160 {0x3804, 0x07}, 161 {0x3805, 0x8f}, 162 {0x3806, 0x04}, 163 {0x3807, 0x47}, 164 {0x3808, 0x07}, 165 {0x3809, 0x88}, 166 {0x380a, 0x04}, 167 {0x380b, 0x44}, 168 {0x3810, 0x00}, 169 {0x3811, 0x02}, 170 {0x3812, 0x00}, 171 {0x3813, 0x02}, 172 {0x3814, 0x01}, 173 {0x3815, 0x01}, 174 {0x3816, 0x01}, 175 {0x3817, 0x01}, 176 177 {0x3820, 0xa0}, 178 {0x3821, 0x00}, 179 {0x3822, 0x80}, 180 {0x3823, 0x08}, 181 {0x3824, 0x00}, 182 {0x3825, 0x20}, 183 {0x3826, 0x00}, 184 {0x3827, 0x08}, 185 {0x382a, 0x00}, 186 {0x382b, 0x08}, 187 {0x382d, 0x00}, 188 {0x382e, 0x00}, 189 {0x382f, 0x23}, 190 {0x3834, 0x00}, 191 {0x3839, 0x00}, 192 {0x383a, 0xd1}, 193 {0x383e, 0x03}, 194 {0x393d, 0x29}, 195 {0x393f, 0x6e}, 196 {0x394b, 0x06}, 197 {0x394c, 0x06}, 198 {0x394d, 0x08}, 199 {0x394f, 0x01}, 200 {0x3950, 0x01}, 201 {0x3951, 0x01}, 202 {0x3952, 0x01}, 203 {0x3953, 0x01}, 204 {0x3954, 0x01}, 205 {0x3955, 0x01}, 206 {0x3956, 0x01}, 207 {0x3957, 0x0e}, 208 {0x3958, 0x08}, 209 {0x3959, 0x08}, 210 {0x395a, 0x08}, 211 {0x395b, 0x13}, 212 {0x395c, 0x09}, 213 {0x395d, 0x05}, 214 {0x395e, 0x02}, 215 {0x395f, 0x00}, 216 {0x395f, 0x00}, 217 {0x3960, 0x00}, 218 {0x3961, 0x00}, 219 {0x3962, 0x00}, 220 {0x3963, 0x00}, 221 {0x3964, 0x00}, 222 {0x3965, 0x00}, 223 {0x3966, 0x00}, 224 {0x3967, 0x00}, 225 {0x3968, 0x01}, 226 {0x3969, 0x01}, 227 {0x396a, 0x01}, 228 {0x396b, 0x01}, 229 {0x396c, 0x10}, 230 {0x396d, 0xf0}, 231 {0x396e, 0x11}, 232 {0x396f, 0x00}, 233 {0x3970, 0x37}, 234 {0x3971, 0x37}, 235 {0x3972, 0x37}, 236 {0x3973, 0x37}, 237 {0x3974, 0x00}, 238 {0x3975, 0x3c}, 239 {0x3976, 0x3c}, 240 {0x3977, 0x3c}, 241 {0x3978, 0x3c}, 242 {0x3c00, 0x0f}, 243 {0x3c20, 0x01}, 244 {0x3c21, 0x08}, 245 {0x3f00, 0x8b}, 246 {0x3f02, 0x0f}, 247 {0x4000, 0xc3}, 248 {0x4001, 0xe0}, 249 {0x4002, 0x00}, 250 {0x4003, 0x40}, 251 {0x4008, 0x04}, 252 {0x4009, 0x23}, 253 {0x400a, 0x04}, 254 {0x400b, 0x01}, 255 {0x4077, 0x06}, 256 {0x4078, 0x00}, 257 {0x4079, 0x1a}, 258 {0x407a, 0x7f}, 259 {0x407b, 0x01}, 260 {0x4080, 0x03}, 261 {0x4081, 0x84}, 262 {0x4308, 0x03}, 263 {0x4309, 0xff}, 264 {0x430d, 0x00}, 265 {0x4806, 0x00}, 266 {0x4813, 0x00}, 267 {0x4837, 0x10}, 268 {0x4857, 0x05}, 269 {0x4500, 0x07}, 270 {0x4501, 0x00}, 271 {0x4503, 0x00}, 272 {0x450a, 0x04}, 273 {0x450e, 0x00}, 274 {0x450f, 0x00}, 275 {0x4900, 0x00}, 276 {0x4901, 0x00}, 277 {0x4902, 0x01}, 278 {0x5001, 0x50}, 279 {0x5006, 0x00}, 280 {0x5080, 0x40}, 281 {0x5181, 0x2b}, 282 {0x5202, 0xa3}, 283 {0x5206, 0x01}, 284 {0x5207, 0x00}, 285 {0x520a, 0x01}, 286 {0x520b, 0x00}, 287 {0x365d, 0x00}, 288 {0x4815, 0x40}, 289 {0x4816, 0x12}, 290 {0x4f00, 0x01}, 291 }; 292 293 static const struct reg_sequence sensor_1928x1092_30fps_1lane_setting[] = { 294 {0x301b, 0xd2}, 295 {0x3027, 0xe1}, 296 {0x380c, 0x08}, 297 {0x380d, 0xe8}, 298 {0x380e, 0x04}, 299 {0x380f, 0x8c}, 300 {0x394e, 0x0b}, 301 {0x4800, 0x24}, 302 {0x5000, 0xf5}, 303 /* plls */ 304 {0x0303, 0x05}, 305 {0x0305, 0x90}, 306 {0x0316, 0x90}, 307 {0x3016, 0x12}, 308 }; 309 310 static const struct reg_sequence sensor_1928x1092_30fps_2lane_setting[] = { 311 {0x301b, 0xf0}, 312 {0x3027, 0xf1}, 313 {0x380c, 0x04}, 314 {0x380d, 0x74}, 315 {0x380e, 0x09}, 316 {0x380f, 0x18}, 317 {0x394e, 0x0a}, 318 {0x4041, 0x20}, 319 {0x4884, 0x04}, 320 {0x4800, 0x64}, 321 {0x4d00, 0x03}, 322 {0x4d01, 0xd8}, 323 {0x4d02, 0xba}, 324 {0x4d03, 0xa0}, 325 {0x4d04, 0xb7}, 326 {0x4d05, 0x34}, 327 {0x4d0d, 0x00}, 328 {0x5000, 0xfd}, 329 {0x481f, 0x30}, 330 /* plls */ 331 {0x0303, 0x05}, 332 {0x0305, 0x90}, 333 {0x0316, 0x90}, 334 {0x3016, 0x32}, 335 }; 336 337 static const char * const ov02c10_test_pattern_menu[] = { 338 "Disabled", 339 "Color Bar", 340 "Top-Bottom Darker Color Bar", 341 "Right-Left Darker Color Bar", 342 "Color Bar type 4", 343 }; 344 345 static const s64 link_freq_menu_items[] = { 346 OV02C10_LINK_FREQ_400MHZ, 347 }; 348 349 static const struct ov02c10_mode supported_modes[] = { 350 { 351 .width = 1928, 352 .height = 1092, 353 .hts = 2280, 354 .vts_min = 1164, 355 .reg_sequence = sensor_1928x1092_30fps_setting, 356 .sequence_length = ARRAY_SIZE(sensor_1928x1092_30fps_setting), 357 .lane_settings = { 358 sensor_1928x1092_30fps_1lane_setting, 359 sensor_1928x1092_30fps_2lane_setting 360 }, 361 .lane_settings_length = { 362 ARRAY_SIZE(sensor_1928x1092_30fps_1lane_setting), 363 ARRAY_SIZE(sensor_1928x1092_30fps_2lane_setting), 364 }, 365 }, 366 }; 367 368 static const char * const ov02c10_supply_names[] = { 369 "dovdd", /* Digital I/O power */ 370 "avdd", /* Analog power */ 371 "dvdd", /* Digital core power */ 372 }; 373 374 struct ov02c10 { 375 struct device *dev; 376 377 struct v4l2_subdev sd; 378 struct media_pad pad; 379 struct v4l2_ctrl_handler ctrl_handler; 380 struct regmap *regmap; 381 382 /* V4L2 Controls */ 383 struct v4l2_ctrl *link_freq; 384 struct v4l2_ctrl *pixel_rate; 385 struct v4l2_ctrl *vblank; 386 struct v4l2_ctrl *hblank; 387 struct v4l2_ctrl *exposure; 388 struct v4l2_ctrl *hflip; 389 struct v4l2_ctrl *vflip; 390 391 struct clk *img_clk; 392 struct gpio_desc *reset; 393 struct regulator_bulk_data supplies[ARRAY_SIZE(ov02c10_supply_names)]; 394 395 /* MIPI lane info */ 396 u32 link_freq_index; 397 u8 mipi_lanes; 398 }; 399 400 static inline struct ov02c10 *to_ov02c10(struct v4l2_subdev *subdev) 401 { 402 return container_of(subdev, struct ov02c10, sd); 403 } 404 405 static int ov02c10_test_pattern(struct ov02c10 *ov02c10, int pattern) 406 { 407 int ret = 0; 408 409 if (!pattern) 410 return cci_update_bits(ov02c10->regmap, OV02C10_REG_TEST_PATTERN, 411 BIT(7), 0, NULL); 412 413 cci_update_bits(ov02c10->regmap, OV02C10_REG_TEST_PATTERN, 414 0x03, pattern - 1, &ret); 415 cci_update_bits(ov02c10->regmap, OV02C10_REG_TEST_PATTERN, 416 BIT(7), OV02C10_TEST_PATTERN_ENABLE, &ret); 417 return ret; 418 } 419 420 static int ov02c10_set_ctrl(struct v4l2_ctrl *ctrl) 421 { 422 struct ov02c10 *ov02c10 = container_of(ctrl->handler, 423 struct ov02c10, ctrl_handler); 424 const u32 height = supported_modes[0].height; 425 s64 exposure_max; 426 int ret = 0; 427 428 /* Propagate change of current control to all related controls */ 429 if (ctrl->id == V4L2_CID_VBLANK) { 430 /* Update max exposure while meeting expected vblanking */ 431 exposure_max = height + ctrl->val - OV02C10_EXPOSURE_MAX_MARGIN; 432 __v4l2_ctrl_modify_range(ov02c10->exposure, 433 ov02c10->exposure->minimum, 434 exposure_max, ov02c10->exposure->step, 435 exposure_max); 436 } 437 438 /* V4L2 controls values will be applied only when power is already up */ 439 if (!pm_runtime_get_if_in_use(ov02c10->dev)) 440 return 0; 441 442 switch (ctrl->id) { 443 case V4L2_CID_ANALOGUE_GAIN: 444 cci_write(ov02c10->regmap, OV02C10_REG_ANALOG_GAIN, 445 ctrl->val << 4, &ret); 446 break; 447 448 case V4L2_CID_DIGITAL_GAIN: 449 cci_write(ov02c10->regmap, OV02C10_REG_DIGITAL_GAIN, 450 ctrl->val << 6, &ret); 451 break; 452 453 case V4L2_CID_EXPOSURE: 454 cci_write(ov02c10->regmap, OV02C10_REG_EXPOSURE, 455 ctrl->val, &ret); 456 break; 457 458 case V4L2_CID_VBLANK: 459 cci_write(ov02c10->regmap, OV02C10_REG_VTS, height + ctrl->val, 460 &ret); 461 break; 462 463 case V4L2_CID_TEST_PATTERN: 464 ret = ov02c10_test_pattern(ov02c10, ctrl->val); 465 break; 466 467 case V4L2_CID_HFLIP: 468 cci_update_bits(ov02c10->regmap, OV02C10_ROTATE_CONTROL, 469 BIT(3), ov02c10->hflip->val << 3, &ret); 470 break; 471 472 case V4L2_CID_VFLIP: 473 cci_update_bits(ov02c10->regmap, OV02C10_ROTATE_CONTROL, 474 BIT(4), ov02c10->vflip->val << 4, &ret); 475 break; 476 477 default: 478 ret = -EINVAL; 479 break; 480 } 481 482 pm_runtime_put(ov02c10->dev); 483 484 return ret; 485 } 486 487 static const struct v4l2_ctrl_ops ov02c10_ctrl_ops = { 488 .s_ctrl = ov02c10_set_ctrl, 489 }; 490 491 static int ov02c10_init_controls(struct ov02c10 *ov02c10) 492 { 493 struct v4l2_ctrl_handler *ctrl_hdlr = &ov02c10->ctrl_handler; 494 const struct ov02c10_mode *mode = &supported_modes[0]; 495 u32 vblank_min, vblank_max, vblank_default, vts_def; 496 struct v4l2_fwnode_device_properties props; 497 s64 exposure_max, h_blank, pixel_rate; 498 int ret; 499 500 v4l2_ctrl_handler_init(ctrl_hdlr, 12); 501 502 ov02c10->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, 503 &ov02c10_ctrl_ops, 504 V4L2_CID_LINK_FREQ, 505 ov02c10->link_freq_index, 0, 506 link_freq_menu_items); 507 if (ov02c10->link_freq) 508 ov02c10->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 509 510 /* MIPI lanes are DDR -> use link-freq * 2 */ 511 pixel_rate = div_u64(link_freq_menu_items[ov02c10->link_freq_index] * 512 2 * ov02c10->mipi_lanes, OV02C10_RGB_DEPTH); 513 514 ov02c10->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops, 515 V4L2_CID_PIXEL_RATE, 0, 516 pixel_rate, 1, pixel_rate); 517 518 /* 519 * For default multiple min by number of lanes to keep the default 520 * FPS the same indepenedent of the lane count. 521 */ 522 vts_def = mode->vts_min * ov02c10->mipi_lanes; 523 524 vblank_min = mode->vts_min - mode->height; 525 vblank_max = OV02C10_VTS_MAX - mode->height; 526 vblank_default = vts_def - mode->height; 527 ov02c10->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops, 528 V4L2_CID_VBLANK, vblank_min, 529 vblank_max, 1, vblank_default); 530 531 h_blank = mode->hts - mode->width; 532 ov02c10->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops, 533 V4L2_CID_HBLANK, h_blank, h_blank, 534 1, h_blank); 535 if (ov02c10->hblank) 536 ov02c10->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 537 538 v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 539 OV02C10_ANAL_GAIN_MIN, OV02C10_ANAL_GAIN_MAX, 540 OV02C10_ANAL_GAIN_STEP, OV02C10_ANAL_GAIN_DEFAULT); 541 v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops, V4L2_CID_DIGITAL_GAIN, 542 OV02C10_DGTL_GAIN_MIN, OV02C10_DGTL_GAIN_MAX, 543 OV02C10_DGTL_GAIN_STEP, OV02C10_DGTL_GAIN_DEFAULT); 544 exposure_max = vts_def - OV02C10_EXPOSURE_MAX_MARGIN; 545 ov02c10->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops, 546 V4L2_CID_EXPOSURE, 547 OV02C10_EXPOSURE_MIN, 548 exposure_max, 549 OV02C10_EXPOSURE_STEP, 550 exposure_max); 551 552 ov02c10->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops, 553 V4L2_CID_HFLIP, 0, 1, 1, 0); 554 if (ov02c10->hflip) 555 ov02c10->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; 556 557 ov02c10->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops, 558 V4L2_CID_VFLIP, 0, 1, 1, 0); 559 if (ov02c10->vflip) 560 ov02c10->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; 561 562 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov02c10_ctrl_ops, 563 V4L2_CID_TEST_PATTERN, 564 ARRAY_SIZE(ov02c10_test_pattern_menu) - 1, 565 0, 0, ov02c10_test_pattern_menu); 566 567 ret = v4l2_fwnode_device_parse(ov02c10->dev, &props); 568 if (ret) 569 return ret; 570 571 v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &ov02c10_ctrl_ops, &props); 572 573 if (ctrl_hdlr->error) 574 return ctrl_hdlr->error; 575 576 ov02c10->sd.ctrl_handler = ctrl_hdlr; 577 578 return 0; 579 } 580 581 static void ov02c10_update_pad_format(const struct ov02c10_mode *mode, 582 struct v4l2_mbus_framefmt *fmt) 583 { 584 fmt->width = mode->width; 585 fmt->height = mode->height; 586 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; 587 fmt->field = V4L2_FIELD_NONE; 588 } 589 590 static int ov02c10_enable_streams(struct v4l2_subdev *sd, 591 struct v4l2_subdev_state *state, 592 u32 pad, u64 streams_mask) 593 { 594 const struct ov02c10_mode *mode = &supported_modes[0]; 595 struct ov02c10 *ov02c10 = to_ov02c10(sd); 596 const struct reg_sequence *reg_sequence; 597 int ret, sequence_length; 598 599 ret = pm_runtime_resume_and_get(ov02c10->dev); 600 if (ret) 601 return ret; 602 603 reg_sequence = mode->reg_sequence; 604 sequence_length = mode->sequence_length; 605 ret = regmap_multi_reg_write(ov02c10->regmap, 606 reg_sequence, sequence_length); 607 if (ret) { 608 dev_err(ov02c10->dev, "failed to set mode\n"); 609 goto out; 610 } 611 612 reg_sequence = mode->lane_settings[ov02c10->mipi_lanes - 1]; 613 sequence_length = mode->lane_settings_length[ov02c10->mipi_lanes - 1]; 614 ret = regmap_multi_reg_write(ov02c10->regmap, 615 reg_sequence, sequence_length); 616 if (ret) { 617 dev_err(ov02c10->dev, "failed to write lane settings\n"); 618 goto out; 619 } 620 621 ret = __v4l2_ctrl_handler_setup(ov02c10->sd.ctrl_handler); 622 if (ret) 623 goto out; 624 625 ret = cci_write(ov02c10->regmap, OV02C10_REG_STREAM_CONTROL, 1, NULL); 626 out: 627 if (ret) 628 pm_runtime_put(ov02c10->dev); 629 630 return ret; 631 } 632 633 static int ov02c10_disable_streams(struct v4l2_subdev *sd, 634 struct v4l2_subdev_state *state, 635 u32 pad, u64 streams_mask) 636 { 637 struct ov02c10 *ov02c10 = to_ov02c10(sd); 638 639 cci_write(ov02c10->regmap, OV02C10_REG_STREAM_CONTROL, 0, NULL); 640 pm_runtime_put(ov02c10->dev); 641 642 return 0; 643 } 644 645 /* This function tries to get power control resources */ 646 static int ov02c10_get_pm_resources(struct device *dev) 647 { 648 struct v4l2_subdev *sd = dev_get_drvdata(dev); 649 struct ov02c10 *ov02c10 = to_ov02c10(sd); 650 int i; 651 652 ov02c10->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 653 if (IS_ERR(ov02c10->reset)) 654 return dev_err_probe(dev, PTR_ERR(ov02c10->reset), 655 "failed to get reset gpio\n"); 656 657 for (i = 0; i < ARRAY_SIZE(ov02c10_supply_names); i++) 658 ov02c10->supplies[i].supply = ov02c10_supply_names[i]; 659 660 return devm_regulator_bulk_get(dev, ARRAY_SIZE(ov02c10_supply_names), 661 ov02c10->supplies); 662 } 663 664 static int ov02c10_power_off(struct device *dev) 665 { 666 struct v4l2_subdev *sd = dev_get_drvdata(dev); 667 struct ov02c10 *ov02c10 = to_ov02c10(sd); 668 669 gpiod_set_value_cansleep(ov02c10->reset, 1); 670 671 regulator_bulk_disable(ARRAY_SIZE(ov02c10_supply_names), 672 ov02c10->supplies); 673 674 clk_disable_unprepare(ov02c10->img_clk); 675 676 return 0; 677 } 678 679 static int ov02c10_power_on(struct device *dev) 680 { 681 struct v4l2_subdev *sd = dev_get_drvdata(dev); 682 struct ov02c10 *ov02c10 = to_ov02c10(sd); 683 int ret; 684 685 ret = clk_prepare_enable(ov02c10->img_clk); 686 if (ret < 0) { 687 dev_err(dev, "failed to enable imaging clock: %d", ret); 688 return ret; 689 } 690 691 ret = regulator_bulk_enable(ARRAY_SIZE(ov02c10_supply_names), 692 ov02c10->supplies); 693 if (ret < 0) { 694 dev_err(dev, "failed to enable regulators: %d", ret); 695 clk_disable_unprepare(ov02c10->img_clk); 696 return ret; 697 } 698 699 if (ov02c10->reset) { 700 /* Assert reset for at least 2ms on back to back off-on */ 701 usleep_range(2000, 2200); 702 gpiod_set_value_cansleep(ov02c10->reset, 0); 703 usleep_range(5000, 5100); 704 } 705 706 return 0; 707 } 708 709 static int ov02c10_set_format(struct v4l2_subdev *sd, 710 struct v4l2_subdev_state *sd_state, 711 struct v4l2_subdev_format *fmt) 712 { 713 const struct ov02c10_mode *mode = &supported_modes[0]; 714 struct ov02c10 *ov02c10 = to_ov02c10(sd); 715 s32 vblank_def, h_blank; 716 717 ov02c10_update_pad_format(mode, &fmt->format); 718 *v4l2_subdev_state_get_format(sd_state, fmt->pad) = fmt->format; 719 720 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) 721 return 0; 722 723 /* Update limits and set FPS to default */ 724 vblank_def = mode->vts_min * ov02c10->mipi_lanes - mode->height; 725 __v4l2_ctrl_modify_range(ov02c10->vblank, mode->vts_min - mode->height, 726 OV02C10_VTS_MAX - mode->height, 1, vblank_def); 727 __v4l2_ctrl_s_ctrl(ov02c10->vblank, vblank_def); 728 h_blank = mode->hts - mode->width; 729 __v4l2_ctrl_modify_range(ov02c10->hblank, h_blank, h_blank, 1, h_blank); 730 731 return 0; 732 } 733 734 static int ov02c10_enum_mbus_code(struct v4l2_subdev *sd, 735 struct v4l2_subdev_state *sd_state, 736 struct v4l2_subdev_mbus_code_enum *code) 737 { 738 if (code->index > 0) 739 return -EINVAL; 740 741 code->code = MEDIA_BUS_FMT_SGRBG10_1X10; 742 743 return 0; 744 } 745 746 static int ov02c10_enum_frame_size(struct v4l2_subdev *sd, 747 struct v4l2_subdev_state *sd_state, 748 struct v4l2_subdev_frame_size_enum *fse) 749 { 750 if (fse->index >= ARRAY_SIZE(supported_modes)) 751 return -EINVAL; 752 753 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10) 754 return -EINVAL; 755 756 fse->min_width = supported_modes[fse->index].width; 757 fse->max_width = fse->min_width; 758 fse->min_height = supported_modes[fse->index].height; 759 fse->max_height = fse->min_height; 760 761 return 0; 762 } 763 764 static int ov02c10_init_state(struct v4l2_subdev *sd, 765 struct v4l2_subdev_state *sd_state) 766 { 767 ov02c10_update_pad_format(&supported_modes[0], 768 v4l2_subdev_state_get_format(sd_state, 0)); 769 770 return 0; 771 } 772 773 static const struct v4l2_subdev_video_ops ov02c10_video_ops = { 774 .s_stream = v4l2_subdev_s_stream_helper, 775 }; 776 777 static const struct v4l2_subdev_pad_ops ov02c10_pad_ops = { 778 .set_fmt = ov02c10_set_format, 779 .get_fmt = v4l2_subdev_get_fmt, 780 .enum_mbus_code = ov02c10_enum_mbus_code, 781 .enum_frame_size = ov02c10_enum_frame_size, 782 .enable_streams = ov02c10_enable_streams, 783 .disable_streams = ov02c10_disable_streams, 784 }; 785 786 static const struct v4l2_subdev_ops ov02c10_subdev_ops = { 787 .video = &ov02c10_video_ops, 788 .pad = &ov02c10_pad_ops, 789 }; 790 791 static const struct media_entity_operations ov02c10_subdev_entity_ops = { 792 .link_validate = v4l2_subdev_link_validate, 793 }; 794 795 static const struct v4l2_subdev_internal_ops ov02c10_internal_ops = { 796 .init_state = ov02c10_init_state, 797 }; 798 799 static int ov02c10_identify_module(struct ov02c10 *ov02c10) 800 { 801 u64 chip_id; 802 int ret; 803 804 ret = cci_read(ov02c10->regmap, OV02C10_REG_CHIP_ID, &chip_id, NULL); 805 if (ret) 806 return ret; 807 808 if (chip_id != OV02C10_CHIP_ID) { 809 dev_err(ov02c10->dev, "chip id mismatch: %x!=%llx", 810 OV02C10_CHIP_ID, chip_id); 811 return -ENXIO; 812 } 813 814 return 0; 815 } 816 817 static int ov02c10_check_hwcfg(struct ov02c10 *ov02c10) 818 { 819 struct v4l2_fwnode_endpoint bus_cfg = { 820 .bus_type = V4L2_MBUS_CSI2_DPHY 821 }; 822 struct device *dev = ov02c10->dev; 823 struct fwnode_handle *ep, *fwnode = dev_fwnode(dev); 824 unsigned long link_freq_bitmap; 825 int ret; 826 827 /* 828 * Sometimes the fwnode graph is initialized by the bridge driver, 829 * wait for this. 830 */ 831 ep = fwnode_graph_get_endpoint_by_id(fwnode, 0, 0, 0); 832 if (!ep) 833 return dev_err_probe(dev, -EPROBE_DEFER, 834 "waiting for fwnode graph endpoint\n"); 835 836 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); 837 fwnode_handle_put(ep); 838 if (ret) 839 return dev_err_probe(dev, ret, "parsing endpoint failed\n"); 840 841 ret = v4l2_link_freq_to_bitmap(dev, bus_cfg.link_frequencies, 842 bus_cfg.nr_of_link_frequencies, 843 link_freq_menu_items, 844 ARRAY_SIZE(link_freq_menu_items), 845 &link_freq_bitmap); 846 if (ret) 847 goto check_hwcfg_error; 848 849 /* v4l2_link_freq_to_bitmap() guarantees at least 1 bit is set */ 850 ov02c10->link_freq_index = ffs(link_freq_bitmap) - 1; 851 852 if (bus_cfg.bus.mipi_csi2.num_data_lanes != 1 && 853 bus_cfg.bus.mipi_csi2.num_data_lanes != 2) { 854 ret = dev_err_probe(dev, -EINVAL, 855 "number of CSI2 data lanes %u is not supported\n", 856 bus_cfg.bus.mipi_csi2.num_data_lanes); 857 goto check_hwcfg_error; 858 } 859 860 ov02c10->mipi_lanes = bus_cfg.bus.mipi_csi2.num_data_lanes; 861 862 check_hwcfg_error: 863 v4l2_fwnode_endpoint_free(&bus_cfg); 864 return ret; 865 } 866 867 static void ov02c10_remove(struct i2c_client *client) 868 { 869 struct v4l2_subdev *sd = i2c_get_clientdata(client); 870 struct ov02c10 *ov02c10 = to_ov02c10(sd); 871 872 v4l2_async_unregister_subdev(sd); 873 v4l2_subdev_cleanup(sd); 874 media_entity_cleanup(&sd->entity); 875 v4l2_ctrl_handler_free(sd->ctrl_handler); 876 pm_runtime_disable(ov02c10->dev); 877 if (!pm_runtime_status_suspended(ov02c10->dev)) { 878 ov02c10_power_off(ov02c10->dev); 879 pm_runtime_set_suspended(ov02c10->dev); 880 } 881 } 882 883 static int ov02c10_probe(struct i2c_client *client) 884 { 885 struct ov02c10 *ov02c10; 886 unsigned long freq; 887 int ret; 888 889 ov02c10 = devm_kzalloc(&client->dev, sizeof(*ov02c10), GFP_KERNEL); 890 if (!ov02c10) 891 return -ENOMEM; 892 893 ov02c10->dev = &client->dev; 894 895 ov02c10->img_clk = devm_v4l2_sensor_clk_get(ov02c10->dev, NULL); 896 if (IS_ERR(ov02c10->img_clk)) 897 return dev_err_probe(ov02c10->dev, PTR_ERR(ov02c10->img_clk), 898 "failed to get imaging clock\n"); 899 900 freq = clk_get_rate(ov02c10->img_clk); 901 if (freq != OV02C10_MCLK) 902 return dev_err_probe(ov02c10->dev, -EINVAL, 903 "external clock %lu is not supported", 904 freq); 905 906 v4l2_i2c_subdev_init(&ov02c10->sd, client, &ov02c10_subdev_ops); 907 908 /* Check HW config */ 909 ret = ov02c10_check_hwcfg(ov02c10); 910 if (ret) 911 return ret; 912 913 ret = ov02c10_get_pm_resources(ov02c10->dev); 914 if (ret) 915 return ret; 916 917 ov02c10->regmap = devm_cci_regmap_init_i2c(client, 16); 918 if (IS_ERR(ov02c10->regmap)) 919 return PTR_ERR(ov02c10->regmap); 920 921 ret = ov02c10_power_on(ov02c10->dev); 922 if (ret) { 923 dev_err_probe(ov02c10->dev, ret, "failed to power on\n"); 924 return ret; 925 } 926 927 ret = ov02c10_identify_module(ov02c10); 928 if (ret) { 929 dev_err(ov02c10->dev, "failed to find sensor: %d", ret); 930 goto probe_error_power_off; 931 } 932 933 ret = ov02c10_init_controls(ov02c10); 934 if (ret) { 935 dev_err(ov02c10->dev, "failed to init controls: %d", ret); 936 goto probe_error_v4l2_ctrl_handler_free; 937 } 938 939 ov02c10->sd.internal_ops = &ov02c10_internal_ops; 940 ov02c10->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 941 ov02c10->sd.entity.ops = &ov02c10_subdev_entity_ops; 942 ov02c10->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 943 ov02c10->pad.flags = MEDIA_PAD_FL_SOURCE; 944 ret = media_entity_pads_init(&ov02c10->sd.entity, 1, &ov02c10->pad); 945 if (ret) { 946 dev_err(ov02c10->dev, "failed to init entity pads: %d", ret); 947 goto probe_error_v4l2_ctrl_handler_free; 948 } 949 950 ov02c10->sd.state_lock = ov02c10->ctrl_handler.lock; 951 ret = v4l2_subdev_init_finalize(&ov02c10->sd); 952 if (ret < 0) { 953 dev_err(ov02c10->dev, "failed to init subdev: %d", ret); 954 goto probe_error_media_entity_cleanup; 955 } 956 957 pm_runtime_set_active(ov02c10->dev); 958 pm_runtime_enable(ov02c10->dev); 959 960 ret = v4l2_async_register_subdev_sensor(&ov02c10->sd); 961 if (ret < 0) { 962 dev_err(ov02c10->dev, "failed to register V4L2 subdev: %d", 963 ret); 964 goto probe_error_v4l2_subdev_cleanup; 965 } 966 967 pm_runtime_idle(ov02c10->dev); 968 return 0; 969 970 probe_error_v4l2_subdev_cleanup: 971 pm_runtime_disable(ov02c10->dev); 972 pm_runtime_set_suspended(ov02c10->dev); 973 v4l2_subdev_cleanup(&ov02c10->sd); 974 975 probe_error_media_entity_cleanup: 976 media_entity_cleanup(&ov02c10->sd.entity); 977 978 probe_error_v4l2_ctrl_handler_free: 979 v4l2_ctrl_handler_free(ov02c10->sd.ctrl_handler); 980 981 probe_error_power_off: 982 ov02c10_power_off(ov02c10->dev); 983 984 return ret; 985 } 986 987 static DEFINE_RUNTIME_DEV_PM_OPS(ov02c10_pm_ops, ov02c10_power_off, 988 ov02c10_power_on, NULL); 989 990 #ifdef CONFIG_ACPI 991 static const struct acpi_device_id ov02c10_acpi_ids[] = { 992 { "OVTI02C1" }, 993 { /* sentinel */ } 994 }; 995 996 MODULE_DEVICE_TABLE(acpi, ov02c10_acpi_ids); 997 #endif 998 999 static const struct of_device_id ov02c10_of_match[] = { 1000 { .compatible = "ovti,ov02c10" }, 1001 { /* sentinel */ } 1002 }; 1003 MODULE_DEVICE_TABLE(of, ov02c10_of_match); 1004 1005 static struct i2c_driver ov02c10_i2c_driver = { 1006 .driver = { 1007 .name = "ov02c10", 1008 .pm = pm_sleep_ptr(&ov02c10_pm_ops), 1009 .acpi_match_table = ACPI_PTR(ov02c10_acpi_ids), 1010 .of_match_table = ov02c10_of_match, 1011 }, 1012 .probe = ov02c10_probe, 1013 .remove = ov02c10_remove, 1014 }; 1015 1016 module_i2c_driver(ov02c10_i2c_driver); 1017 1018 MODULE_AUTHOR("Hao Yao <hao.yao@intel.com>"); 1019 MODULE_AUTHOR("Heimir Thor Sverrisson <heimir.sverrisson@gmail.com>"); 1020 MODULE_AUTHOR("Hans de Goede <hansg@kernel.org>"); 1021 MODULE_DESCRIPTION("OmniVision OV02C10 sensor driver"); 1022 MODULE_LICENSE("GPL"); 1023