1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2023 Intel Corporation. 4 */ 5 6 #include <linux/unaligned.h> 7 8 #include <linux/acpi.h> 9 #include <linux/bitfield.h> 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/gpio/consumer.h> 13 #include <linux/i2c.h> 14 #include <linux/module.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 #include <linux/regulator/consumer.h> 18 19 #include <media/v4l2-cci.h> 20 #include <media/v4l2-ctrls.h> 21 #include <media/v4l2-device.h> 22 #include <media/v4l2-fwnode.h> 23 24 #define OV01A10_LINK_FREQ_400MHZ 400000000ULL 25 #define OV01A10_SCLK 80000000LL 26 #define OV01A10_DATA_LANES 1 27 #define OV01A10_MCLK 19200000 28 29 #define OV01A10_REG_CHIP_ID CCI_REG24(0x300a) 30 #define OV01A10_CHIP_ID 0x560141 31 32 #define OV01A10_REG_MODE_SELECT CCI_REG8(0x0100) 33 #define OV01A10_MODE_STANDBY 0x00 34 #define OV01A10_MODE_STREAMING 0x01 35 36 /* pixel array */ 37 #define OV01A10_NATIVE_WIDTH 1296 38 #define OV01A10_NATIVE_HEIGHT 816 39 #define OV01A10_DEFAULT_WIDTH 1280 40 #define OV01A10_DEFAULT_HEIGHT 800 41 42 /* vertical and horizontal timings */ 43 #define OV01A10_VTS_DEF 0x0700 44 #define OV01A10_VTS_MIN 0x0380 45 #define OV01A10_VTS_MAX 0xffff 46 #define OV01A10_HTS_DEF 1488 47 48 /* exposure controls */ 49 #define OV01A10_REG_EXPOSURE CCI_REG16(0x3501) 50 #define OV01A10_EXPOSURE_MIN 4 51 #define OV01A10_EXPOSURE_MAX_MARGIN 8 52 #define OV01A10_EXPOSURE_STEP 1 53 54 /* analog gain controls */ 55 #define OV01A10_REG_ANALOG_GAIN CCI_REG16(0x3508) 56 #define OV01A10_ANAL_GAIN_MIN 0x100 57 #define OV01A10_ANAL_GAIN_MAX 0x3fff 58 #define OV01A10_ANAL_GAIN_STEP 1 59 60 /* digital gain controls */ 61 #define OV01A10_REG_DIGITAL_GAIN_B CCI_REG24(0x350a) 62 #define OV01A10_REG_DIGITAL_GAIN_GB CCI_REG24(0x3510) 63 #define OV01A10_REG_DIGITAL_GAIN_GR CCI_REG24(0x3513) 64 #define OV01A10_REG_DIGITAL_GAIN_R CCI_REG24(0x3516) 65 #define OV01A10_DGTL_GAIN_MIN 0 66 #define OV01A10_DGTL_GAIN_MAX 0x3fff 67 #define OV01A10_DGTL_GAIN_STEP 1 68 #define OV01A10_DGTL_GAIN_DEFAULT 1024 69 70 /* timing control */ 71 #define OV01A10_REG_X_ADDR_START CCI_REG16(0x3800) 72 #define OV01A10_REG_Y_ADDR_START CCI_REG16(0x3802) 73 #define OV01A10_REG_X_ADDR_END CCI_REG16(0x3804) 74 #define OV01A10_REG_Y_ADDR_END CCI_REG16(0x3806) 75 #define OV01A10_REG_X_OUTPUT_SIZE CCI_REG16(0x3808) 76 #define OV01A10_REG_Y_OUTPUT_SIZE CCI_REG16(0x380a) 77 #define OV01A10_REG_HTS CCI_REG16(0x380c) /* in units of 2 pixels */ 78 #define OV01A10_REG_VTS CCI_REG16(0x380e) 79 #define OV01A10_REG_X_WIN CCI_REG16(0x3810) 80 #define OV01A10_REG_Y_WIN CCI_REG16(0x3812) 81 82 /* flip and mirror control */ 83 #define OV01A10_REG_FORMAT1 CCI_REG8(0x3820) 84 #define OV01A10_VFLIP_MASK BIT(4) 85 #define OV01A10_HFLIP_MASK BIT(3) 86 87 /* test pattern control */ 88 #define OV01A10_REG_TEST_PATTERN CCI_REG8(0x4503) 89 #define OV01A10_TEST_PATTERN_ENABLE BIT(7) 90 91 struct ov01a10_link_freq_config { 92 const struct reg_sequence *regs; 93 int regs_len; 94 }; 95 96 static const struct reg_sequence mipi_data_rate_720mbps[] = { 97 {0x0103, 0x01}, 98 {0x0302, 0x00}, 99 {0x0303, 0x06}, 100 {0x0304, 0x01}, 101 {0x0305, 0xf4}, 102 {0x0306, 0x00}, 103 {0x0308, 0x01}, 104 {0x0309, 0x00}, 105 {0x030c, 0x01}, 106 {0x0322, 0x01}, 107 {0x0323, 0x06}, 108 {0x0324, 0x01}, 109 {0x0325, 0x68}, 110 }; 111 112 static const struct reg_sequence ov01a10_global_setting[] = { 113 {0x3002, 0xa1}, 114 {0x301e, 0xf0}, 115 {0x3022, 0x01}, 116 {0x3504, 0x0c}, 117 {0x3601, 0xc0}, 118 {0x3603, 0x71}, 119 {0x3610, 0x68}, 120 {0x3611, 0x86}, 121 {0x3640, 0x10}, 122 {0x3641, 0x80}, 123 {0x3642, 0xdc}, 124 {0x3646, 0x55}, 125 {0x3647, 0x57}, 126 {0x364b, 0x00}, 127 {0x3653, 0x10}, 128 {0x3655, 0x00}, 129 {0x3656, 0x00}, 130 {0x365f, 0x0f}, 131 {0x3661, 0x45}, 132 {0x3662, 0x24}, 133 {0x3663, 0x11}, 134 {0x3664, 0x07}, 135 {0x3709, 0x34}, 136 {0x370b, 0x6f}, 137 {0x3714, 0x22}, 138 {0x371b, 0x27}, 139 {0x371c, 0x67}, 140 {0x371d, 0xa7}, 141 {0x371e, 0xe7}, 142 {0x3730, 0x81}, 143 {0x3733, 0x10}, 144 {0x3734, 0x40}, 145 {0x3737, 0x04}, 146 {0x3739, 0x1c}, 147 {0x3767, 0x00}, 148 {0x376c, 0x81}, 149 {0x3772, 0x14}, 150 {0x37c2, 0x04}, 151 {0x37d8, 0x03}, 152 {0x37d9, 0x0c}, 153 {0x37e0, 0x00}, 154 {0x37e1, 0x08}, 155 {0x37e2, 0x10}, 156 {0x37e3, 0x04}, 157 {0x37e4, 0x04}, 158 {0x37e5, 0x03}, 159 {0x37e6, 0x04}, 160 {0x3814, 0x01}, 161 {0x3815, 0x01}, 162 {0x3816, 0x01}, 163 {0x3817, 0x01}, 164 {0x3822, 0x13}, 165 {0x3832, 0x28}, 166 {0x3833, 0x10}, 167 {0x3b00, 0x00}, 168 {0x3c80, 0x00}, 169 {0x3c88, 0x02}, 170 {0x3c8c, 0x07}, 171 {0x3c8d, 0x40}, 172 {0x3cc7, 0x80}, 173 {0x4000, 0xc3}, 174 {0x4001, 0xe0}, 175 {0x4003, 0x40}, 176 {0x4008, 0x02}, 177 {0x4009, 0x19}, 178 {0x400a, 0x01}, 179 {0x400b, 0x6c}, 180 {0x4011, 0x00}, 181 {0x4041, 0x00}, 182 {0x4300, 0xff}, 183 {0x4301, 0x00}, 184 {0x4302, 0x0f}, 185 {0x4601, 0x50}, 186 {0x4800, 0x64}, 187 {0x481f, 0x34}, 188 {0x4825, 0x33}, 189 {0x4837, 0x11}, 190 {0x4881, 0x40}, 191 {0x4883, 0x01}, 192 {0x4890, 0x00}, 193 {0x4901, 0x00}, 194 {0x4902, 0x00}, 195 {0x4b00, 0x2a}, 196 {0x4b0d, 0x00}, 197 {0x450a, 0x04}, 198 {0x450b, 0x00}, 199 {0x5000, 0x65}, 200 {0x5200, 0x18}, 201 {0x5004, 0x00}, 202 {0x5080, 0x40}, 203 {0x0325, 0xc2}, 204 }; 205 206 static const char * const ov01a10_test_pattern_menu[] = { 207 "Disabled", 208 "Color Bar", 209 "Left-Right Darker Color Bar", 210 "Bottom-Top Darker Color Bar", 211 }; 212 213 static const s64 link_freq_menu_items[] = { 214 OV01A10_LINK_FREQ_400MHZ, 215 }; 216 217 static const struct ov01a10_link_freq_config link_freq_configs[] = { 218 { 219 .regs = mipi_data_rate_720mbps, 220 .regs_len = ARRAY_SIZE(mipi_data_rate_720mbps), 221 }, 222 }; 223 224 static const struct v4l2_rect ov01a10_default_crop = { 225 .left = (OV01A10_NATIVE_WIDTH - OV01A10_DEFAULT_WIDTH) / 2, 226 .top = (OV01A10_NATIVE_HEIGHT - OV01A10_DEFAULT_HEIGHT) / 2, 227 .width = OV01A10_DEFAULT_WIDTH, 228 .height = OV01A10_DEFAULT_HEIGHT, 229 }; 230 231 static const char * const ov01a10_supply_names[] = { 232 "dovdd", /* Digital I/O power */ 233 "avdd", /* Analog power */ 234 "dvdd", /* Digital core power */ 235 }; 236 237 struct ov01a10_sensor_cfg { 238 const char *model; 239 u32 bus_fmt; 240 int pattern_size; 241 int border_size; 242 u8 format1_base_val; 243 bool invert_hflip_shift; 244 bool invert_vflip_shift; 245 }; 246 247 struct ov01a10 { 248 struct device *dev; 249 struct regmap *regmap; 250 const struct ov01a10_sensor_cfg *cfg; 251 struct v4l2_subdev sd; 252 struct media_pad pad; 253 struct v4l2_ctrl_handler ctrl_handler; 254 255 /* v4l2 controls */ 256 struct v4l2_ctrl *link_freq; 257 struct v4l2_ctrl *pixel_rate; 258 struct v4l2_ctrl *vblank; 259 struct v4l2_ctrl *hblank; 260 struct v4l2_ctrl *exposure; 261 struct v4l2_ctrl *hflip; 262 struct v4l2_ctrl *vflip; 263 264 u32 link_freq_index; 265 266 struct clk *clk; 267 struct gpio_desc *reset; 268 struct gpio_desc *powerdown; 269 struct regulator_bulk_data supplies[ARRAY_SIZE(ov01a10_supply_names)]; 270 }; 271 272 static inline struct ov01a10 *to_ov01a10(struct v4l2_subdev *subdev) 273 { 274 return container_of(subdev, struct ov01a10, sd); 275 } 276 277 static struct v4l2_mbus_framefmt *ov01a10_get_active_format(struct ov01a10 *ov01a10) 278 { 279 struct v4l2_subdev_state *active_state = 280 v4l2_subdev_get_locked_active_state(&ov01a10->sd); 281 282 return v4l2_subdev_state_get_format(active_state, 0); 283 } 284 285 static struct v4l2_rect *ov01a10_get_active_crop(struct ov01a10 *ov01a10) 286 { 287 struct v4l2_subdev_state *active_state = 288 v4l2_subdev_get_locked_active_state(&ov01a10->sd); 289 290 return v4l2_subdev_state_get_crop(active_state, 0); 291 } 292 293 static int ov01a10_update_digital_gain(struct ov01a10 *ov01a10, u32 d_gain) 294 { 295 u32 real = d_gain << 6; 296 int ret = 0; 297 298 cci_write(ov01a10->regmap, OV01A10_REG_DIGITAL_GAIN_B, real, &ret); 299 cci_write(ov01a10->regmap, OV01A10_REG_DIGITAL_GAIN_GB, real, &ret); 300 cci_write(ov01a10->regmap, OV01A10_REG_DIGITAL_GAIN_GR, real, &ret); 301 cci_write(ov01a10->regmap, OV01A10_REG_DIGITAL_GAIN_R, real, &ret); 302 303 return ret; 304 } 305 306 static int ov01a10_test_pattern(struct ov01a10 *ov01a10, u32 pattern) 307 { 308 if (pattern) 309 pattern |= OV01A10_TEST_PATTERN_ENABLE; 310 311 return cci_write(ov01a10->regmap, OV01A10_REG_TEST_PATTERN, pattern, 312 NULL); 313 } 314 315 static void ov01a10_set_format1(struct ov01a10 *ov01a10, int *ret) 316 { 317 u8 val = ov01a10->cfg->format1_base_val; 318 319 /* hflip register bit is inverted */ 320 if (!ov01a10->hflip->val) 321 val |= FIELD_PREP(OV01A10_HFLIP_MASK, 0x1); 322 323 if (ov01a10->vflip->val) 324 val |= FIELD_PREP(OV01A10_VFLIP_MASK, 0x1); 325 326 cci_write(ov01a10->regmap, OV01A10_REG_FORMAT1, val, ret); 327 } 328 329 static int ov01a10_set_hflip(struct ov01a10 *ov01a10, bool hflip) 330 { 331 struct v4l2_rect *crop = ov01a10_get_active_crop(ov01a10); 332 const struct ov01a10_sensor_cfg *cfg = ov01a10->cfg; 333 u32 offset; 334 int ret = 0; 335 336 offset = crop->left; 337 if ((hflip ^ cfg->invert_hflip_shift) && cfg->border_size) 338 offset++; 339 340 cci_write(ov01a10->regmap, OV01A10_REG_X_WIN, offset, &ret); 341 ov01a10_set_format1(ov01a10, &ret); 342 343 return ret; 344 } 345 346 static int ov01a10_set_vflip(struct ov01a10 *ov01a10, bool vflip) 347 { 348 struct v4l2_rect *crop = ov01a10_get_active_crop(ov01a10); 349 const struct ov01a10_sensor_cfg *cfg = ov01a10->cfg; 350 u32 offset; 351 int ret = 0; 352 353 offset = crop->top; 354 if ((vflip ^ cfg->invert_vflip_shift) && cfg->border_size) 355 offset++; 356 357 cci_write(ov01a10->regmap, OV01A10_REG_Y_WIN, offset, &ret); 358 ov01a10_set_format1(ov01a10, &ret); 359 360 return ret; 361 } 362 363 static int ov01a10_set_ctrl(struct v4l2_ctrl *ctrl) 364 { 365 struct ov01a10 *ov01a10 = container_of(ctrl->handler, 366 struct ov01a10, ctrl_handler); 367 struct v4l2_mbus_framefmt *fmt = ov01a10_get_active_format(ov01a10); 368 s64 exposure_max; 369 int ret = 0; 370 371 if (ctrl->id == V4L2_CID_VBLANK) { 372 exposure_max = fmt->height + ctrl->val - 373 OV01A10_EXPOSURE_MAX_MARGIN; 374 __v4l2_ctrl_modify_range(ov01a10->exposure, 375 OV01A10_EXPOSURE_MIN, exposure_max, 376 OV01A10_EXPOSURE_STEP, exposure_max); 377 } 378 379 if (!pm_runtime_get_if_in_use(ov01a10->dev)) 380 return 0; 381 382 switch (ctrl->id) { 383 case V4L2_CID_ANALOGUE_GAIN: 384 ret = cci_write(ov01a10->regmap, OV01A10_REG_ANALOG_GAIN, 385 ctrl->val, NULL); 386 break; 387 388 case V4L2_CID_DIGITAL_GAIN: 389 ret = ov01a10_update_digital_gain(ov01a10, ctrl->val); 390 break; 391 392 case V4L2_CID_EXPOSURE: 393 ret = cci_write(ov01a10->regmap, OV01A10_REG_EXPOSURE, 394 ctrl->val, NULL); 395 break; 396 397 case V4L2_CID_VBLANK: 398 ret = cci_write(ov01a10->regmap, OV01A10_REG_VTS, 399 fmt->height + ctrl->val, NULL); 400 break; 401 402 case V4L2_CID_TEST_PATTERN: 403 ret = ov01a10_test_pattern(ov01a10, ctrl->val); 404 break; 405 406 case V4L2_CID_HFLIP: 407 ov01a10_set_hflip(ov01a10, ctrl->val); 408 break; 409 410 case V4L2_CID_VFLIP: 411 ov01a10_set_vflip(ov01a10, ctrl->val); 412 break; 413 414 default: 415 ret = -EINVAL; 416 break; 417 } 418 419 pm_runtime_put(ov01a10->dev); 420 421 return ret; 422 } 423 424 static const struct v4l2_ctrl_ops ov01a10_ctrl_ops = { 425 .s_ctrl = ov01a10_set_ctrl, 426 }; 427 428 static int ov01a10_init_controls(struct ov01a10 *ov01a10) 429 { 430 struct v4l2_fwnode_device_properties props; 431 u32 vblank_min, vblank_max, vblank_default; 432 struct v4l2_ctrl_handler *ctrl_hdlr; 433 s64 exposure_max, h_blank; 434 int ret = 0; 435 436 ret = v4l2_fwnode_device_parse(ov01a10->dev, &props); 437 if (ret) 438 return ret; 439 440 ctrl_hdlr = &ov01a10->ctrl_handler; 441 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 12); 442 if (ret) 443 return ret; 444 445 ov01a10->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, 446 &ov01a10_ctrl_ops, 447 V4L2_CID_LINK_FREQ, 448 ov01a10->link_freq_index, 0, 449 link_freq_menu_items); 450 451 ov01a10->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov01a10_ctrl_ops, 452 V4L2_CID_PIXEL_RATE, 0, 453 OV01A10_SCLK, 1, OV01A10_SCLK); 454 455 vblank_min = OV01A10_VTS_MIN - OV01A10_DEFAULT_HEIGHT; 456 vblank_max = OV01A10_VTS_MAX - OV01A10_DEFAULT_HEIGHT; 457 vblank_default = OV01A10_VTS_DEF - OV01A10_DEFAULT_HEIGHT; 458 ov01a10->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov01a10_ctrl_ops, 459 V4L2_CID_VBLANK, vblank_min, 460 vblank_max, 1, vblank_default); 461 462 h_blank = OV01A10_HTS_DEF - OV01A10_DEFAULT_WIDTH; 463 ov01a10->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov01a10_ctrl_ops, 464 V4L2_CID_HBLANK, h_blank, h_blank, 465 1, h_blank); 466 467 v4l2_ctrl_new_std(ctrl_hdlr, &ov01a10_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 468 OV01A10_ANAL_GAIN_MIN, OV01A10_ANAL_GAIN_MAX, 469 OV01A10_ANAL_GAIN_STEP, OV01A10_ANAL_GAIN_MIN); 470 v4l2_ctrl_new_std(ctrl_hdlr, &ov01a10_ctrl_ops, V4L2_CID_DIGITAL_GAIN, 471 OV01A10_DGTL_GAIN_MIN, OV01A10_DGTL_GAIN_MAX, 472 OV01A10_DGTL_GAIN_STEP, OV01A10_DGTL_GAIN_DEFAULT); 473 474 exposure_max = OV01A10_VTS_DEF - OV01A10_EXPOSURE_MAX_MARGIN; 475 ov01a10->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov01a10_ctrl_ops, 476 V4L2_CID_EXPOSURE, 477 OV01A10_EXPOSURE_MIN, 478 exposure_max, 479 OV01A10_EXPOSURE_STEP, 480 exposure_max); 481 482 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov01a10_ctrl_ops, 483 V4L2_CID_TEST_PATTERN, 484 ARRAY_SIZE(ov01a10_test_pattern_menu) - 1, 485 0, 0, ov01a10_test_pattern_menu); 486 487 ov01a10->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &ov01a10_ctrl_ops, 488 V4L2_CID_HFLIP, 0, 1, 1, 0); 489 ov01a10->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &ov01a10_ctrl_ops, 490 V4L2_CID_VFLIP, 0, 1, 1, 0); 491 492 ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &ov01a10_ctrl_ops, 493 &props); 494 if (ret) 495 goto fail; 496 497 if (ctrl_hdlr->error) { 498 ret = ctrl_hdlr->error; 499 goto fail; 500 } 501 502 ov01a10->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 503 ov01a10->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 504 505 ov01a10->sd.ctrl_handler = ctrl_hdlr; 506 507 return 0; 508 fail: 509 v4l2_ctrl_handler_free(ctrl_hdlr); 510 511 return ret; 512 } 513 514 static void ov01a10_fill_format(struct ov01a10 *ov01a10, 515 struct v4l2_mbus_framefmt *fmt, 516 unsigned int width, unsigned int height) 517 { 518 memset(fmt, 0, sizeof(*fmt)); 519 fmt->width = width; 520 fmt->height = height; 521 fmt->code = ov01a10->cfg->bus_fmt; 522 fmt->field = V4L2_FIELD_NONE; 523 fmt->colorspace = V4L2_COLORSPACE_RAW; 524 } 525 526 static int ov01a10_set_mode(struct ov01a10 *ov01a10) 527 { 528 struct v4l2_mbus_framefmt *fmt = ov01a10_get_active_format(ov01a10); 529 int ret = 0; 530 531 cci_write(ov01a10->regmap, OV01A10_REG_X_ADDR_START, 0, &ret); 532 cci_write(ov01a10->regmap, OV01A10_REG_Y_ADDR_START, 0, &ret); 533 cci_write(ov01a10->regmap, OV01A10_REG_X_ADDR_END, 534 OV01A10_NATIVE_WIDTH - 1, &ret); 535 cci_write(ov01a10->regmap, OV01A10_REG_Y_ADDR_END, 536 OV01A10_NATIVE_HEIGHT - 1, &ret); 537 cci_write(ov01a10->regmap, OV01A10_REG_X_OUTPUT_SIZE, 538 fmt->width, &ret); 539 cci_write(ov01a10->regmap, OV01A10_REG_Y_OUTPUT_SIZE, 540 fmt->height, &ret); 541 /* HTS register is in units of 2 pixels */ 542 cci_write(ov01a10->regmap, OV01A10_REG_HTS, 543 OV01A10_HTS_DEF / 2, &ret); 544 /* OV01A10_REG_VTS is set by vblank control */ 545 /* OV01A10_REG_X_WIN is set by hlip control */ 546 /* OV01A10_REG_Y_WIN is set by vflip control */ 547 548 return ret; 549 } 550 551 static int ov01a10_start_streaming(struct ov01a10 *ov01a10) 552 { 553 const struct ov01a10_link_freq_config *freq_cfg; 554 int ret; 555 556 freq_cfg = &link_freq_configs[ov01a10->link_freq_index]; 557 ret = regmap_multi_reg_write(ov01a10->regmap, freq_cfg->regs, 558 freq_cfg->regs_len); 559 if (ret) { 560 dev_err(ov01a10->dev, "failed to set plls\n"); 561 return ret; 562 } 563 564 ret = regmap_multi_reg_write(ov01a10->regmap, ov01a10_global_setting, 565 ARRAY_SIZE(ov01a10_global_setting)); 566 if (ret) { 567 dev_err(ov01a10->dev, "failed to initialize sensor\n"); 568 return ret; 569 } 570 571 ret = ov01a10_set_mode(ov01a10); 572 if (ret) { 573 dev_err(ov01a10->dev, "failed to set mode\n"); 574 return ret; 575 } 576 577 ret = __v4l2_ctrl_handler_setup(ov01a10->sd.ctrl_handler); 578 if (ret) 579 return ret; 580 581 return cci_write(ov01a10->regmap, OV01A10_REG_MODE_SELECT, 582 OV01A10_MODE_STREAMING, NULL); 583 } 584 585 static void ov01a10_stop_streaming(struct ov01a10 *ov01a10) 586 { 587 cci_write(ov01a10->regmap, OV01A10_REG_MODE_SELECT, 588 OV01A10_MODE_STANDBY, NULL); 589 } 590 591 static int ov01a10_set_stream(struct v4l2_subdev *sd, int enable) 592 { 593 struct ov01a10 *ov01a10 = to_ov01a10(sd); 594 struct v4l2_subdev_state *state; 595 int ret = 0; 596 597 state = v4l2_subdev_lock_and_get_active_state(sd); 598 599 if (enable) { 600 ret = pm_runtime_resume_and_get(ov01a10->dev); 601 if (ret < 0) 602 goto unlock; 603 604 ret = ov01a10_start_streaming(ov01a10); 605 if (ret) { 606 pm_runtime_put(ov01a10->dev); 607 goto unlock; 608 } 609 } else { 610 ov01a10_stop_streaming(ov01a10); 611 pm_runtime_put(ov01a10->dev); 612 } 613 614 unlock: 615 v4l2_subdev_unlock_state(state); 616 617 return ret; 618 } 619 620 static void ov01a10_update_blank_ctrls(struct ov01a10 *ov01a10, 621 unsigned int width, unsigned int height) 622 { 623 s32 hblank, vblank_def; 624 625 vblank_def = OV01A10_VTS_DEF - height; 626 __v4l2_ctrl_modify_range(ov01a10->vblank, 627 OV01A10_VTS_MIN - height, 628 OV01A10_VTS_MAX - height, 1, 629 vblank_def); 630 __v4l2_ctrl_s_ctrl(ov01a10->vblank, vblank_def); 631 632 hblank = OV01A10_HTS_DEF - width; 633 __v4l2_ctrl_modify_range(ov01a10->hblank, hblank, hblank, 1, hblank); 634 } 635 636 static int ov01a10_set_format(struct v4l2_subdev *sd, 637 struct v4l2_subdev_state *sd_state, 638 struct v4l2_subdev_format *fmt) 639 { 640 struct v4l2_rect *crop = v4l2_subdev_state_get_crop(sd_state, fmt->pad); 641 struct ov01a10 *ov01a10 = to_ov01a10(sd); 642 const int pattern_size = ov01a10->cfg->pattern_size; 643 const int border_size = ov01a10->cfg->border_size; 644 unsigned int width, height; 645 646 width = clamp_val(ALIGN(fmt->format.width, pattern_size), 647 pattern_size, 648 OV01A10_NATIVE_WIDTH - 2 * border_size); 649 height = clamp_val(ALIGN(fmt->format.height, pattern_size), 650 pattern_size, 651 OV01A10_NATIVE_HEIGHT - 2 * border_size); 652 653 /* Center image for userspace which does not set the crop first */ 654 if (width != crop->width || height != crop->height) { 655 crop->left = ALIGN((OV01A10_NATIVE_WIDTH - width) / 2, 656 pattern_size); 657 crop->top = ALIGN((OV01A10_NATIVE_HEIGHT - height) / 2, 658 pattern_size); 659 crop->width = width; 660 crop->height = height; 661 } 662 663 ov01a10_fill_format(ov01a10, &fmt->format, width, height); 664 *v4l2_subdev_state_get_format(sd_state, fmt->pad) = fmt->format; 665 666 if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) 667 ov01a10_update_blank_ctrls(ov01a10, width, height); 668 669 return 0; 670 } 671 672 static int ov01a10_init_state(struct v4l2_subdev *sd, 673 struct v4l2_subdev_state *sd_state) 674 { 675 struct ov01a10 *ov01a10 = to_ov01a10(sd); 676 677 *v4l2_subdev_state_get_crop(sd_state, 0) = ov01a10_default_crop; 678 ov01a10_fill_format(ov01a10, v4l2_subdev_state_get_format(sd_state, 0), 679 OV01A10_DEFAULT_WIDTH, OV01A10_DEFAULT_HEIGHT); 680 681 return 0; 682 } 683 684 static int ov01a10_enum_mbus_code(struct v4l2_subdev *sd, 685 struct v4l2_subdev_state *sd_state, 686 struct v4l2_subdev_mbus_code_enum *code) 687 { 688 struct ov01a10 *ov01a10 = to_ov01a10(sd); 689 690 if (code->index > 0) 691 return -EINVAL; 692 693 code->code = ov01a10->cfg->bus_fmt; 694 695 return 0; 696 } 697 698 static int ov01a10_enum_frame_size(struct v4l2_subdev *sd, 699 struct v4l2_subdev_state *sd_state, 700 struct v4l2_subdev_frame_size_enum *fse) 701 { 702 struct ov01a10 *ov01a10 = to_ov01a10(sd); 703 const int pattern_size = ov01a10->cfg->pattern_size; 704 const int border_size = ov01a10->cfg->border_size; 705 706 if (fse->index) 707 return -EINVAL; 708 709 fse->min_width = pattern_size; 710 fse->max_width = OV01A10_NATIVE_WIDTH - 2 * border_size; 711 fse->min_height = pattern_size; 712 fse->max_height = OV01A10_NATIVE_HEIGHT - 2 * border_size; 713 714 return 0; 715 } 716 717 static int ov01a10_get_selection(struct v4l2_subdev *sd, 718 struct v4l2_subdev_state *state, 719 struct v4l2_subdev_selection *sel) 720 { 721 struct ov01a10 *ov01a10 = to_ov01a10(sd); 722 const int border_size = ov01a10->cfg->border_size; 723 724 switch (sel->target) { 725 case V4L2_SEL_TGT_CROP: 726 sel->r = *v4l2_subdev_state_get_crop(state, sel->pad); 727 return 0; 728 case V4L2_SEL_TGT_CROP_DEFAULT: 729 sel->r = ov01a10_default_crop; 730 return 0; 731 case V4L2_SEL_TGT_CROP_BOUNDS: 732 /* Keep a border for hvflip shift to preserve bayer-pattern */ 733 sel->r.left = border_size; 734 sel->r.top = border_size; 735 sel->r.width = OV01A10_NATIVE_WIDTH - 2 * border_size; 736 sel->r.height = OV01A10_NATIVE_HEIGHT - 2 * border_size; 737 return 0; 738 case V4L2_SEL_TGT_NATIVE_SIZE: 739 sel->r.left = 0; 740 sel->r.top = 0; 741 sel->r.width = OV01A10_NATIVE_WIDTH; 742 sel->r.height = OV01A10_NATIVE_HEIGHT; 743 return 0; 744 } 745 746 return -EINVAL; 747 } 748 749 static int ov01a10_set_selection(struct v4l2_subdev *sd, 750 struct v4l2_subdev_state *sd_state, 751 struct v4l2_subdev_selection *sel) 752 { 753 struct ov01a10 *ov01a10 = to_ov01a10(sd); 754 const int pattern_size = ov01a10->cfg->pattern_size; 755 const int border_size = ov01a10->cfg->border_size; 756 struct v4l2_mbus_framefmt *format; 757 struct v4l2_rect *crop; 758 struct v4l2_rect rect; 759 760 if (sel->target != V4L2_SEL_TGT_CROP) 761 return -EINVAL; 762 763 /* 764 * Clamp the boundaries of the crop rectangle to the size of the sensor 765 * pixel array. Align to pattern-size to ensure pattern isn't disrupted. 766 */ 767 rect.left = clamp_val(ALIGN(sel->r.left, pattern_size), border_size, 768 OV01A10_NATIVE_WIDTH - 2 * border_size); 769 rect.top = clamp_val(ALIGN(sel->r.top, pattern_size), border_size, 770 OV01A10_NATIVE_HEIGHT - 2 * border_size); 771 rect.width = clamp_val(ALIGN(sel->r.width, pattern_size), pattern_size, 772 OV01A10_NATIVE_WIDTH - rect.left - border_size); 773 rect.height = clamp_val(ALIGN(sel->r.height, pattern_size), pattern_size, 774 OV01A10_NATIVE_HEIGHT - rect.top - border_size); 775 776 crop = v4l2_subdev_state_get_crop(sd_state, sel->pad); 777 778 /* Reset the output size if the crop rectangle size has changed */ 779 if (rect.width != crop->width || rect.height != crop->height) { 780 format = v4l2_subdev_state_get_format(sd_state, sel->pad); 781 format->width = rect.width; 782 format->height = rect.height; 783 784 if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) 785 ov01a10_update_blank_ctrls(ov01a10, rect.width, 786 rect.height); 787 } 788 789 *crop = rect; 790 sel->r = rect; 791 792 return 0; 793 } 794 795 static const struct v4l2_subdev_core_ops ov01a10_core_ops = { 796 .log_status = v4l2_ctrl_subdev_log_status, 797 }; 798 799 static const struct v4l2_subdev_video_ops ov01a10_video_ops = { 800 .s_stream = ov01a10_set_stream, 801 }; 802 803 static const struct v4l2_subdev_pad_ops ov01a10_pad_ops = { 804 .set_fmt = ov01a10_set_format, 805 .get_fmt = v4l2_subdev_get_fmt, 806 .get_selection = ov01a10_get_selection, 807 .set_selection = ov01a10_set_selection, 808 .enum_mbus_code = ov01a10_enum_mbus_code, 809 .enum_frame_size = ov01a10_enum_frame_size, 810 }; 811 812 static const struct v4l2_subdev_ops ov01a10_subdev_ops = { 813 .core = &ov01a10_core_ops, 814 .video = &ov01a10_video_ops, 815 .pad = &ov01a10_pad_ops, 816 }; 817 818 static const struct v4l2_subdev_internal_ops ov01a10_internal_ops = { 819 .init_state = ov01a10_init_state, 820 }; 821 822 static const struct media_entity_operations ov01a10_subdev_entity_ops = { 823 .link_validate = v4l2_subdev_link_validate, 824 }; 825 826 static int ov01a10_get_pm_resources(struct ov01a10 *ov01a10) 827 { 828 unsigned long freq; 829 int i, ret; 830 831 ov01a10->clk = devm_v4l2_sensor_clk_get(ov01a10->dev, NULL); 832 if (IS_ERR(ov01a10->clk)) 833 return dev_err_probe(ov01a10->dev, PTR_ERR(ov01a10->clk), 834 "getting clock\n"); 835 836 freq = clk_get_rate(ov01a10->clk); 837 if (freq != OV01A10_MCLK) 838 return dev_err_probe(ov01a10->dev, -EINVAL, 839 "external clock %lu is not supported", 840 freq); 841 842 ov01a10->reset = devm_gpiod_get_optional(ov01a10->dev, "reset", 843 GPIOD_OUT_HIGH); 844 if (IS_ERR(ov01a10->reset)) 845 return dev_err_probe(ov01a10->dev, PTR_ERR(ov01a10->reset), 846 "getting reset gpio\n"); 847 848 ov01a10->powerdown = devm_gpiod_get_optional(ov01a10->dev, "powerdown", 849 GPIOD_OUT_HIGH); 850 if (IS_ERR(ov01a10->powerdown)) 851 return dev_err_probe(ov01a10->dev, PTR_ERR(ov01a10->powerdown), 852 "getting powerdown gpio\n"); 853 854 for (i = 0; i < ARRAY_SIZE(ov01a10_supply_names); i++) 855 ov01a10->supplies[i].supply = ov01a10_supply_names[i]; 856 857 ret = devm_regulator_bulk_get(ov01a10->dev, 858 ARRAY_SIZE(ov01a10_supply_names), 859 ov01a10->supplies); 860 if (ret) 861 return dev_err_probe(ov01a10->dev, ret, "getting regulators\n"); 862 863 return 0; 864 } 865 866 static int ov01a10_power_on(struct device *dev) 867 { 868 struct v4l2_subdev *sd = dev_get_drvdata(dev); 869 struct ov01a10 *ov01a10 = to_ov01a10(sd); 870 int ret; 871 872 ret = clk_prepare_enable(ov01a10->clk); 873 if (ret) { 874 dev_err(dev, "Error enabling clk: %d\n", ret); 875 return ret; 876 } 877 878 ret = regulator_bulk_enable(ARRAY_SIZE(ov01a10_supply_names), 879 ov01a10->supplies); 880 if (ret) { 881 dev_err(dev, "Error enabling regulators: %d\n", ret); 882 clk_disable_unprepare(ov01a10->clk); 883 return ret; 884 } 885 886 if (ov01a10->reset || ov01a10->powerdown) { 887 /* Assert reset/powerdown for at least 2ms on back to back off-on */ 888 fsleep(2000); 889 gpiod_set_value_cansleep(ov01a10->powerdown, 0); 890 gpiod_set_value_cansleep(ov01a10->reset, 0); 891 fsleep(20000); 892 } 893 894 return 0; 895 } 896 897 static int ov01a10_power_off(struct device *dev) 898 { 899 struct v4l2_subdev *sd = dev_get_drvdata(dev); 900 struct ov01a10 *ov01a10 = to_ov01a10(sd); 901 902 gpiod_set_value_cansleep(ov01a10->reset, 1); 903 gpiod_set_value_cansleep(ov01a10->powerdown, 1); 904 905 regulator_bulk_disable(ARRAY_SIZE(ov01a10_supply_names), 906 ov01a10->supplies); 907 908 clk_disable_unprepare(ov01a10->clk); 909 return 0; 910 } 911 912 static int ov01a10_identify_module(struct ov01a10 *ov01a10) 913 { 914 int ret; 915 u64 val; 916 917 ret = cci_read(ov01a10->regmap, OV01A10_REG_CHIP_ID, &val, NULL); 918 if (ret) 919 return ret; 920 921 if (val != OV01A10_CHIP_ID) { 922 dev_err(ov01a10->dev, "chip id mismatch: %x!=%llx\n", 923 OV01A10_CHIP_ID, val); 924 return -EIO; 925 } 926 927 return 0; 928 } 929 930 static int ov01a10_check_hwcfg(struct ov01a10 *ov01a10) 931 { 932 struct v4l2_fwnode_endpoint bus_cfg = { 933 .bus_type = V4L2_MBUS_CSI2_DPHY 934 }; 935 struct fwnode_handle *ep, *fwnode = dev_fwnode(ov01a10->dev); 936 unsigned long link_freq_bitmap; 937 int ret; 938 939 /* 940 * Sometimes the fwnode graph is initialized by the bridge driver, 941 * wait for this. 942 */ 943 ep = fwnode_graph_get_endpoint_by_id(fwnode, 0, 0, 0); 944 if (!ep) 945 return dev_err_probe(ov01a10->dev, -EPROBE_DEFER, 946 "waiting for fwnode graph endpoint\n"); 947 948 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); 949 fwnode_handle_put(ep); 950 if (ret) 951 return dev_err_probe(ov01a10->dev, ret, "parsing endpoint\n"); 952 953 ret = v4l2_link_freq_to_bitmap(ov01a10->dev, 954 bus_cfg.link_frequencies, 955 bus_cfg.nr_of_link_frequencies, 956 link_freq_menu_items, 957 ARRAY_SIZE(link_freq_menu_items), 958 &link_freq_bitmap); 959 if (ret) 960 goto check_hwcfg_error; 961 962 /* v4l2_link_freq_to_bitmap() guarantees at least 1 bit is set */ 963 ov01a10->link_freq_index = ffs(link_freq_bitmap) - 1; 964 965 if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV01A10_DATA_LANES) { 966 ret = dev_err_probe(ov01a10->dev, -EINVAL, 967 "number of CSI2 data lanes %u is not supported\n", 968 bus_cfg.bus.mipi_csi2.num_data_lanes); 969 goto check_hwcfg_error; 970 } 971 972 check_hwcfg_error: 973 v4l2_fwnode_endpoint_free(&bus_cfg); 974 return ret; 975 } 976 977 static void ov01a10_remove(struct i2c_client *client) 978 { 979 struct v4l2_subdev *sd = i2c_get_clientdata(client); 980 981 v4l2_async_unregister_subdev(sd); 982 v4l2_subdev_cleanup(sd); 983 media_entity_cleanup(&sd->entity); 984 v4l2_ctrl_handler_free(sd->ctrl_handler); 985 986 pm_runtime_disable(&client->dev); 987 if (!pm_runtime_status_suspended(&client->dev)) { 988 ov01a10_power_off(&client->dev); 989 pm_runtime_set_suspended(&client->dev); 990 } 991 } 992 993 static int ov01a10_probe(struct i2c_client *client) 994 { 995 const struct ov01a10_sensor_cfg *cfg; 996 struct ov01a10 *ov01a10; 997 int ret; 998 999 cfg = device_get_match_data(&client->dev); 1000 if (!cfg) 1001 return -EINVAL; 1002 1003 ov01a10 = devm_kzalloc(&client->dev, sizeof(*ov01a10), GFP_KERNEL); 1004 if (!ov01a10) 1005 return -ENOMEM; 1006 1007 ov01a10->dev = &client->dev; 1008 ov01a10->cfg = cfg; 1009 1010 ov01a10->regmap = devm_cci_regmap_init_i2c(client, 16); 1011 if (IS_ERR(ov01a10->regmap)) 1012 return PTR_ERR(ov01a10->regmap); 1013 1014 v4l2_i2c_subdev_init(&ov01a10->sd, client, &ov01a10_subdev_ops); 1015 /* Override driver->name with actual sensor model */ 1016 v4l2_i2c_subdev_set_name(&ov01a10->sd, client, cfg->model, NULL); 1017 ov01a10->sd.internal_ops = &ov01a10_internal_ops; 1018 1019 ret = ov01a10_check_hwcfg(ov01a10); 1020 if (ret) 1021 return ret; 1022 1023 ret = ov01a10_get_pm_resources(ov01a10); 1024 if (ret) 1025 return ret; 1026 1027 ret = ov01a10_power_on(&client->dev); 1028 if (ret) 1029 return ret; 1030 1031 ret = ov01a10_identify_module(ov01a10); 1032 if (ret) 1033 goto err_power_off; 1034 1035 ret = ov01a10_init_controls(ov01a10); 1036 if (ret) 1037 goto err_power_off; 1038 1039 ov01a10->sd.state_lock = ov01a10->ctrl_handler.lock; 1040 ov01a10->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1041 ov01a10->sd.entity.ops = &ov01a10_subdev_entity_ops; 1042 ov01a10->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1043 ov01a10->pad.flags = MEDIA_PAD_FL_SOURCE; 1044 1045 ret = media_entity_pads_init(&ov01a10->sd.entity, 1, &ov01a10->pad); 1046 if (ret) 1047 goto err_handler_free; 1048 1049 ret = v4l2_subdev_init_finalize(&ov01a10->sd); 1050 if (ret) 1051 goto err_media_entity_cleanup; 1052 1053 /* 1054 * Device is already turned on by i2c-core with ACPI domain PM. 1055 * Enable runtime PM and turn off the device. 1056 */ 1057 pm_runtime_set_active(&client->dev); 1058 pm_runtime_enable(&client->dev); 1059 pm_runtime_idle(&client->dev); 1060 1061 ret = v4l2_async_register_subdev_sensor(&ov01a10->sd); 1062 if (ret) 1063 goto err_pm_disable; 1064 1065 return 0; 1066 1067 err_pm_disable: 1068 pm_runtime_disable(&client->dev); 1069 pm_runtime_set_suspended(&client->dev); 1070 v4l2_subdev_cleanup(&ov01a10->sd); 1071 1072 err_media_entity_cleanup: 1073 media_entity_cleanup(&ov01a10->sd.entity); 1074 1075 err_handler_free: 1076 v4l2_ctrl_handler_free(ov01a10->sd.ctrl_handler); 1077 1078 err_power_off: 1079 ov01a10_power_off(&client->dev); 1080 1081 return ret; 1082 } 1083 1084 static DEFINE_RUNTIME_DEV_PM_OPS(ov01a10_pm_ops, ov01a10_power_off, 1085 ov01a10_power_on, NULL); 1086 1087 #ifdef CONFIG_ACPI 1088 /* 1089 * The native ov01a10 bayer-pattern is GBRG, but there was a driver bug enabling 1090 * hflip/mirroring by default resulting in BGGR. Because of this bug Intel's 1091 * proprietary IPU6 userspace stack expects BGGR. So we report BGGR to not break 1092 * userspace and fix things up by shifting the crop window-x coordinate by 1 1093 * when hflip is *disabled*. 1094 */ 1095 static const struct ov01a10_sensor_cfg ov01a10_cfg = { 1096 .model = "ov01a10", 1097 .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10, 1098 .pattern_size = 2, /* 2x2 */ 1099 .border_size = 2, 1100 .format1_base_val = 0xa0, 1101 .invert_hflip_shift = true, 1102 .invert_vflip_shift = false, 1103 }; 1104 1105 static const struct ov01a10_sensor_cfg ov01a1b_cfg = { 1106 .model = "ov01a1b", 1107 .bus_fmt = MEDIA_BUS_FMT_Y10_1X10, 1108 .pattern_size = 2, /* Keep coordinates aligned to a multiple of 2 */ 1109 .border_size = 0, 1110 .format1_base_val = 0xa0, 1111 }; 1112 1113 static const struct acpi_device_id ov01a10_acpi_ids[] = { 1114 { "OVTI01A0", (uintptr_t)&ov01a10_cfg }, 1115 { "OVTI01AB", (uintptr_t)&ov01a1b_cfg }, 1116 { } 1117 }; 1118 1119 MODULE_DEVICE_TABLE(acpi, ov01a10_acpi_ids); 1120 #endif 1121 1122 static struct i2c_driver ov01a10_i2c_driver = { 1123 .driver = { 1124 .name = "ov01a10", 1125 .pm = pm_sleep_ptr(&ov01a10_pm_ops), 1126 .acpi_match_table = ACPI_PTR(ov01a10_acpi_ids), 1127 }, 1128 .probe = ov01a10_probe, 1129 .remove = ov01a10_remove, 1130 }; 1131 1132 module_i2c_driver(ov01a10_i2c_driver); 1133 1134 MODULE_AUTHOR("Bingbu Cao <bingbu.cao@intel.com>"); 1135 MODULE_AUTHOR("Wang Yating <yating.wang@intel.com>"); 1136 MODULE_DESCRIPTION("OmniVision OV01A10 sensor driver"); 1137 MODULE_LICENSE("GPL"); 1138