1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2024-2025 Linaro Ltd 3 4 #include <linux/clk.h> 5 #include <linux/delay.h> 6 #include <linux/gpio/consumer.h> 7 #include <linux/i2c.h> 8 #include <linux/module.h> 9 #include <linux/pm_runtime.h> 10 #include <linux/regulator/consumer.h> 11 #include <linux/units.h> 12 #include <media/v4l2-cci.h> 13 #include <media/v4l2-ctrls.h> 14 #include <media/v4l2-device.h> 15 #include <media/v4l2-fwnode.h> 16 17 #define OG0VE1B_LINK_FREQ_500MHZ (500 * HZ_PER_MHZ) 18 #define OG0VE1B_MCLK_FREQ_24MHZ (24 * HZ_PER_MHZ) 19 20 #define OG0VE1B_REG_CHIP_ID CCI_REG24(0x300a) 21 #define OG0VE1B_CHIP_ID 0xc75645 22 23 #define OG0VE1B_REG_MODE_SELECT CCI_REG8(0x0100) 24 #define OG0VE1B_MODE_STANDBY 0x00 25 #define OG0VE1B_MODE_STREAMING BIT(0) 26 27 #define OG0VE1B_REG_SOFTWARE_RST CCI_REG8(0x0103) 28 #define OG0VE1B_SOFTWARE_RST BIT(0) 29 30 /* Exposure controls from sensor */ 31 #define OG0VE1B_REG_EXPOSURE CCI_REG24(0x3500) 32 #define OG0VE1B_EXPOSURE_MIN 1 33 #define OG0VE1B_EXPOSURE_MAX_MARGIN 14 34 #define OG0VE1B_EXPOSURE_STEP 1 35 #define OG0VE1B_EXPOSURE_DEFAULT 554 36 37 /* Analogue gain controls from sensor */ 38 #define OG0VE1B_REG_ANALOGUE_GAIN CCI_REG16(0x350a) 39 #define OG0VE1B_ANALOGUE_GAIN_MIN 1 40 #define OG0VE1B_ANALOGUE_GAIN_MAX 0x1ff 41 #define OG0VE1B_ANALOGUE_GAIN_STEP 1 42 #define OG0VE1B_ANALOGUE_GAIN_DEFAULT 16 43 44 /* Vertical timing size */ 45 #define OG0VE1B_REG_VTS CCI_REG16(0x380e) 46 #define OG0VE1B_VTS_MAX 0xffff 47 48 /* Test pattern */ 49 #define OG0VE1B_REG_PRE_ISP CCI_REG8(0x5e00) 50 #define OG0VE1B_TEST_PATTERN_ENABLE BIT(7) 51 52 #define to_og0ve1b(_sd) container_of(_sd, struct og0ve1b, sd) 53 54 static const s64 og0ve1b_link_freq_menu[] = { 55 OG0VE1B_LINK_FREQ_500MHZ, 56 }; 57 58 struct og0ve1b_reg_list { 59 const struct cci_reg_sequence *regs; 60 unsigned int num_regs; 61 }; 62 63 struct og0ve1b_mode { 64 u32 width; /* Frame width in pixels */ 65 u32 height; /* Frame height in pixels */ 66 u32 hts; /* Horizontal timing size */ 67 u32 vts; /* Default vertical timing size */ 68 u32 bpp; /* Bits per pixel */ 69 70 const struct og0ve1b_reg_list reg_list; /* Sensor register setting */ 71 }; 72 73 static const char * const og0ve1b_test_pattern_menu[] = { 74 "Disabled", 75 "Vertical Colour Bars", 76 }; 77 78 static const char * const og0ve1b_supply_names[] = { 79 "avdd", /* Analog power */ 80 "dovdd", /* Digital I/O power */ 81 "dvdd", /* Digital core power */ 82 }; 83 84 #define OG0VE1B_NUM_SUPPLIES ARRAY_SIZE(og0ve1b_supply_names) 85 86 struct og0ve1b { 87 struct device *dev; 88 struct regmap *regmap; 89 struct clk *xvclk; 90 struct gpio_desc *reset_gpio; 91 struct regulator_bulk_data supplies[OG0VE1B_NUM_SUPPLIES]; 92 93 struct v4l2_subdev sd; 94 struct media_pad pad; 95 96 struct v4l2_ctrl *vblank; 97 struct v4l2_ctrl *exposure; 98 struct v4l2_ctrl_handler ctrl_handler; 99 100 /* Saved register value */ 101 u64 pre_isp; 102 }; 103 104 static const struct cci_reg_sequence og0ve1b_640x480_120fps_mode[] = { 105 { CCI_REG8(0x30a0), 0x02 }, 106 { CCI_REG8(0x30a1), 0x00 }, 107 { CCI_REG8(0x30a2), 0x48 }, 108 { CCI_REG8(0x30a3), 0x34 }, 109 { CCI_REG8(0x30a4), 0xf7 }, 110 { CCI_REG8(0x30a5), 0x00 }, 111 { CCI_REG8(0x3082), 0x32 }, 112 { CCI_REG8(0x3083), 0x01 }, 113 { CCI_REG8(0x301c), 0xf0 }, 114 { CCI_REG8(0x301e), 0x0b }, 115 { CCI_REG8(0x3106), 0x10 }, 116 { CCI_REG8(0x3708), 0x77 }, 117 { CCI_REG8(0x3709), 0xf8 }, 118 { CCI_REG8(0x3717), 0x00 }, 119 { CCI_REG8(0x3782), 0x00 }, 120 { CCI_REG8(0x3783), 0x47 }, 121 { CCI_REG8(0x37a2), 0x00 }, 122 { CCI_REG8(0x3503), 0x07 }, 123 { CCI_REG8(0x3509), 0x10 }, 124 { CCI_REG8(0x3600), 0x83 }, 125 { CCI_REG8(0x3601), 0x21 }, 126 { CCI_REG8(0x3602), 0xf1 }, 127 { CCI_REG8(0x360a), 0x18 }, 128 { CCI_REG8(0x360e), 0xb3 }, 129 { CCI_REG8(0x3613), 0x20 }, 130 { CCI_REG8(0x366a), 0x78 }, 131 { CCI_REG8(0x3706), 0x63 }, 132 { CCI_REG8(0x3713), 0x00 }, 133 { CCI_REG8(0x3716), 0xb0 }, 134 { CCI_REG8(0x37a1), 0x38 }, 135 { CCI_REG8(0x3800), 0x00 }, 136 { CCI_REG8(0x3801), 0x04 }, 137 { CCI_REG8(0x3802), 0x00 }, 138 { CCI_REG8(0x3803), 0x04 }, 139 { CCI_REG8(0x3804), 0x02 }, 140 { CCI_REG8(0x3805), 0x8b }, 141 { CCI_REG8(0x3806), 0x01 }, 142 { CCI_REG8(0x3807), 0xeb }, 143 { CCI_REG8(0x3808), 0x02 }, /* output width */ 144 { CCI_REG8(0x3809), 0x80 }, 145 { CCI_REG8(0x380a), 0x01 }, /* output height */ 146 { CCI_REG8(0x380b), 0xe0 }, 147 { CCI_REG8(0x380c), 0x03 }, /* horizontal timing size */ 148 { CCI_REG8(0x380d), 0x18 }, 149 { CCI_REG8(0x3811), 0x04 }, 150 { CCI_REG8(0x3813), 0x04 }, 151 { CCI_REG8(0x3814), 0x11 }, 152 { CCI_REG8(0x3815), 0x11 }, 153 { CCI_REG8(0x3820), 0x00 }, 154 { CCI_REG8(0x3821), 0x00 }, 155 { CCI_REG8(0x3823), 0x04 }, 156 { CCI_REG8(0x382a), 0x00 }, 157 { CCI_REG8(0x382b), 0x03 }, 158 { CCI_REG8(0x3840), 0x00 }, 159 { CCI_REG8(0x389e), 0x00 }, 160 { CCI_REG8(0x3c05), 0x08 }, 161 { CCI_REG8(0x3c26), 0x02 }, 162 { CCI_REG8(0x3c27), 0xc0 }, 163 { CCI_REG8(0x3c28), 0x00 }, 164 { CCI_REG8(0x3c29), 0x40 }, 165 { CCI_REG8(0x3c2c), 0x00 }, 166 { CCI_REG8(0x3c2d), 0x50 }, 167 { CCI_REG8(0x3c2e), 0x02 }, 168 { CCI_REG8(0x3c2f), 0x66 }, 169 { CCI_REG8(0x3c33), 0x08 }, 170 { CCI_REG8(0x3c35), 0x00 }, 171 { CCI_REG8(0x3c36), 0x00 }, 172 { CCI_REG8(0x3c37), 0x00 }, 173 { CCI_REG8(0x3f52), 0x9b }, 174 { CCI_REG8(0x4001), 0x42 }, 175 { CCI_REG8(0x4004), 0x08 }, 176 { CCI_REG8(0x4005), 0x00 }, 177 { CCI_REG8(0x4007), 0x28 }, 178 { CCI_REG8(0x4009), 0x40 }, 179 { CCI_REG8(0x4307), 0x30 }, 180 { CCI_REG8(0x4500), 0x80 }, 181 { CCI_REG8(0x4501), 0x02 }, 182 { CCI_REG8(0x4502), 0x47 }, 183 { CCI_REG8(0x4504), 0x7f }, 184 { CCI_REG8(0x4601), 0x48 }, 185 { CCI_REG8(0x4800), 0x64 }, 186 { CCI_REG8(0x4801), 0x0f }, 187 { CCI_REG8(0x4806), 0x2f }, 188 { CCI_REG8(0x4819), 0xaa }, 189 { CCI_REG8(0x4823), 0x3e }, 190 { CCI_REG8(0x5000), 0x85 }, 191 { CCI_REG8(0x5e00), 0x0c }, 192 { CCI_REG8(0x3899), 0x09 }, 193 { CCI_REG8(0x4f00), 0x64 }, 194 { CCI_REG8(0x4f02), 0x0a }, 195 { CCI_REG8(0x4f05), 0x0e }, 196 { CCI_REG8(0x4f06), 0x11 }, 197 { CCI_REG8(0x4f08), 0x0b }, 198 { CCI_REG8(0x4f0a), 0xc4 }, 199 { CCI_REG8(0x4f20), 0x1f }, 200 { CCI_REG8(0x4f25), 0x10 }, 201 { CCI_REG8(0x3016), 0x10 }, 202 { CCI_REG8(0x3017), 0x00 }, 203 { CCI_REG8(0x3018), 0x00 }, 204 { CCI_REG8(0x3019), 0x00 }, 205 { CCI_REG8(0x301a), 0x00 }, 206 { CCI_REG8(0x301b), 0x00 }, 207 { CCI_REG8(0x301c), 0x72 }, 208 { CCI_REG8(0x3037), 0x40 }, 209 { CCI_REG8(0x4f2c), 0x00 }, 210 { CCI_REG8(0x4f21), 0x00 }, 211 { CCI_REG8(0x4f23), 0x00 }, 212 { CCI_REG8(0x4f2a), 0x00 }, 213 { CCI_REG8(0x3665), 0xe7 }, 214 { CCI_REG8(0x3668), 0x48 }, 215 { CCI_REG8(0x3671), 0x3c }, 216 { CCI_REG8(0x389a), 0x02 }, 217 { CCI_REG8(0x389b), 0x00 }, 218 { CCI_REG8(0x303c), 0xa0 }, 219 { CCI_REG8(0x300f), 0xf0 }, 220 { CCI_REG8(0x304b), 0x0f }, 221 { CCI_REG8(0x3662), 0x24 }, 222 { CCI_REG8(0x3006), 0x40 }, 223 { CCI_REG8(0x4f26), 0x45 }, 224 { CCI_REG8(0x3607), 0x34 }, 225 { CCI_REG8(0x3608), 0x01 }, 226 { CCI_REG8(0x360a), 0x0c }, 227 { CCI_REG8(0x360b), 0x86 }, 228 { CCI_REG8(0x360c), 0xcc }, 229 { CCI_REG8(0x3013), 0x00 }, 230 { CCI_REG8(0x3083), 0x02 }, 231 { CCI_REG8(0x3084), 0x12 }, 232 { CCI_REG8(0x4601), 0x38 }, 233 { CCI_REG8(0x366f), 0x3a }, 234 { CCI_REG8(0x3713), 0x19 }, 235 { CCI_REG8(0x37a2), 0x00 }, 236 { CCI_REG8(0x3f43), 0x27 }, 237 { CCI_REG8(0x3f45), 0x27 }, 238 { CCI_REG8(0x3f47), 0x32 }, 239 { CCI_REG8(0x3f49), 0x3e }, 240 { CCI_REG8(0x3f4b), 0x20 }, 241 { CCI_REG8(0x3f4d), 0x30 }, 242 { CCI_REG8(0x4300), 0x3f }, 243 { CCI_REG8(0x4009), 0x10 }, 244 { CCI_REG8(0x3f02), 0x68 }, 245 { CCI_REG8(0x3700), 0x8c }, 246 { CCI_REG8(0x370b), 0x7e }, 247 { CCI_REG8(0x3f47), 0x35 }, 248 }; 249 250 static const struct og0ve1b_mode supported_modes[] = { 251 { 252 .width = 640, 253 .height = 480, 254 .hts = 792, 255 .vts = 568, 256 .bpp = 8, 257 .reg_list = { 258 .regs = og0ve1b_640x480_120fps_mode, 259 .num_regs = ARRAY_SIZE(og0ve1b_640x480_120fps_mode), 260 }, 261 }, 262 }; 263 264 static int og0ve1b_enable_test_pattern(struct og0ve1b *og0ve1b, u32 pattern) 265 { 266 u64 val = og0ve1b->pre_isp; 267 268 if (pattern) 269 val |= OG0VE1B_TEST_PATTERN_ENABLE; 270 else 271 val &= ~OG0VE1B_TEST_PATTERN_ENABLE; 272 273 return cci_write(og0ve1b->regmap, OG0VE1B_REG_PRE_ISP, val, NULL); 274 } 275 276 static int og0ve1b_set_ctrl(struct v4l2_ctrl *ctrl) 277 { 278 struct og0ve1b *og0ve1b = container_of(ctrl->handler, struct og0ve1b, 279 ctrl_handler); 280 const struct og0ve1b_mode *mode = &supported_modes[0]; 281 s64 exposure_max; 282 int ret; 283 284 /* Propagate change of current control to all related controls */ 285 switch (ctrl->id) { 286 case V4L2_CID_VBLANK: 287 /* Update max exposure while meeting expected vblanking */ 288 exposure_max = ctrl->val + mode->height - 289 OG0VE1B_EXPOSURE_MAX_MARGIN; 290 ret = __v4l2_ctrl_modify_range(og0ve1b->exposure, 291 og0ve1b->exposure->minimum, 292 exposure_max, 293 og0ve1b->exposure->step, 294 og0ve1b->exposure->default_value); 295 if (ret) 296 return ret; 297 } 298 299 /* V4L2 controls are applied, when sensor is powered up for streaming */ 300 if (!pm_runtime_get_if_active(og0ve1b->dev)) 301 return 0; 302 303 switch (ctrl->id) { 304 case V4L2_CID_ANALOGUE_GAIN: 305 ret = cci_write(og0ve1b->regmap, OG0VE1B_REG_ANALOGUE_GAIN, 306 ctrl->val, NULL); 307 break; 308 case V4L2_CID_EXPOSURE: 309 ret = cci_write(og0ve1b->regmap, OG0VE1B_REG_EXPOSURE, 310 ctrl->val << 4, NULL); 311 break; 312 case V4L2_CID_VBLANK: 313 ret = cci_write(og0ve1b->regmap, OG0VE1B_REG_VTS, 314 ctrl->val + mode->height, NULL); 315 break; 316 case V4L2_CID_TEST_PATTERN: 317 ret = og0ve1b_enable_test_pattern(og0ve1b, ctrl->val); 318 break; 319 default: 320 ret = -EINVAL; 321 break; 322 } 323 324 pm_runtime_put(og0ve1b->dev); 325 326 return ret; 327 } 328 329 static const struct v4l2_ctrl_ops og0ve1b_ctrl_ops = { 330 .s_ctrl = og0ve1b_set_ctrl, 331 }; 332 333 static int og0ve1b_init_controls(struct og0ve1b *og0ve1b) 334 { 335 struct v4l2_ctrl_handler *ctrl_hdlr = &og0ve1b->ctrl_handler; 336 const struct og0ve1b_mode *mode = &supported_modes[0]; 337 s64 exposure_max, pixel_rate, h_blank, v_blank; 338 struct v4l2_fwnode_device_properties props; 339 struct v4l2_ctrl *ctrl; 340 int ret; 341 342 v4l2_ctrl_handler_init(ctrl_hdlr, 9); 343 344 ctrl = v4l2_ctrl_new_int_menu(ctrl_hdlr, &og0ve1b_ctrl_ops, 345 V4L2_CID_LINK_FREQ, 346 ARRAY_SIZE(og0ve1b_link_freq_menu) - 1, 347 0, og0ve1b_link_freq_menu); 348 if (ctrl) 349 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY; 350 351 pixel_rate = og0ve1b_link_freq_menu[0] / mode->bpp; 352 v4l2_ctrl_new_std(ctrl_hdlr, &og0ve1b_ctrl_ops, V4L2_CID_PIXEL_RATE, 353 0, pixel_rate, 1, pixel_rate); 354 355 h_blank = mode->hts - mode->width; 356 ctrl = v4l2_ctrl_new_std(ctrl_hdlr, &og0ve1b_ctrl_ops, V4L2_CID_HBLANK, 357 h_blank, h_blank, 1, h_blank); 358 if (ctrl) 359 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY; 360 361 v_blank = mode->vts - mode->height; 362 og0ve1b->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &og0ve1b_ctrl_ops, 363 V4L2_CID_VBLANK, v_blank, 364 OG0VE1B_VTS_MAX - mode->height, 1, 365 v_blank); 366 367 v4l2_ctrl_new_std(ctrl_hdlr, &og0ve1b_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 368 OG0VE1B_ANALOGUE_GAIN_MIN, OG0VE1B_ANALOGUE_GAIN_MAX, 369 OG0VE1B_ANALOGUE_GAIN_STEP, 370 OG0VE1B_ANALOGUE_GAIN_DEFAULT); 371 372 exposure_max = mode->vts - OG0VE1B_EXPOSURE_MAX_MARGIN; 373 og0ve1b->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &og0ve1b_ctrl_ops, 374 V4L2_CID_EXPOSURE, 375 OG0VE1B_EXPOSURE_MIN, 376 exposure_max, 377 OG0VE1B_EXPOSURE_STEP, 378 OG0VE1B_EXPOSURE_DEFAULT); 379 380 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &og0ve1b_ctrl_ops, 381 V4L2_CID_TEST_PATTERN, 382 ARRAY_SIZE(og0ve1b_test_pattern_menu) - 1, 383 0, 0, og0ve1b_test_pattern_menu); 384 385 if (ctrl_hdlr->error) 386 return ctrl_hdlr->error; 387 388 ret = v4l2_fwnode_device_parse(og0ve1b->dev, &props); 389 if (ret) 390 goto error_free_hdlr; 391 392 ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &og0ve1b_ctrl_ops, 393 &props); 394 if (ret) 395 goto error_free_hdlr; 396 397 og0ve1b->sd.ctrl_handler = ctrl_hdlr; 398 399 return 0; 400 401 error_free_hdlr: 402 v4l2_ctrl_handler_free(ctrl_hdlr); 403 404 return ret; 405 } 406 407 static void og0ve1b_update_pad_format(const struct og0ve1b_mode *mode, 408 struct v4l2_mbus_framefmt *fmt) 409 { 410 fmt->code = MEDIA_BUS_FMT_Y8_1X8; 411 fmt->width = mode->width; 412 fmt->height = mode->height; 413 fmt->field = V4L2_FIELD_NONE; 414 fmt->colorspace = V4L2_COLORSPACE_RAW; 415 fmt->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 416 fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE; 417 fmt->xfer_func = V4L2_XFER_FUNC_NONE; 418 } 419 420 static int og0ve1b_enable_streams(struct v4l2_subdev *sd, 421 struct v4l2_subdev_state *state, u32 pad, 422 u64 streams_mask) 423 { 424 const struct og0ve1b_reg_list *reg_list = &supported_modes[0].reg_list; 425 struct og0ve1b *og0ve1b = to_og0ve1b(sd); 426 int ret; 427 428 ret = pm_runtime_resume_and_get(og0ve1b->dev); 429 if (ret) 430 return ret; 431 432 /* Skip a step of explicit entering into the standby mode */ 433 ret = cci_write(og0ve1b->regmap, OG0VE1B_REG_SOFTWARE_RST, 434 OG0VE1B_SOFTWARE_RST, NULL); 435 if (ret) { 436 dev_err(og0ve1b->dev, "failed to software reset: %d\n", ret); 437 goto error; 438 } 439 440 ret = cci_multi_reg_write(og0ve1b->regmap, reg_list->regs, 441 reg_list->num_regs, NULL); 442 if (ret) { 443 dev_err(og0ve1b->dev, "failed to set mode: %d\n", ret); 444 goto error; 445 } 446 447 ret = __v4l2_ctrl_handler_setup(og0ve1b->sd.ctrl_handler); 448 if (ret) 449 goto error; 450 451 ret = cci_write(og0ve1b->regmap, OG0VE1B_REG_MODE_SELECT, 452 OG0VE1B_MODE_STREAMING, NULL); 453 if (ret) { 454 dev_err(og0ve1b->dev, "failed to start streaming: %d\n", ret); 455 goto error; 456 } 457 458 return 0; 459 460 error: 461 pm_runtime_put_autosuspend(og0ve1b->dev); 462 463 return ret; 464 } 465 466 static int og0ve1b_disable_streams(struct v4l2_subdev *sd, 467 struct v4l2_subdev_state *state, u32 pad, 468 u64 streams_mask) 469 { 470 struct og0ve1b *og0ve1b = to_og0ve1b(sd); 471 int ret; 472 473 ret = cci_write(og0ve1b->regmap, OG0VE1B_REG_MODE_SELECT, 474 OG0VE1B_MODE_STANDBY, NULL); 475 if (ret) 476 dev_err(og0ve1b->dev, "failed to stop streaming: %d\n", ret); 477 478 pm_runtime_put_autosuspend(og0ve1b->dev); 479 480 return ret; 481 } 482 483 static int og0ve1b_set_pad_format(struct v4l2_subdev *sd, 484 struct v4l2_subdev_state *state, 485 struct v4l2_subdev_format *fmt) 486 { 487 struct v4l2_mbus_framefmt *format; 488 const struct og0ve1b_mode *mode; 489 490 format = v4l2_subdev_state_get_format(state, 0); 491 492 mode = v4l2_find_nearest_size(supported_modes, 493 ARRAY_SIZE(supported_modes), 494 width, height, 495 fmt->format.width, 496 fmt->format.height); 497 498 og0ve1b_update_pad_format(mode, &fmt->format); 499 *format = fmt->format; 500 501 return 0; 502 } 503 504 static int og0ve1b_enum_mbus_code(struct v4l2_subdev *sd, 505 struct v4l2_subdev_state *sd_state, 506 struct v4l2_subdev_mbus_code_enum *code) 507 { 508 if (code->index > 0) 509 return -EINVAL; 510 511 code->code = MEDIA_BUS_FMT_Y8_1X8; 512 513 return 0; 514 } 515 516 static int og0ve1b_enum_frame_size(struct v4l2_subdev *sd, 517 struct v4l2_subdev_state *sd_state, 518 struct v4l2_subdev_frame_size_enum *fse) 519 { 520 if (fse->index >= ARRAY_SIZE(supported_modes)) 521 return -EINVAL; 522 523 if (fse->code != MEDIA_BUS_FMT_Y8_1X8) 524 return -EINVAL; 525 526 fse->min_width = supported_modes[fse->index].width; 527 fse->max_width = fse->min_width; 528 fse->min_height = supported_modes[fse->index].height; 529 fse->max_height = fse->min_height; 530 531 return 0; 532 } 533 534 static int og0ve1b_init_state(struct v4l2_subdev *sd, 535 struct v4l2_subdev_state *state) 536 { 537 struct v4l2_subdev_format fmt = { 538 .which = V4L2_SUBDEV_FORMAT_TRY, 539 .pad = 0, 540 .format = { 541 .code = MEDIA_BUS_FMT_Y8_1X8, 542 .width = supported_modes[0].width, 543 .height = supported_modes[0].height, 544 }, 545 }; 546 547 og0ve1b_set_pad_format(sd, state, &fmt); 548 549 return 0; 550 } 551 552 static const struct v4l2_subdev_video_ops og0ve1b_video_ops = { 553 .s_stream = v4l2_subdev_s_stream_helper, 554 }; 555 556 static const struct v4l2_subdev_pad_ops og0ve1b_pad_ops = { 557 .set_fmt = og0ve1b_set_pad_format, 558 .get_fmt = v4l2_subdev_get_fmt, 559 .enum_mbus_code = og0ve1b_enum_mbus_code, 560 .enum_frame_size = og0ve1b_enum_frame_size, 561 .enable_streams = og0ve1b_enable_streams, 562 .disable_streams = og0ve1b_disable_streams, 563 }; 564 565 static const struct v4l2_subdev_ops og0ve1b_subdev_ops = { 566 .video = &og0ve1b_video_ops, 567 .pad = &og0ve1b_pad_ops, 568 }; 569 570 static const struct v4l2_subdev_internal_ops og0ve1b_internal_ops = { 571 .init_state = og0ve1b_init_state, 572 }; 573 574 static const struct media_entity_operations og0ve1b_subdev_entity_ops = { 575 .link_validate = v4l2_subdev_link_validate, 576 }; 577 578 static int og0ve1b_identify_sensor(struct og0ve1b *og0ve1b) 579 { 580 u64 val; 581 int ret; 582 583 ret = cci_read(og0ve1b->regmap, OG0VE1B_REG_CHIP_ID, &val, NULL); 584 if (ret) { 585 dev_err(og0ve1b->dev, "failed to read chip id: %d\n", ret); 586 return ret; 587 } 588 589 if (val != OG0VE1B_CHIP_ID) { 590 dev_err(og0ve1b->dev, "chip id mismatch: %x!=%llx\n", 591 OG0VE1B_CHIP_ID, val); 592 return -ENODEV; 593 } 594 595 ret = cci_read(og0ve1b->regmap, OG0VE1B_REG_PRE_ISP, 596 &og0ve1b->pre_isp, NULL); 597 if (ret) 598 dev_err(og0ve1b->dev, "failed to read pre_isp: %d\n", ret); 599 600 return ret; 601 } 602 603 static int og0ve1b_check_hwcfg(struct og0ve1b *og0ve1b) 604 { 605 struct fwnode_handle *fwnode = dev_fwnode(og0ve1b->dev), *ep; 606 struct v4l2_fwnode_endpoint bus_cfg = { 607 .bus_type = V4L2_MBUS_CSI2_DPHY, 608 }; 609 unsigned long freq_bitmap; 610 int ret; 611 612 if (!fwnode) 613 return -ENODEV; 614 615 ep = fwnode_graph_get_next_endpoint(fwnode, NULL); 616 if (!ep) 617 return -EINVAL; 618 619 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); 620 fwnode_handle_put(ep); 621 if (ret) 622 return ret; 623 624 ret = v4l2_link_freq_to_bitmap(og0ve1b->dev, 625 bus_cfg.link_frequencies, 626 bus_cfg.nr_of_link_frequencies, 627 og0ve1b_link_freq_menu, 628 ARRAY_SIZE(og0ve1b_link_freq_menu), 629 &freq_bitmap); 630 631 v4l2_fwnode_endpoint_free(&bus_cfg); 632 633 return ret; 634 } 635 636 static int og0ve1b_power_on(struct device *dev) 637 { 638 struct v4l2_subdev *sd = dev_get_drvdata(dev); 639 struct og0ve1b *og0ve1b = to_og0ve1b(sd); 640 int ret; 641 642 ret = regulator_bulk_enable(OG0VE1B_NUM_SUPPLIES, og0ve1b->supplies); 643 if (ret) 644 return ret; 645 646 gpiod_set_value_cansleep(og0ve1b->reset_gpio, 0); 647 usleep_range(10 * USEC_PER_MSEC, 15 * USEC_PER_MSEC); 648 649 ret = clk_prepare_enable(og0ve1b->xvclk); 650 if (ret) 651 goto reset_gpio; 652 653 return 0; 654 655 reset_gpio: 656 gpiod_set_value_cansleep(og0ve1b->reset_gpio, 1); 657 658 regulator_bulk_disable(OG0VE1B_NUM_SUPPLIES, og0ve1b->supplies); 659 660 return ret; 661 } 662 663 static int og0ve1b_power_off(struct device *dev) 664 { 665 struct v4l2_subdev *sd = dev_get_drvdata(dev); 666 struct og0ve1b *og0ve1b = to_og0ve1b(sd); 667 668 clk_disable_unprepare(og0ve1b->xvclk); 669 670 gpiod_set_value_cansleep(og0ve1b->reset_gpio, 1); 671 672 regulator_bulk_disable(OG0VE1B_NUM_SUPPLIES, og0ve1b->supplies); 673 674 return 0; 675 } 676 677 static int og0ve1b_probe(struct i2c_client *client) 678 { 679 struct og0ve1b *og0ve1b; 680 unsigned long freq; 681 unsigned int i; 682 int ret; 683 684 og0ve1b = devm_kzalloc(&client->dev, sizeof(*og0ve1b), GFP_KERNEL); 685 if (!og0ve1b) 686 return -ENOMEM; 687 688 og0ve1b->dev = &client->dev; 689 690 v4l2_i2c_subdev_init(&og0ve1b->sd, client, &og0ve1b_subdev_ops); 691 692 og0ve1b->regmap = devm_cci_regmap_init_i2c(client, 16); 693 if (IS_ERR(og0ve1b->regmap)) 694 return dev_err_probe(og0ve1b->dev, PTR_ERR(og0ve1b->regmap), 695 "failed to init CCI\n"); 696 697 og0ve1b->xvclk = devm_v4l2_sensor_clk_get(og0ve1b->dev, NULL); 698 if (IS_ERR(og0ve1b->xvclk)) 699 return dev_err_probe(og0ve1b->dev, PTR_ERR(og0ve1b->xvclk), 700 "failed to get XVCLK clock\n"); 701 702 freq = clk_get_rate(og0ve1b->xvclk); 703 if (freq && freq != OG0VE1B_MCLK_FREQ_24MHZ) 704 return dev_err_probe(og0ve1b->dev, -EINVAL, 705 "XVCLK clock frequency %lu is not supported\n", 706 freq); 707 708 ret = og0ve1b_check_hwcfg(og0ve1b); 709 if (ret) 710 return dev_err_probe(og0ve1b->dev, ret, 711 "failed to check HW configuration\n"); 712 713 og0ve1b->reset_gpio = devm_gpiod_get_optional(og0ve1b->dev, "reset", 714 GPIOD_OUT_HIGH); 715 if (IS_ERR(og0ve1b->reset_gpio)) 716 return dev_err_probe(og0ve1b->dev, PTR_ERR(og0ve1b->reset_gpio), 717 "cannot get reset GPIO\n"); 718 719 for (i = 0; i < OG0VE1B_NUM_SUPPLIES; i++) 720 og0ve1b->supplies[i].supply = og0ve1b_supply_names[i]; 721 722 ret = devm_regulator_bulk_get(og0ve1b->dev, OG0VE1B_NUM_SUPPLIES, 723 og0ve1b->supplies); 724 if (ret) 725 return dev_err_probe(og0ve1b->dev, ret, 726 "failed to get supply regulators\n"); 727 728 /* The sensor must be powered on to read the CHIP_ID register */ 729 ret = og0ve1b_power_on(og0ve1b->dev); 730 if (ret) 731 return ret; 732 733 ret = og0ve1b_identify_sensor(og0ve1b); 734 if (ret) { 735 dev_err_probe(og0ve1b->dev, ret, "failed to find sensor\n"); 736 goto power_off; 737 } 738 739 ret = og0ve1b_init_controls(og0ve1b); 740 if (ret) { 741 dev_err_probe(og0ve1b->dev, ret, "failed to init controls\n"); 742 goto power_off; 743 } 744 745 og0ve1b->sd.state_lock = og0ve1b->ctrl_handler.lock; 746 og0ve1b->sd.internal_ops = &og0ve1b_internal_ops; 747 og0ve1b->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 748 og0ve1b->sd.entity.ops = &og0ve1b_subdev_entity_ops; 749 og0ve1b->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 750 og0ve1b->pad.flags = MEDIA_PAD_FL_SOURCE; 751 752 ret = media_entity_pads_init(&og0ve1b->sd.entity, 1, &og0ve1b->pad); 753 if (ret) { 754 dev_err_probe(og0ve1b->dev, ret, 755 "failed to init media entity pads\n"); 756 goto v4l2_ctrl_handler_free; 757 } 758 759 ret = v4l2_subdev_init_finalize(&og0ve1b->sd); 760 if (ret < 0) { 761 dev_err_probe(og0ve1b->dev, ret, 762 "failed to init media entity pads\n"); 763 goto media_entity_cleanup; 764 } 765 766 pm_runtime_set_active(og0ve1b->dev); 767 pm_runtime_enable(og0ve1b->dev); 768 769 ret = v4l2_async_register_subdev_sensor(&og0ve1b->sd); 770 if (ret < 0) { 771 dev_err_probe(og0ve1b->dev, ret, 772 "failed to register V4L2 subdev\n"); 773 goto subdev_cleanup; 774 } 775 776 /* Enable runtime PM and turn off the device */ 777 pm_runtime_idle(og0ve1b->dev); 778 pm_runtime_set_autosuspend_delay(og0ve1b->dev, 1000); 779 pm_runtime_use_autosuspend(og0ve1b->dev); 780 781 return 0; 782 783 subdev_cleanup: 784 v4l2_subdev_cleanup(&og0ve1b->sd); 785 pm_runtime_disable(og0ve1b->dev); 786 pm_runtime_set_suspended(og0ve1b->dev); 787 788 media_entity_cleanup: 789 media_entity_cleanup(&og0ve1b->sd.entity); 790 791 v4l2_ctrl_handler_free: 792 v4l2_ctrl_handler_free(og0ve1b->sd.ctrl_handler); 793 794 power_off: 795 og0ve1b_power_off(og0ve1b->dev); 796 797 return ret; 798 } 799 800 static void og0ve1b_remove(struct i2c_client *client) 801 { 802 struct v4l2_subdev *sd = i2c_get_clientdata(client); 803 struct og0ve1b *og0ve1b = to_og0ve1b(sd); 804 805 v4l2_async_unregister_subdev(sd); 806 v4l2_subdev_cleanup(sd); 807 media_entity_cleanup(&sd->entity); 808 v4l2_ctrl_handler_free(sd->ctrl_handler); 809 pm_runtime_disable(og0ve1b->dev); 810 811 if (!pm_runtime_status_suspended(og0ve1b->dev)) { 812 og0ve1b_power_off(og0ve1b->dev); 813 pm_runtime_set_suspended(og0ve1b->dev); 814 } 815 } 816 817 static const struct dev_pm_ops og0ve1b_pm_ops = { 818 SET_RUNTIME_PM_OPS(og0ve1b_power_off, og0ve1b_power_on, NULL) 819 }; 820 821 static const struct of_device_id og0ve1b_of_match[] = { 822 { .compatible = "ovti,og0ve1b" }, 823 { /* sentinel */ } 824 }; 825 MODULE_DEVICE_TABLE(of, og0ve1b_of_match); 826 827 static struct i2c_driver og0ve1b_i2c_driver = { 828 .driver = { 829 .name = "og0ve1b", 830 .pm = &og0ve1b_pm_ops, 831 .of_match_table = og0ve1b_of_match, 832 }, 833 .probe = og0ve1b_probe, 834 .remove = og0ve1b_remove, 835 }; 836 837 module_i2c_driver(og0ve1b_i2c_driver); 838 839 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>"); 840 MODULE_DESCRIPTION("OmniVision OG0VE1B sensor driver"); 841 MODULE_LICENSE("GPL"); 842