1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for MT9V022, MT9V024, MT9V032, and MT9V034 CMOS Image Sensors 4 * 5 * Copyright (C) 2010, Laurent Pinchart <laurent.pinchart@ideasonboard.com> 6 * 7 * Based on the MT9M001 driver, 8 * 9 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/i2c.h> 16 #include <linux/log2.h> 17 #include <linux/module.h> 18 #include <linux/mutex.h> 19 #include <linux/of.h> 20 #include <linux/of_graph.h> 21 #include <linux/regmap.h> 22 #include <linux/slab.h> 23 #include <linux/v4l2-mediabus.h> 24 #include <linux/videodev2.h> 25 26 #include <media/v4l2-ctrls.h> 27 #include <media/v4l2-device.h> 28 #include <media/v4l2-fwnode.h> 29 #include <media/v4l2-subdev.h> 30 31 /* The first four rows are black rows. The active area spans 753x481 pixels. */ 32 #define MT9V032_PIXEL_ARRAY_HEIGHT 485 33 #define MT9V032_PIXEL_ARRAY_WIDTH 753 34 35 #define MT9V032_SYSCLK_FREQ_DEF 26600000 36 37 #define MT9V032_CHIP_VERSION 0x00 38 #define MT9V032_CHIP_ID_REV1 0x1311 39 #define MT9V032_CHIP_ID_REV3 0x1313 40 #define MT9V034_CHIP_ID_REV1 0X1324 41 #define MT9V032_COLUMN_START 0x01 42 #define MT9V032_COLUMN_START_MIN 1 43 #define MT9V032_COLUMN_START_DEF 1 44 #define MT9V032_COLUMN_START_MAX 752 45 #define MT9V032_ROW_START 0x02 46 #define MT9V032_ROW_START_MIN 4 47 #define MT9V032_ROW_START_DEF 5 48 #define MT9V032_ROW_START_MAX 482 49 #define MT9V032_WINDOW_HEIGHT 0x03 50 #define MT9V032_WINDOW_HEIGHT_MIN 1 51 #define MT9V032_WINDOW_HEIGHT_DEF 480 52 #define MT9V032_WINDOW_HEIGHT_MAX 480 53 #define MT9V032_WINDOW_WIDTH 0x04 54 #define MT9V032_WINDOW_WIDTH_MIN 1 55 #define MT9V032_WINDOW_WIDTH_DEF 752 56 #define MT9V032_WINDOW_WIDTH_MAX 752 57 #define MT9V032_HORIZONTAL_BLANKING 0x05 58 #define MT9V032_HORIZONTAL_BLANKING_MIN 43 59 #define MT9V034_HORIZONTAL_BLANKING_MIN 61 60 #define MT9V032_HORIZONTAL_BLANKING_DEF 94 61 #define MT9V032_HORIZONTAL_BLANKING_MAX 1023 62 #define MT9V032_VERTICAL_BLANKING 0x06 63 #define MT9V032_VERTICAL_BLANKING_MIN 4 64 #define MT9V034_VERTICAL_BLANKING_MIN 2 65 #define MT9V032_VERTICAL_BLANKING_DEF 45 66 #define MT9V032_VERTICAL_BLANKING_MAX 3000 67 #define MT9V034_VERTICAL_BLANKING_MAX 32288 68 #define MT9V032_CHIP_CONTROL 0x07 69 #define MT9V032_CHIP_CONTROL_MASTER_MODE (1 << 3) 70 #define MT9V032_CHIP_CONTROL_DOUT_ENABLE (1 << 7) 71 #define MT9V032_CHIP_CONTROL_SEQUENTIAL (1 << 8) 72 #define MT9V032_SHUTTER_WIDTH1 0x08 73 #define MT9V032_SHUTTER_WIDTH2 0x09 74 #define MT9V032_SHUTTER_WIDTH_CONTROL 0x0a 75 #define MT9V032_TOTAL_SHUTTER_WIDTH 0x0b 76 #define MT9V032_TOTAL_SHUTTER_WIDTH_MIN 1 77 #define MT9V034_TOTAL_SHUTTER_WIDTH_MIN 0 78 #define MT9V032_TOTAL_SHUTTER_WIDTH_DEF 480 79 #define MT9V032_TOTAL_SHUTTER_WIDTH_MAX 32767 80 #define MT9V034_TOTAL_SHUTTER_WIDTH_MAX 32765 81 #define MT9V032_RESET 0x0c 82 #define MT9V032_READ_MODE 0x0d 83 #define MT9V032_READ_MODE_ROW_BIN_MASK (3 << 0) 84 #define MT9V032_READ_MODE_ROW_BIN_SHIFT 0 85 #define MT9V032_READ_MODE_COLUMN_BIN_MASK (3 << 2) 86 #define MT9V032_READ_MODE_COLUMN_BIN_SHIFT 2 87 #define MT9V032_READ_MODE_ROW_FLIP (1 << 4) 88 #define MT9V032_READ_MODE_COLUMN_FLIP (1 << 5) 89 #define MT9V032_READ_MODE_DARK_COLUMNS (1 << 6) 90 #define MT9V032_READ_MODE_DARK_ROWS (1 << 7) 91 #define MT9V032_READ_MODE_RESERVED 0x0300 92 #define MT9V032_PIXEL_OPERATION_MODE 0x0f 93 #define MT9V034_PIXEL_OPERATION_MODE_HDR (1 << 0) 94 #define MT9V034_PIXEL_OPERATION_MODE_COLOR (1 << 1) 95 #define MT9V032_PIXEL_OPERATION_MODE_COLOR (1 << 2) 96 #define MT9V032_PIXEL_OPERATION_MODE_HDR (1 << 6) 97 #define MT9V032_ANALOG_GAIN 0x35 98 #define MT9V032_ANALOG_GAIN_MIN 16 99 #define MT9V032_ANALOG_GAIN_DEF 16 100 #define MT9V032_ANALOG_GAIN_MAX 64 101 #define MT9V032_MAX_ANALOG_GAIN 0x36 102 #define MT9V032_MAX_ANALOG_GAIN_MAX 127 103 #define MT9V032_FRAME_DARK_AVERAGE 0x42 104 #define MT9V032_DARK_AVG_THRESH 0x46 105 #define MT9V032_DARK_AVG_LOW_THRESH_MASK (255 << 0) 106 #define MT9V032_DARK_AVG_LOW_THRESH_SHIFT 0 107 #define MT9V032_DARK_AVG_HIGH_THRESH_MASK (255 << 8) 108 #define MT9V032_DARK_AVG_HIGH_THRESH_SHIFT 8 109 #define MT9V032_ROW_NOISE_CORR_CONTROL 0x70 110 #define MT9V034_ROW_NOISE_CORR_ENABLE (1 << 0) 111 #define MT9V034_ROW_NOISE_CORR_USE_BLK_AVG (1 << 1) 112 #define MT9V032_ROW_NOISE_CORR_ENABLE (1 << 5) 113 #define MT9V032_ROW_NOISE_CORR_USE_BLK_AVG (1 << 7) 114 #define MT9V032_PIXEL_CLOCK 0x74 115 #define MT9V034_PIXEL_CLOCK 0x72 116 #define MT9V032_PIXEL_CLOCK_INV_LINE (1 << 0) 117 #define MT9V032_PIXEL_CLOCK_INV_FRAME (1 << 1) 118 #define MT9V032_PIXEL_CLOCK_XOR_LINE (1 << 2) 119 #define MT9V032_PIXEL_CLOCK_CONT_LINE (1 << 3) 120 #define MT9V032_PIXEL_CLOCK_INV_PXL_CLK (1 << 4) 121 #define MT9V032_TEST_PATTERN 0x7f 122 #define MT9V032_TEST_PATTERN_DATA_MASK (1023 << 0) 123 #define MT9V032_TEST_PATTERN_DATA_SHIFT 0 124 #define MT9V032_TEST_PATTERN_USE_DATA (1 << 10) 125 #define MT9V032_TEST_PATTERN_GRAY_MASK (3 << 11) 126 #define MT9V032_TEST_PATTERN_GRAY_NONE (0 << 11) 127 #define MT9V032_TEST_PATTERN_GRAY_VERTICAL (1 << 11) 128 #define MT9V032_TEST_PATTERN_GRAY_HORIZONTAL (2 << 11) 129 #define MT9V032_TEST_PATTERN_GRAY_DIAGONAL (3 << 11) 130 #define MT9V032_TEST_PATTERN_ENABLE (1 << 13) 131 #define MT9V032_TEST_PATTERN_FLIP (1 << 14) 132 #define MT9V032_AEGC_DESIRED_BIN 0xa5 133 #define MT9V032_AEC_UPDATE_FREQUENCY 0xa6 134 #define MT9V032_AEC_LPF 0xa8 135 #define MT9V032_AGC_UPDATE_FREQUENCY 0xa9 136 #define MT9V032_AGC_LPF 0xaa 137 #define MT9V032_AEC_AGC_ENABLE 0xaf 138 #define MT9V032_AEC_ENABLE (1 << 0) 139 #define MT9V032_AGC_ENABLE (1 << 1) 140 #define MT9V034_AEC_MAX_SHUTTER_WIDTH 0xad 141 #define MT9V032_AEC_MAX_SHUTTER_WIDTH 0xbd 142 #define MT9V032_THERMAL_INFO 0xc1 143 144 enum mt9v032_model { 145 MT9V032_MODEL_V022_COLOR, /* MT9V022IX7ATC */ 146 MT9V032_MODEL_V022_MONO, /* MT9V022IX7ATM */ 147 MT9V032_MODEL_V024_COLOR, /* MT9V024IA7XTC */ 148 MT9V032_MODEL_V024_MONO, /* MT9V024IA7XTM */ 149 MT9V032_MODEL_V032_COLOR, /* MT9V032C12STM */ 150 MT9V032_MODEL_V032_MONO, /* MT9V032C12STC */ 151 MT9V032_MODEL_V034_COLOR, 152 MT9V032_MODEL_V034_MONO, 153 }; 154 155 struct mt9v032_model_version { 156 unsigned int version; 157 const char *name; 158 }; 159 160 struct mt9v032_model_data { 161 unsigned int min_row_time; 162 unsigned int min_hblank; 163 unsigned int min_vblank; 164 unsigned int max_vblank; 165 unsigned int min_shutter; 166 unsigned int max_shutter; 167 unsigned int pclk_reg; 168 unsigned int aec_max_shutter_reg; 169 const struct v4l2_ctrl_config * const aec_max_shutter_v4l2_ctrl; 170 }; 171 172 struct mt9v032_model_info { 173 const struct mt9v032_model_data *data; 174 bool color; 175 }; 176 177 static const struct mt9v032_model_version mt9v032_versions[] = { 178 { MT9V032_CHIP_ID_REV1, "MT9V022/MT9V032 rev1/2" }, 179 { MT9V032_CHIP_ID_REV3, "MT9V022/MT9V032 rev3" }, 180 { MT9V034_CHIP_ID_REV1, "MT9V024/MT9V034 rev1" }, 181 }; 182 183 struct mt9v032_platform_data { 184 unsigned int clk_pol:1; 185 186 const s64 *link_freqs; 187 s64 link_def_freq; 188 }; 189 190 struct mt9v032 { 191 struct device *dev; 192 193 struct v4l2_subdev subdev; 194 struct media_pad pad; 195 196 struct v4l2_mbus_framefmt format; 197 struct v4l2_rect crop; 198 unsigned int hratio; 199 unsigned int vratio; 200 201 struct v4l2_ctrl_handler ctrls; 202 struct { 203 struct v4l2_ctrl *link_freq; 204 struct v4l2_ctrl *pixel_rate; 205 }; 206 207 struct mutex power_lock; 208 int power_count; 209 210 struct regmap *regmap; 211 struct clk *clk; 212 struct gpio_desc *reset_gpio; 213 struct gpio_desc *standby_gpio; 214 215 struct mt9v032_platform_data pdata; 216 const struct mt9v032_model_info *model; 217 const struct mt9v032_model_version *version; 218 219 u32 sysclk; 220 u16 aec_agc; 221 u16 hblank; 222 struct { 223 struct v4l2_ctrl *test_pattern; 224 struct v4l2_ctrl *test_pattern_color; 225 }; 226 }; 227 228 static struct mt9v032 *to_mt9v032(struct v4l2_subdev *sd) 229 { 230 return container_of(sd, struct mt9v032, subdev); 231 } 232 233 static int 234 mt9v032_update_aec_agc(struct mt9v032 *mt9v032, u16 which, int enable) 235 { 236 struct regmap *map = mt9v032->regmap; 237 u16 value = mt9v032->aec_agc; 238 int ret; 239 240 if (enable) 241 value |= which; 242 else 243 value &= ~which; 244 245 ret = regmap_write(map, MT9V032_AEC_AGC_ENABLE, value); 246 if (ret < 0) 247 return ret; 248 249 mt9v032->aec_agc = value; 250 return 0; 251 } 252 253 static int 254 mt9v032_update_hblank(struct mt9v032 *mt9v032) 255 { 256 struct v4l2_rect *crop = &mt9v032->crop; 257 unsigned int min_hblank = mt9v032->model->data->min_hblank; 258 unsigned int hblank; 259 260 if (mt9v032->version->version == MT9V034_CHIP_ID_REV1) 261 min_hblank += (mt9v032->hratio - 1) * 10; 262 min_hblank = max_t(int, mt9v032->model->data->min_row_time - crop->width, 263 min_hblank); 264 hblank = max_t(unsigned int, mt9v032->hblank, min_hblank); 265 266 return regmap_write(mt9v032->regmap, MT9V032_HORIZONTAL_BLANKING, 267 hblank); 268 } 269 270 static int mt9v032_power_on(struct mt9v032 *mt9v032) 271 { 272 struct regmap *map = mt9v032->regmap; 273 int ret; 274 275 gpiod_set_value_cansleep(mt9v032->reset_gpio, 1); 276 277 ret = clk_set_rate(mt9v032->clk, mt9v032->sysclk); 278 if (ret < 0) 279 return ret; 280 281 /* System clock has to be enabled before releasing the reset */ 282 ret = clk_prepare_enable(mt9v032->clk); 283 if (ret) 284 return ret; 285 286 udelay(1); 287 288 if (mt9v032->reset_gpio) { 289 gpiod_set_value_cansleep(mt9v032->reset_gpio, 0); 290 291 /* After releasing reset we need to wait 10 clock cycles 292 * before accessing the sensor over I2C. As the minimum SYSCLK 293 * frequency is 13MHz, waiting 1µs will be enough in the worst 294 * case. 295 */ 296 udelay(1); 297 } 298 299 /* Reset the chip and stop data read out */ 300 ret = regmap_write(map, MT9V032_RESET, 1); 301 if (ret < 0) 302 goto err; 303 304 ret = regmap_write(map, MT9V032_RESET, 0); 305 if (ret < 0) 306 goto err; 307 308 ret = regmap_write(map, MT9V032_CHIP_CONTROL, 309 MT9V032_CHIP_CONTROL_MASTER_MODE); 310 if (ret < 0) 311 goto err; 312 313 return 0; 314 315 err: 316 clk_disable_unprepare(mt9v032->clk); 317 return ret; 318 } 319 320 static void mt9v032_power_off(struct mt9v032 *mt9v032) 321 { 322 clk_disable_unprepare(mt9v032->clk); 323 } 324 325 static int __mt9v032_set_power(struct mt9v032 *mt9v032, bool on) 326 { 327 struct regmap *map = mt9v032->regmap; 328 int ret; 329 330 if (!on) { 331 mt9v032_power_off(mt9v032); 332 return 0; 333 } 334 335 ret = mt9v032_power_on(mt9v032); 336 if (ret < 0) 337 return ret; 338 339 /* Configure the pixel clock polarity */ 340 if (mt9v032->pdata.clk_pol) { 341 ret = regmap_write(map, mt9v032->model->data->pclk_reg, 342 MT9V032_PIXEL_CLOCK_INV_PXL_CLK); 343 if (ret < 0) 344 return ret; 345 } 346 347 /* Disable the noise correction algorithm and restore the controls. */ 348 ret = regmap_write(map, MT9V032_ROW_NOISE_CORR_CONTROL, 0); 349 if (ret < 0) 350 return ret; 351 352 return v4l2_ctrl_handler_setup(&mt9v032->ctrls); 353 } 354 355 /* ----------------------------------------------------------------------------- 356 * V4L2 subdev video operations 357 */ 358 359 static struct v4l2_mbus_framefmt * 360 __mt9v032_get_pad_format(struct mt9v032 *mt9v032, 361 struct v4l2_subdev_state *sd_state, 362 unsigned int pad, enum v4l2_subdev_format_whence which) 363 { 364 switch (which) { 365 case V4L2_SUBDEV_FORMAT_TRY: 366 return v4l2_subdev_state_get_format(sd_state, pad); 367 case V4L2_SUBDEV_FORMAT_ACTIVE: 368 return &mt9v032->format; 369 default: 370 return NULL; 371 } 372 } 373 374 static struct v4l2_rect * 375 __mt9v032_get_pad_crop(struct mt9v032 *mt9v032, 376 struct v4l2_subdev_state *sd_state, 377 unsigned int pad, enum v4l2_subdev_format_whence which) 378 { 379 switch (which) { 380 case V4L2_SUBDEV_FORMAT_TRY: 381 return v4l2_subdev_state_get_crop(sd_state, pad); 382 case V4L2_SUBDEV_FORMAT_ACTIVE: 383 return &mt9v032->crop; 384 default: 385 return NULL; 386 } 387 } 388 389 static int mt9v032_s_stream(struct v4l2_subdev *subdev, int enable) 390 { 391 const u16 mode = MT9V032_CHIP_CONTROL_DOUT_ENABLE 392 | MT9V032_CHIP_CONTROL_SEQUENTIAL; 393 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 394 struct v4l2_rect *crop = &mt9v032->crop; 395 struct regmap *map = mt9v032->regmap; 396 unsigned int hbin; 397 unsigned int vbin; 398 int ret; 399 400 if (!enable) 401 return regmap_update_bits(map, MT9V032_CHIP_CONTROL, mode, 0); 402 403 /* Configure the window size and row/column bin */ 404 hbin = fls(mt9v032->hratio) - 1; 405 vbin = fls(mt9v032->vratio) - 1; 406 ret = regmap_update_bits(map, MT9V032_READ_MODE, 407 ~MT9V032_READ_MODE_RESERVED, 408 hbin << MT9V032_READ_MODE_COLUMN_BIN_SHIFT | 409 vbin << MT9V032_READ_MODE_ROW_BIN_SHIFT); 410 if (ret < 0) 411 return ret; 412 413 ret = regmap_write(map, MT9V032_COLUMN_START, crop->left); 414 if (ret < 0) 415 return ret; 416 417 ret = regmap_write(map, MT9V032_ROW_START, crop->top); 418 if (ret < 0) 419 return ret; 420 421 ret = regmap_write(map, MT9V032_WINDOW_WIDTH, crop->width); 422 if (ret < 0) 423 return ret; 424 425 ret = regmap_write(map, MT9V032_WINDOW_HEIGHT, crop->height); 426 if (ret < 0) 427 return ret; 428 429 ret = mt9v032_update_hblank(mt9v032); 430 if (ret < 0) 431 return ret; 432 433 /* Switch to master "normal" mode */ 434 return regmap_update_bits(map, MT9V032_CHIP_CONTROL, mode, mode); 435 } 436 437 static int mt9v032_enum_mbus_code(struct v4l2_subdev *subdev, 438 struct v4l2_subdev_state *sd_state, 439 struct v4l2_subdev_mbus_code_enum *code) 440 { 441 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 442 443 if (code->index > 0) 444 return -EINVAL; 445 446 code->code = mt9v032->format.code; 447 return 0; 448 } 449 450 static int mt9v032_enum_frame_size(struct v4l2_subdev *subdev, 451 struct v4l2_subdev_state *sd_state, 452 struct v4l2_subdev_frame_size_enum *fse) 453 { 454 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 455 456 if (fse->index >= 3) 457 return -EINVAL; 458 if (mt9v032->format.code != fse->code) 459 return -EINVAL; 460 461 fse->min_width = MT9V032_WINDOW_WIDTH_DEF / (1 << fse->index); 462 fse->max_width = fse->min_width; 463 fse->min_height = MT9V032_WINDOW_HEIGHT_DEF / (1 << fse->index); 464 fse->max_height = fse->min_height; 465 466 return 0; 467 } 468 469 static int mt9v032_get_format(struct v4l2_subdev *subdev, 470 struct v4l2_subdev_state *sd_state, 471 struct v4l2_subdev_format *format) 472 { 473 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 474 475 format->format = *__mt9v032_get_pad_format(mt9v032, sd_state, 476 format->pad, 477 format->which); 478 return 0; 479 } 480 481 static void mt9v032_configure_pixel_rate(struct mt9v032 *mt9v032) 482 { 483 int ret; 484 485 ret = v4l2_ctrl_s_ctrl_int64(mt9v032->pixel_rate, 486 mt9v032->sysclk / mt9v032->hratio); 487 if (ret < 0) 488 dev_warn(mt9v032->dev, "failed to set pixel rate (%d)\n", ret); 489 } 490 491 static unsigned int mt9v032_calc_ratio(unsigned int input, unsigned int output) 492 { 493 /* Compute the power-of-two binning factor closest to the input size to 494 * output size ratio. Given that the output size is bounded by input/4 495 * and input, a generic implementation would be an ineffective luxury. 496 */ 497 if (output * 3 > input * 2) 498 return 1; 499 if (output * 3 > input) 500 return 2; 501 return 4; 502 } 503 504 static int mt9v032_set_format(struct v4l2_subdev *subdev, 505 struct v4l2_subdev_state *sd_state, 506 struct v4l2_subdev_format *format) 507 { 508 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 509 struct v4l2_mbus_framefmt *__format; 510 struct v4l2_rect *__crop; 511 unsigned int width; 512 unsigned int height; 513 unsigned int hratio; 514 unsigned int vratio; 515 516 __crop = __mt9v032_get_pad_crop(mt9v032, sd_state, format->pad, 517 format->which); 518 519 /* Clamp the width and height to avoid dividing by zero. */ 520 width = clamp(ALIGN(format->format.width, 2), 521 max_t(unsigned int, __crop->width / 4, 522 MT9V032_WINDOW_WIDTH_MIN), 523 __crop->width); 524 height = clamp(ALIGN(format->format.height, 2), 525 max_t(unsigned int, __crop->height / 4, 526 MT9V032_WINDOW_HEIGHT_MIN), 527 __crop->height); 528 529 hratio = mt9v032_calc_ratio(__crop->width, width); 530 vratio = mt9v032_calc_ratio(__crop->height, height); 531 532 __format = __mt9v032_get_pad_format(mt9v032, sd_state, format->pad, 533 format->which); 534 __format->width = __crop->width / hratio; 535 __format->height = __crop->height / vratio; 536 537 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 538 mt9v032->hratio = hratio; 539 mt9v032->vratio = vratio; 540 mt9v032_configure_pixel_rate(mt9v032); 541 } 542 543 format->format = *__format; 544 545 return 0; 546 } 547 548 static int mt9v032_get_selection(struct v4l2_subdev *subdev, 549 struct v4l2_subdev_state *sd_state, 550 struct v4l2_subdev_selection *sel) 551 { 552 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 553 554 if (sel->target != V4L2_SEL_TGT_CROP) 555 return -EINVAL; 556 557 sel->r = *__mt9v032_get_pad_crop(mt9v032, sd_state, sel->pad, 558 sel->which); 559 return 0; 560 } 561 562 static int mt9v032_set_selection(struct v4l2_subdev *subdev, 563 struct v4l2_subdev_state *sd_state, 564 struct v4l2_subdev_selection *sel) 565 { 566 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 567 struct v4l2_mbus_framefmt *__format; 568 struct v4l2_rect *__crop; 569 struct v4l2_rect rect; 570 571 if (sel->target != V4L2_SEL_TGT_CROP) 572 return -EINVAL; 573 574 /* Clamp the crop rectangle boundaries and align them to a non multiple 575 * of 2 pixels to ensure a GRBG Bayer pattern. 576 */ 577 rect.left = clamp(ALIGN(sel->r.left + 1, 2) - 1, 578 MT9V032_COLUMN_START_MIN, 579 MT9V032_COLUMN_START_MAX); 580 rect.top = clamp(ALIGN(sel->r.top + 1, 2) - 1, 581 MT9V032_ROW_START_MIN, 582 MT9V032_ROW_START_MAX); 583 rect.width = clamp_t(unsigned int, ALIGN(sel->r.width, 2), 584 MT9V032_WINDOW_WIDTH_MIN, 585 MT9V032_WINDOW_WIDTH_MAX); 586 rect.height = clamp_t(unsigned int, ALIGN(sel->r.height, 2), 587 MT9V032_WINDOW_HEIGHT_MIN, 588 MT9V032_WINDOW_HEIGHT_MAX); 589 590 rect.width = min_t(unsigned int, 591 rect.width, MT9V032_PIXEL_ARRAY_WIDTH - rect.left); 592 rect.height = min_t(unsigned int, 593 rect.height, MT9V032_PIXEL_ARRAY_HEIGHT - rect.top); 594 595 __crop = __mt9v032_get_pad_crop(mt9v032, sd_state, sel->pad, 596 sel->which); 597 598 if (rect.width != __crop->width || rect.height != __crop->height) { 599 /* Reset the output image size if the crop rectangle size has 600 * been modified. 601 */ 602 __format = __mt9v032_get_pad_format(mt9v032, sd_state, 603 sel->pad, 604 sel->which); 605 __format->width = rect.width; 606 __format->height = rect.height; 607 if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 608 mt9v032->hratio = 1; 609 mt9v032->vratio = 1; 610 mt9v032_configure_pixel_rate(mt9v032); 611 } 612 } 613 614 *__crop = rect; 615 sel->r = rect; 616 617 return 0; 618 } 619 620 /* ----------------------------------------------------------------------------- 621 * V4L2 subdev control operations 622 */ 623 624 #define V4L2_CID_TEST_PATTERN_COLOR (V4L2_CID_USER_BASE | 0x1001) 625 /* 626 * Value between 1 and 64 to set the desired bin. This is effectively a measure 627 * of how bright the image is supposed to be. Both AGC and AEC try to reach 628 * this. 629 */ 630 #define V4L2_CID_AEGC_DESIRED_BIN (V4L2_CID_USER_BASE | 0x1002) 631 /* 632 * LPF is the low pass filter capability of the chip. Both AEC and AGC have 633 * this setting. This limits the speed in which AGC/AEC adjust their settings. 634 * Possible values are 0-2. 0 means no LPF. For 1 and 2 this equation is used: 635 * 636 * if |(calculated new exp - current exp)| > (current exp / 4) 637 * next exp = calculated new exp 638 * else 639 * next exp = current exp + ((calculated new exp - current exp) / 2^LPF) 640 */ 641 #define V4L2_CID_AEC_LPF (V4L2_CID_USER_BASE | 0x1003) 642 #define V4L2_CID_AGC_LPF (V4L2_CID_USER_BASE | 0x1004) 643 /* 644 * Value between 0 and 15. This is the number of frames being skipped before 645 * updating the auto exposure/gain. 646 */ 647 #define V4L2_CID_AEC_UPDATE_INTERVAL (V4L2_CID_USER_BASE | 0x1005) 648 #define V4L2_CID_AGC_UPDATE_INTERVAL (V4L2_CID_USER_BASE | 0x1006) 649 /* 650 * Maximum shutter width used for AEC. 651 */ 652 #define V4L2_CID_AEC_MAX_SHUTTER_WIDTH (V4L2_CID_USER_BASE | 0x1007) 653 654 static int mt9v032_s_ctrl(struct v4l2_ctrl *ctrl) 655 { 656 struct mt9v032 *mt9v032 = 657 container_of(ctrl->handler, struct mt9v032, ctrls); 658 struct regmap *map = mt9v032->regmap; 659 u32 freq; 660 u16 data; 661 662 switch (ctrl->id) { 663 case V4L2_CID_AUTOGAIN: 664 return mt9v032_update_aec_agc(mt9v032, MT9V032_AGC_ENABLE, 665 ctrl->val); 666 667 case V4L2_CID_GAIN: 668 return regmap_write(map, MT9V032_ANALOG_GAIN, ctrl->val); 669 670 case V4L2_CID_EXPOSURE_AUTO: 671 return mt9v032_update_aec_agc(mt9v032, MT9V032_AEC_ENABLE, 672 !ctrl->val); 673 674 case V4L2_CID_EXPOSURE: 675 return regmap_write(map, MT9V032_TOTAL_SHUTTER_WIDTH, 676 ctrl->val); 677 678 case V4L2_CID_HBLANK: 679 mt9v032->hblank = ctrl->val; 680 return mt9v032_update_hblank(mt9v032); 681 682 case V4L2_CID_VBLANK: 683 return regmap_write(map, MT9V032_VERTICAL_BLANKING, 684 ctrl->val); 685 686 case V4L2_CID_PIXEL_RATE: 687 case V4L2_CID_LINK_FREQ: 688 if (mt9v032->link_freq == NULL) 689 break; 690 691 freq = mt9v032->pdata.link_freqs[mt9v032->link_freq->val]; 692 *mt9v032->pixel_rate->p_new.p_s64 = freq; 693 mt9v032->sysclk = freq; 694 break; 695 696 case V4L2_CID_TEST_PATTERN: 697 switch (mt9v032->test_pattern->val) { 698 case 0: 699 data = 0; 700 break; 701 case 1: 702 data = MT9V032_TEST_PATTERN_GRAY_VERTICAL 703 | MT9V032_TEST_PATTERN_ENABLE; 704 break; 705 case 2: 706 data = MT9V032_TEST_PATTERN_GRAY_HORIZONTAL 707 | MT9V032_TEST_PATTERN_ENABLE; 708 break; 709 case 3: 710 data = MT9V032_TEST_PATTERN_GRAY_DIAGONAL 711 | MT9V032_TEST_PATTERN_ENABLE; 712 break; 713 default: 714 data = (mt9v032->test_pattern_color->val << 715 MT9V032_TEST_PATTERN_DATA_SHIFT) 716 | MT9V032_TEST_PATTERN_USE_DATA 717 | MT9V032_TEST_PATTERN_ENABLE 718 | MT9V032_TEST_PATTERN_FLIP; 719 break; 720 } 721 return regmap_write(map, MT9V032_TEST_PATTERN, data); 722 723 case V4L2_CID_AEGC_DESIRED_BIN: 724 return regmap_write(map, MT9V032_AEGC_DESIRED_BIN, ctrl->val); 725 726 case V4L2_CID_AEC_LPF: 727 return regmap_write(map, MT9V032_AEC_LPF, ctrl->val); 728 729 case V4L2_CID_AGC_LPF: 730 return regmap_write(map, MT9V032_AGC_LPF, ctrl->val); 731 732 case V4L2_CID_AEC_UPDATE_INTERVAL: 733 return regmap_write(map, MT9V032_AEC_UPDATE_FREQUENCY, 734 ctrl->val); 735 736 case V4L2_CID_AGC_UPDATE_INTERVAL: 737 return regmap_write(map, MT9V032_AGC_UPDATE_FREQUENCY, 738 ctrl->val); 739 740 case V4L2_CID_AEC_MAX_SHUTTER_WIDTH: 741 return regmap_write(map, 742 mt9v032->model->data->aec_max_shutter_reg, 743 ctrl->val); 744 } 745 746 return 0; 747 } 748 749 static const struct v4l2_ctrl_ops mt9v032_ctrl_ops = { 750 .s_ctrl = mt9v032_s_ctrl, 751 }; 752 753 static const char * const mt9v032_test_pattern_menu[] = { 754 "Disabled", 755 "Gray Vertical Shade", 756 "Gray Horizontal Shade", 757 "Gray Diagonal Shade", 758 "Plain", 759 }; 760 761 static const struct v4l2_ctrl_config mt9v032_test_pattern_color = { 762 .ops = &mt9v032_ctrl_ops, 763 .id = V4L2_CID_TEST_PATTERN_COLOR, 764 .type = V4L2_CTRL_TYPE_INTEGER, 765 .name = "Test Pattern Color", 766 .min = 0, 767 .max = 1023, 768 .step = 1, 769 .def = 0, 770 .flags = 0, 771 }; 772 773 static const struct v4l2_ctrl_config mt9v032_aegc_controls[] = { 774 { 775 .ops = &mt9v032_ctrl_ops, 776 .id = V4L2_CID_AEGC_DESIRED_BIN, 777 .type = V4L2_CTRL_TYPE_INTEGER, 778 .name = "AEC/AGC Desired Bin", 779 .min = 1, 780 .max = 64, 781 .step = 1, 782 .def = 58, 783 .flags = 0, 784 }, { 785 .ops = &mt9v032_ctrl_ops, 786 .id = V4L2_CID_AEC_LPF, 787 .type = V4L2_CTRL_TYPE_INTEGER, 788 .name = "AEC Low Pass Filter", 789 .min = 0, 790 .max = 2, 791 .step = 1, 792 .def = 0, 793 .flags = 0, 794 }, { 795 .ops = &mt9v032_ctrl_ops, 796 .id = V4L2_CID_AGC_LPF, 797 .type = V4L2_CTRL_TYPE_INTEGER, 798 .name = "AGC Low Pass Filter", 799 .min = 0, 800 .max = 2, 801 .step = 1, 802 .def = 2, 803 .flags = 0, 804 }, { 805 .ops = &mt9v032_ctrl_ops, 806 .id = V4L2_CID_AEC_UPDATE_INTERVAL, 807 .type = V4L2_CTRL_TYPE_INTEGER, 808 .name = "AEC Update Interval", 809 .min = 0, 810 .max = 16, 811 .step = 1, 812 .def = 2, 813 .flags = 0, 814 }, { 815 .ops = &mt9v032_ctrl_ops, 816 .id = V4L2_CID_AGC_UPDATE_INTERVAL, 817 .type = V4L2_CTRL_TYPE_INTEGER, 818 .name = "AGC Update Interval", 819 .min = 0, 820 .max = 16, 821 .step = 1, 822 .def = 2, 823 .flags = 0, 824 } 825 }; 826 827 static const struct v4l2_ctrl_config mt9v032_aec_max_shutter_width = { 828 .ops = &mt9v032_ctrl_ops, 829 .id = V4L2_CID_AEC_MAX_SHUTTER_WIDTH, 830 .type = V4L2_CTRL_TYPE_INTEGER, 831 .name = "AEC Max Shutter Width", 832 .min = 1, 833 .max = 2047, 834 .step = 1, 835 .def = 480, 836 .flags = 0, 837 }; 838 839 static const struct v4l2_ctrl_config mt9v034_aec_max_shutter_width = { 840 .ops = &mt9v032_ctrl_ops, 841 .id = V4L2_CID_AEC_MAX_SHUTTER_WIDTH, 842 .type = V4L2_CTRL_TYPE_INTEGER, 843 .name = "AEC Max Shutter Width", 844 .min = 1, 845 .max = 32765, 846 .step = 1, 847 .def = 480, 848 .flags = 0, 849 }; 850 851 /* ----------------------------------------------------------------------------- 852 * V4L2 subdev core operations 853 */ 854 855 static int mt9v032_set_power(struct v4l2_subdev *subdev, int on) 856 { 857 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 858 int ret = 0; 859 860 mutex_lock(&mt9v032->power_lock); 861 862 /* If the power count is modified from 0 to != 0 or from != 0 to 0, 863 * update the power state. 864 */ 865 if (mt9v032->power_count == !on) { 866 ret = __mt9v032_set_power(mt9v032, !!on); 867 if (ret < 0) 868 goto done; 869 } 870 871 /* Update the power count. */ 872 mt9v032->power_count += on ? 1 : -1; 873 WARN_ON(mt9v032->power_count < 0); 874 875 done: 876 mutex_unlock(&mt9v032->power_lock); 877 return ret; 878 } 879 880 /* ----------------------------------------------------------------------------- 881 * V4L2 subdev internal operations 882 */ 883 884 static int mt9v032_registered(struct v4l2_subdev *subdev) 885 { 886 struct i2c_client *client = v4l2_get_subdevdata(subdev); 887 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 888 unsigned int i; 889 u32 version; 890 int ret; 891 892 dev_info(mt9v032->dev, "Probing MT9V032 at address 0x%02x\n", 893 client->addr); 894 895 ret = mt9v032_power_on(mt9v032); 896 if (ret < 0) { 897 dev_err(mt9v032->dev, "MT9V032 power up failed\n"); 898 return ret; 899 } 900 901 /* Read and check the sensor version */ 902 ret = regmap_read(mt9v032->regmap, MT9V032_CHIP_VERSION, &version); 903 904 mt9v032_power_off(mt9v032); 905 906 if (ret < 0) { 907 dev_err(mt9v032->dev, "Failed reading chip version\n"); 908 return ret; 909 } 910 911 for (i = 0; i < ARRAY_SIZE(mt9v032_versions); ++i) { 912 if (mt9v032_versions[i].version == version) { 913 mt9v032->version = &mt9v032_versions[i]; 914 break; 915 } 916 } 917 918 if (mt9v032->version == NULL) { 919 dev_err(mt9v032->dev, "Unsupported chip version 0x%04x\n", 920 version); 921 return -ENODEV; 922 } 923 924 dev_info(mt9v032->dev, "%s detected at address 0x%02x\n", 925 mt9v032->version->name, client->addr); 926 927 mt9v032_configure_pixel_rate(mt9v032); 928 929 return ret; 930 } 931 932 static int mt9v032_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh) 933 { 934 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 935 struct v4l2_mbus_framefmt *format; 936 struct v4l2_rect *crop; 937 938 crop = v4l2_subdev_state_get_crop(fh->state, 0); 939 crop->left = MT9V032_COLUMN_START_DEF; 940 crop->top = MT9V032_ROW_START_DEF; 941 crop->width = MT9V032_WINDOW_WIDTH_DEF; 942 crop->height = MT9V032_WINDOW_HEIGHT_DEF; 943 944 format = v4l2_subdev_state_get_format(fh->state, 0); 945 946 if (mt9v032->model->color) 947 format->code = MEDIA_BUS_FMT_SGRBG10_1X10; 948 else 949 format->code = MEDIA_BUS_FMT_Y10_1X10; 950 951 format->width = MT9V032_WINDOW_WIDTH_DEF; 952 format->height = MT9V032_WINDOW_HEIGHT_DEF; 953 format->field = V4L2_FIELD_NONE; 954 format->colorspace = V4L2_COLORSPACE_SRGB; 955 956 return mt9v032_set_power(subdev, 1); 957 } 958 959 static int mt9v032_close(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh) 960 { 961 return mt9v032_set_power(subdev, 0); 962 } 963 964 static const struct v4l2_subdev_core_ops mt9v032_subdev_core_ops = { 965 .s_power = mt9v032_set_power, 966 }; 967 968 static const struct v4l2_subdev_video_ops mt9v032_subdev_video_ops = { 969 .s_stream = mt9v032_s_stream, 970 }; 971 972 static const struct v4l2_subdev_pad_ops mt9v032_subdev_pad_ops = { 973 .enum_mbus_code = mt9v032_enum_mbus_code, 974 .enum_frame_size = mt9v032_enum_frame_size, 975 .get_fmt = mt9v032_get_format, 976 .set_fmt = mt9v032_set_format, 977 .get_selection = mt9v032_get_selection, 978 .set_selection = mt9v032_set_selection, 979 }; 980 981 static const struct v4l2_subdev_ops mt9v032_subdev_ops = { 982 .core = &mt9v032_subdev_core_ops, 983 .video = &mt9v032_subdev_video_ops, 984 .pad = &mt9v032_subdev_pad_ops, 985 }; 986 987 static const struct v4l2_subdev_internal_ops mt9v032_subdev_internal_ops = { 988 .registered = mt9v032_registered, 989 .open = mt9v032_open, 990 .close = mt9v032_close, 991 }; 992 993 static const struct regmap_config mt9v032_regmap_config = { 994 .reg_bits = 8, 995 .val_bits = 16, 996 .max_register = 0xff, 997 .cache_type = REGCACHE_MAPLE, 998 }; 999 1000 /* ----------------------------------------------------------------------------- 1001 * Driver initialization and probing 1002 */ 1003 1004 static int mt9v032_get_pdata(struct mt9v032 *mt9v032) 1005 { 1006 struct mt9v032_platform_data *pdata = &mt9v032->pdata; 1007 struct v4l2_fwnode_endpoint endpoint = { .bus_type = 0 }; 1008 struct device_node *np __free(device_node) = NULL; 1009 struct property *prop; 1010 1011 np = of_graph_get_endpoint_by_regs(mt9v032->dev->of_node, 0, -1); 1012 if (!np) 1013 return -EINVAL; 1014 1015 if (v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &endpoint) < 0) 1016 return -EINVAL; 1017 1018 prop = of_find_property(np, "link-frequencies", NULL); 1019 if (prop) { 1020 u64 *link_freqs; 1021 size_t size = prop->length / sizeof(*link_freqs); 1022 1023 link_freqs = devm_kcalloc(mt9v032->dev, size, 1024 sizeof(*link_freqs), GFP_KERNEL); 1025 if (!link_freqs) 1026 return -EINVAL; 1027 1028 if (of_property_read_u64_array(np, "link-frequencies", 1029 link_freqs, size) < 0) 1030 return -EINVAL; 1031 1032 pdata->link_freqs = link_freqs; 1033 pdata->link_def_freq = link_freqs[0]; 1034 } 1035 1036 pdata->clk_pol = !!(endpoint.bus.parallel.flags & 1037 V4L2_MBUS_PCLK_SAMPLE_RISING); 1038 1039 return 0; 1040 } 1041 1042 static int mt9v032_probe(struct i2c_client *client) 1043 { 1044 struct mt9v032 *mt9v032; 1045 unsigned int i; 1046 int ret; 1047 1048 mt9v032 = devm_kzalloc(&client->dev, sizeof(*mt9v032), GFP_KERNEL); 1049 if (!mt9v032) 1050 return -ENOMEM; 1051 1052 mt9v032->dev = &client->dev; 1053 1054 mt9v032->regmap = devm_regmap_init_i2c(client, &mt9v032_regmap_config); 1055 if (IS_ERR(mt9v032->regmap)) 1056 return PTR_ERR(mt9v032->regmap); 1057 1058 mt9v032->clk = devm_v4l2_sensor_clk_get(mt9v032->dev, NULL); 1059 if (IS_ERR(mt9v032->clk)) 1060 return dev_err_probe(mt9v032->dev, PTR_ERR(mt9v032->clk), 1061 "failed to get the clock\n"); 1062 1063 mt9v032->reset_gpio = devm_gpiod_get_optional(mt9v032->dev, "reset", 1064 GPIOD_OUT_HIGH); 1065 if (IS_ERR(mt9v032->reset_gpio)) 1066 return PTR_ERR(mt9v032->reset_gpio); 1067 1068 mt9v032->standby_gpio = devm_gpiod_get_optional(mt9v032->dev, "standby", 1069 GPIOD_OUT_LOW); 1070 if (IS_ERR(mt9v032->standby_gpio)) 1071 return PTR_ERR(mt9v032->standby_gpio); 1072 1073 mutex_init(&mt9v032->power_lock); 1074 1075 ret = mt9v032_get_pdata(mt9v032); 1076 if (ret) 1077 return dev_err_probe(mt9v032->dev, -EINVAL, 1078 "Failed to parse DT properties\n"); 1079 1080 mt9v032->model = device_get_match_data(mt9v032->dev); 1081 1082 v4l2_ctrl_handler_init(&mt9v032->ctrls, 11 + 1083 ARRAY_SIZE(mt9v032_aegc_controls)); 1084 1085 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops, 1086 V4L2_CID_AUTOGAIN, 0, 1, 1, 1); 1087 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops, 1088 V4L2_CID_GAIN, MT9V032_ANALOG_GAIN_MIN, 1089 MT9V032_ANALOG_GAIN_MAX, 1, MT9V032_ANALOG_GAIN_DEF); 1090 v4l2_ctrl_new_std_menu(&mt9v032->ctrls, &mt9v032_ctrl_ops, 1091 V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0, 1092 V4L2_EXPOSURE_AUTO); 1093 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops, 1094 V4L2_CID_EXPOSURE, mt9v032->model->data->min_shutter, 1095 mt9v032->model->data->max_shutter, 1, 1096 MT9V032_TOTAL_SHUTTER_WIDTH_DEF); 1097 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops, 1098 V4L2_CID_HBLANK, mt9v032->model->data->min_hblank, 1099 MT9V032_HORIZONTAL_BLANKING_MAX, 1, 1100 MT9V032_HORIZONTAL_BLANKING_DEF); 1101 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops, 1102 V4L2_CID_VBLANK, mt9v032->model->data->min_vblank, 1103 mt9v032->model->data->max_vblank, 1, 1104 MT9V032_VERTICAL_BLANKING_DEF); 1105 mt9v032->test_pattern = v4l2_ctrl_new_std_menu_items(&mt9v032->ctrls, 1106 &mt9v032_ctrl_ops, V4L2_CID_TEST_PATTERN, 1107 ARRAY_SIZE(mt9v032_test_pattern_menu) - 1, 0, 0, 1108 mt9v032_test_pattern_menu); 1109 mt9v032->test_pattern_color = v4l2_ctrl_new_custom(&mt9v032->ctrls, 1110 &mt9v032_test_pattern_color, NULL); 1111 1112 v4l2_ctrl_new_custom(&mt9v032->ctrls, 1113 mt9v032->model->data->aec_max_shutter_v4l2_ctrl, 1114 NULL); 1115 for (i = 0; i < ARRAY_SIZE(mt9v032_aegc_controls); ++i) 1116 v4l2_ctrl_new_custom(&mt9v032->ctrls, &mt9v032_aegc_controls[i], 1117 NULL); 1118 1119 v4l2_ctrl_cluster(2, &mt9v032->test_pattern); 1120 1121 mt9v032->pixel_rate = 1122 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops, 1123 V4L2_CID_PIXEL_RATE, 1, INT_MAX, 1, 1); 1124 1125 if (mt9v032->pdata.link_freqs) { 1126 const struct mt9v032_platform_data *pdata = &mt9v032->pdata; 1127 unsigned int def = 0; 1128 1129 for (i = 0; pdata->link_freqs[i]; ++i) { 1130 if (pdata->link_freqs[i] == pdata->link_def_freq) 1131 def = i; 1132 } 1133 1134 mt9v032->link_freq = 1135 v4l2_ctrl_new_int_menu(&mt9v032->ctrls, 1136 &mt9v032_ctrl_ops, 1137 V4L2_CID_LINK_FREQ, i - 1, def, 1138 pdata->link_freqs); 1139 v4l2_ctrl_cluster(2, &mt9v032->link_freq); 1140 } 1141 1142 1143 mt9v032->subdev.ctrl_handler = &mt9v032->ctrls; 1144 1145 if (mt9v032->ctrls.error) { 1146 dev_err(mt9v032->dev, "control initialization error %d\n", 1147 mt9v032->ctrls.error); 1148 ret = mt9v032->ctrls.error; 1149 goto err; 1150 } 1151 1152 mt9v032->crop.left = MT9V032_COLUMN_START_DEF; 1153 mt9v032->crop.top = MT9V032_ROW_START_DEF; 1154 mt9v032->crop.width = MT9V032_WINDOW_WIDTH_DEF; 1155 mt9v032->crop.height = MT9V032_WINDOW_HEIGHT_DEF; 1156 1157 if (mt9v032->model->color) 1158 mt9v032->format.code = MEDIA_BUS_FMT_SGRBG10_1X10; 1159 else 1160 mt9v032->format.code = MEDIA_BUS_FMT_Y10_1X10; 1161 1162 mt9v032->format.width = MT9V032_WINDOW_WIDTH_DEF; 1163 mt9v032->format.height = MT9V032_WINDOW_HEIGHT_DEF; 1164 mt9v032->format.field = V4L2_FIELD_NONE; 1165 mt9v032->format.colorspace = V4L2_COLORSPACE_SRGB; 1166 1167 mt9v032->hratio = 1; 1168 mt9v032->vratio = 1; 1169 1170 mt9v032->aec_agc = MT9V032_AEC_ENABLE | MT9V032_AGC_ENABLE; 1171 mt9v032->hblank = MT9V032_HORIZONTAL_BLANKING_DEF; 1172 mt9v032->sysclk = MT9V032_SYSCLK_FREQ_DEF; 1173 1174 v4l2_i2c_subdev_init(&mt9v032->subdev, client, &mt9v032_subdev_ops); 1175 mt9v032->subdev.internal_ops = &mt9v032_subdev_internal_ops; 1176 mt9v032->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1177 1178 mt9v032->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1179 mt9v032->pad.flags = MEDIA_PAD_FL_SOURCE; 1180 ret = media_entity_pads_init(&mt9v032->subdev.entity, 1, &mt9v032->pad); 1181 if (ret < 0) 1182 goto err; 1183 1184 mt9v032->subdev.dev = mt9v032->dev; 1185 ret = v4l2_async_register_subdev(&mt9v032->subdev); 1186 if (ret < 0) 1187 goto err; 1188 1189 return 0; 1190 1191 err: 1192 media_entity_cleanup(&mt9v032->subdev.entity); 1193 v4l2_ctrl_handler_free(&mt9v032->ctrls); 1194 return ret; 1195 } 1196 1197 static void mt9v032_remove(struct i2c_client *client) 1198 { 1199 struct v4l2_subdev *subdev = i2c_get_clientdata(client); 1200 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 1201 1202 v4l2_async_unregister_subdev(subdev); 1203 v4l2_ctrl_handler_free(&mt9v032->ctrls); 1204 media_entity_cleanup(&subdev->entity); 1205 } 1206 1207 static const struct mt9v032_model_data mt9v032_model_data[] = { 1208 { 1209 /* MT9V022, MT9V032 revisions 1/2/3 */ 1210 .min_row_time = 660, 1211 .min_hblank = MT9V032_HORIZONTAL_BLANKING_MIN, 1212 .min_vblank = MT9V032_VERTICAL_BLANKING_MIN, 1213 .max_vblank = MT9V032_VERTICAL_BLANKING_MAX, 1214 .min_shutter = MT9V032_TOTAL_SHUTTER_WIDTH_MIN, 1215 .max_shutter = MT9V032_TOTAL_SHUTTER_WIDTH_MAX, 1216 .pclk_reg = MT9V032_PIXEL_CLOCK, 1217 .aec_max_shutter_reg = MT9V032_AEC_MAX_SHUTTER_WIDTH, 1218 .aec_max_shutter_v4l2_ctrl = &mt9v032_aec_max_shutter_width, 1219 }, { 1220 /* MT9V024, MT9V034 */ 1221 .min_row_time = 690, 1222 .min_hblank = MT9V034_HORIZONTAL_BLANKING_MIN, 1223 .min_vblank = MT9V034_VERTICAL_BLANKING_MIN, 1224 .max_vblank = MT9V034_VERTICAL_BLANKING_MAX, 1225 .min_shutter = MT9V034_TOTAL_SHUTTER_WIDTH_MIN, 1226 .max_shutter = MT9V034_TOTAL_SHUTTER_WIDTH_MAX, 1227 .pclk_reg = MT9V034_PIXEL_CLOCK, 1228 .aec_max_shutter_reg = MT9V034_AEC_MAX_SHUTTER_WIDTH, 1229 .aec_max_shutter_v4l2_ctrl = &mt9v034_aec_max_shutter_width, 1230 }, 1231 }; 1232 1233 static const struct mt9v032_model_info mt9v032_models[] = { 1234 [MT9V032_MODEL_V022_COLOR] = { 1235 .data = &mt9v032_model_data[0], 1236 .color = true, 1237 }, 1238 [MT9V032_MODEL_V022_MONO] = { 1239 .data = &mt9v032_model_data[0], 1240 .color = false, 1241 }, 1242 [MT9V032_MODEL_V024_COLOR] = { 1243 .data = &mt9v032_model_data[1], 1244 .color = true, 1245 }, 1246 [MT9V032_MODEL_V024_MONO] = { 1247 .data = &mt9v032_model_data[1], 1248 .color = false, 1249 }, 1250 [MT9V032_MODEL_V032_COLOR] = { 1251 .data = &mt9v032_model_data[0], 1252 .color = true, 1253 }, 1254 [MT9V032_MODEL_V032_MONO] = { 1255 .data = &mt9v032_model_data[0], 1256 .color = false, 1257 }, 1258 [MT9V032_MODEL_V034_COLOR] = { 1259 .data = &mt9v032_model_data[1], 1260 .color = true, 1261 }, 1262 [MT9V032_MODEL_V034_MONO] = { 1263 .data = &mt9v032_model_data[1], 1264 .color = false, 1265 }, 1266 }; 1267 1268 static const struct of_device_id mt9v032_of_match[] = { 1269 { .compatible = "aptina,mt9v022", .data = &mt9v032_models[MT9V032_MODEL_V022_COLOR] }, 1270 { .compatible = "aptina,mt9v022m", .data = &mt9v032_models[MT9V032_MODEL_V022_MONO] }, 1271 { .compatible = "aptina,mt9v024", .data = &mt9v032_models[MT9V032_MODEL_V024_COLOR] }, 1272 { .compatible = "aptina,mt9v024m", .data = &mt9v032_models[MT9V032_MODEL_V024_MONO] }, 1273 { .compatible = "aptina,mt9v032", .data = &mt9v032_models[MT9V032_MODEL_V032_COLOR] }, 1274 { .compatible = "aptina,mt9v032m", .data = &mt9v032_models[MT9V032_MODEL_V032_MONO] }, 1275 { .compatible = "aptina,mt9v034", .data = &mt9v032_models[MT9V032_MODEL_V034_COLOR] }, 1276 { .compatible = "aptina,mt9v034m", .data = &mt9v032_models[MT9V032_MODEL_V034_MONO] }, 1277 { /* Sentinel */ } 1278 }; 1279 MODULE_DEVICE_TABLE(of, mt9v032_of_match); 1280 1281 static struct i2c_driver mt9v032_driver = { 1282 .driver = { 1283 .name = "mt9v032", 1284 .of_match_table = mt9v032_of_match, 1285 }, 1286 .probe = mt9v032_probe, 1287 .remove = mt9v032_remove, 1288 }; 1289 1290 module_i2c_driver(mt9v032_driver); 1291 1292 MODULE_DESCRIPTION("Aptina MT9V032 Camera driver"); 1293 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>"); 1294 MODULE_LICENSE("GPL"); 1295