xref: /linux/drivers/media/i2c/max96714.c (revision a3a02a52bcfcbcc4a637d4b68bf1bc391c9fad02) 
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Maxim GMSL2 Deserializer Driver
4  *
5  * Copyright (C) 2024 Collabora Ltd.
6  */
7 
8 #include <linux/bitfield.h>
9 #include <linux/bitops.h>
10 #include <linux/fwnode.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/i2c.h>
13 #include <linux/i2c-mux.h>
14 #include <linux/module.h>
15 #include <linux/regmap.h>
16 #include <linux/regulator/consumer.h>
17 
18 #include <media/v4l2-cci.h>
19 #include <media/v4l2-ctrls.h>
20 #include <media/v4l2-fwnode.h>
21 #include <media/v4l2-subdev.h>
22 
23 #define MAX96714_DEVICE_ID  0xc9
24 #define MAX96714F_DEVICE_ID 0xca
25 #define MAX96714_NPORTS     2
26 #define MAX96714_PAD_SINK   0
27 #define MAX96714_PAD_SOURCE 1
28 
29 /* DEV */
30 #define MAX96714_REG13                 CCI_REG8(0x0d)
31 #define MAX96714_DEV_REV               CCI_REG8(0x0e)
32 #define MAX96714_DEV_REV_MASK          GENMASK(3, 0)
33 #define MAX96714_LINK_LOCK             CCI_REG8(0x13)
34 #define MAX96714_LINK_LOCK_BIT         BIT(3)
35 #define MAX96714_IO_CHK0               CCI_REG8(0x38)
36 #define MAX96714_PATTERN_CLK_FREQ      GENMASK(1, 0)
37 /* VID_RX */
38 #define MAX96714_VIDEO_RX8             CCI_REG8(0x11a)
39 #define MAX96714_VID_LOCK              BIT(6)
40 
41 /* VRX_PATGEN_0 */
42 #define MAX96714_PATGEN_0              CCI_REG8(0x240)
43 #define MAX96714_PATGEN_1              CCI_REG8(0x241)
44 #define MAX96714_PATGEN_MODE           GENMASK(5, 4)
45 #define MAX96714_PATGEN_VS_DLY         CCI_REG24(0x242)
46 #define MAX96714_PATGEN_VS_HIGH        CCI_REG24(0x245)
47 #define MAX96714_PATGEN_VS_LOW         CCI_REG24(0x248)
48 #define MAX96714_PATGEN_V2H            CCI_REG24(0x24b)
49 #define MAX96714_PATGEN_HS_HIGH        CCI_REG16(0x24e)
50 #define MAX96714_PATGEN_HS_LOW         CCI_REG16(0x250)
51 #define MAX96714_PATGEN_HS_CNT         CCI_REG16(0x252)
52 #define MAX96714_PATGEN_V2D            CCI_REG24(0x254)
53 #define MAX96714_PATGEN_DE_HIGH        CCI_REG16(0x257)
54 #define MAX96714_PATGEN_DE_LOW         CCI_REG16(0x259)
55 #define MAX96714_PATGEN_DE_CNT         CCI_REG16(0x25B)
56 #define MAX96714_PATGEN_GRAD_INC       CCI_REG8(0x25d)
57 #define MAX96714_PATGEN_CHKB_COLOR_A   CCI_REG24(0x25E)
58 #define MAX96714_PATGEN_CHKB_COLOR_B   CCI_REG24(0x261)
59 #define MAX96714_PATGEN_CHKB_RPT_CNT_A CCI_REG8(0x264)
60 #define MAX96714_PATGEN_CHKB_RPT_CNT_B CCI_REG8(0x265)
61 #define MAX96714_PATGEN_CHKB_ALT       CCI_REG8(0x266)
62 /* BACKTOP */
63 #define MAX96714_BACKTOP25             CCI_REG8(0x320)
64 #define CSI_DPLL_FREQ_MASK             GENMASK(4, 0)
65 
66 /* MIPI_PHY */
67 #define MAX96714_MIPI_PHY0             CCI_REG8(0x330)
68 #define MAX96714_FORCE_CSI_OUT         BIT(7)
69 #define MAX96714_MIPI_STDBY_N          CCI_REG8(0x332)
70 #define MAX96714_MIPI_STDBY_MASK       GENMASK(5, 4)
71 #define MAX96714_MIPI_LANE_MAP         CCI_REG8(0x333)
72 #define MAX96714_MIPI_POLARITY         CCI_REG8(0x335)
73 #define MAX96714_MIPI_POLARITY_MASK    GENMASK(5, 0)
74 
75 /* MIPI_TX */
76 #define MAX96714_MIPI_LANE_CNT         CCI_REG8(0x44a)
77 #define MAX96714_CSI2_LANE_CNT_MASK    GENMASK(7, 6)
78 #define MAX96714_MIPI_TX52             CCI_REG8(0x474)
79 #define MAX96714_TUN_EN                BIT(0)
80 
81 #define MHZ(v) ((u32)((v)  * 1000000U))
82 
83 enum max96714_vpg_mode {
84 	MAX96714_VPG_DISABLED = 0,
85 	MAX96714_VPG_CHECKERBOARD = 1,
86 	MAX96714_VPG_GRADIENT = 2,
87 };
88 
89 struct max96714_rxport {
90 	struct {
91 		struct v4l2_subdev   *sd;
92 		u16                  pad;
93 		struct fwnode_handle *ep_fwnode;
94 	} source;
95 	struct regulator	     *poc;
96 };
97 
98 struct max96714_txport {
99 	struct v4l2_fwnode_endpoint vep;
100 };
101 
102 struct max96714_priv {
103 	struct i2c_client                 *client;
104 	struct regmap                     *regmap;
105 	struct gpio_desc                  *pd_gpio;
106 	struct max96714_rxport            rxport;
107 	struct i2c_mux_core               *mux;
108 	u64                               enabled_source_streams;
109 	struct v4l2_subdev		  sd;
110 	struct media_pad		  pads[MAX96714_NPORTS];
111 	struct v4l2_mbus_config_mipi_csi2 mipi_csi2;
112 	struct v4l2_ctrl_handler          ctrl_handler;
113 	struct v4l2_async_notifier        notifier;
114 	s64                               tx_link_freq;
115 	enum max96714_vpg_mode            pattern;
116 };
117 
118 static inline struct max96714_priv *sd_to_max96714(struct v4l2_subdev *sd)
119 {
120 	return container_of(sd, struct max96714_priv, sd);
121 }
122 
123 static int max96714_enable_tx_port(struct max96714_priv *priv)
124 {
125 	return cci_update_bits(priv->regmap, MAX96714_MIPI_STDBY_N,
126 			       MAX96714_MIPI_STDBY_MASK,
127 			       MAX96714_MIPI_STDBY_MASK, NULL);
128 }
129 
130 static int max96714_disable_tx_port(struct max96714_priv *priv)
131 {
132 	return cci_update_bits(priv->regmap, MAX96714_MIPI_STDBY_N,
133 			       MAX96714_MIPI_STDBY_MASK, 0, NULL);
134 }
135 
136 static bool max96714_tx_port_enabled(struct max96714_priv *priv)
137 {
138 	u64 val;
139 
140 	cci_read(priv->regmap, MAX96714_MIPI_STDBY_N, &val, NULL);
141 
142 	return val & MAX96714_MIPI_STDBY_MASK;
143 }
144 
145 static int max96714_apply_patgen_timing(struct max96714_priv *priv,
146 					struct v4l2_subdev_state *state)
147 {
148 	struct v4l2_mbus_framefmt *fmt =
149 		v4l2_subdev_state_get_format(state, MAX96714_PAD_SOURCE);
150 	const u32 h_active = fmt->width;
151 	const u32 h_fp = 88;
152 	const u32 h_sw = 44;
153 	const u32 h_bp = 148;
154 	u32 h_tot;
155 	const u32 v_active = fmt->height;
156 	const u32 v_fp = 4;
157 	const u32 v_sw = 5;
158 	const u32 v_bp = 36;
159 	u32 v_tot;
160 	int ret = 0;
161 
162 	h_tot = h_active + h_fp + h_sw + h_bp;
163 	v_tot = v_active + v_fp + v_sw + v_bp;
164 
165 	/* 75 Mhz pixel clock */
166 	cci_update_bits(priv->regmap, MAX96714_IO_CHK0,
167 			MAX96714_PATTERN_CLK_FREQ, 1, &ret);
168 
169 	dev_info(&priv->client->dev, "height: %d width: %d\n", fmt->height,
170 		 fmt->width);
171 
172 	cci_write(priv->regmap, MAX96714_PATGEN_VS_DLY, 0, &ret);
173 	cci_write(priv->regmap, MAX96714_PATGEN_VS_HIGH, v_sw * h_tot, &ret);
174 	cci_write(priv->regmap, MAX96714_PATGEN_VS_LOW,
175 		  (v_active + v_fp + v_bp) * h_tot, &ret);
176 	cci_write(priv->regmap, MAX96714_PATGEN_HS_HIGH, h_sw, &ret);
177 	cci_write(priv->regmap, MAX96714_PATGEN_HS_LOW, h_active + h_fp + h_bp,
178 		  &ret);
179 	cci_write(priv->regmap, MAX96714_PATGEN_V2D,
180 		  h_tot * (v_sw + v_bp) + (h_sw + h_bp), &ret);
181 	cci_write(priv->regmap, MAX96714_PATGEN_HS_CNT, v_tot, &ret);
182 	cci_write(priv->regmap, MAX96714_PATGEN_DE_HIGH, h_active, &ret);
183 	cci_write(priv->regmap, MAX96714_PATGEN_DE_LOW, h_fp + h_sw + h_bp,
184 		  &ret);
185 	cci_write(priv->regmap, MAX96714_PATGEN_DE_CNT, v_active, &ret);
186 	/* B G R */
187 	cci_write(priv->regmap, MAX96714_PATGEN_CHKB_COLOR_A, 0xfecc00, &ret);
188 	/* B G R */
189 	cci_write(priv->regmap, MAX96714_PATGEN_CHKB_COLOR_B, 0x006aa7, &ret);
190 	cci_write(priv->regmap, MAX96714_PATGEN_CHKB_RPT_CNT_A, 0x3c, &ret);
191 	cci_write(priv->regmap, MAX96714_PATGEN_CHKB_RPT_CNT_B, 0x3c, &ret);
192 	cci_write(priv->regmap, MAX96714_PATGEN_CHKB_ALT, 0x3c, &ret);
193 	cci_write(priv->regmap, MAX96714_PATGEN_GRAD_INC, 0x10, &ret);
194 
195 	return ret;
196 }
197 
198 static int max96714_apply_patgen(struct max96714_priv *priv,
199 				 struct v4l2_subdev_state *state)
200 {
201 	unsigned int val;
202 	int ret = 0;
203 
204 	if (priv->pattern)
205 		ret = max96714_apply_patgen_timing(priv, state);
206 
207 	cci_write(priv->regmap, MAX96714_PATGEN_0, priv->pattern ? 0xfb : 0,
208 		  &ret);
209 
210 	val = FIELD_PREP(MAX96714_PATGEN_MODE, priv->pattern);
211 	cci_update_bits(priv->regmap, MAX96714_PATGEN_1, MAX96714_PATGEN_MODE,
212 			val, &ret);
213 	return ret;
214 }
215 
216 static int max96714_s_ctrl(struct v4l2_ctrl *ctrl)
217 {
218 	struct max96714_priv *priv =
219 		container_of(ctrl->handler, struct max96714_priv, ctrl_handler);
220 	int ret;
221 
222 	switch (ctrl->id) {
223 	case V4L2_CID_TEST_PATTERN:
224 		if (priv->enabled_source_streams)
225 			return -EBUSY;
226 		priv->pattern = ctrl->val;
227 		break;
228 	default:
229 		return -EINVAL;
230 	}
231 
232 	ret = cci_update_bits(priv->regmap, MAX96714_MIPI_PHY0,
233 			      MAX96714_FORCE_CSI_OUT,
234 			      priv->pattern ? MAX96714_FORCE_CSI_OUT : 0, NULL);
235 
236 	/* Pattern generator doesn't work with tunnel mode */
237 	return cci_update_bits(priv->regmap, MAX96714_MIPI_TX52,
238 			       MAX96714_TUN_EN,
239 			       priv->pattern ? 0 : MAX96714_TUN_EN, &ret);
240 }
241 
242 static const char * const max96714_test_pattern[] = {
243 	"Disabled",
244 	"Checkerboard",
245 	"Gradient"
246 };
247 
248 static const struct v4l2_ctrl_ops max96714_ctrl_ops = {
249 	.s_ctrl = max96714_s_ctrl,
250 };
251 
252 static int max96714_enable_streams(struct v4l2_subdev *sd,
253 				   struct v4l2_subdev_state *state,
254 				   u32 source_pad, u64 streams_mask)
255 {
256 	struct max96714_priv *priv = sd_to_max96714(sd);
257 	u64 sink_streams;
258 	int ret;
259 
260 	if (!priv->enabled_source_streams)
261 		max96714_enable_tx_port(priv);
262 
263 	ret = max96714_apply_patgen(priv, state);
264 	if (ret)
265 		goto err;
266 
267 	if (!priv->pattern) {
268 		if (!priv->rxport.source.sd) {
269 			ret = -ENODEV;
270 			goto err;
271 		}
272 
273 		sink_streams =
274 			v4l2_subdev_state_xlate_streams(state,
275 							MAX96714_PAD_SOURCE,
276 							MAX96714_PAD_SINK,
277 							&streams_mask);
278 
279 		ret = v4l2_subdev_enable_streams(priv->rxport.source.sd,
280 						 priv->rxport.source.pad,
281 						 sink_streams);
282 		if (ret)
283 			goto err;
284 	}
285 
286 	priv->enabled_source_streams |= streams_mask;
287 
288 	return 0;
289 
290 err:
291 	if (!priv->enabled_source_streams)
292 		max96714_disable_tx_port(priv);
293 
294 	return ret;
295 }
296 
297 static int max96714_disable_streams(struct v4l2_subdev *sd,
298 				    struct v4l2_subdev_state *state,
299 				    u32 source_pad, u64 streams_mask)
300 {
301 	struct max96714_priv *priv = sd_to_max96714(sd);
302 	u64 sink_streams;
303 
304 	if (!priv->pattern) {
305 		int ret;
306 
307 		sink_streams =
308 			v4l2_subdev_state_xlate_streams(state,
309 							MAX96714_PAD_SOURCE,
310 							MAX96714_PAD_SINK,
311 							&streams_mask);
312 
313 		ret = v4l2_subdev_disable_streams(priv->rxport.source.sd,
314 						  priv->rxport.source.pad,
315 						  sink_streams);
316 		if (ret)
317 			return ret;
318 	}
319 
320 	priv->enabled_source_streams &= ~streams_mask;
321 
322 	if (!priv->enabled_source_streams)
323 		max96714_disable_tx_port(priv);
324 
325 	return 0;
326 }
327 
328 static int max96714_set_fmt(struct v4l2_subdev *sd,
329 			    struct v4l2_subdev_state *state,
330 			    struct v4l2_subdev_format *format)
331 {
332 	struct max96714_priv *priv = sd_to_max96714(sd);
333 	struct v4l2_mbus_framefmt *fmt;
334 
335 	if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE &&
336 	    priv->enabled_source_streams)
337 		return -EBUSY;
338 
339 	/* No transcoding, source and sink formats must match. */
340 	if (format->pad == MAX96714_PAD_SOURCE)
341 		return v4l2_subdev_get_fmt(sd, state, format);
342 
343 	fmt = v4l2_subdev_state_get_format(state, format->pad, format->stream);
344 	if (!fmt)
345 		return -EINVAL;
346 
347 	*fmt = format->format;
348 
349 	fmt = v4l2_subdev_state_get_opposite_stream_format(state, format->pad,
350 							   format->stream);
351 	if (!fmt)
352 		return -EINVAL;
353 
354 	*fmt = format->format;
355 
356 	return 0;
357 }
358 
359 static int _max96714_set_routing(struct v4l2_subdev *sd,
360 				 struct v4l2_subdev_state *state,
361 				 enum v4l2_subdev_format_whence which,
362 				 struct v4l2_subdev_krouting *routing)
363 {
364 	static const struct v4l2_mbus_framefmt format = {
365 		.width = 1280,
366 		.height = 1080,
367 		.code = MEDIA_BUS_FMT_Y8_1X8,
368 		.field = V4L2_FIELD_NONE,
369 	};
370 	int ret;
371 
372 	/*
373 	 * Note: we can only support up to V4L2_FRAME_DESC_ENTRY_MAX, until
374 	 * frame desc is made dynamically allocated.
375 	 */
376 	if (routing->num_routes > V4L2_FRAME_DESC_ENTRY_MAX)
377 		return -EINVAL;
378 
379 	ret = v4l2_subdev_routing_validate(sd, routing,
380 					   V4L2_SUBDEV_ROUTING_ONLY_1_TO_1);
381 	if (ret)
382 		return ret;
383 
384 	return v4l2_subdev_set_routing_with_fmt(sd, state, routing, &format);
385 }
386 
387 static int max96714_set_routing(struct v4l2_subdev *sd,
388 				struct v4l2_subdev_state *state,
389 				enum v4l2_subdev_format_whence which,
390 				struct v4l2_subdev_krouting *routing)
391 {
392 	struct max96714_priv *priv = sd_to_max96714(sd);
393 
394 	if (which == V4L2_SUBDEV_FORMAT_ACTIVE && priv->enabled_source_streams)
395 		return -EBUSY;
396 
397 	return _max96714_set_routing(sd, state, which, routing);
398 }
399 
400 static int max96714_init_state(struct v4l2_subdev *sd,
401 			       struct v4l2_subdev_state *state)
402 {
403 	struct v4l2_subdev_route routes[] = {
404 		{
405 			.sink_pad = MAX96714_PAD_SINK,
406 			.sink_stream = 0,
407 			.source_pad = MAX96714_PAD_SOURCE,
408 			.source_stream = 0,
409 			.flags = V4L2_SUBDEV_ROUTE_FL_ACTIVE,
410 		}
411 	};
412 	struct v4l2_subdev_krouting routing = {
413 		.num_routes = ARRAY_SIZE(routes),
414 		.routes = routes,
415 	};
416 
417 	return _max96714_set_routing(sd, state, V4L2_SUBDEV_FORMAT_ACTIVE,
418 				     &routing);
419 }
420 
421 static const struct v4l2_subdev_pad_ops max96714_pad_ops = {
422 	.enable_streams = max96714_enable_streams,
423 	.disable_streams = max96714_disable_streams,
424 
425 	.set_routing = max96714_set_routing,
426 	.get_fmt = v4l2_subdev_get_fmt,
427 	.set_fmt = max96714_set_fmt,
428 };
429 
430 static bool max96714_link_locked(struct max96714_priv *priv)
431 {
432 	u64 val = 0;
433 
434 	cci_read(priv->regmap, MAX96714_LINK_LOCK, &val, NULL);
435 
436 	return val & MAX96714_LINK_LOCK_BIT;
437 }
438 
439 static void max96714_link_status(struct max96714_priv *priv)
440 {
441 	struct device *dev = &priv->client->dev;
442 
443 	dev_info(dev, "Link locked:%d\n", max96714_link_locked(priv));
444 }
445 
446 static bool max96714_pipe_locked(struct max96714_priv *priv)
447 {
448 	u64 val;
449 
450 	cci_read(priv->regmap, MAX96714_VIDEO_RX8, &val, NULL);
451 
452 	return val & MAX96714_VID_LOCK;
453 }
454 
455 static void max96714_pipe_status(struct max96714_priv *priv)
456 {
457 	struct device *dev = &priv->client->dev;
458 
459 	dev_info(dev, "Pipe vidlock:%d\n", max96714_pipe_locked(priv));
460 }
461 
462 static void max96714_csi_status(struct max96714_priv *priv)
463 {
464 	struct device *dev = &priv->client->dev;
465 	u64 freq = 0;
466 
467 	cci_read(priv->regmap, MAX96714_BACKTOP25, &freq, NULL);
468 	freq = FIELD_GET(CSI_DPLL_FREQ_MASK, freq);
469 
470 	dev_info(dev, "CSI controller DPLL freq:%u00MHz CSIPHY enabled:%d\n",
471 		 (u8)freq, max96714_tx_port_enabled(priv));
472 }
473 
474 static int max96714_log_status(struct v4l2_subdev *sd)
475 {
476 	struct max96714_priv *priv = sd_to_max96714(sd);
477 	struct device *dev = &priv->client->dev;
478 
479 	dev_info(dev, "Deserializer: max96714\n");
480 
481 	max96714_link_status(priv);
482 	max96714_pipe_status(priv);
483 	max96714_csi_status(priv);
484 
485 	return 0;
486 }
487 
488 static const struct v4l2_subdev_core_ops max96714_subdev_core_ops = {
489 	.log_status = max96714_log_status,
490 };
491 
492 static const struct v4l2_subdev_video_ops max96714_video_ops = {
493 	.s_stream	= v4l2_subdev_s_stream_helper,
494 };
495 
496 static const struct v4l2_subdev_internal_ops max96714_internal_ops = {
497 	.init_state = max96714_init_state,
498 };
499 
500 static const struct v4l2_subdev_ops max96714_subdev_ops = {
501 	.video = &max96714_video_ops,
502 	.core = &max96714_subdev_core_ops,
503 	.pad = &max96714_pad_ops,
504 };
505 
506 static const struct media_entity_operations max96714_entity_ops = {
507 	.link_validate = v4l2_subdev_link_validate,
508 };
509 
510 static int max96714_notify_bound(struct v4l2_async_notifier *notifier,
511 				 struct v4l2_subdev *subdev,
512 				 struct v4l2_async_connection *asd)
513 {
514 	struct max96714_priv *priv = sd_to_max96714(notifier->sd);
515 	struct device *dev = &priv->client->dev;
516 	int ret;
517 
518 	ret = media_entity_get_fwnode_pad(&subdev->entity,
519 					  priv->rxport.source.ep_fwnode,
520 					  MEDIA_PAD_FL_SOURCE);
521 	if (ret < 0) {
522 		dev_err(dev, "Failed to find pad for %s\n", subdev->name);
523 		return ret;
524 	}
525 
526 	priv->rxport.source.sd = subdev;
527 	priv->rxport.source.pad = ret;
528 
529 	ret = media_create_pad_link(&priv->rxport.source.sd->entity,
530 				    priv->rxport.source.pad, &priv->sd.entity,
531 				    MAX96714_PAD_SINK,
532 				    MEDIA_LNK_FL_ENABLED |
533 				    MEDIA_LNK_FL_IMMUTABLE);
534 	if (ret) {
535 		dev_err(dev, "Unable to link %s:%u -> %s:%u\n",
536 			priv->rxport.source.sd->name, priv->rxport.source.pad,
537 			priv->sd.name, MAX96714_PAD_SINK);
538 		return ret;
539 	}
540 
541 	return 0;
542 }
543 
544 static const struct v4l2_async_notifier_operations max96714_notify_ops = {
545 	.bound = max96714_notify_bound,
546 };
547 
548 static int max96714_v4l2_notifier_register(struct max96714_priv *priv)
549 {
550 	struct device *dev = &priv->client->dev;
551 	struct max96714_rxport *rxport = &priv->rxport;
552 	struct v4l2_async_connection *asd;
553 	int ret;
554 
555 	if (!rxport->source.ep_fwnode)
556 		return 0;
557 
558 	v4l2_async_subdev_nf_init(&priv->notifier, &priv->sd);
559 
560 	asd = v4l2_async_nf_add_fwnode(&priv->notifier,
561 				       rxport->source.ep_fwnode,
562 				       struct v4l2_async_connection);
563 	if (IS_ERR(asd)) {
564 		dev_err(dev, "Failed to add subdev: %pe", asd);
565 		v4l2_async_nf_cleanup(&priv->notifier);
566 		return PTR_ERR(asd);
567 	}
568 
569 	priv->notifier.ops = &max96714_notify_ops;
570 
571 	ret = v4l2_async_nf_register(&priv->notifier);
572 	if (ret) {
573 		dev_err(dev, "Failed to register subdev_notifier");
574 		v4l2_async_nf_cleanup(&priv->notifier);
575 		return ret;
576 	}
577 
578 	return 0;
579 }
580 
581 static int max96714_create_subdev(struct max96714_priv *priv)
582 {
583 	struct device *dev = &priv->client->dev;
584 	int ret;
585 
586 	v4l2_i2c_subdev_init(&priv->sd, priv->client, &max96714_subdev_ops);
587 	priv->sd.internal_ops = &max96714_internal_ops;
588 
589 	v4l2_ctrl_handler_init(&priv->ctrl_handler, 1);
590 	priv->sd.ctrl_handler = &priv->ctrl_handler;
591 
592 	v4l2_ctrl_new_int_menu(&priv->ctrl_handler, NULL, V4L2_CID_LINK_FREQ,
593 			       0, 0, &priv->tx_link_freq);
594 	v4l2_ctrl_new_std_menu_items(&priv->ctrl_handler,
595 				     &max96714_ctrl_ops,
596 				     V4L2_CID_TEST_PATTERN,
597 				     ARRAY_SIZE(max96714_test_pattern) - 1,
598 				     0, 0, max96714_test_pattern);
599 	if (priv->ctrl_handler.error) {
600 		ret = priv->ctrl_handler.error;
601 		goto err_free_ctrl;
602 	}
603 
604 	priv->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_STREAMS;
605 	priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
606 	priv->sd.entity.ops = &max96714_entity_ops;
607 
608 	priv->pads[MAX96714_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
609 	priv->pads[MAX96714_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
610 
611 	ret = media_entity_pads_init(&priv->sd.entity,
612 				     MAX96714_NPORTS,
613 				     priv->pads);
614 	if (ret)
615 		goto err_free_ctrl;
616 
617 	priv->sd.state_lock = priv->sd.ctrl_handler->lock;
618 
619 	ret = v4l2_subdev_init_finalize(&priv->sd);
620 	if (ret)
621 		goto err_entity_cleanup;
622 
623 	ret = max96714_v4l2_notifier_register(priv);
624 	if (ret) {
625 		dev_err(dev, "v4l2 subdev notifier register failed: %d\n", ret);
626 		goto err_subdev_cleanup;
627 	}
628 
629 	ret = v4l2_async_register_subdev(&priv->sd);
630 	if (ret) {
631 		dev_err(dev, "v4l2_async_register_subdev error: %d\n", ret);
632 		goto err_unreg_notif;
633 	}
634 
635 	return 0;
636 
637 err_unreg_notif:
638 	v4l2_async_nf_unregister(&priv->notifier);
639 	v4l2_async_nf_cleanup(&priv->notifier);
640 err_subdev_cleanup:
641 	v4l2_subdev_cleanup(&priv->sd);
642 err_entity_cleanup:
643 	media_entity_cleanup(&priv->sd.entity);
644 err_free_ctrl:
645 	v4l2_ctrl_handler_free(&priv->ctrl_handler);
646 
647 	return ret;
648 };
649 
650 static void max96714_destroy_subdev(struct max96714_priv *priv)
651 {
652 	v4l2_async_nf_unregister(&priv->notifier);
653 	v4l2_async_nf_cleanup(&priv->notifier);
654 	v4l2_async_unregister_subdev(&priv->sd);
655 
656 	v4l2_subdev_cleanup(&priv->sd);
657 
658 	media_entity_cleanup(&priv->sd.entity);
659 	v4l2_ctrl_handler_free(&priv->ctrl_handler);
660 }
661 
662 static int max96714_i2c_mux_select(struct i2c_mux_core *mux, u32 chan)
663 {
664 	return 0;
665 }
666 
667 static int max96714_i2c_mux_init(struct max96714_priv *priv)
668 {
669 	priv->mux = i2c_mux_alloc(priv->client->adapter, &priv->client->dev,
670 				  1, 0, I2C_MUX_LOCKED | I2C_MUX_GATE,
671 				  max96714_i2c_mux_select, NULL);
672 	if (!priv->mux)
673 		return -ENOMEM;
674 
675 	return i2c_mux_add_adapter(priv->mux, 0, 0);
676 }
677 
678 static int max96714_init_tx_port(struct max96714_priv *priv)
679 {
680 	struct v4l2_mbus_config_mipi_csi2 *mipi;
681 	unsigned long lanes_used = 0;
682 	unsigned int val, lane;
683 	int ret;
684 
685 	ret = max96714_disable_tx_port(priv);
686 
687 	mipi = &priv->mipi_csi2;
688 	val = div_u64(priv->tx_link_freq * 2, MHZ(100));
689 
690 	cci_update_bits(priv->regmap, MAX96714_BACKTOP25,
691 			CSI_DPLL_FREQ_MASK, val, &ret);
692 
693 	val = FIELD_PREP(MAX96714_CSI2_LANE_CNT_MASK, mipi->num_data_lanes - 1);
694 	cci_update_bits(priv->regmap, MAX96714_MIPI_LANE_CNT,
695 			MAX96714_CSI2_LANE_CNT_MASK, val, &ret);
696 
697 	/* lanes polarity */
698 	val = 0;
699 	for (lane = 0; lane < mipi->num_data_lanes + 1; lane++) {
700 		if (!mipi->lane_polarities[lane])
701 			continue;
702 		if (lane == 0)
703 			/* clock lane */
704 			val |= BIT(5);
705 		else if (lane < 3)
706 			/* Lane D0 and D1 */
707 			val |= BIT(lane - 1);
708 		else
709 			/* D2 and D3 */
710 			val |= BIT(lane);
711 	}
712 
713 	cci_update_bits(priv->regmap, MAX96714_MIPI_POLARITY,
714 			MAX96714_MIPI_POLARITY_MASK, val, &ret);
715 
716 	/* lanes mapping */
717 	val = 0;
718 	for (lane = 0; lane < mipi->num_data_lanes; lane++) {
719 		val |= (mipi->data_lanes[lane] - 1) << (lane * 2);
720 		lanes_used |= BIT(mipi->data_lanes[lane] - 1);
721 	}
722 
723 	/*
724 	 * Unused lanes need to be mapped as well to not have
725 	 * the same lanes mapped twice.
726 	 */
727 	for (; lane < 4; lane++) {
728 		unsigned int idx = find_first_zero_bit(&lanes_used, 4);
729 
730 		val |= idx << (lane * 2);
731 		lanes_used |= BIT(idx);
732 	}
733 
734 	return cci_write(priv->regmap, MAX96714_MIPI_LANE_MAP, val, &ret);
735 }
736 
737 static int max96714_rxport_enable_poc(struct max96714_priv *priv)
738 {
739 	struct max96714_rxport *rxport = &priv->rxport;
740 
741 	if (!rxport->poc)
742 		return 0;
743 
744 	return regulator_enable(rxport->poc);
745 }
746 
747 static int max96714_rxport_disable_poc(struct max96714_priv *priv)
748 {
749 	struct max96714_rxport *rxport = &priv->rxport;
750 
751 	if (!rxport->poc)
752 		return 0;
753 
754 	return regulator_disable(rxport->poc);
755 }
756 
757 static int max96714_parse_dt_txport(struct max96714_priv *priv)
758 {
759 	struct device *dev = &priv->client->dev;
760 	struct v4l2_fwnode_endpoint vep = {
761 		.bus_type = V4L2_MBUS_CSI2_DPHY
762 	};
763 	struct fwnode_handle *ep_fwnode;
764 	u32 num_data_lanes;
765 	int ret;
766 
767 	ep_fwnode = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev),
768 						    MAX96714_PAD_SOURCE, 0, 0);
769 	if (!ep_fwnode)
770 		return -EINVAL;
771 
772 	ret = v4l2_fwnode_endpoint_alloc_parse(ep_fwnode, &vep);
773 	fwnode_handle_put(ep_fwnode);
774 	if (ret) {
775 		dev_err(dev, "tx: failed to parse endpoint data\n");
776 		return -EINVAL;
777 	}
778 
779 	if (vep.nr_of_link_frequencies != 1) {
780 		ret = -EINVAL;
781 		goto err_free_vep;
782 	}
783 
784 	priv->tx_link_freq = vep.link_frequencies[0];
785 	/* Min 50MHz, Max 1250MHz, 50MHz step */
786 	if (priv->tx_link_freq < MHZ(50) || priv->tx_link_freq > MHZ(1250) ||
787 	    (u32)priv->tx_link_freq % MHZ(50)) {
788 		dev_err(dev, "tx: invalid link frequency\n");
789 		ret = -EINVAL;
790 		goto err_free_vep;
791 	}
792 
793 	num_data_lanes = vep.bus.mipi_csi2.num_data_lanes;
794 	if (num_data_lanes < 1 || num_data_lanes > 4) {
795 		dev_err(dev,
796 			"tx: invalid number of data lanes must be 1 to 4\n");
797 		ret = -EINVAL;
798 		goto err_free_vep;
799 	}
800 
801 	memcpy(&priv->mipi_csi2, &vep.bus.mipi_csi2, sizeof(priv->mipi_csi2));
802 
803 err_free_vep:
804 	v4l2_fwnode_endpoint_free(&vep);
805 
806 	return ret;
807 }
808 
809 static int max96714_parse_dt_rxport(struct max96714_priv *priv)
810 {
811 	static const char *poc_name = "port0-poc";
812 	struct max96714_rxport *rxport = &priv->rxport;
813 	struct device *dev = &priv->client->dev;
814 	struct fwnode_handle *ep_fwnode;
815 	int ret;
816 
817 	ep_fwnode = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev),
818 						    MAX96714_PAD_SINK, 0, 0);
819 	if (!ep_fwnode)
820 		return -ENOENT;
821 
822 	rxport->source.ep_fwnode = fwnode_graph_get_remote_endpoint(ep_fwnode);
823 	fwnode_handle_put(ep_fwnode);
824 
825 	if (!rxport->source.ep_fwnode) {
826 		dev_err(dev, "rx: no remote endpoint\n");
827 		return -EINVAL;
828 	}
829 
830 	rxport->poc = devm_regulator_get_optional(dev, poc_name);
831 	if (IS_ERR(rxport->poc)) {
832 		ret = PTR_ERR(rxport->poc);
833 		if (ret == -ENODEV) {
834 			rxport->poc = NULL;
835 		} else {
836 			dev_err(dev, "rx: failed to get POC supply: %d\n", ret);
837 			goto err_put_source_ep_fwnode;
838 		}
839 	}
840 
841 	return 0;
842 
843 err_put_source_ep_fwnode:
844 	fwnode_handle_put(rxport->source.ep_fwnode);
845 	return ret;
846 }
847 
848 static int max96714_parse_dt(struct max96714_priv *priv)
849 {
850 	int ret;
851 
852 	ret = max96714_parse_dt_txport(priv);
853 	if (ret)
854 		return ret;
855 
856 	ret = max96714_parse_dt_rxport(priv);
857 	/*
858 	 * The deserializer can create a test pattern even if the
859 	 * rx port is not connected to a serializer.
860 	 */
861 	if (ret && ret == -ENOENT)
862 		ret = 0;
863 
864 	return ret;
865 }
866 
867 static int max96714_enable_core_hw(struct max96714_priv *priv)
868 {
869 	struct device *dev = &priv->client->dev;
870 	u64 val;
871 	int ret;
872 
873 	if (priv->pd_gpio) {
874 		/* wait min 2 ms for reset to complete */
875 		gpiod_set_value_cansleep(priv->pd_gpio, 1);
876 		fsleep(2000);
877 		gpiod_set_value_cansleep(priv->pd_gpio, 0);
878 		/* wait min 2 ms for power up to finish */
879 		fsleep(2000);
880 	}
881 
882 	ret = cci_read(priv->regmap, MAX96714_REG13, &val, NULL);
883 	if (ret) {
884 		dev_err_probe(dev, ret, "Cannot read first register, abort\n");
885 		goto err_pd_gpio;
886 	}
887 
888 	if (val != MAX96714_DEVICE_ID && val != MAX96714F_DEVICE_ID) {
889 		dev_err(dev, "Unsupported device id expected %x got %x\n",
890 			MAX96714F_DEVICE_ID, (u8)val);
891 		ret = -EOPNOTSUPP;
892 		goto err_pd_gpio;
893 	}
894 
895 	ret = cci_read(priv->regmap, MAX96714_DEV_REV, &val, NULL);
896 	if (ret)
897 		goto err_pd_gpio;
898 
899 	dev_dbg(dev, "Found %x (rev %lx)\n", MAX96714F_DEVICE_ID,
900 		(u8)val & MAX96714_DEV_REV_MASK);
901 
902 	ret = cci_read(priv->regmap, MAX96714_MIPI_TX52, &val, NULL);
903 	if (ret)
904 		goto err_pd_gpio;
905 
906 	if (!(val & MAX96714_TUN_EN)) {
907 		dev_err(dev, "Only supporting tunnel mode");
908 		ret = -EOPNOTSUPP;
909 		goto err_pd_gpio;
910 	}
911 
912 	return 0;
913 
914 err_pd_gpio:
915 	gpiod_set_value_cansleep(priv->pd_gpio, 1);
916 	return ret;
917 }
918 
919 static void max96714_disable_core_hw(struct max96714_priv *priv)
920 {
921 	gpiod_set_value_cansleep(priv->pd_gpio, 1);
922 }
923 
924 static int max96714_get_hw_resources(struct max96714_priv *priv)
925 {
926 	struct device *dev = &priv->client->dev;
927 
928 	priv->regmap = devm_cci_regmap_init_i2c(priv->client, 16);
929 	if (IS_ERR(priv->regmap))
930 		return PTR_ERR(priv->regmap);
931 
932 	priv->pd_gpio =
933 		devm_gpiod_get_optional(dev, "powerdown", GPIOD_OUT_HIGH);
934 	if (IS_ERR(priv->pd_gpio))
935 		return dev_err_probe(dev, PTR_ERR(priv->pd_gpio),
936 				     "Cannot get powerdown GPIO\n");
937 	return 0;
938 }
939 
940 static int max96714_probe(struct i2c_client *client)
941 {
942 	struct device *dev = &client->dev;
943 	struct max96714_priv *priv;
944 	int ret;
945 
946 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
947 	if (!priv)
948 		return -ENOMEM;
949 
950 	priv->client = client;
951 
952 	ret = max96714_get_hw_resources(priv);
953 	if (ret)
954 		return ret;
955 
956 	ret = max96714_enable_core_hw(priv);
957 	if (ret)
958 		return ret;
959 
960 	ret = max96714_parse_dt(priv);
961 	if (ret)
962 		goto err_disable_core_hw;
963 
964 	max96714_init_tx_port(priv);
965 
966 	ret = max96714_rxport_enable_poc(priv);
967 	if (ret)
968 		goto err_free_ports;
969 
970 	ret = max96714_i2c_mux_init(priv);
971 	if (ret)
972 		goto err_disable_poc;
973 
974 	ret = max96714_create_subdev(priv);
975 	if (ret)
976 		goto err_del_mux;
977 
978 	return 0;
979 
980 err_del_mux:
981 	i2c_mux_del_adapters(priv->mux);
982 err_disable_poc:
983 	max96714_rxport_disable_poc(priv);
984 err_free_ports:
985 	fwnode_handle_put(priv->rxport.source.ep_fwnode);
986 err_disable_core_hw:
987 	max96714_disable_core_hw(priv);
988 
989 	return ret;
990 }
991 
992 static void max96714_remove(struct i2c_client *client)
993 {
994 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
995 	struct max96714_priv *priv = sd_to_max96714(sd);
996 
997 	max96714_destroy_subdev(priv);
998 	i2c_mux_del_adapters(priv->mux);
999 	max96714_rxport_disable_poc(priv);
1000 	fwnode_handle_put(priv->rxport.source.ep_fwnode);
1001 	max96714_disable_core_hw(priv);
1002 	gpiod_set_value_cansleep(priv->pd_gpio, 1);
1003 }
1004 
1005 static const struct of_device_id max96714_of_ids[] = {
1006 	{ .compatible = "maxim,max96714f" },
1007 	{ }
1008 };
1009 MODULE_DEVICE_TABLE(of, max96714_of_ids);
1010 
1011 static struct i2c_driver max96714_i2c_driver = {
1012 	.driver	= {
1013 		.name		= "max96714",
1014 		.of_match_table	= max96714_of_ids,
1015 	},
1016 	.probe		= max96714_probe,
1017 	.remove		= max96714_remove,
1018 };
1019 
1020 module_i2c_driver(max96714_i2c_driver);
1021 
1022 MODULE_LICENSE("GPL");
1023 MODULE_DESCRIPTION("Maxim Integrated GMSL2 Deserializers Driver");
1024 MODULE_AUTHOR("Julien Massot <julien.massot@collabora.com>");
1025