1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Maxim GMSL2 Deserializer Driver 4 * 5 * Copyright (C) 2024 Collabora Ltd. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bitops.h> 10 #include <linux/fwnode.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/i2c.h> 13 #include <linux/i2c-mux.h> 14 #include <linux/module.h> 15 #include <linux/regmap.h> 16 #include <linux/regulator/consumer.h> 17 18 #include <media/v4l2-cci.h> 19 #include <media/v4l2-ctrls.h> 20 #include <media/v4l2-fwnode.h> 21 #include <media/v4l2-subdev.h> 22 23 #define MAX96714_DEVICE_ID 0xc9 24 #define MAX96714F_DEVICE_ID 0xca 25 #define MAX96714_NPORTS 2 26 #define MAX96714_PAD_SINK 0 27 #define MAX96714_PAD_SOURCE 1 28 #define MAX96714_CSI_NLANES 4 29 30 /* DEV */ 31 #define MAX96714_REG13 CCI_REG8(0x0d) 32 #define MAX96714_DEV_REV CCI_REG8(0x0e) 33 #define MAX96714_DEV_REV_MASK GENMASK(3, 0) 34 #define MAX96714_LINK_LOCK CCI_REG8(0x13) 35 #define MAX96714_LINK_LOCK_BIT BIT(3) 36 #define MAX96714_IO_CHK0 CCI_REG8(0x38) 37 #define MAX96714_PATTERN_CLK_FREQ GENMASK(1, 0) 38 /* VID_RX */ 39 #define MAX96714_VIDEO_RX8 CCI_REG8(0x11a) 40 #define MAX96714_VID_LOCK BIT(6) 41 42 /* VRX_PATGEN_0 */ 43 #define MAX96714_PATGEN_0 CCI_REG8(0x240) 44 #define MAX96714_PATGEN_1 CCI_REG8(0x241) 45 #define MAX96714_PATGEN_MODE GENMASK(5, 4) 46 #define MAX96714_PATGEN_VS_DLY CCI_REG24(0x242) 47 #define MAX96714_PATGEN_VS_HIGH CCI_REG24(0x245) 48 #define MAX96714_PATGEN_VS_LOW CCI_REG24(0x248) 49 #define MAX96714_PATGEN_V2H CCI_REG24(0x24b) 50 #define MAX96714_PATGEN_HS_HIGH CCI_REG16(0x24e) 51 #define MAX96714_PATGEN_HS_LOW CCI_REG16(0x250) 52 #define MAX96714_PATGEN_HS_CNT CCI_REG16(0x252) 53 #define MAX96714_PATGEN_V2D CCI_REG24(0x254) 54 #define MAX96714_PATGEN_DE_HIGH CCI_REG16(0x257) 55 #define MAX96714_PATGEN_DE_LOW CCI_REG16(0x259) 56 #define MAX96714_PATGEN_DE_CNT CCI_REG16(0x25b) 57 #define MAX96714_PATGEN_GRAD_INC CCI_REG8(0x25d) 58 #define MAX96714_PATGEN_CHKB_COLOR_A CCI_REG24(0x25e) 59 #define MAX96714_PATGEN_CHKB_COLOR_B CCI_REG24(0x261) 60 #define MAX96714_PATGEN_CHKB_RPT_CNT_A CCI_REG8(0x264) 61 #define MAX96714_PATGEN_CHKB_RPT_CNT_B CCI_REG8(0x265) 62 #define MAX96714_PATGEN_CHKB_ALT CCI_REG8(0x266) 63 /* BACKTOP */ 64 #define MAX96714_BACKTOP25 CCI_REG8(0x320) 65 #define CSI_DPLL_FREQ_MASK GENMASK(4, 0) 66 67 /* MIPI_PHY */ 68 #define MAX96714_MIPI_PHY0 CCI_REG8(0x330) 69 #define MAX96714_FORCE_CSI_OUT BIT(7) 70 #define MAX96714_MIPI_STDBY_N CCI_REG8(0x332) 71 #define MAX96714_MIPI_STDBY_MASK GENMASK(5, 4) 72 #define MAX96714_MIPI_LANE_MAP CCI_REG8(0x333) 73 #define MAX96714_MIPI_POLARITY CCI_REG8(0x335) 74 #define MAX96714_MIPI_POLARITY_MASK GENMASK(5, 0) 75 76 /* MIPI_TX */ 77 #define MAX96714_MIPI_LANE_CNT CCI_REG8(0x44a) 78 #define MAX96714_CSI2_LANE_CNT_MASK GENMASK(7, 6) 79 #define MAX96714_MIPI_TX52 CCI_REG8(0x474) 80 #define MAX96714_TUN_EN BIT(0) 81 82 #define MHZ(v) ((u32)((v) * 1000000U)) 83 84 enum max96714_vpg_mode { 85 MAX96714_VPG_DISABLED = 0, 86 MAX96714_VPG_CHECKERBOARD = 1, 87 MAX96714_VPG_GRADIENT = 2, 88 }; 89 90 struct max96714_rxport { 91 struct { 92 struct v4l2_subdev *sd; 93 u16 pad; 94 struct fwnode_handle *ep_fwnode; 95 } source; 96 struct regulator *poc; 97 }; 98 99 struct max96714_txport { 100 struct v4l2_fwnode_endpoint vep; 101 }; 102 103 struct max96714_priv { 104 struct i2c_client *client; 105 struct regmap *regmap; 106 struct gpio_desc *pd_gpio; 107 struct max96714_rxport rxport; 108 struct i2c_mux_core *mux; 109 u64 enabled_source_streams; 110 struct v4l2_subdev sd; 111 struct media_pad pads[MAX96714_NPORTS]; 112 struct v4l2_mbus_config_mipi_csi2 mipi_csi2; 113 struct v4l2_ctrl_handler ctrl_handler; 114 struct v4l2_async_notifier notifier; 115 s64 tx_link_freq; 116 enum max96714_vpg_mode pattern; 117 }; 118 119 static inline struct max96714_priv *sd_to_max96714(struct v4l2_subdev *sd) 120 { 121 return container_of(sd, struct max96714_priv, sd); 122 } 123 124 static int max96714_enable_tx_port(struct max96714_priv *priv) 125 { 126 return cci_update_bits(priv->regmap, MAX96714_MIPI_STDBY_N, 127 MAX96714_MIPI_STDBY_MASK, 128 MAX96714_MIPI_STDBY_MASK, NULL); 129 } 130 131 static int max96714_disable_tx_port(struct max96714_priv *priv) 132 { 133 return cci_update_bits(priv->regmap, MAX96714_MIPI_STDBY_N, 134 MAX96714_MIPI_STDBY_MASK, 0, NULL); 135 } 136 137 static bool max96714_tx_port_enabled(struct max96714_priv *priv) 138 { 139 u64 val; 140 141 cci_read(priv->regmap, MAX96714_MIPI_STDBY_N, &val, NULL); 142 143 return val & MAX96714_MIPI_STDBY_MASK; 144 } 145 146 static int max96714_apply_patgen_timing(struct max96714_priv *priv, 147 struct v4l2_subdev_state *state) 148 { 149 struct v4l2_mbus_framefmt *fmt = 150 v4l2_subdev_state_get_format(state, MAX96714_PAD_SOURCE); 151 const u32 h_active = fmt->width; 152 const u32 h_fp = 88; 153 const u32 h_sw = 44; 154 const u32 h_bp = 148; 155 u32 h_tot; 156 const u32 v_active = fmt->height; 157 const u32 v_fp = 4; 158 const u32 v_sw = 5; 159 const u32 v_bp = 36; 160 u32 v_tot; 161 int ret = 0; 162 163 h_tot = h_active + h_fp + h_sw + h_bp; 164 v_tot = v_active + v_fp + v_sw + v_bp; 165 166 /* 75 Mhz pixel clock */ 167 cci_update_bits(priv->regmap, MAX96714_IO_CHK0, 168 MAX96714_PATTERN_CLK_FREQ, 1, &ret); 169 170 dev_info(&priv->client->dev, "height: %d width: %d\n", fmt->height, 171 fmt->width); 172 173 cci_write(priv->regmap, MAX96714_PATGEN_VS_DLY, 0, &ret); 174 cci_write(priv->regmap, MAX96714_PATGEN_VS_HIGH, v_sw * h_tot, &ret); 175 cci_write(priv->regmap, MAX96714_PATGEN_VS_LOW, 176 (v_active + v_fp + v_bp) * h_tot, &ret); 177 cci_write(priv->regmap, MAX96714_PATGEN_HS_HIGH, h_sw, &ret); 178 cci_write(priv->regmap, MAX96714_PATGEN_HS_LOW, h_active + h_fp + h_bp, 179 &ret); 180 cci_write(priv->regmap, MAX96714_PATGEN_V2D, 181 h_tot * (v_sw + v_bp) + (h_sw + h_bp), &ret); 182 cci_write(priv->regmap, MAX96714_PATGEN_HS_CNT, v_tot, &ret); 183 cci_write(priv->regmap, MAX96714_PATGEN_DE_HIGH, h_active, &ret); 184 cci_write(priv->regmap, MAX96714_PATGEN_DE_LOW, h_fp + h_sw + h_bp, 185 &ret); 186 cci_write(priv->regmap, MAX96714_PATGEN_DE_CNT, v_active, &ret); 187 /* B G R */ 188 cci_write(priv->regmap, MAX96714_PATGEN_CHKB_COLOR_A, 0xfecc00, &ret); 189 /* B G R */ 190 cci_write(priv->regmap, MAX96714_PATGEN_CHKB_COLOR_B, 0x006aa7, &ret); 191 cci_write(priv->regmap, MAX96714_PATGEN_CHKB_RPT_CNT_A, 0x3c, &ret); 192 cci_write(priv->regmap, MAX96714_PATGEN_CHKB_RPT_CNT_B, 0x3c, &ret); 193 cci_write(priv->regmap, MAX96714_PATGEN_CHKB_ALT, 0x3c, &ret); 194 cci_write(priv->regmap, MAX96714_PATGEN_GRAD_INC, 0x10, &ret); 195 196 return ret; 197 } 198 199 static int max96714_apply_patgen(struct max96714_priv *priv, 200 struct v4l2_subdev_state *state) 201 { 202 unsigned int val; 203 int ret = 0; 204 205 if (priv->pattern) 206 ret = max96714_apply_patgen_timing(priv, state); 207 208 cci_write(priv->regmap, MAX96714_PATGEN_0, priv->pattern ? 0xfb : 0, 209 &ret); 210 211 val = FIELD_PREP(MAX96714_PATGEN_MODE, priv->pattern); 212 cci_update_bits(priv->regmap, MAX96714_PATGEN_1, MAX96714_PATGEN_MODE, 213 val, &ret); 214 return ret; 215 } 216 217 static int max96714_s_ctrl(struct v4l2_ctrl *ctrl) 218 { 219 struct max96714_priv *priv = 220 container_of(ctrl->handler, struct max96714_priv, ctrl_handler); 221 int ret; 222 223 switch (ctrl->id) { 224 case V4L2_CID_TEST_PATTERN: 225 if (priv->enabled_source_streams) 226 return -EBUSY; 227 priv->pattern = ctrl->val; 228 break; 229 default: 230 return -EINVAL; 231 } 232 233 ret = cci_update_bits(priv->regmap, MAX96714_MIPI_PHY0, 234 MAX96714_FORCE_CSI_OUT, 235 priv->pattern ? MAX96714_FORCE_CSI_OUT : 0, NULL); 236 237 /* Pattern generator doesn't work with tunnel mode */ 238 return cci_update_bits(priv->regmap, MAX96714_MIPI_TX52, 239 MAX96714_TUN_EN, 240 priv->pattern ? 0 : MAX96714_TUN_EN, &ret); 241 } 242 243 static const char * const max96714_test_pattern[] = { 244 "Disabled", 245 "Checkerboard", 246 "Gradient" 247 }; 248 249 static const struct v4l2_ctrl_ops max96714_ctrl_ops = { 250 .s_ctrl = max96714_s_ctrl, 251 }; 252 253 static int max96714_enable_streams(struct v4l2_subdev *sd, 254 struct v4l2_subdev_state *state, 255 u32 source_pad, u64 streams_mask) 256 { 257 struct max96714_priv *priv = sd_to_max96714(sd); 258 u64 sink_streams; 259 int ret; 260 261 if (!priv->enabled_source_streams) 262 max96714_enable_tx_port(priv); 263 264 ret = max96714_apply_patgen(priv, state); 265 if (ret) 266 goto err; 267 268 if (!priv->pattern) { 269 if (!priv->rxport.source.sd) { 270 ret = -ENODEV; 271 goto err; 272 } 273 274 sink_streams = 275 v4l2_subdev_state_xlate_streams(state, 276 MAX96714_PAD_SOURCE, 277 MAX96714_PAD_SINK, 278 &streams_mask); 279 280 ret = v4l2_subdev_enable_streams(priv->rxport.source.sd, 281 priv->rxport.source.pad, 282 sink_streams); 283 if (ret) 284 goto err; 285 } 286 287 priv->enabled_source_streams |= streams_mask; 288 289 return 0; 290 291 err: 292 if (!priv->enabled_source_streams) 293 max96714_disable_tx_port(priv); 294 295 return ret; 296 } 297 298 static int max96714_disable_streams(struct v4l2_subdev *sd, 299 struct v4l2_subdev_state *state, 300 u32 source_pad, u64 streams_mask) 301 { 302 struct max96714_priv *priv = sd_to_max96714(sd); 303 u64 sink_streams; 304 305 if (!priv->pattern) { 306 int ret; 307 308 sink_streams = 309 v4l2_subdev_state_xlate_streams(state, 310 MAX96714_PAD_SOURCE, 311 MAX96714_PAD_SINK, 312 &streams_mask); 313 314 ret = v4l2_subdev_disable_streams(priv->rxport.source.sd, 315 priv->rxport.source.pad, 316 sink_streams); 317 if (ret) 318 return ret; 319 } 320 321 priv->enabled_source_streams &= ~streams_mask; 322 323 if (!priv->enabled_source_streams) 324 max96714_disable_tx_port(priv); 325 326 return 0; 327 } 328 329 static int max96714_set_fmt(struct v4l2_subdev *sd, 330 struct v4l2_subdev_state *state, 331 struct v4l2_subdev_format *format) 332 { 333 struct max96714_priv *priv = sd_to_max96714(sd); 334 struct v4l2_mbus_framefmt *fmt; 335 336 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE && 337 priv->enabled_source_streams) 338 return -EBUSY; 339 340 /* No transcoding, source and sink formats must match. */ 341 if (format->pad == MAX96714_PAD_SOURCE) 342 return v4l2_subdev_get_fmt(sd, state, format); 343 344 fmt = v4l2_subdev_state_get_format(state, format->pad, format->stream); 345 if (!fmt) 346 return -EINVAL; 347 348 *fmt = format->format; 349 350 fmt = v4l2_subdev_state_get_opposite_stream_format(state, format->pad, 351 format->stream); 352 if (!fmt) 353 return -EINVAL; 354 355 *fmt = format->format; 356 357 return 0; 358 } 359 360 static int _max96714_set_routing(struct v4l2_subdev *sd, 361 struct v4l2_subdev_state *state, 362 enum v4l2_subdev_format_whence which, 363 struct v4l2_subdev_krouting *routing) 364 { 365 static const struct v4l2_mbus_framefmt format = { 366 .width = 1280, 367 .height = 1080, 368 .code = MEDIA_BUS_FMT_Y8_1X8, 369 .field = V4L2_FIELD_NONE, 370 }; 371 int ret; 372 373 /* 374 * Note: we can only support up to V4L2_FRAME_DESC_ENTRY_MAX, until 375 * frame desc is made dynamically allocated. 376 */ 377 if (routing->num_routes > V4L2_FRAME_DESC_ENTRY_MAX) 378 return -EINVAL; 379 380 ret = v4l2_subdev_routing_validate(sd, routing, 381 V4L2_SUBDEV_ROUTING_ONLY_1_TO_1); 382 if (ret) 383 return ret; 384 385 return v4l2_subdev_set_routing_with_fmt(sd, state, routing, &format); 386 } 387 388 static int max96714_set_routing(struct v4l2_subdev *sd, 389 struct v4l2_subdev_state *state, 390 enum v4l2_subdev_format_whence which, 391 struct v4l2_subdev_krouting *routing) 392 { 393 struct max96714_priv *priv = sd_to_max96714(sd); 394 395 if (which == V4L2_SUBDEV_FORMAT_ACTIVE && priv->enabled_source_streams) 396 return -EBUSY; 397 398 return _max96714_set_routing(sd, state, which, routing); 399 } 400 401 static int max96714_init_state(struct v4l2_subdev *sd, 402 struct v4l2_subdev_state *state) 403 { 404 struct v4l2_subdev_route routes[] = { 405 { 406 .sink_pad = MAX96714_PAD_SINK, 407 .sink_stream = 0, 408 .source_pad = MAX96714_PAD_SOURCE, 409 .source_stream = 0, 410 .flags = V4L2_SUBDEV_ROUTE_FL_ACTIVE, 411 } 412 }; 413 struct v4l2_subdev_krouting routing = { 414 .num_routes = ARRAY_SIZE(routes), 415 .routes = routes, 416 }; 417 418 return _max96714_set_routing(sd, state, V4L2_SUBDEV_FORMAT_ACTIVE, 419 &routing); 420 } 421 422 static const struct v4l2_subdev_pad_ops max96714_pad_ops = { 423 .enable_streams = max96714_enable_streams, 424 .disable_streams = max96714_disable_streams, 425 426 .set_routing = max96714_set_routing, 427 .get_fmt = v4l2_subdev_get_fmt, 428 .set_fmt = max96714_set_fmt, 429 }; 430 431 static bool max96714_link_locked(struct max96714_priv *priv) 432 { 433 u64 val = 0; 434 435 cci_read(priv->regmap, MAX96714_LINK_LOCK, &val, NULL); 436 437 return val & MAX96714_LINK_LOCK_BIT; 438 } 439 440 static void max96714_link_status(struct max96714_priv *priv) 441 { 442 struct device *dev = &priv->client->dev; 443 444 dev_info(dev, "Link locked:%d\n", max96714_link_locked(priv)); 445 } 446 447 static bool max96714_pipe_locked(struct max96714_priv *priv) 448 { 449 u64 val; 450 451 cci_read(priv->regmap, MAX96714_VIDEO_RX8, &val, NULL); 452 453 return val & MAX96714_VID_LOCK; 454 } 455 456 static void max96714_pipe_status(struct max96714_priv *priv) 457 { 458 struct device *dev = &priv->client->dev; 459 460 dev_info(dev, "Pipe vidlock:%d\n", max96714_pipe_locked(priv)); 461 } 462 463 static void max96714_csi_status(struct max96714_priv *priv) 464 { 465 struct device *dev = &priv->client->dev; 466 u64 freq = 0; 467 468 cci_read(priv->regmap, MAX96714_BACKTOP25, &freq, NULL); 469 freq = FIELD_GET(CSI_DPLL_FREQ_MASK, freq); 470 471 dev_info(dev, "CSI controller DPLL freq:%u00MHz CSIPHY enabled:%d\n", 472 (u8)freq, max96714_tx_port_enabled(priv)); 473 } 474 475 static int max96714_log_status(struct v4l2_subdev *sd) 476 { 477 struct max96714_priv *priv = sd_to_max96714(sd); 478 struct device *dev = &priv->client->dev; 479 480 dev_info(dev, "Deserializer: max96714\n"); 481 482 max96714_link_status(priv); 483 max96714_pipe_status(priv); 484 max96714_csi_status(priv); 485 486 return 0; 487 } 488 489 static const struct v4l2_subdev_core_ops max96714_subdev_core_ops = { 490 .log_status = max96714_log_status, 491 }; 492 493 static const struct v4l2_subdev_video_ops max96714_video_ops = { 494 .s_stream = v4l2_subdev_s_stream_helper, 495 }; 496 497 static const struct v4l2_subdev_internal_ops max96714_internal_ops = { 498 .init_state = max96714_init_state, 499 }; 500 501 static const struct v4l2_subdev_ops max96714_subdev_ops = { 502 .video = &max96714_video_ops, 503 .core = &max96714_subdev_core_ops, 504 .pad = &max96714_pad_ops, 505 }; 506 507 static const struct media_entity_operations max96714_entity_ops = { 508 .link_validate = v4l2_subdev_link_validate, 509 }; 510 511 static int max96714_notify_bound(struct v4l2_async_notifier *notifier, 512 struct v4l2_subdev *subdev, 513 struct v4l2_async_connection *asd) 514 { 515 struct max96714_priv *priv = sd_to_max96714(notifier->sd); 516 struct device *dev = &priv->client->dev; 517 int ret; 518 519 ret = media_entity_get_fwnode_pad(&subdev->entity, 520 priv->rxport.source.ep_fwnode, 521 MEDIA_PAD_FL_SOURCE); 522 if (ret < 0) { 523 dev_err(dev, "Failed to find pad for %s\n", subdev->name); 524 return ret; 525 } 526 527 priv->rxport.source.sd = subdev; 528 priv->rxport.source.pad = ret; 529 530 ret = media_create_pad_link(&priv->rxport.source.sd->entity, 531 priv->rxport.source.pad, &priv->sd.entity, 532 MAX96714_PAD_SINK, 533 MEDIA_LNK_FL_ENABLED | 534 MEDIA_LNK_FL_IMMUTABLE); 535 if (ret) { 536 dev_err(dev, "Unable to link %s:%u -> %s:%u\n", 537 priv->rxport.source.sd->name, priv->rxport.source.pad, 538 priv->sd.name, MAX96714_PAD_SINK); 539 return ret; 540 } 541 542 return 0; 543 } 544 545 static const struct v4l2_async_notifier_operations max96714_notify_ops = { 546 .bound = max96714_notify_bound, 547 }; 548 549 static int max96714_v4l2_notifier_register(struct max96714_priv *priv) 550 { 551 struct device *dev = &priv->client->dev; 552 struct max96714_rxport *rxport = &priv->rxport; 553 struct v4l2_async_connection *asd; 554 int ret; 555 556 if (!rxport->source.ep_fwnode) 557 return 0; 558 559 v4l2_async_subdev_nf_init(&priv->notifier, &priv->sd); 560 561 asd = v4l2_async_nf_add_fwnode(&priv->notifier, 562 rxport->source.ep_fwnode, 563 struct v4l2_async_connection); 564 if (IS_ERR(asd)) { 565 dev_err(dev, "Failed to add subdev: %pe", asd); 566 v4l2_async_nf_cleanup(&priv->notifier); 567 return PTR_ERR(asd); 568 } 569 570 priv->notifier.ops = &max96714_notify_ops; 571 572 ret = v4l2_async_nf_register(&priv->notifier); 573 if (ret) { 574 dev_err(dev, "Failed to register subdev_notifier"); 575 v4l2_async_nf_cleanup(&priv->notifier); 576 return ret; 577 } 578 579 return 0; 580 } 581 582 static int max96714_create_subdev(struct max96714_priv *priv) 583 { 584 struct device *dev = &priv->client->dev; 585 int ret; 586 587 v4l2_i2c_subdev_init(&priv->sd, priv->client, &max96714_subdev_ops); 588 priv->sd.internal_ops = &max96714_internal_ops; 589 590 v4l2_ctrl_handler_init(&priv->ctrl_handler, 1); 591 priv->sd.ctrl_handler = &priv->ctrl_handler; 592 593 v4l2_ctrl_new_int_menu(&priv->ctrl_handler, NULL, V4L2_CID_LINK_FREQ, 594 0, 0, &priv->tx_link_freq); 595 v4l2_ctrl_new_std_menu_items(&priv->ctrl_handler, 596 &max96714_ctrl_ops, 597 V4L2_CID_TEST_PATTERN, 598 ARRAY_SIZE(max96714_test_pattern) - 1, 599 0, 0, max96714_test_pattern); 600 if (priv->ctrl_handler.error) { 601 ret = priv->ctrl_handler.error; 602 goto err_free_ctrl; 603 } 604 605 priv->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_STREAMS; 606 priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 607 priv->sd.entity.ops = &max96714_entity_ops; 608 609 priv->pads[MAX96714_PAD_SINK].flags = MEDIA_PAD_FL_SINK; 610 priv->pads[MAX96714_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; 611 612 ret = media_entity_pads_init(&priv->sd.entity, 613 MAX96714_NPORTS, 614 priv->pads); 615 if (ret) 616 goto err_free_ctrl; 617 618 priv->sd.state_lock = priv->sd.ctrl_handler->lock; 619 620 ret = v4l2_subdev_init_finalize(&priv->sd); 621 if (ret) 622 goto err_entity_cleanup; 623 624 ret = max96714_v4l2_notifier_register(priv); 625 if (ret) { 626 dev_err(dev, "v4l2 subdev notifier register failed: %d\n", ret); 627 goto err_subdev_cleanup; 628 } 629 630 ret = v4l2_async_register_subdev(&priv->sd); 631 if (ret) { 632 dev_err(dev, "v4l2_async_register_subdev error: %d\n", ret); 633 goto err_unreg_notif; 634 } 635 636 return 0; 637 638 err_unreg_notif: 639 v4l2_async_nf_unregister(&priv->notifier); 640 v4l2_async_nf_cleanup(&priv->notifier); 641 err_subdev_cleanup: 642 v4l2_subdev_cleanup(&priv->sd); 643 err_entity_cleanup: 644 media_entity_cleanup(&priv->sd.entity); 645 err_free_ctrl: 646 v4l2_ctrl_handler_free(&priv->ctrl_handler); 647 648 return ret; 649 }; 650 651 static void max96714_destroy_subdev(struct max96714_priv *priv) 652 { 653 v4l2_async_nf_unregister(&priv->notifier); 654 v4l2_async_nf_cleanup(&priv->notifier); 655 v4l2_async_unregister_subdev(&priv->sd); 656 657 v4l2_subdev_cleanup(&priv->sd); 658 659 media_entity_cleanup(&priv->sd.entity); 660 v4l2_ctrl_handler_free(&priv->ctrl_handler); 661 } 662 663 static int max96714_i2c_mux_select(struct i2c_mux_core *mux, u32 chan) 664 { 665 return 0; 666 } 667 668 static int max96714_i2c_mux_init(struct max96714_priv *priv) 669 { 670 priv->mux = i2c_mux_alloc(priv->client->adapter, &priv->client->dev, 671 1, 0, I2C_MUX_LOCKED | I2C_MUX_GATE, 672 max96714_i2c_mux_select, NULL); 673 if (!priv->mux) 674 return -ENOMEM; 675 676 return i2c_mux_add_adapter(priv->mux, 0, 0); 677 } 678 679 static int max96714_init_tx_port(struct max96714_priv *priv) 680 { 681 struct v4l2_mbus_config_mipi_csi2 *mipi; 682 unsigned long lanes_used = 0; 683 unsigned int val, lane; 684 int ret; 685 686 ret = max96714_disable_tx_port(priv); 687 688 mipi = &priv->mipi_csi2; 689 val = div_u64(priv->tx_link_freq * 2, MHZ(100)); 690 691 cci_update_bits(priv->regmap, MAX96714_BACKTOP25, 692 CSI_DPLL_FREQ_MASK, val, &ret); 693 694 val = FIELD_PREP(MAX96714_CSI2_LANE_CNT_MASK, mipi->num_data_lanes - 1); 695 cci_update_bits(priv->regmap, MAX96714_MIPI_LANE_CNT, 696 MAX96714_CSI2_LANE_CNT_MASK, val, &ret); 697 698 /* lanes polarity */ 699 val = 0; 700 for (lane = 0; lane < mipi->num_data_lanes + 1; lane++) { 701 if (!mipi->lane_polarities[lane]) 702 continue; 703 if (lane == 0) 704 /* clock lane */ 705 val |= BIT(5); 706 else if (lane < 3) 707 /* Lane D0 and D1 */ 708 val |= BIT(lane - 1); 709 else 710 /* D2 and D3 */ 711 val |= BIT(lane); 712 } 713 714 cci_update_bits(priv->regmap, MAX96714_MIPI_POLARITY, 715 MAX96714_MIPI_POLARITY_MASK, val, &ret); 716 717 /* lanes mapping */ 718 val = 0; 719 for (lane = 0; lane < mipi->num_data_lanes; lane++) { 720 val |= (mipi->data_lanes[lane] - 1) << (lane * 2); 721 lanes_used |= BIT(mipi->data_lanes[lane] - 1); 722 } 723 724 /* 725 * Unused lanes need to be mapped as well to not have 726 * the same lanes mapped twice. 727 */ 728 for (; lane < MAX96714_CSI_NLANES; lane++) { 729 unsigned int idx = find_first_zero_bit(&lanes_used, 730 MAX96714_CSI_NLANES); 731 732 val |= idx << (lane * 2); 733 lanes_used |= BIT(idx); 734 } 735 736 return cci_write(priv->regmap, MAX96714_MIPI_LANE_MAP, val, &ret); 737 } 738 739 static int max96714_rxport_enable_poc(struct max96714_priv *priv) 740 { 741 struct max96714_rxport *rxport = &priv->rxport; 742 743 if (!rxport->poc) 744 return 0; 745 746 return regulator_enable(rxport->poc); 747 } 748 749 static int max96714_rxport_disable_poc(struct max96714_priv *priv) 750 { 751 struct max96714_rxport *rxport = &priv->rxport; 752 753 if (!rxport->poc) 754 return 0; 755 756 return regulator_disable(rxport->poc); 757 } 758 759 static int max96714_parse_dt_txport(struct max96714_priv *priv) 760 { 761 struct device *dev = &priv->client->dev; 762 struct v4l2_fwnode_endpoint vep = { .bus_type = V4L2_MBUS_CSI2_DPHY }; 763 struct fwnode_handle *ep_fwnode; 764 u32 num_data_lanes; 765 int ret; 766 767 ep_fwnode = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 768 MAX96714_PAD_SOURCE, 0, 0); 769 if (!ep_fwnode) 770 return -EINVAL; 771 772 ret = v4l2_fwnode_endpoint_alloc_parse(ep_fwnode, &vep); 773 fwnode_handle_put(ep_fwnode); 774 if (ret) { 775 dev_err(dev, "tx: failed to parse endpoint data\n"); 776 return -EINVAL; 777 } 778 779 if (vep.nr_of_link_frequencies != 1) { 780 ret = -EINVAL; 781 goto err_free_vep; 782 } 783 784 priv->tx_link_freq = vep.link_frequencies[0]; 785 /* Min 50MHz, Max 1250MHz, 50MHz step */ 786 if (priv->tx_link_freq < MHZ(50) || priv->tx_link_freq > MHZ(1250) || 787 (u32)priv->tx_link_freq % MHZ(50)) { 788 dev_err(dev, "tx: invalid link frequency\n"); 789 ret = -EINVAL; 790 goto err_free_vep; 791 } 792 793 num_data_lanes = vep.bus.mipi_csi2.num_data_lanes; 794 if (num_data_lanes < 1 || num_data_lanes > MAX96714_CSI_NLANES) { 795 dev_err(dev, 796 "tx: invalid number of data lanes must be 1 to 4\n"); 797 ret = -EINVAL; 798 goto err_free_vep; 799 } 800 801 priv->mipi_csi2 = vep.bus.mipi_csi2; 802 803 err_free_vep: 804 v4l2_fwnode_endpoint_free(&vep); 805 806 return ret; 807 } 808 809 static int max96714_parse_dt_rxport(struct max96714_priv *priv) 810 { 811 static const char *poc_name = "port0-poc"; 812 struct max96714_rxport *rxport = &priv->rxport; 813 struct device *dev = &priv->client->dev; 814 struct fwnode_handle *ep_fwnode; 815 int ret; 816 817 ep_fwnode = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 818 MAX96714_PAD_SINK, 0, 0); 819 if (!ep_fwnode) 820 return -ENOENT; 821 822 rxport->source.ep_fwnode = fwnode_graph_get_remote_endpoint(ep_fwnode); 823 fwnode_handle_put(ep_fwnode); 824 825 if (!rxport->source.ep_fwnode) { 826 dev_err(dev, "rx: no remote endpoint\n"); 827 return -EINVAL; 828 } 829 830 rxport->poc = devm_regulator_get_optional(dev, poc_name); 831 if (IS_ERR(rxport->poc)) { 832 ret = PTR_ERR(rxport->poc); 833 if (ret == -ENODEV) { 834 rxport->poc = NULL; 835 } else { 836 dev_err(dev, "rx: failed to get POC supply: %d\n", ret); 837 goto err_put_source_ep_fwnode; 838 } 839 } 840 841 return 0; 842 843 err_put_source_ep_fwnode: 844 fwnode_handle_put(rxport->source.ep_fwnode); 845 return ret; 846 } 847 848 static int max96714_parse_dt(struct max96714_priv *priv) 849 { 850 int ret; 851 852 ret = max96714_parse_dt_txport(priv); 853 if (ret) 854 return ret; 855 856 ret = max96714_parse_dt_rxport(priv); 857 /* 858 * The deserializer can create a test pattern even if the 859 * rx port is not connected to a serializer. 860 */ 861 if (ret && ret == -ENOENT) 862 ret = 0; 863 864 return ret; 865 } 866 867 static int max96714_enable_core_hw(struct max96714_priv *priv) 868 { 869 struct device *dev = &priv->client->dev; 870 u64 val; 871 int ret; 872 873 if (priv->pd_gpio) { 874 /* wait min 2 ms for reset to complete */ 875 gpiod_set_value_cansleep(priv->pd_gpio, 1); 876 fsleep(2000); 877 gpiod_set_value_cansleep(priv->pd_gpio, 0); 878 /* wait min 2 ms for power up to finish */ 879 fsleep(2000); 880 } 881 882 ret = cci_read(priv->regmap, MAX96714_REG13, &val, NULL); 883 if (ret) { 884 dev_err_probe(dev, ret, "Cannot read first register, abort\n"); 885 goto err_pd_gpio; 886 } 887 888 if (val != MAX96714_DEVICE_ID && val != MAX96714F_DEVICE_ID) { 889 dev_err(dev, "Unsupported device id expected %x got %x\n", 890 MAX96714F_DEVICE_ID, (u8)val); 891 ret = -EOPNOTSUPP; 892 goto err_pd_gpio; 893 } 894 895 ret = cci_read(priv->regmap, MAX96714_DEV_REV, &val, NULL); 896 if (ret) 897 goto err_pd_gpio; 898 899 dev_dbg(dev, "Found %x (rev %lx)\n", MAX96714F_DEVICE_ID, 900 (u8)val & MAX96714_DEV_REV_MASK); 901 902 ret = cci_read(priv->regmap, MAX96714_MIPI_TX52, &val, NULL); 903 if (ret) 904 goto err_pd_gpio; 905 906 if (!(val & MAX96714_TUN_EN)) { 907 dev_err(dev, "Only supporting tunnel mode"); 908 ret = -EOPNOTSUPP; 909 goto err_pd_gpio; 910 } 911 912 return 0; 913 914 err_pd_gpio: 915 gpiod_set_value_cansleep(priv->pd_gpio, 1); 916 return ret; 917 } 918 919 static void max96714_disable_core_hw(struct max96714_priv *priv) 920 { 921 gpiod_set_value_cansleep(priv->pd_gpio, 1); 922 } 923 924 static int max96714_get_hw_resources(struct max96714_priv *priv) 925 { 926 struct device *dev = &priv->client->dev; 927 928 priv->regmap = devm_cci_regmap_init_i2c(priv->client, 16); 929 if (IS_ERR(priv->regmap)) 930 return PTR_ERR(priv->regmap); 931 932 priv->pd_gpio = 933 devm_gpiod_get_optional(dev, "powerdown", GPIOD_OUT_HIGH); 934 if (IS_ERR(priv->pd_gpio)) 935 return dev_err_probe(dev, PTR_ERR(priv->pd_gpio), 936 "Cannot get powerdown GPIO\n"); 937 return 0; 938 } 939 940 static int max96714_probe(struct i2c_client *client) 941 { 942 struct device *dev = &client->dev; 943 struct max96714_priv *priv; 944 int ret; 945 946 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 947 if (!priv) 948 return -ENOMEM; 949 950 priv->client = client; 951 952 ret = max96714_get_hw_resources(priv); 953 if (ret) 954 return ret; 955 956 ret = max96714_enable_core_hw(priv); 957 if (ret) 958 return ret; 959 960 ret = max96714_parse_dt(priv); 961 if (ret) 962 goto err_disable_core_hw; 963 964 max96714_init_tx_port(priv); 965 966 ret = max96714_rxport_enable_poc(priv); 967 if (ret) 968 goto err_free_ports; 969 970 ret = max96714_i2c_mux_init(priv); 971 if (ret) 972 goto err_disable_poc; 973 974 ret = max96714_create_subdev(priv); 975 if (ret) 976 goto err_del_mux; 977 978 return 0; 979 980 err_del_mux: 981 i2c_mux_del_adapters(priv->mux); 982 err_disable_poc: 983 max96714_rxport_disable_poc(priv); 984 err_free_ports: 985 fwnode_handle_put(priv->rxport.source.ep_fwnode); 986 err_disable_core_hw: 987 max96714_disable_core_hw(priv); 988 989 return ret; 990 } 991 992 static void max96714_remove(struct i2c_client *client) 993 { 994 struct v4l2_subdev *sd = i2c_get_clientdata(client); 995 struct max96714_priv *priv = sd_to_max96714(sd); 996 997 max96714_destroy_subdev(priv); 998 i2c_mux_del_adapters(priv->mux); 999 max96714_rxport_disable_poc(priv); 1000 fwnode_handle_put(priv->rxport.source.ep_fwnode); 1001 max96714_disable_core_hw(priv); 1002 gpiod_set_value_cansleep(priv->pd_gpio, 1); 1003 } 1004 1005 static const struct of_device_id max96714_of_ids[] = { 1006 { .compatible = "maxim,max96714f" }, 1007 { } 1008 }; 1009 MODULE_DEVICE_TABLE(of, max96714_of_ids); 1010 1011 static struct i2c_driver max96714_i2c_driver = { 1012 .driver = { 1013 .name = "max96714", 1014 .of_match_table = max96714_of_ids, 1015 }, 1016 .probe = max96714_probe, 1017 .remove = max96714_remove, 1018 }; 1019 1020 module_i2c_driver(max96714_i2c_driver); 1021 1022 MODULE_LICENSE("GPL"); 1023 MODULE_DESCRIPTION("Maxim Integrated GMSL2 Deserializers Driver"); 1024 MODULE_AUTHOR("Julien Massot <julien.massot@collabora.com>"); 1025