1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Sony imx412 Camera Sensor Driver 4 * 5 * Copyright (C) 2021 Intel Corporation 6 */ 7 #include <linux/unaligned.h> 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/i2c.h> 12 #include <linux/module.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/regulator/consumer.h> 15 16 #include <media/v4l2-cci.h> 17 #include <media/v4l2-ctrls.h> 18 #include <media/v4l2-fwnode.h> 19 #include <media/v4l2-subdev.h> 20 21 /* Streaming Mode */ 22 #define IMX412_REG_MODE_SELECT CCI_REG8(0x0100) 23 #define IMX412_MODE_STANDBY 0x00 24 #define IMX412_MODE_STREAMING 0x01 25 26 /* Lines per frame */ 27 #define IMX412_REG_LPFR CCI_REG16(0x0340) 28 29 /* Chip ID */ 30 #define IMX412_REG_ID CCI_REG16(0x0016) 31 #define IMX412_ID 0x577 32 33 /* Exposure control */ 34 #define IMX412_REG_EXPOSURE_CIT CCI_REG16(0x0202) 35 #define IMX412_EXPOSURE_MIN 8 36 #define IMX412_EXPOSURE_OFFSET 22 37 #define IMX412_EXPOSURE_STEP 1 38 #define IMX412_EXPOSURE_DEFAULT 0x0648 39 40 /* Analog gain control */ 41 #define IMX412_REG_AGAIN CCI_REG16(0x0204) 42 #define IMX412_AGAIN_MIN 0 43 #define IMX412_AGAIN_MAX 978 44 #define IMX412_AGAIN_STEP 1 45 #define IMX412_AGAIN_DEFAULT 0 46 47 /* Group hold register */ 48 #define IMX412_REG_HOLD CCI_REG8(0x0104) 49 50 /* Input clock rate */ 51 #define IMX412_INCLK_RATE 24000000 52 53 /* CSI2 HW configuration */ 54 #define IMX412_LINK_FREQ 600000000 55 #define IMX412_NUM_DATA_LANES 4 56 57 #define IMX412_REG_MIN 0x00 58 #define IMX412_REG_MAX 0xffff 59 60 /** 61 * struct imx412_reg_list - imx412 sensor register list 62 * @num_of_regs: Number of registers in the list 63 * @regs: Pointer to register list 64 */ 65 struct imx412_reg_list { 66 u32 num_of_regs; 67 const struct cci_reg_sequence *regs; 68 }; 69 70 /** 71 * struct imx412_mode - imx412 sensor mode structure 72 * @width: Frame width 73 * @height: Frame height 74 * @code: Format code 75 * @hblank: Horizontal blanking in lines 76 * @vblank: Vertical blanking in lines 77 * @vblank_min: Minimum vertical blanking in lines 78 * @vblank_max: Maximum vertical blanking in lines 79 * @pclk: Sensor pixel clock 80 * @link_freq_idx: Link frequency index 81 * @reg_list: Register list for sensor mode 82 */ 83 struct imx412_mode { 84 u32 width; 85 u32 height; 86 u32 code; 87 u32 hblank; 88 u32 vblank; 89 u32 vblank_min; 90 u32 vblank_max; 91 u64 pclk; 92 u32 link_freq_idx; 93 struct imx412_reg_list reg_list; 94 }; 95 96 static const char * const imx412_supply_names[] = { 97 "dovdd", /* Digital I/O power */ 98 "avdd", /* Analog power */ 99 "dvdd", /* Digital core power */ 100 }; 101 102 /** 103 * struct imx412 - imx412 sensor device structure 104 * @dev: Pointer to generic device 105 * @cci: CCI register map 106 * @client: Pointer to i2c client 107 * @sd: V4L2 sub-device 108 * @pad: Media pad. Only one pad supported 109 * @reset_gpio: Sensor reset gpio 110 * @inclk: Sensor input clock 111 * @supplies: Regulator supplies 112 * @ctrl_handler: V4L2 control handler 113 * @link_freq_ctrl: Pointer to link frequency control 114 * @pclk_ctrl: Pointer to pixel clock control 115 * @hblank_ctrl: Pointer to horizontal blanking control 116 * @vblank_ctrl: Pointer to vertical blanking control 117 * @exp_ctrl: Pointer to exposure control 118 * @again_ctrl: Pointer to analog gain control 119 * @vblank: Vertical blanking in lines 120 * @cur_mode: Pointer to current selected sensor mode 121 */ 122 struct imx412 { 123 struct device *dev; 124 struct regmap *cci; 125 struct i2c_client *client; 126 struct v4l2_subdev sd; 127 struct media_pad pad; 128 struct gpio_desc *reset_gpio; 129 struct clk *inclk; 130 struct regulator_bulk_data supplies[ARRAY_SIZE(imx412_supply_names)]; 131 struct v4l2_ctrl_handler ctrl_handler; 132 struct v4l2_ctrl *link_freq_ctrl; 133 struct v4l2_ctrl *pclk_ctrl; 134 struct v4l2_ctrl *hblank_ctrl; 135 struct v4l2_ctrl *vblank_ctrl; 136 struct { 137 struct v4l2_ctrl *exp_ctrl; 138 struct v4l2_ctrl *again_ctrl; 139 }; 140 u32 vblank; 141 const struct imx412_mode *cur_mode; 142 }; 143 144 static const s64 link_freq[] = { 145 IMX412_LINK_FREQ, 146 }; 147 148 /* Sensor mode registers */ 149 static const struct cci_reg_sequence mode_4056x3040_regs[] = { 150 { CCI_REG8(0x0136), 0x18 }, 151 { CCI_REG8(0x0137), 0x00 }, 152 { CCI_REG8(0x3c7e), 0x08 }, 153 { CCI_REG8(0x3c7f), 0x02 }, 154 { CCI_REG8(0x38a8), 0x1f }, 155 { CCI_REG8(0x38a9), 0xff }, 156 { CCI_REG8(0x38aa), 0x1f }, 157 { CCI_REG8(0x38ab), 0xff }, 158 { CCI_REG8(0x55d4), 0x00 }, 159 { CCI_REG8(0x55d5), 0x00 }, 160 { CCI_REG8(0x55d6), 0x07 }, 161 { CCI_REG8(0x55d7), 0xff }, 162 { CCI_REG8(0x55e8), 0x07 }, 163 { CCI_REG8(0x55e9), 0xff }, 164 { CCI_REG8(0x55ea), 0x00 }, 165 { CCI_REG8(0x55eb), 0x00 }, 166 { CCI_REG8(0x575c), 0x07 }, 167 { CCI_REG8(0x575d), 0xff }, 168 { CCI_REG8(0x575e), 0x00 }, 169 { CCI_REG8(0x575f), 0x00 }, 170 { CCI_REG8(0x5764), 0x00 }, 171 { CCI_REG8(0x5765), 0x00 }, 172 { CCI_REG8(0x5766), 0x07 }, 173 { CCI_REG8(0x5767), 0xff }, 174 { CCI_REG8(0x5974), 0x04 }, 175 { CCI_REG8(0x5975), 0x01 }, 176 { CCI_REG8(0x5f10), 0x09 }, 177 { CCI_REG8(0x5f11), 0x92 }, 178 { CCI_REG8(0x5f12), 0x32 }, 179 { CCI_REG8(0x5f13), 0x72 }, 180 { CCI_REG8(0x5f14), 0x16 }, 181 { CCI_REG8(0x5f15), 0xba }, 182 { CCI_REG8(0x5f17), 0x13 }, 183 { CCI_REG8(0x5f18), 0x24 }, 184 { CCI_REG8(0x5f19), 0x60 }, 185 { CCI_REG8(0x5f1a), 0xe3 }, 186 { CCI_REG8(0x5f1b), 0xad }, 187 { CCI_REG8(0x5f1c), 0x74 }, 188 { CCI_REG8(0x5f2d), 0x25 }, 189 { CCI_REG8(0x5f5c), 0xd0 }, 190 { CCI_REG8(0x6a22), 0x00 }, 191 { CCI_REG8(0x6a23), 0x1d }, 192 { CCI_REG8(0x7ba8), 0x00 }, 193 { CCI_REG8(0x7ba9), 0x00 }, 194 { CCI_REG8(0x886b), 0x00 }, 195 { CCI_REG8(0x9002), 0x0a }, 196 { CCI_REG8(0x9004), 0x1a }, 197 { CCI_REG8(0x9214), 0x93 }, 198 { CCI_REG8(0x9215), 0x69 }, 199 { CCI_REG8(0x9216), 0x93 }, 200 { CCI_REG8(0x9217), 0x6b }, 201 { CCI_REG8(0x9218), 0x93 }, 202 { CCI_REG8(0x9219), 0x6d }, 203 { CCI_REG8(0x921a), 0x57 }, 204 { CCI_REG8(0x921b), 0x58 }, 205 { CCI_REG8(0x921c), 0x57 }, 206 { CCI_REG8(0x921d), 0x59 }, 207 { CCI_REG8(0x921e), 0x57 }, 208 { CCI_REG8(0x921f), 0x5a }, 209 { CCI_REG8(0x9220), 0x57 }, 210 { CCI_REG8(0x9221), 0x5b }, 211 { CCI_REG8(0x9222), 0x93 }, 212 { CCI_REG8(0x9223), 0x02 }, 213 { CCI_REG8(0x9224), 0x93 }, 214 { CCI_REG8(0x9225), 0x03 }, 215 { CCI_REG8(0x9226), 0x93 }, 216 { CCI_REG8(0x9227), 0x04 }, 217 { CCI_REG8(0x9228), 0x93 }, 218 { CCI_REG8(0x9229), 0x05 }, 219 { CCI_REG8(0x922a), 0x98 }, 220 { CCI_REG8(0x922b), 0x21 }, 221 { CCI_REG8(0x922c), 0xb2 }, 222 { CCI_REG8(0x922d), 0xdb }, 223 { CCI_REG8(0x922e), 0xb2 }, 224 { CCI_REG8(0x922f), 0xdc }, 225 { CCI_REG8(0x9230), 0xb2 }, 226 { CCI_REG8(0x9231), 0xdd }, 227 { CCI_REG8(0x9232), 0xe2 }, 228 { CCI_REG8(0x9233), 0xe1 }, 229 { CCI_REG8(0x9234), 0xb2 }, 230 { CCI_REG8(0x9235), 0xe2 }, 231 { CCI_REG8(0x9236), 0xb2 }, 232 { CCI_REG8(0x9237), 0xe3 }, 233 { CCI_REG8(0x9238), 0xb7 }, 234 { CCI_REG8(0x9239), 0xb9 }, 235 { CCI_REG8(0x923a), 0xb7 }, 236 { CCI_REG8(0x923b), 0xbb }, 237 { CCI_REG8(0x923c), 0xb7 }, 238 { CCI_REG8(0x923d), 0xbc }, 239 { CCI_REG8(0x923e), 0xb7 }, 240 { CCI_REG8(0x923f), 0xc5 }, 241 { CCI_REG8(0x9240), 0xb7 }, 242 { CCI_REG8(0x9241), 0xc7 }, 243 { CCI_REG8(0x9242), 0xb7 }, 244 { CCI_REG8(0x9243), 0xc9 }, 245 { CCI_REG8(0x9244), 0x98 }, 246 { CCI_REG8(0x9245), 0x56 }, 247 { CCI_REG8(0x9246), 0x98 }, 248 { CCI_REG8(0x9247), 0x55 }, 249 { CCI_REG8(0x9380), 0x00 }, 250 { CCI_REG8(0x9381), 0x62 }, 251 { CCI_REG8(0x9382), 0x00 }, 252 { CCI_REG8(0x9383), 0x56 }, 253 { CCI_REG8(0x9384), 0x00 }, 254 { CCI_REG8(0x9385), 0x52 }, 255 { CCI_REG8(0x9388), 0x00 }, 256 { CCI_REG8(0x9389), 0x55 }, 257 { CCI_REG8(0x938a), 0x00 }, 258 { CCI_REG8(0x938b), 0x55 }, 259 { CCI_REG8(0x938c), 0x00 }, 260 { CCI_REG8(0x938d), 0x41 }, 261 { CCI_REG8(0x5078), 0x01 }, 262 { CCI_REG8(0x0112), 0x0a }, 263 { CCI_REG8(0x0113), 0x0a }, 264 { CCI_REG8(0x0114), 0x03 }, 265 { CCI_REG8(0x0342), 0x11 }, 266 { CCI_REG8(0x0343), 0xa0 }, 267 { CCI_REG8(0x0340), 0x0d }, 268 { CCI_REG8(0x0341), 0xda }, 269 { CCI_REG8(0x3210), 0x00 }, 270 { CCI_REG8(0x0344), 0x00 }, 271 { CCI_REG8(0x0345), 0x00 }, 272 { CCI_REG8(0x0346), 0x00 }, 273 { CCI_REG8(0x0347), 0x00 }, 274 { CCI_REG8(0x0348), 0x0f }, 275 { CCI_REG8(0x0349), 0xd7 }, 276 { CCI_REG8(0x034a), 0x0b }, 277 { CCI_REG8(0x034b), 0xdf }, 278 { CCI_REG8(0x00e3), 0x00 }, 279 { CCI_REG8(0x00e4), 0x00 }, 280 { CCI_REG8(0x00e5), 0x01 }, 281 { CCI_REG8(0x00fc), 0x0a }, 282 { CCI_REG8(0x00fd), 0x0a }, 283 { CCI_REG8(0x00fe), 0x0a }, 284 { CCI_REG8(0x00ff), 0x0a }, 285 { CCI_REG8(0xe013), 0x00 }, 286 { CCI_REG8(0x0220), 0x00 }, 287 { CCI_REG8(0x0221), 0x11 }, 288 { CCI_REG8(0x0381), 0x01 }, 289 { CCI_REG8(0x0383), 0x01 }, 290 { CCI_REG8(0x0385), 0x01 }, 291 { CCI_REG8(0x0387), 0x01 }, 292 { CCI_REG8(0x0900), 0x00 }, 293 { CCI_REG8(0x0901), 0x11 }, 294 { CCI_REG8(0x0902), 0x00 }, 295 { CCI_REG8(0x3140), 0x02 }, 296 { CCI_REG8(0x3241), 0x11 }, 297 { CCI_REG8(0x3250), 0x03 }, 298 { CCI_REG8(0x3e10), 0x00 }, 299 { CCI_REG8(0x3e11), 0x00 }, 300 { CCI_REG8(0x3f0d), 0x00 }, 301 { CCI_REG8(0x3f42), 0x00 }, 302 { CCI_REG8(0x3f43), 0x00 }, 303 { CCI_REG8(0x0401), 0x00 }, 304 { CCI_REG8(0x0404), 0x00 }, 305 { CCI_REG8(0x0405), 0x10 }, 306 { CCI_REG8(0x0408), 0x00 }, 307 { CCI_REG8(0x0409), 0x00 }, 308 { CCI_REG8(0x040a), 0x00 }, 309 { CCI_REG8(0x040b), 0x00 }, 310 { CCI_REG8(0x040c), 0x0f }, 311 { CCI_REG8(0x040d), 0xd8 }, 312 { CCI_REG8(0x040e), 0x0b }, 313 { CCI_REG8(0x040f), 0xe0 }, 314 { CCI_REG8(0x034c), 0x0f }, 315 { CCI_REG8(0x034d), 0xd8 }, 316 { CCI_REG8(0x034e), 0x0b }, 317 { CCI_REG8(0x034f), 0xe0 }, 318 { CCI_REG8(0x0301), 0x05 }, 319 { CCI_REG8(0x0303), 0x02 }, 320 { CCI_REG8(0x0305), 0x04 }, 321 { CCI_REG8(0x0306), 0x00 }, 322 { CCI_REG8(0x0307), 0xc8 }, 323 { CCI_REG8(0x0309), 0x0a }, 324 { CCI_REG8(0x030b), 0x01 }, 325 { CCI_REG8(0x030d), 0x02 }, 326 { CCI_REG8(0x030e), 0x01 }, 327 { CCI_REG8(0x030f), 0x5e }, 328 { CCI_REG8(0x0310), 0x00 }, 329 { CCI_REG8(0x0820), 0x12 }, 330 { CCI_REG8(0x0821), 0xc0 }, 331 { CCI_REG8(0x0822), 0x00 }, 332 { CCI_REG8(0x0823), 0x00 }, 333 { CCI_REG8(0x3e20), 0x01 }, 334 { CCI_REG8(0x3e37), 0x00 }, 335 { CCI_REG8(0x3f50), 0x00 }, 336 { CCI_REG8(0x3f56), 0x00 }, 337 { CCI_REG8(0x3f57), 0xe2 }, 338 { CCI_REG8(0x3c0a), 0x5a }, 339 { CCI_REG8(0x3c0b), 0x55 }, 340 { CCI_REG8(0x3c0c), 0x28 }, 341 { CCI_REG8(0x3c0d), 0x07 }, 342 { CCI_REG8(0x3c0e), 0xff }, 343 { CCI_REG8(0x3c0f), 0x00 }, 344 { CCI_REG8(0x3c10), 0x00 }, 345 { CCI_REG8(0x3c11), 0x02 }, 346 { CCI_REG8(0x3c12), 0x00 }, 347 { CCI_REG8(0x3c13), 0x03 }, 348 { CCI_REG8(0x3c14), 0x00 }, 349 { CCI_REG8(0x3c15), 0x00 }, 350 { CCI_REG8(0x3c16), 0x0c }, 351 { CCI_REG8(0x3c17), 0x0c }, 352 { CCI_REG8(0x3c18), 0x0c }, 353 { CCI_REG8(0x3c19), 0x0a }, 354 { CCI_REG8(0x3c1a), 0x0a }, 355 { CCI_REG8(0x3c1b), 0x0a }, 356 { CCI_REG8(0x3c1c), 0x00 }, 357 { CCI_REG8(0x3c1d), 0x00 }, 358 { CCI_REG8(0x3c1e), 0x00 }, 359 { CCI_REG8(0x3c1f), 0x00 }, 360 { CCI_REG8(0x3c20), 0x00 }, 361 { CCI_REG8(0x3c21), 0x00 }, 362 { CCI_REG8(0x3c22), 0x3f }, 363 { CCI_REG8(0x3c23), 0x0a }, 364 { CCI_REG8(0x3e35), 0x01 }, 365 { CCI_REG8(0x3f4a), 0x03 }, 366 { CCI_REG8(0x3f4b), 0xbf }, 367 { CCI_REG8(0x3f26), 0x00 }, 368 { CCI_REG8(0x0202), 0x0d }, 369 { CCI_REG8(0x0203), 0xc4 }, 370 { CCI_REG8(0x0204), 0x00 }, 371 { CCI_REG8(0x0205), 0x00 }, 372 { CCI_REG8(0x020e), 0x01 }, 373 { CCI_REG8(0x020f), 0x00 }, 374 { CCI_REG8(0x0210), 0x01 }, 375 { CCI_REG8(0x0211), 0x00 }, 376 { CCI_REG8(0x0212), 0x01 }, 377 { CCI_REG8(0x0213), 0x00 }, 378 { CCI_REG8(0x0214), 0x01 }, 379 { CCI_REG8(0x0215), 0x00 }, 380 { CCI_REG8(0xbcf1), 0x00 }, 381 }; 382 383 /* Supported sensor mode configurations */ 384 static const struct imx412_mode supported_mode = { 385 .width = 4056, 386 .height = 3040, 387 .hblank = 456, 388 .vblank = 506, 389 .vblank_min = 506, 390 .vblank_max = 32420, 391 .pclk = 480000000, 392 .link_freq_idx = 0, 393 .code = MEDIA_BUS_FMT_SRGGB10_1X10, 394 .reg_list = { 395 .num_of_regs = ARRAY_SIZE(mode_4056x3040_regs), 396 .regs = mode_4056x3040_regs, 397 }, 398 }; 399 400 /** 401 * to_imx412() - imx412 V4L2 sub-device to imx412 device. 402 * @subdev: pointer to imx412 V4L2 sub-device 403 * 404 * Return: pointer to imx412 device 405 */ 406 static inline struct imx412 *to_imx412(struct v4l2_subdev *subdev) 407 { 408 return container_of(subdev, struct imx412, sd); 409 } 410 411 /** 412 * imx412_update_controls() - Update control ranges based on streaming mode 413 * @imx412: pointer to imx412 device 414 * @mode: pointer to imx412_mode sensor mode 415 * 416 * Return: 0 if successful, error code otherwise. 417 */ 418 static int imx412_update_controls(struct imx412 *imx412, 419 const struct imx412_mode *mode) 420 { 421 int ret; 422 423 ret = __v4l2_ctrl_s_ctrl(imx412->link_freq_ctrl, mode->link_freq_idx); 424 if (ret) 425 return ret; 426 427 ret = __v4l2_ctrl_s_ctrl(imx412->hblank_ctrl, mode->hblank); 428 if (ret) 429 return ret; 430 431 return __v4l2_ctrl_modify_range(imx412->vblank_ctrl, mode->vblank_min, 432 mode->vblank_max, 1, mode->vblank); 433 } 434 435 /** 436 * imx412_update_exp_gain() - Set updated exposure and gain 437 * @imx412: pointer to imx412 device 438 * @exposure: updated exposure value 439 * @gain: updated analog gain value 440 * 441 * Return: 0 if successful, error code otherwise. 442 */ 443 static int imx412_update_exp_gain(struct imx412 *imx412, u32 exposure, u32 gain) 444 { 445 u32 lpfr; 446 int ret = 0; 447 int ret_hold; 448 449 lpfr = imx412->vblank + imx412->cur_mode->height; 450 451 dev_dbg(imx412->dev, "Set exp %u, analog gain %u, lpfr %u\n", 452 exposure, gain, lpfr); 453 454 cci_write(imx412->cci, IMX412_REG_HOLD, 1, &ret); 455 456 cci_write(imx412->cci, IMX412_REG_LPFR, lpfr, &ret); 457 458 cci_write(imx412->cci, IMX412_REG_EXPOSURE_CIT, exposure, &ret); 459 460 cci_write(imx412->cci, IMX412_REG_AGAIN, gain, &ret); 461 462 ret_hold = cci_write(imx412->cci, IMX412_REG_HOLD, 0, NULL); 463 if (ret_hold) 464 return ret_hold; 465 466 return ret; 467 } 468 469 static int imx412_set_ctrl(struct v4l2_ctrl *ctrl) 470 { 471 struct imx412 *imx412 = 472 container_of(ctrl->handler, struct imx412, ctrl_handler); 473 u32 analog_gain; 474 u32 exposure; 475 int ret; 476 477 switch (ctrl->id) { 478 case V4L2_CID_VBLANK: 479 imx412->vblank = imx412->vblank_ctrl->val; 480 481 dev_dbg(imx412->dev, "Received vblank %u, new lpfr %u\n", 482 imx412->vblank, 483 imx412->vblank + imx412->cur_mode->height); 484 485 ret = __v4l2_ctrl_modify_range(imx412->exp_ctrl, 486 IMX412_EXPOSURE_MIN, 487 imx412->vblank + 488 imx412->cur_mode->height - 489 IMX412_EXPOSURE_OFFSET, 490 1, IMX412_EXPOSURE_DEFAULT); 491 break; 492 case V4L2_CID_EXPOSURE: 493 /* Set controls only if sensor is in power on state */ 494 if (!pm_runtime_get_if_in_use(imx412->dev)) 495 return 0; 496 497 exposure = ctrl->val; 498 analog_gain = imx412->again_ctrl->val; 499 500 dev_dbg(imx412->dev, "Received exp %u, analog gain %u\n", 501 exposure, analog_gain); 502 503 ret = imx412_update_exp_gain(imx412, exposure, analog_gain); 504 505 pm_runtime_put(imx412->dev); 506 507 break; 508 default: 509 dev_err(imx412->dev, "Invalid control %d\n", ctrl->id); 510 ret = -EINVAL; 511 } 512 513 return ret; 514 } 515 516 /* V4l2 subdevice control ops*/ 517 static const struct v4l2_ctrl_ops imx412_ctrl_ops = { 518 .s_ctrl = imx412_set_ctrl, 519 }; 520 521 static int imx412_enum_mbus_code(struct v4l2_subdev *sd, 522 struct v4l2_subdev_state *sd_state, 523 struct v4l2_subdev_mbus_code_enum *code) 524 { 525 if (code->index > 0) 526 return -EINVAL; 527 528 code->code = supported_mode.code; 529 530 return 0; 531 } 532 533 static int imx412_enum_frame_size(struct v4l2_subdev *sd, 534 struct v4l2_subdev_state *sd_state, 535 struct v4l2_subdev_frame_size_enum *fsize) 536 { 537 if (fsize->index > 0) 538 return -EINVAL; 539 540 if (fsize->code != supported_mode.code) 541 return -EINVAL; 542 543 fsize->min_width = supported_mode.width; 544 fsize->max_width = fsize->min_width; 545 fsize->min_height = supported_mode.height; 546 fsize->max_height = fsize->min_height; 547 548 return 0; 549 } 550 551 /** 552 * imx412_fill_pad_format() - Fill subdevice pad format 553 * from selected sensor mode 554 * @imx412: pointer to imx412 device 555 * @mode: pointer to imx412_mode sensor mode 556 * @fmt: V4L2 sub-device format need to be filled 557 */ 558 static void imx412_fill_pad_format(struct imx412 *imx412, 559 const struct imx412_mode *mode, 560 struct v4l2_subdev_format *fmt) 561 { 562 fmt->format.width = mode->width; 563 fmt->format.height = mode->height; 564 fmt->format.code = mode->code; 565 fmt->format.field = V4L2_FIELD_NONE; 566 fmt->format.colorspace = V4L2_COLORSPACE_RAW; 567 fmt->format.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 568 fmt->format.quantization = V4L2_QUANTIZATION_DEFAULT; 569 fmt->format.xfer_func = V4L2_XFER_FUNC_NONE; 570 } 571 572 static int imx412_get_pad_format(struct v4l2_subdev *sd, 573 struct v4l2_subdev_state *sd_state, 574 struct v4l2_subdev_format *fmt) 575 { 576 struct imx412 *imx412 = to_imx412(sd); 577 578 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 579 struct v4l2_mbus_framefmt *framefmt; 580 581 framefmt = v4l2_subdev_state_get_format(sd_state, fmt->pad); 582 fmt->format = *framefmt; 583 } else { 584 imx412_fill_pad_format(imx412, imx412->cur_mode, fmt); 585 } 586 587 return 0; 588 } 589 590 static int imx412_set_pad_format(struct v4l2_subdev *sd, 591 struct v4l2_subdev_state *sd_state, 592 struct v4l2_subdev_format *fmt) 593 { 594 struct imx412 *imx412 = to_imx412(sd); 595 const struct imx412_mode *mode; 596 int ret = 0; 597 598 mode = &supported_mode; 599 imx412_fill_pad_format(imx412, mode, fmt); 600 601 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 602 struct v4l2_mbus_framefmt *framefmt; 603 604 framefmt = v4l2_subdev_state_get_format(sd_state, fmt->pad); 605 *framefmt = fmt->format; 606 } else { 607 ret = imx412_update_controls(imx412, mode); 608 if (!ret) 609 imx412->cur_mode = mode; 610 } 611 612 return ret; 613 } 614 615 static int imx412_init_state(struct v4l2_subdev *sd, 616 struct v4l2_subdev_state *sd_state) 617 { 618 struct imx412 *imx412 = to_imx412(sd); 619 struct v4l2_subdev_format fmt = { 0 }; 620 621 fmt.which = sd_state ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE; 622 imx412_fill_pad_format(imx412, &supported_mode, &fmt); 623 624 return imx412_set_pad_format(sd, sd_state, &fmt); 625 } 626 627 /** 628 * imx412_enable_streams() - Enable specified streams for the sensor 629 * @sd: pointer to the V4L2 subdevice 630 * @state: pointer to the subdevice state 631 * @pad: pad number for which streams are enabled 632 * @streams_mask: bitmask specifying the streams to enable 633 * 634 * Return: 0 if successful, error code otherwise. 635 */ 636 static int imx412_enable_streams(struct v4l2_subdev *sd, 637 struct v4l2_subdev_state *state, 638 u32 pad, u64 streams_mask) 639 { 640 const struct imx412_reg_list *reg_list; 641 struct imx412 *imx412 = to_imx412(sd); 642 int ret; 643 644 ret = pm_runtime_resume_and_get(imx412->dev); 645 if (ret < 0) 646 return ret; 647 648 /* Write sensor mode registers */ 649 reg_list = &imx412->cur_mode->reg_list; 650 ret = cci_multi_reg_write(imx412->cci, reg_list->regs, 651 reg_list->num_of_regs, NULL); 652 if (ret) { 653 dev_err(imx412->dev, "fail to write initial registers\n"); 654 goto err_rpm_put; 655 } 656 657 /* Setup handler will write actual exposure and gain */ 658 ret = __v4l2_ctrl_handler_setup(imx412->sd.ctrl_handler); 659 if (ret) { 660 dev_err(imx412->dev, "fail to setup handler\n"); 661 goto err_rpm_put; 662 } 663 664 /* Delay is required before streaming*/ 665 usleep_range(7400, 8000); 666 667 /* Start streaming */ 668 ret = cci_write(imx412->cci, IMX412_REG_MODE_SELECT, 669 IMX412_MODE_STREAMING, NULL); 670 if (ret) { 671 dev_err(imx412->dev, "fail to start streaming\n"); 672 goto err_rpm_put; 673 } 674 675 return 0; 676 677 err_rpm_put: 678 pm_runtime_put(imx412->dev); 679 680 return ret; 681 } 682 683 /** 684 * imx412_disable_streams() - Enable specified streams for the sensor 685 * @sd: pointer to the V4L2 subdevice 686 * @state: pointer to the subdevice state 687 * @pad: pad number for which streams are disabled 688 * @streams_mask: bitmask specifying the streams to disable 689 * 690 * Return: 0 if successful, error code otherwise. 691 */ 692 static int imx412_disable_streams(struct v4l2_subdev *sd, 693 struct v4l2_subdev_state *state, 694 u32 pad, u64 streams_mask) 695 { 696 struct imx412 *imx412 = to_imx412(sd); 697 int ret; 698 699 ret = cci_write(imx412->cci, IMX412_REG_MODE_SELECT, 700 IMX412_MODE_STANDBY, NULL); 701 702 if (ret) 703 dev_err(imx412->dev, "failed to set stream off\n"); 704 705 pm_runtime_put(imx412->dev); 706 707 return 0; 708 } 709 710 /** 711 * imx412_detect() - Detect imx412 sensor 712 * @imx412: pointer to imx412 device 713 * 714 * Return: 0 if successful, -EIO if sensor id does not match 715 */ 716 static int imx412_detect(struct imx412 *imx412) 717 { 718 int ret; 719 u64 val; 720 721 ret = cci_read(imx412->cci, IMX412_REG_ID, &val, NULL); 722 if (ret) 723 return dev_err_probe(imx412->dev, ret, 724 "failed to read chip id %x\n", 725 IMX412_ID); 726 727 if (val != IMX412_ID) { 728 return dev_err_probe(imx412->dev, -ENODEV, 729 "chip id mismatch: %x!=%llx", 730 IMX412_ID, val); 731 } 732 733 return 0; 734 } 735 736 /** 737 * imx412_parse_hw_config() - Parse HW configuration and check if supported 738 * @imx412: pointer to imx412 device 739 * 740 * Return: 0 if successful, error code otherwise. 741 */ 742 static int imx412_parse_hw_config(struct imx412 *imx412) 743 { 744 struct fwnode_handle *fwnode = dev_fwnode(imx412->dev); 745 struct v4l2_fwnode_endpoint bus_cfg = { 746 .bus_type = V4L2_MBUS_CSI2_DPHY 747 }; 748 struct fwnode_handle *ep; 749 unsigned long rate; 750 unsigned int i; 751 int ret; 752 753 if (!fwnode) 754 return -ENXIO; 755 756 /* Request optional reset pin */ 757 imx412->reset_gpio = devm_gpiod_get_optional(imx412->dev, "reset", 758 GPIOD_OUT_HIGH); 759 if (IS_ERR(imx412->reset_gpio)) { 760 dev_err(imx412->dev, "failed to get reset gpio %pe\n", 761 imx412->reset_gpio); 762 return PTR_ERR(imx412->reset_gpio); 763 } 764 765 /* Get sensor input clock */ 766 imx412->inclk = devm_v4l2_sensor_clk_get(imx412->dev, NULL); 767 if (IS_ERR(imx412->inclk)) 768 return dev_err_probe(imx412->dev, PTR_ERR(imx412->inclk), 769 "could not get inclk\n"); 770 771 rate = clk_get_rate(imx412->inclk); 772 if (rate != IMX412_INCLK_RATE) { 773 dev_err(imx412->dev, "inclk frequency mismatch\n"); 774 return -EINVAL; 775 } 776 777 /* Get optional DT defined regulators */ 778 for (i = 0; i < ARRAY_SIZE(imx412_supply_names); i++) 779 imx412->supplies[i].supply = imx412_supply_names[i]; 780 781 ret = devm_regulator_bulk_get(imx412->dev, 782 ARRAY_SIZE(imx412_supply_names), 783 imx412->supplies); 784 if (ret) 785 return ret; 786 787 ep = fwnode_graph_get_next_endpoint(fwnode, NULL); 788 if (!ep) 789 return -ENXIO; 790 791 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); 792 fwnode_handle_put(ep); 793 if (ret) 794 return ret; 795 796 if (bus_cfg.bus.mipi_csi2.num_data_lanes != IMX412_NUM_DATA_LANES) { 797 dev_err(imx412->dev, 798 "number of CSI2 data lanes %d is not supported\n", 799 bus_cfg.bus.mipi_csi2.num_data_lanes); 800 ret = -EINVAL; 801 goto done_endpoint_free; 802 } 803 804 if (!bus_cfg.nr_of_link_frequencies) { 805 dev_err(imx412->dev, "no link frequencies defined\n"); 806 ret = -EINVAL; 807 goto done_endpoint_free; 808 } 809 810 for (i = 0; i < bus_cfg.nr_of_link_frequencies; i++) 811 if (bus_cfg.link_frequencies[i] == IMX412_LINK_FREQ) 812 goto done_endpoint_free; 813 814 ret = -EINVAL; 815 816 done_endpoint_free: 817 v4l2_fwnode_endpoint_free(&bus_cfg); 818 819 return ret; 820 } 821 822 /* V4l2 subdevice ops */ 823 static const struct v4l2_subdev_video_ops imx412_video_ops = { 824 .s_stream = v4l2_subdev_s_stream_helper, 825 }; 826 827 static const struct v4l2_subdev_pad_ops imx412_pad_ops = { 828 .enum_mbus_code = imx412_enum_mbus_code, 829 .enum_frame_size = imx412_enum_frame_size, 830 .get_fmt = imx412_get_pad_format, 831 .set_fmt = imx412_set_pad_format, 832 .enable_streams = imx412_enable_streams, 833 .disable_streams = imx412_disable_streams, 834 }; 835 836 static const struct v4l2_subdev_ops imx412_subdev_ops = { 837 .video = &imx412_video_ops, 838 .pad = &imx412_pad_ops, 839 }; 840 841 static const struct v4l2_subdev_internal_ops imx412_internal_ops = { 842 .init_state = imx412_init_state, 843 }; 844 845 static int imx412_power_on(struct device *dev) 846 { 847 struct v4l2_subdev *sd = dev_get_drvdata(dev); 848 struct imx412 *imx412 = to_imx412(sd); 849 int ret; 850 851 ret = regulator_bulk_enable(ARRAY_SIZE(imx412_supply_names), 852 imx412->supplies); 853 if (ret < 0) { 854 dev_err(dev, "failed to enable regulators\n"); 855 return ret; 856 } 857 858 gpiod_set_value_cansleep(imx412->reset_gpio, 0); 859 860 ret = clk_prepare_enable(imx412->inclk); 861 if (ret) { 862 dev_err(imx412->dev, "fail to enable inclk\n"); 863 goto error_reset; 864 } 865 866 /* 867 * Certain Arducam IMX577 module variants require a longer reset settle 868 * time. Increasing the delay from 1ms to 10ms ensures reliable startup. 869 */ 870 usleep_range(10000, 12000); 871 872 return 0; 873 874 error_reset: 875 gpiod_set_value_cansleep(imx412->reset_gpio, 1); 876 regulator_bulk_disable(ARRAY_SIZE(imx412_supply_names), 877 imx412->supplies); 878 879 return ret; 880 } 881 882 static int imx412_power_off(struct device *dev) 883 { 884 struct v4l2_subdev *sd = dev_get_drvdata(dev); 885 struct imx412 *imx412 = to_imx412(sd); 886 887 clk_disable_unprepare(imx412->inclk); 888 889 gpiod_set_value_cansleep(imx412->reset_gpio, 1); 890 891 regulator_bulk_disable(ARRAY_SIZE(imx412_supply_names), 892 imx412->supplies); 893 894 return 0; 895 } 896 897 /** 898 * imx412_init_controls() - Initialize sensor subdevice controls 899 * @imx412: pointer to imx412 device 900 * 901 * Return: 0 if successful, error code otherwise. 902 */ 903 static int imx412_init_controls(struct imx412 *imx412) 904 { 905 struct v4l2_ctrl_handler *ctrl_hdlr = &imx412->ctrl_handler; 906 const struct imx412_mode *mode = imx412->cur_mode; 907 u32 lpfr; 908 int ret; 909 910 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 6); 911 if (ret) 912 return ret; 913 914 /* Initialize exposure and gain */ 915 lpfr = mode->vblank + mode->height; 916 imx412->exp_ctrl = v4l2_ctrl_new_std(ctrl_hdlr, 917 &imx412_ctrl_ops, 918 V4L2_CID_EXPOSURE, 919 IMX412_EXPOSURE_MIN, 920 lpfr - IMX412_EXPOSURE_OFFSET, 921 IMX412_EXPOSURE_STEP, 922 IMX412_EXPOSURE_DEFAULT); 923 924 imx412->again_ctrl = v4l2_ctrl_new_std(ctrl_hdlr, 925 &imx412_ctrl_ops, 926 V4L2_CID_ANALOGUE_GAIN, 927 IMX412_AGAIN_MIN, 928 IMX412_AGAIN_MAX, 929 IMX412_AGAIN_STEP, 930 IMX412_AGAIN_DEFAULT); 931 932 v4l2_ctrl_cluster(2, &imx412->exp_ctrl); 933 934 imx412->vblank_ctrl = v4l2_ctrl_new_std(ctrl_hdlr, 935 &imx412_ctrl_ops, 936 V4L2_CID_VBLANK, 937 mode->vblank_min, 938 mode->vblank_max, 939 1, mode->vblank); 940 941 /* Read only controls */ 942 imx412->pclk_ctrl = v4l2_ctrl_new_std(ctrl_hdlr, 943 &imx412_ctrl_ops, 944 V4L2_CID_PIXEL_RATE, 945 mode->pclk, mode->pclk, 946 1, mode->pclk); 947 948 imx412->link_freq_ctrl = v4l2_ctrl_new_int_menu(ctrl_hdlr, 949 &imx412_ctrl_ops, 950 V4L2_CID_LINK_FREQ, 951 ARRAY_SIZE(link_freq) - 952 1, 953 mode->link_freq_idx, 954 link_freq); 955 if (imx412->link_freq_ctrl) 956 imx412->link_freq_ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY; 957 958 imx412->hblank_ctrl = v4l2_ctrl_new_std(ctrl_hdlr, 959 &imx412_ctrl_ops, 960 V4L2_CID_HBLANK, 961 IMX412_REG_MIN, 962 IMX412_REG_MAX, 963 1, mode->hblank); 964 if (imx412->hblank_ctrl) 965 imx412->hblank_ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY; 966 967 if (ctrl_hdlr->error) { 968 dev_err(imx412->dev, "control init failed: %d\n", 969 ctrl_hdlr->error); 970 v4l2_ctrl_handler_free(ctrl_hdlr); 971 return ctrl_hdlr->error; 972 } 973 974 imx412->sd.ctrl_handler = ctrl_hdlr; 975 976 return 0; 977 } 978 979 static int imx412_probe(struct i2c_client *client) 980 { 981 struct imx412 *imx412; 982 const char *name; 983 int ret; 984 985 imx412 = devm_kzalloc(&client->dev, sizeof(*imx412), GFP_KERNEL); 986 if (!imx412) 987 return -ENOMEM; 988 989 imx412->dev = &client->dev; 990 name = device_get_match_data(&client->dev); 991 if (!name) 992 return -ENODEV; 993 994 imx412->cci = devm_cci_regmap_init_i2c(client, 16); 995 if (IS_ERR(imx412->cci)) 996 return dev_err_probe(imx412->dev, PTR_ERR(imx412->cci), 997 "Failed to init CCI\n"); 998 999 /* Initialize subdev */ 1000 v4l2_i2c_subdev_init(&imx412->sd, client, &imx412_subdev_ops); 1001 imx412->sd.internal_ops = &imx412_internal_ops; 1002 1003 ret = imx412_parse_hw_config(imx412); 1004 if (ret) { 1005 dev_err(imx412->dev, "HW configuration is not supported\n"); 1006 return ret; 1007 } 1008 1009 ret = imx412_power_on(imx412->dev); 1010 if (ret) 1011 return dev_err_probe(imx412->dev, ret, 1012 "failed to power-on the sensor\n"); 1013 1014 /* Check module identity */ 1015 ret = imx412_detect(imx412); 1016 if (ret) { 1017 dev_err(imx412->dev, "failed to find sensor: %d\n", ret); 1018 goto error_power_off; 1019 } 1020 1021 /* Set default mode to max resolution */ 1022 imx412->cur_mode = &supported_mode; 1023 imx412->vblank = imx412->cur_mode->vblank; 1024 1025 ret = imx412_init_controls(imx412); 1026 if (ret) { 1027 dev_err(imx412->dev, "failed to init controls: %d\n", ret); 1028 goto error_power_off; 1029 } 1030 1031 /* Initialize subdev */ 1032 imx412->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1033 imx412->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1034 1035 v4l2_i2c_subdev_set_name(&imx412->sd, client, name, NULL); 1036 1037 /* Initialize source pad */ 1038 imx412->pad.flags = MEDIA_PAD_FL_SOURCE; 1039 ret = media_entity_pads_init(&imx412->sd.entity, 1, &imx412->pad); 1040 if (ret) { 1041 dev_err(imx412->dev, "failed to init entity pads: %d\n", ret); 1042 goto error_handler_free; 1043 } 1044 1045 imx412->sd.state_lock = imx412->ctrl_handler.lock; 1046 ret = v4l2_subdev_init_finalize(&imx412->sd); 1047 if (ret < 0) { 1048 dev_err_probe(imx412->dev, ret, "subdev init error\n"); 1049 goto error_media_entity; 1050 } 1051 1052 pm_runtime_set_active(imx412->dev); 1053 pm_runtime_enable(imx412->dev); 1054 1055 ret = v4l2_async_register_subdev_sensor(&imx412->sd); 1056 if (ret < 0) { 1057 dev_err_probe(imx412->dev, ret, 1058 "failed to register sub-device\n"); 1059 goto error_subdev_cleanup; 1060 } 1061 1062 pm_runtime_idle(imx412->dev); 1063 1064 return 0; 1065 1066 error_subdev_cleanup: 1067 v4l2_subdev_cleanup(&imx412->sd); 1068 pm_runtime_disable(imx412->dev); 1069 pm_runtime_set_suspended(imx412->dev); 1070 error_media_entity: 1071 media_entity_cleanup(&imx412->sd.entity); 1072 error_handler_free: 1073 v4l2_ctrl_handler_free(imx412->sd.ctrl_handler); 1074 error_power_off: 1075 imx412_power_off(imx412->dev); 1076 1077 return ret; 1078 } 1079 1080 static void imx412_remove(struct i2c_client *client) 1081 { 1082 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1083 1084 v4l2_async_unregister_subdev(sd); 1085 v4l2_subdev_cleanup(sd); 1086 media_entity_cleanup(&sd->entity); 1087 v4l2_ctrl_handler_free(sd->ctrl_handler); 1088 1089 pm_runtime_disable(&client->dev); 1090 if (!pm_runtime_status_suspended(&client->dev)) 1091 imx412_power_off(&client->dev); 1092 pm_runtime_set_suspended(&client->dev); 1093 } 1094 1095 static const struct dev_pm_ops imx412_pm_ops = { 1096 SET_RUNTIME_PM_OPS(imx412_power_off, imx412_power_on, NULL) 1097 }; 1098 1099 static const struct of_device_id imx412_of_match[] = { 1100 { .compatible = "sony,imx412", .data = "imx412" }, 1101 { .compatible = "sony,imx577", .data = "imx577" }, 1102 { } 1103 }; 1104 1105 MODULE_DEVICE_TABLE(of, imx412_of_match); 1106 1107 static struct i2c_driver imx412_driver = { 1108 .probe = imx412_probe, 1109 .remove = imx412_remove, 1110 .driver = { 1111 .name = "imx412", 1112 .pm = &imx412_pm_ops, 1113 .of_match_table = imx412_of_match, 1114 }, 1115 }; 1116 1117 module_i2c_driver(imx412_driver); 1118 1119 MODULE_DESCRIPTION("Sony imx412 sensor driver"); 1120 MODULE_LICENSE("GPL"); 1121