xref: /linux/drivers/media/i2c/imx355.c (revision fbf5df34a4dbcd09d433dd4f0916bf9b2ddb16de) 
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2018 Intel Corporation
3 
4 #include <linux/acpi.h>
5 #include <linux/clk.h>
6 #include <linux/delay.h>
7 #include <linux/gpio/consumer.h>
8 #include <linux/i2c.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/pm_runtime.h>
12 #include <linux/regulator/consumer.h>
13 #include <linux/unaligned.h>
14 
15 #include <media/v4l2-ctrls.h>
16 #include <media/v4l2-device.h>
17 #include <media/v4l2-event.h>
18 #include <media/v4l2-fwnode.h>
19 
20 #define IMX355_REG_MODE_SELECT		0x0100
21 #define IMX355_MODE_STANDBY		0x00
22 #define IMX355_MODE_STREAMING		0x01
23 
24 /* Chip ID */
25 #define IMX355_REG_CHIP_ID		0x0016
26 #define IMX355_CHIP_ID			0x0355
27 
28 /* V_TIMING internal */
29 #define IMX355_REG_FLL			0x0340
30 #define IMX355_FLL_MAX			0xffff
31 
32 /* Exposure control */
33 #define IMX355_REG_EXPOSURE		0x0202
34 #define IMX355_EXPOSURE_MIN		1
35 #define IMX355_EXPOSURE_STEP		1
36 #define IMX355_EXPOSURE_DEFAULT		0x0282
37 
38 /* Analog gain control */
39 #define IMX355_REG_ANALOG_GAIN		0x0204
40 #define IMX355_ANA_GAIN_MIN		0
41 #define IMX355_ANA_GAIN_MAX		960
42 #define IMX355_ANA_GAIN_STEP		1
43 #define IMX355_ANA_GAIN_DEFAULT		0
44 
45 /* Digital gain control */
46 #define IMX355_REG_DPGA_USE_GLOBAL_GAIN	0x3070
47 #define IMX355_REG_DIG_GAIN_GLOBAL	0x020e
48 #define IMX355_DGTL_GAIN_MIN		256
49 #define IMX355_DGTL_GAIN_MAX		4095
50 #define IMX355_DGTL_GAIN_STEP		1
51 #define IMX355_DGTL_GAIN_DEFAULT	256
52 
53 /* Test Pattern Control */
54 #define IMX355_REG_TEST_PATTERN		0x0600
55 #define IMX355_TEST_PATTERN_DISABLED		0
56 #define IMX355_TEST_PATTERN_SOLID_COLOR		1
57 #define IMX355_TEST_PATTERN_COLOR_BARS		2
58 #define IMX355_TEST_PATTERN_GRAY_COLOR_BARS	3
59 #define IMX355_TEST_PATTERN_PN9			4
60 
61 /* Flip Control */
62 #define IMX355_REG_ORIENTATION		0x0101
63 
64 /* default link frequency and external clock */
65 #define IMX355_LINK_FREQ_DEFAULT	360000000LL
66 #define IMX355_EXT_CLK			19200000
67 #define IMX355_LINK_FREQ_INDEX		0
68 
69 /* number of data lanes */
70 #define IMX355_DATA_LANES		4
71 
72 struct imx355_reg {
73 	u16 address;
74 	u8 val;
75 };
76 
77 struct imx355_reg_list {
78 	u32 num_of_regs;
79 	const struct imx355_reg *regs;
80 };
81 
82 /* Mode : resolution and related config&values */
83 struct imx355_mode {
84 	/* Frame width */
85 	u32 width;
86 	/* Frame height */
87 	u32 height;
88 
89 	/* V-timing */
90 	u32 fll_def;
91 	u32 fll_min;
92 
93 	/* H-timing */
94 	u32 llp;
95 
96 	/* index of link frequency */
97 	u32 link_freq_index;
98 
99 	/* Default register values */
100 	struct imx355_reg_list reg_list;
101 };
102 
103 struct imx355_hwcfg {
104 	unsigned long link_freq_bitmap;
105 };
106 
107 struct imx355 {
108 	struct device *dev;
109 	struct clk *clk;
110 
111 	struct v4l2_subdev sd;
112 	struct media_pad pad;
113 
114 	struct v4l2_ctrl_handler ctrl_handler;
115 	/* V4L2 Controls */
116 	struct v4l2_ctrl *link_freq;
117 	struct v4l2_ctrl *pixel_rate;
118 	struct v4l2_ctrl *vblank;
119 	struct v4l2_ctrl *hblank;
120 	struct v4l2_ctrl *exposure;
121 	struct v4l2_ctrl *vflip;
122 	struct v4l2_ctrl *hflip;
123 
124 	/* Current mode */
125 	const struct imx355_mode *cur_mode;
126 
127 	struct imx355_hwcfg *hwcfg;
128 
129 	/*
130 	 * Mutex for serialized access:
131 	 * Protect sensor set pad format and start/stop streaming safely.
132 	 * Protect access to sensor v4l2 controls.
133 	 */
134 	struct mutex mutex;
135 
136 	struct gpio_desc *reset_gpio;
137 	struct regulator_bulk_data *supplies;
138 };
139 
140 static const struct regulator_bulk_data imx355_supplies[] = {
141 	{ .supply = "avdd" },
142 	{ .supply = "dvdd" },
143 	{ .supply = "dovdd" },
144 };
145 
146 static const struct imx355_reg imx355_global_regs[] = {
147 	{ 0x0136, 0x13 },
148 	{ 0x0137, 0x33 },
149 	{ 0x304e, 0x03 },
150 	{ 0x4348, 0x16 },
151 	{ 0x4350, 0x19 },
152 	{ 0x4408, 0x0a },
153 	{ 0x440c, 0x0b },
154 	{ 0x4411, 0x5f },
155 	{ 0x4412, 0x2c },
156 	{ 0x4623, 0x00 },
157 	{ 0x462c, 0x0f },
158 	{ 0x462d, 0x00 },
159 	{ 0x462e, 0x00 },
160 	{ 0x4684, 0x54 },
161 	{ 0x480a, 0x07 },
162 	{ 0x4908, 0x07 },
163 	{ 0x4909, 0x07 },
164 	{ 0x490d, 0x0a },
165 	{ 0x491e, 0x0f },
166 	{ 0x4921, 0x06 },
167 	{ 0x4923, 0x28 },
168 	{ 0x4924, 0x28 },
169 	{ 0x4925, 0x29 },
170 	{ 0x4926, 0x29 },
171 	{ 0x4927, 0x1f },
172 	{ 0x4928, 0x20 },
173 	{ 0x4929, 0x20 },
174 	{ 0x492a, 0x20 },
175 	{ 0x492c, 0x05 },
176 	{ 0x492d, 0x06 },
177 	{ 0x492e, 0x06 },
178 	{ 0x492f, 0x06 },
179 	{ 0x4930, 0x03 },
180 	{ 0x4931, 0x04 },
181 	{ 0x4932, 0x04 },
182 	{ 0x4933, 0x05 },
183 	{ 0x595e, 0x01 },
184 	{ 0x5963, 0x01 },
185 	{ 0x3030, 0x01 },
186 	{ 0x3031, 0x01 },
187 	{ 0x3045, 0x01 },
188 	{ 0x4010, 0x00 },
189 	{ 0x4011, 0x00 },
190 	{ 0x4012, 0x00 },
191 	{ 0x4013, 0x01 },
192 	{ 0x68a8, 0xfe },
193 	{ 0x68a9, 0xff },
194 	{ 0x6888, 0x00 },
195 	{ 0x6889, 0x00 },
196 	{ 0x68b0, 0x00 },
197 	{ 0x3058, 0x00 },
198 	{ 0x305a, 0x00 },
199 };
200 
201 static const struct imx355_reg_list imx355_global_setting = {
202 	.num_of_regs = ARRAY_SIZE(imx355_global_regs),
203 	.regs = imx355_global_regs,
204 };
205 
206 static const struct imx355_reg mode_3268x2448_regs[] = {
207 	{ 0x0112, 0x0a },
208 	{ 0x0113, 0x0a },
209 	{ 0x0114, 0x03 },
210 	{ 0x0342, 0x0e },
211 	{ 0x0343, 0x58 },
212 	{ 0x0340, 0x0a },
213 	{ 0x0341, 0x37 },
214 	{ 0x0344, 0x00 },
215 	{ 0x0345, 0x08 },
216 	{ 0x0346, 0x00 },
217 	{ 0x0347, 0x08 },
218 	{ 0x0348, 0x0c },
219 	{ 0x0349, 0xcb },
220 	{ 0x034a, 0x09 },
221 	{ 0x034b, 0x97 },
222 	{ 0x0220, 0x00 },
223 	{ 0x0222, 0x01 },
224 	{ 0x0900, 0x00 },
225 	{ 0x0901, 0x11 },
226 	{ 0x0902, 0x00 },
227 	{ 0x034c, 0x0c },
228 	{ 0x034d, 0xc4 },
229 	{ 0x034e, 0x09 },
230 	{ 0x034f, 0x90 },
231 	{ 0x0301, 0x05 },
232 	{ 0x0303, 0x01 },
233 	{ 0x0305, 0x02 },
234 	{ 0x0306, 0x00 },
235 	{ 0x0307, 0x78 },
236 	{ 0x030b, 0x01 },
237 	{ 0x030d, 0x02 },
238 	{ 0x030e, 0x00 },
239 	{ 0x030f, 0x4b },
240 	{ 0x0310, 0x00 },
241 	{ 0x0700, 0x00 },
242 	{ 0x0701, 0x10 },
243 	{ 0x0820, 0x0b },
244 	{ 0x0821, 0x40 },
245 	{ 0x3088, 0x04 },
246 	{ 0x6813, 0x02 },
247 	{ 0x6835, 0x07 },
248 	{ 0x6836, 0x01 },
249 	{ 0x6837, 0x04 },
250 	{ 0x684d, 0x07 },
251 	{ 0x684e, 0x01 },
252 	{ 0x684f, 0x04 },
253 };
254 
255 static const struct imx355_reg mode_3264x2448_regs[] = {
256 	{ 0x0112, 0x0a },
257 	{ 0x0113, 0x0a },
258 	{ 0x0114, 0x03 },
259 	{ 0x0342, 0x0e },
260 	{ 0x0343, 0x58 },
261 	{ 0x0340, 0x0a },
262 	{ 0x0341, 0x37 },
263 	{ 0x0344, 0x00 },
264 	{ 0x0345, 0x08 },
265 	{ 0x0346, 0x00 },
266 	{ 0x0347, 0x08 },
267 	{ 0x0348, 0x0c },
268 	{ 0x0349, 0xc7 },
269 	{ 0x034a, 0x09 },
270 	{ 0x034b, 0x97 },
271 	{ 0x0220, 0x00 },
272 	{ 0x0222, 0x01 },
273 	{ 0x0900, 0x00 },
274 	{ 0x0901, 0x11 },
275 	{ 0x0902, 0x00 },
276 	{ 0x034c, 0x0c },
277 	{ 0x034d, 0xc0 },
278 	{ 0x034e, 0x09 },
279 	{ 0x034f, 0x90 },
280 	{ 0x0301, 0x05 },
281 	{ 0x0303, 0x01 },
282 	{ 0x0305, 0x02 },
283 	{ 0x0306, 0x00 },
284 	{ 0x0307, 0x78 },
285 	{ 0x030b, 0x01 },
286 	{ 0x030d, 0x02 },
287 	{ 0x030e, 0x00 },
288 	{ 0x030f, 0x4b },
289 	{ 0x0310, 0x00 },
290 	{ 0x0700, 0x00 },
291 	{ 0x0701, 0x10 },
292 	{ 0x0820, 0x0b },
293 	{ 0x0821, 0x40 },
294 	{ 0x3088, 0x04 },
295 	{ 0x6813, 0x02 },
296 	{ 0x6835, 0x07 },
297 	{ 0x6836, 0x01 },
298 	{ 0x6837, 0x04 },
299 	{ 0x684d, 0x07 },
300 	{ 0x684e, 0x01 },
301 	{ 0x684f, 0x04 },
302 };
303 
304 static const struct imx355_reg mode_3280x2464_regs[] = {
305 	{ 0x0112, 0x0a },
306 	{ 0x0113, 0x0a },
307 	{ 0x0114, 0x03 },
308 	{ 0x0342, 0x0e },
309 	{ 0x0343, 0x58 },
310 	{ 0x0340, 0x0a },
311 	{ 0x0341, 0x37 },
312 	{ 0x0344, 0x00 },
313 	{ 0x0345, 0x00 },
314 	{ 0x0346, 0x00 },
315 	{ 0x0347, 0x00 },
316 	{ 0x0348, 0x0c },
317 	{ 0x0349, 0xcf },
318 	{ 0x034a, 0x09 },
319 	{ 0x034b, 0x9f },
320 	{ 0x0220, 0x00 },
321 	{ 0x0222, 0x01 },
322 	{ 0x0900, 0x00 },
323 	{ 0x0901, 0x11 },
324 	{ 0x0902, 0x00 },
325 	{ 0x034c, 0x0c },
326 	{ 0x034d, 0xd0 },
327 	{ 0x034e, 0x09 },
328 	{ 0x034f, 0xa0 },
329 	{ 0x0301, 0x05 },
330 	{ 0x0303, 0x01 },
331 	{ 0x0305, 0x02 },
332 	{ 0x0306, 0x00 },
333 	{ 0x0307, 0x78 },
334 	{ 0x030b, 0x01 },
335 	{ 0x030d, 0x02 },
336 	{ 0x030e, 0x00 },
337 	{ 0x030f, 0x4b },
338 	{ 0x0310, 0x00 },
339 	{ 0x0700, 0x00 },
340 	{ 0x0701, 0x10 },
341 	{ 0x0820, 0x0b },
342 	{ 0x0821, 0x40 },
343 	{ 0x3088, 0x04 },
344 	{ 0x6813, 0x02 },
345 	{ 0x6835, 0x07 },
346 	{ 0x6836, 0x01 },
347 	{ 0x6837, 0x04 },
348 	{ 0x684d, 0x07 },
349 	{ 0x684e, 0x01 },
350 	{ 0x684f, 0x04 },
351 };
352 
353 static const struct imx355_reg mode_1940x1096_regs[] = {
354 	{ 0x0112, 0x0a },
355 	{ 0x0113, 0x0a },
356 	{ 0x0114, 0x03 },
357 	{ 0x0342, 0x0e },
358 	{ 0x0343, 0x58 },
359 	{ 0x0340, 0x05 },
360 	{ 0x0341, 0x1a },
361 	{ 0x0344, 0x02 },
362 	{ 0x0345, 0xa0 },
363 	{ 0x0346, 0x02 },
364 	{ 0x0347, 0xac },
365 	{ 0x0348, 0x0a },
366 	{ 0x0349, 0x33 },
367 	{ 0x034a, 0x06 },
368 	{ 0x034b, 0xf3 },
369 	{ 0x0220, 0x00 },
370 	{ 0x0222, 0x01 },
371 	{ 0x0900, 0x00 },
372 	{ 0x0901, 0x11 },
373 	{ 0x0902, 0x00 },
374 	{ 0x034c, 0x07 },
375 	{ 0x034d, 0x94 },
376 	{ 0x034e, 0x04 },
377 	{ 0x034f, 0x48 },
378 	{ 0x0301, 0x05 },
379 	{ 0x0303, 0x01 },
380 	{ 0x0305, 0x02 },
381 	{ 0x0306, 0x00 },
382 	{ 0x0307, 0x78 },
383 	{ 0x030b, 0x01 },
384 	{ 0x030d, 0x02 },
385 	{ 0x030e, 0x00 },
386 	{ 0x030f, 0x4b },
387 	{ 0x0310, 0x00 },
388 	{ 0x0700, 0x00 },
389 	{ 0x0701, 0x10 },
390 	{ 0x0820, 0x0b },
391 	{ 0x0821, 0x40 },
392 	{ 0x3088, 0x04 },
393 	{ 0x6813, 0x02 },
394 	{ 0x6835, 0x07 },
395 	{ 0x6836, 0x01 },
396 	{ 0x6837, 0x04 },
397 	{ 0x684d, 0x07 },
398 	{ 0x684e, 0x01 },
399 	{ 0x684f, 0x04 },
400 };
401 
402 static const struct imx355_reg mode_1936x1096_regs[] = {
403 	{ 0x0112, 0x0a },
404 	{ 0x0113, 0x0a },
405 	{ 0x0114, 0x03 },
406 	{ 0x0342, 0x0e },
407 	{ 0x0343, 0x58 },
408 	{ 0x0340, 0x05 },
409 	{ 0x0341, 0x1a },
410 	{ 0x0344, 0x02 },
411 	{ 0x0345, 0xa0 },
412 	{ 0x0346, 0x02 },
413 	{ 0x0347, 0xac },
414 	{ 0x0348, 0x0a },
415 	{ 0x0349, 0x2f },
416 	{ 0x034a, 0x06 },
417 	{ 0x034b, 0xf3 },
418 	{ 0x0220, 0x00 },
419 	{ 0x0222, 0x01 },
420 	{ 0x0900, 0x00 },
421 	{ 0x0901, 0x11 },
422 	{ 0x0902, 0x00 },
423 	{ 0x034c, 0x07 },
424 	{ 0x034d, 0x90 },
425 	{ 0x034e, 0x04 },
426 	{ 0x034f, 0x48 },
427 	{ 0x0301, 0x05 },
428 	{ 0x0303, 0x01 },
429 	{ 0x0305, 0x02 },
430 	{ 0x0306, 0x00 },
431 	{ 0x0307, 0x78 },
432 	{ 0x030b, 0x01 },
433 	{ 0x030d, 0x02 },
434 	{ 0x030e, 0x00 },
435 	{ 0x030f, 0x4b },
436 	{ 0x0310, 0x00 },
437 	{ 0x0700, 0x00 },
438 	{ 0x0701, 0x10 },
439 	{ 0x0820, 0x0b },
440 	{ 0x0821, 0x40 },
441 	{ 0x3088, 0x04 },
442 	{ 0x6813, 0x02 },
443 	{ 0x6835, 0x07 },
444 	{ 0x6836, 0x01 },
445 	{ 0x6837, 0x04 },
446 	{ 0x684d, 0x07 },
447 	{ 0x684e, 0x01 },
448 	{ 0x684f, 0x04 },
449 };
450 
451 static const struct imx355_reg mode_1924x1080_regs[] = {
452 	{ 0x0112, 0x0a },
453 	{ 0x0113, 0x0a },
454 	{ 0x0114, 0x03 },
455 	{ 0x0342, 0x0e },
456 	{ 0x0343, 0x58 },
457 	{ 0x0340, 0x05 },
458 	{ 0x0341, 0x1a },
459 	{ 0x0344, 0x02 },
460 	{ 0x0345, 0xa8 },
461 	{ 0x0346, 0x02 },
462 	{ 0x0347, 0xb4 },
463 	{ 0x0348, 0x0a },
464 	{ 0x0349, 0x2b },
465 	{ 0x034a, 0x06 },
466 	{ 0x034b, 0xeb },
467 	{ 0x0220, 0x00 },
468 	{ 0x0222, 0x01 },
469 	{ 0x0900, 0x00 },
470 	{ 0x0901, 0x11 },
471 	{ 0x0902, 0x00 },
472 	{ 0x034c, 0x07 },
473 	{ 0x034d, 0x84 },
474 	{ 0x034e, 0x04 },
475 	{ 0x034f, 0x38 },
476 	{ 0x0301, 0x05 },
477 	{ 0x0303, 0x01 },
478 	{ 0x0305, 0x02 },
479 	{ 0x0306, 0x00 },
480 	{ 0x0307, 0x78 },
481 	{ 0x030b, 0x01 },
482 	{ 0x030d, 0x02 },
483 	{ 0x030e, 0x00 },
484 	{ 0x030f, 0x4b },
485 	{ 0x0310, 0x00 },
486 	{ 0x0700, 0x00 },
487 	{ 0x0701, 0x10 },
488 	{ 0x0820, 0x0b },
489 	{ 0x0821, 0x40 },
490 	{ 0x3088, 0x04 },
491 	{ 0x6813, 0x02 },
492 	{ 0x6835, 0x07 },
493 	{ 0x6836, 0x01 },
494 	{ 0x6837, 0x04 },
495 	{ 0x684d, 0x07 },
496 	{ 0x684e, 0x01 },
497 	{ 0x684f, 0x04 },
498 };
499 
500 static const struct imx355_reg mode_1920x1080_regs[] = {
501 	{ 0x0112, 0x0a },
502 	{ 0x0113, 0x0a },
503 	{ 0x0114, 0x03 },
504 	{ 0x0342, 0x0e },
505 	{ 0x0343, 0x58 },
506 	{ 0x0340, 0x05 },
507 	{ 0x0341, 0x1a },
508 	{ 0x0344, 0x02 },
509 	{ 0x0345, 0xa8 },
510 	{ 0x0346, 0x02 },
511 	{ 0x0347, 0xb4 },
512 	{ 0x0348, 0x0a },
513 	{ 0x0349, 0x27 },
514 	{ 0x034a, 0x06 },
515 	{ 0x034b, 0xeb },
516 	{ 0x0220, 0x00 },
517 	{ 0x0222, 0x01 },
518 	{ 0x0900, 0x00 },
519 	{ 0x0901, 0x11 },
520 	{ 0x0902, 0x00 },
521 	{ 0x034c, 0x07 },
522 	{ 0x034d, 0x80 },
523 	{ 0x034e, 0x04 },
524 	{ 0x034f, 0x38 },
525 	{ 0x0301, 0x05 },
526 	{ 0x0303, 0x01 },
527 	{ 0x0305, 0x02 },
528 	{ 0x0306, 0x00 },
529 	{ 0x0307, 0x78 },
530 	{ 0x030b, 0x01 },
531 	{ 0x030d, 0x02 },
532 	{ 0x030e, 0x00 },
533 	{ 0x030f, 0x4b },
534 	{ 0x0310, 0x00 },
535 	{ 0x0700, 0x00 },
536 	{ 0x0701, 0x10 },
537 	{ 0x0820, 0x0b },
538 	{ 0x0821, 0x40 },
539 	{ 0x3088, 0x04 },
540 	{ 0x6813, 0x02 },
541 	{ 0x6835, 0x07 },
542 	{ 0x6836, 0x01 },
543 	{ 0x6837, 0x04 },
544 	{ 0x684d, 0x07 },
545 	{ 0x684e, 0x01 },
546 	{ 0x684f, 0x04 },
547 };
548 
549 static const struct imx355_reg mode_1640x1232_regs[] = {
550 	{ 0x0112, 0x0a },
551 	{ 0x0113, 0x0a },
552 	{ 0x0114, 0x03 },
553 	{ 0x0342, 0x07 },
554 	{ 0x0343, 0x2c },
555 	{ 0x0340, 0x05 },
556 	{ 0x0341, 0x1a },
557 	{ 0x0344, 0x00 },
558 	{ 0x0345, 0x00 },
559 	{ 0x0346, 0x00 },
560 	{ 0x0347, 0x00 },
561 	{ 0x0348, 0x0c },
562 	{ 0x0349, 0xcf },
563 	{ 0x034a, 0x09 },
564 	{ 0x034b, 0x9f },
565 	{ 0x0220, 0x00 },
566 	{ 0x0222, 0x01 },
567 	{ 0x0900, 0x01 },
568 	{ 0x0901, 0x22 },
569 	{ 0x0902, 0x00 },
570 	{ 0x034c, 0x06 },
571 	{ 0x034d, 0x68 },
572 	{ 0x034e, 0x04 },
573 	{ 0x034f, 0xd0 },
574 	{ 0x0301, 0x05 },
575 	{ 0x0303, 0x01 },
576 	{ 0x0305, 0x02 },
577 	{ 0x0306, 0x00 },
578 	{ 0x0307, 0x78 },
579 	{ 0x030b, 0x01 },
580 	{ 0x030d, 0x02 },
581 	{ 0x030e, 0x00 },
582 	{ 0x030f, 0x4b },
583 	{ 0x0310, 0x00 },
584 	{ 0x0700, 0x00 },
585 	{ 0x0701, 0x10 },
586 	{ 0x0820, 0x0b },
587 	{ 0x0821, 0x40 },
588 	{ 0x3088, 0x04 },
589 	{ 0x6813, 0x02 },
590 	{ 0x6835, 0x07 },
591 	{ 0x6836, 0x01 },
592 	{ 0x6837, 0x04 },
593 	{ 0x684d, 0x07 },
594 	{ 0x684e, 0x01 },
595 	{ 0x684f, 0x04 },
596 };
597 
598 static const struct imx355_reg mode_1640x922_regs[] = {
599 	{ 0x0112, 0x0a },
600 	{ 0x0113, 0x0a },
601 	{ 0x0114, 0x03 },
602 	{ 0x0342, 0x07 },
603 	{ 0x0343, 0x2c },
604 	{ 0x0340, 0x05 },
605 	{ 0x0341, 0x1a },
606 	{ 0x0344, 0x00 },
607 	{ 0x0345, 0x00 },
608 	{ 0x0346, 0x01 },
609 	{ 0x0347, 0x30 },
610 	{ 0x0348, 0x0c },
611 	{ 0x0349, 0xcf },
612 	{ 0x034a, 0x08 },
613 	{ 0x034b, 0x63 },
614 	{ 0x0220, 0x00 },
615 	{ 0x0222, 0x01 },
616 	{ 0x0900, 0x01 },
617 	{ 0x0901, 0x22 },
618 	{ 0x0902, 0x00 },
619 	{ 0x034c, 0x06 },
620 	{ 0x034d, 0x68 },
621 	{ 0x034e, 0x03 },
622 	{ 0x034f, 0x9a },
623 	{ 0x0301, 0x05 },
624 	{ 0x0303, 0x01 },
625 	{ 0x0305, 0x02 },
626 	{ 0x0306, 0x00 },
627 	{ 0x0307, 0x78 },
628 	{ 0x030b, 0x01 },
629 	{ 0x030d, 0x02 },
630 	{ 0x030e, 0x00 },
631 	{ 0x030f, 0x4b },
632 	{ 0x0310, 0x00 },
633 	{ 0x0700, 0x00 },
634 	{ 0x0701, 0x10 },
635 	{ 0x0820, 0x0b },
636 	{ 0x0821, 0x40 },
637 	{ 0x3088, 0x04 },
638 	{ 0x6813, 0x02 },
639 	{ 0x6835, 0x07 },
640 	{ 0x6836, 0x01 },
641 	{ 0x6837, 0x04 },
642 	{ 0x684d, 0x07 },
643 	{ 0x684e, 0x01 },
644 	{ 0x684f, 0x04 },
645 };
646 
647 static const struct imx355_reg mode_1300x736_regs[] = {
648 	{ 0x0112, 0x0a },
649 	{ 0x0113, 0x0a },
650 	{ 0x0114, 0x03 },
651 	{ 0x0342, 0x07 },
652 	{ 0x0343, 0x2c },
653 	{ 0x0340, 0x05 },
654 	{ 0x0341, 0x1a },
655 	{ 0x0344, 0x01 },
656 	{ 0x0345, 0x58 },
657 	{ 0x0346, 0x01 },
658 	{ 0x0347, 0xf0 },
659 	{ 0x0348, 0x0b },
660 	{ 0x0349, 0x7f },
661 	{ 0x034a, 0x07 },
662 	{ 0x034b, 0xaf },
663 	{ 0x0220, 0x00 },
664 	{ 0x0222, 0x01 },
665 	{ 0x0900, 0x01 },
666 	{ 0x0901, 0x22 },
667 	{ 0x0902, 0x00 },
668 	{ 0x034c, 0x05 },
669 	{ 0x034d, 0x14 },
670 	{ 0x034e, 0x02 },
671 	{ 0x034f, 0xe0 },
672 	{ 0x0301, 0x05 },
673 	{ 0x0303, 0x01 },
674 	{ 0x0305, 0x02 },
675 	{ 0x0306, 0x00 },
676 	{ 0x0307, 0x78 },
677 	{ 0x030b, 0x01 },
678 	{ 0x030d, 0x02 },
679 	{ 0x030e, 0x00 },
680 	{ 0x030f, 0x4b },
681 	{ 0x0310, 0x00 },
682 	{ 0x0700, 0x00 },
683 	{ 0x0701, 0x10 },
684 	{ 0x0820, 0x0b },
685 	{ 0x0821, 0x40 },
686 	{ 0x3088, 0x04 },
687 	{ 0x6813, 0x02 },
688 	{ 0x6835, 0x07 },
689 	{ 0x6836, 0x01 },
690 	{ 0x6837, 0x04 },
691 	{ 0x684d, 0x07 },
692 	{ 0x684e, 0x01 },
693 	{ 0x684f, 0x04 },
694 };
695 
696 static const struct imx355_reg mode_1296x736_regs[] = {
697 	{ 0x0112, 0x0a },
698 	{ 0x0113, 0x0a },
699 	{ 0x0114, 0x03 },
700 	{ 0x0342, 0x07 },
701 	{ 0x0343, 0x2c },
702 	{ 0x0340, 0x05 },
703 	{ 0x0341, 0x1a },
704 	{ 0x0344, 0x01 },
705 	{ 0x0345, 0x58 },
706 	{ 0x0346, 0x01 },
707 	{ 0x0347, 0xf0 },
708 	{ 0x0348, 0x0b },
709 	{ 0x0349, 0x77 },
710 	{ 0x034a, 0x07 },
711 	{ 0x034b, 0xaf },
712 	{ 0x0220, 0x00 },
713 	{ 0x0222, 0x01 },
714 	{ 0x0900, 0x01 },
715 	{ 0x0901, 0x22 },
716 	{ 0x0902, 0x00 },
717 	{ 0x034c, 0x05 },
718 	{ 0x034d, 0x10 },
719 	{ 0x034e, 0x02 },
720 	{ 0x034f, 0xe0 },
721 	{ 0x0301, 0x05 },
722 	{ 0x0303, 0x01 },
723 	{ 0x0305, 0x02 },
724 	{ 0x0306, 0x00 },
725 	{ 0x0307, 0x78 },
726 	{ 0x030b, 0x01 },
727 	{ 0x030d, 0x02 },
728 	{ 0x030e, 0x00 },
729 	{ 0x030f, 0x4b },
730 	{ 0x0310, 0x00 },
731 	{ 0x0700, 0x00 },
732 	{ 0x0701, 0x10 },
733 	{ 0x0820, 0x0b },
734 	{ 0x0821, 0x40 },
735 	{ 0x3088, 0x04 },
736 	{ 0x6813, 0x02 },
737 	{ 0x6835, 0x07 },
738 	{ 0x6836, 0x01 },
739 	{ 0x6837, 0x04 },
740 	{ 0x684d, 0x07 },
741 	{ 0x684e, 0x01 },
742 	{ 0x684f, 0x04 },
743 };
744 
745 static const struct imx355_reg mode_1284x720_regs[] = {
746 	{ 0x0112, 0x0a },
747 	{ 0x0113, 0x0a },
748 	{ 0x0114, 0x03 },
749 	{ 0x0342, 0x07 },
750 	{ 0x0343, 0x2c },
751 	{ 0x0340, 0x05 },
752 	{ 0x0341, 0x1a },
753 	{ 0x0344, 0x01 },
754 	{ 0x0345, 0x68 },
755 	{ 0x0346, 0x02 },
756 	{ 0x0347, 0x00 },
757 	{ 0x0348, 0x0b },
758 	{ 0x0349, 0x6f },
759 	{ 0x034a, 0x07 },
760 	{ 0x034b, 0x9f },
761 	{ 0x0220, 0x00 },
762 	{ 0x0222, 0x01 },
763 	{ 0x0900, 0x01 },
764 	{ 0x0901, 0x22 },
765 	{ 0x0902, 0x00 },
766 	{ 0x034c, 0x05 },
767 	{ 0x034d, 0x04 },
768 	{ 0x034e, 0x02 },
769 	{ 0x034f, 0xd0 },
770 	{ 0x0301, 0x05 },
771 	{ 0x0303, 0x01 },
772 	{ 0x0305, 0x02 },
773 	{ 0x0306, 0x00 },
774 	{ 0x0307, 0x78 },
775 	{ 0x030b, 0x01 },
776 	{ 0x030d, 0x02 },
777 	{ 0x030e, 0x00 },
778 	{ 0x030f, 0x4b },
779 	{ 0x0310, 0x00 },
780 	{ 0x0700, 0x00 },
781 	{ 0x0701, 0x10 },
782 	{ 0x0820, 0x0b },
783 	{ 0x0821, 0x40 },
784 	{ 0x3088, 0x04 },
785 	{ 0x6813, 0x02 },
786 	{ 0x6835, 0x07 },
787 	{ 0x6836, 0x01 },
788 	{ 0x6837, 0x04 },
789 	{ 0x684d, 0x07 },
790 	{ 0x684e, 0x01 },
791 	{ 0x684f, 0x04 },
792 };
793 
794 static const struct imx355_reg mode_1280x720_regs[] = {
795 	{ 0x0112, 0x0a },
796 	{ 0x0113, 0x0a },
797 	{ 0x0114, 0x03 },
798 	{ 0x0342, 0x07 },
799 	{ 0x0343, 0x2c },
800 	{ 0x0340, 0x05 },
801 	{ 0x0341, 0x1a },
802 	{ 0x0344, 0x01 },
803 	{ 0x0345, 0x68 },
804 	{ 0x0346, 0x02 },
805 	{ 0x0347, 0x00 },
806 	{ 0x0348, 0x0b },
807 	{ 0x0349, 0x67 },
808 	{ 0x034a, 0x07 },
809 	{ 0x034b, 0x9f },
810 	{ 0x0220, 0x00 },
811 	{ 0x0222, 0x01 },
812 	{ 0x0900, 0x01 },
813 	{ 0x0901, 0x22 },
814 	{ 0x0902, 0x00 },
815 	{ 0x034c, 0x05 },
816 	{ 0x034d, 0x00 },
817 	{ 0x034e, 0x02 },
818 	{ 0x034f, 0xd0 },
819 	{ 0x0301, 0x05 },
820 	{ 0x0303, 0x01 },
821 	{ 0x0305, 0x02 },
822 	{ 0x0306, 0x00 },
823 	{ 0x0307, 0x78 },
824 	{ 0x030b, 0x01 },
825 	{ 0x030d, 0x02 },
826 	{ 0x030e, 0x00 },
827 	{ 0x030f, 0x4b },
828 	{ 0x0310, 0x00 },
829 	{ 0x0700, 0x00 },
830 	{ 0x0701, 0x10 },
831 	{ 0x0820, 0x0b },
832 	{ 0x0821, 0x40 },
833 	{ 0x3088, 0x04 },
834 	{ 0x6813, 0x02 },
835 	{ 0x6835, 0x07 },
836 	{ 0x6836, 0x01 },
837 	{ 0x6837, 0x04 },
838 	{ 0x684d, 0x07 },
839 	{ 0x684e, 0x01 },
840 	{ 0x684f, 0x04 },
841 };
842 
843 static const struct imx355_reg mode_820x616_regs[] = {
844 	{ 0x0112, 0x0a },
845 	{ 0x0113, 0x0a },
846 	{ 0x0114, 0x03 },
847 	{ 0x0342, 0x0e },
848 	{ 0x0343, 0x58 },
849 	{ 0x0340, 0x02 },
850 	{ 0x0341, 0x8c },
851 	{ 0x0344, 0x00 },
852 	{ 0x0345, 0x00 },
853 	{ 0x0346, 0x00 },
854 	{ 0x0347, 0x00 },
855 	{ 0x0348, 0x0c },
856 	{ 0x0349, 0xcf },
857 	{ 0x034a, 0x09 },
858 	{ 0x034b, 0x9f },
859 	{ 0x0220, 0x00 },
860 	{ 0x0222, 0x01 },
861 	{ 0x0900, 0x01 },
862 	{ 0x0901, 0x44 },
863 	{ 0x0902, 0x00 },
864 	{ 0x034c, 0x03 },
865 	{ 0x034d, 0x34 },
866 	{ 0x034e, 0x02 },
867 	{ 0x034f, 0x68 },
868 	{ 0x0301, 0x05 },
869 	{ 0x0303, 0x01 },
870 	{ 0x0305, 0x02 },
871 	{ 0x0306, 0x00 },
872 	{ 0x0307, 0x78 },
873 	{ 0x030b, 0x01 },
874 	{ 0x030d, 0x02 },
875 	{ 0x030e, 0x00 },
876 	{ 0x030f, 0x4b },
877 	{ 0x0310, 0x00 },
878 	{ 0x0700, 0x02 },
879 	{ 0x0701, 0x78 },
880 	{ 0x0820, 0x0b },
881 	{ 0x0821, 0x40 },
882 	{ 0x3088, 0x04 },
883 	{ 0x6813, 0x02 },
884 	{ 0x6835, 0x07 },
885 	{ 0x6836, 0x01 },
886 	{ 0x6837, 0x04 },
887 	{ 0x684d, 0x07 },
888 	{ 0x684e, 0x01 },
889 	{ 0x684f, 0x04 },
890 };
891 
892 static const char * const imx355_test_pattern_menu[] = {
893 	"Disabled",
894 	"Solid Colour",
895 	"Eight Vertical Colour Bars",
896 	"Colour Bars With Fade to Grey",
897 	"Pseudorandom Sequence (PN9)",
898 };
899 
900 /*
901  * When adding more than the one below, make sure the disallowed ones will
902  * actually be disabled in the LINK_FREQ control.
903  */
904 static const s64 link_freq_menu_items[] = {
905 	IMX355_LINK_FREQ_DEFAULT,
906 };
907 
908 /* Mode configs */
909 static const struct imx355_mode supported_modes[] = {
910 	{
911 		.width = 3280,
912 		.height = 2464,
913 		.fll_def = 2615,
914 		.fll_min = 2615,
915 		.llp = 3672,
916 		.link_freq_index = IMX355_LINK_FREQ_INDEX,
917 		.reg_list = {
918 			.num_of_regs = ARRAY_SIZE(mode_3280x2464_regs),
919 			.regs = mode_3280x2464_regs,
920 		},
921 	},
922 	{
923 		.width = 3268,
924 		.height = 2448,
925 		.fll_def = 2615,
926 		.fll_min = 2615,
927 		.llp = 3672,
928 		.link_freq_index = IMX355_LINK_FREQ_INDEX,
929 		.reg_list = {
930 			.num_of_regs = ARRAY_SIZE(mode_3268x2448_regs),
931 			.regs = mode_3268x2448_regs,
932 		},
933 	},
934 	{
935 		.width = 3264,
936 		.height = 2448,
937 		.fll_def = 2615,
938 		.fll_min = 2615,
939 		.llp = 3672,
940 		.link_freq_index = IMX355_LINK_FREQ_INDEX,
941 		.reg_list = {
942 			.num_of_regs = ARRAY_SIZE(mode_3264x2448_regs),
943 			.regs = mode_3264x2448_regs,
944 		},
945 	},
946 	{
947 		.width = 1940,
948 		.height = 1096,
949 		.fll_def = 1306,
950 		.fll_min = 1306,
951 		.llp = 3672,
952 		.link_freq_index = IMX355_LINK_FREQ_INDEX,
953 		.reg_list = {
954 			.num_of_regs = ARRAY_SIZE(mode_1940x1096_regs),
955 			.regs = mode_1940x1096_regs,
956 		},
957 	},
958 	{
959 		.width = 1936,
960 		.height = 1096,
961 		.fll_def = 1306,
962 		.fll_min = 1306,
963 		.llp = 3672,
964 		.link_freq_index = IMX355_LINK_FREQ_INDEX,
965 		.reg_list = {
966 			.num_of_regs = ARRAY_SIZE(mode_1936x1096_regs),
967 			.regs = mode_1936x1096_regs,
968 		},
969 	},
970 	{
971 		.width = 1924,
972 		.height = 1080,
973 		.fll_def = 1306,
974 		.fll_min = 1306,
975 		.llp = 3672,
976 		.link_freq_index = IMX355_LINK_FREQ_INDEX,
977 		.reg_list = {
978 			.num_of_regs = ARRAY_SIZE(mode_1924x1080_regs),
979 			.regs = mode_1924x1080_regs,
980 		},
981 	},
982 	{
983 		.width = 1920,
984 		.height = 1080,
985 		.fll_def = 1306,
986 		.fll_min = 1306,
987 		.llp = 3672,
988 		.link_freq_index = IMX355_LINK_FREQ_INDEX,
989 		.reg_list = {
990 			.num_of_regs = ARRAY_SIZE(mode_1920x1080_regs),
991 			.regs = mode_1920x1080_regs,
992 		},
993 	},
994 	{
995 		.width = 1640,
996 		.height = 1232,
997 		.fll_def = 1306,
998 		.fll_min = 1306,
999 		.llp = 1836,
1000 		.link_freq_index = IMX355_LINK_FREQ_INDEX,
1001 		.reg_list = {
1002 			.num_of_regs = ARRAY_SIZE(mode_1640x1232_regs),
1003 			.regs = mode_1640x1232_regs,
1004 		},
1005 	},
1006 	{
1007 		.width = 1640,
1008 		.height = 922,
1009 		.fll_def = 1306,
1010 		.fll_min = 1306,
1011 		.llp = 1836,
1012 		.link_freq_index = IMX355_LINK_FREQ_INDEX,
1013 		.reg_list = {
1014 			.num_of_regs = ARRAY_SIZE(mode_1640x922_regs),
1015 			.regs = mode_1640x922_regs,
1016 		},
1017 	},
1018 	{
1019 		.width = 1300,
1020 		.height = 736,
1021 		.fll_def = 1306,
1022 		.fll_min = 1306,
1023 		.llp = 1836,
1024 		.link_freq_index = IMX355_LINK_FREQ_INDEX,
1025 		.reg_list = {
1026 			.num_of_regs = ARRAY_SIZE(mode_1300x736_regs),
1027 			.regs = mode_1300x736_regs,
1028 		},
1029 	},
1030 	{
1031 		.width = 1296,
1032 		.height = 736,
1033 		.fll_def = 1306,
1034 		.fll_min = 1306,
1035 		.llp = 1836,
1036 		.link_freq_index = IMX355_LINK_FREQ_INDEX,
1037 		.reg_list = {
1038 			.num_of_regs = ARRAY_SIZE(mode_1296x736_regs),
1039 			.regs = mode_1296x736_regs,
1040 		},
1041 	},
1042 	{
1043 		.width = 1284,
1044 		.height = 720,
1045 		.fll_def = 1306,
1046 		.fll_min = 1306,
1047 		.llp = 1836,
1048 		.link_freq_index = IMX355_LINK_FREQ_INDEX,
1049 		.reg_list = {
1050 			.num_of_regs = ARRAY_SIZE(mode_1284x720_regs),
1051 			.regs = mode_1284x720_regs,
1052 		},
1053 	},
1054 	{
1055 		.width = 1280,
1056 		.height = 720,
1057 		.fll_def = 1306,
1058 		.fll_min = 1306,
1059 		.llp = 1836,
1060 		.link_freq_index = IMX355_LINK_FREQ_INDEX,
1061 		.reg_list = {
1062 			.num_of_regs = ARRAY_SIZE(mode_1280x720_regs),
1063 			.regs = mode_1280x720_regs,
1064 		},
1065 	},
1066 	{
1067 		.width = 820,
1068 		.height = 616,
1069 		.fll_def = 652,
1070 		.fll_min = 652,
1071 		.llp = 3672,
1072 		.link_freq_index = IMX355_LINK_FREQ_INDEX,
1073 		.reg_list = {
1074 			.num_of_regs = ARRAY_SIZE(mode_820x616_regs),
1075 			.regs = mode_820x616_regs,
1076 		},
1077 	},
1078 };
1079 
1080 static inline struct imx355 *to_imx355(struct v4l2_subdev *_sd)
1081 {
1082 	return container_of(_sd, struct imx355, sd);
1083 }
1084 
1085 /* Get bayer order based on flip setting. */
1086 static u32 imx355_get_format_code(struct imx355 *imx355)
1087 {
1088 	/*
1089 	 * Only one bayer order is supported.
1090 	 * It depends on the flip settings.
1091 	 */
1092 	u32 code;
1093 	static const u32 codes[2][2] = {
1094 		{ MEDIA_BUS_FMT_SRGGB10_1X10, MEDIA_BUS_FMT_SGRBG10_1X10, },
1095 		{ MEDIA_BUS_FMT_SGBRG10_1X10, MEDIA_BUS_FMT_SBGGR10_1X10, },
1096 	};
1097 
1098 	lockdep_assert_held(&imx355->mutex);
1099 	code = codes[imx355->vflip->val][imx355->hflip->val];
1100 
1101 	return code;
1102 }
1103 
1104 /* Read registers up to 4 at a time */
1105 static int imx355_read_reg(struct imx355 *imx355, u16 reg, u32 len, u32 *val)
1106 {
1107 	struct i2c_client *client = v4l2_get_subdevdata(&imx355->sd);
1108 	struct i2c_msg msgs[2];
1109 	u8 addr_buf[2];
1110 	u8 data_buf[4] = { 0 };
1111 	int ret;
1112 
1113 	if (len > 4)
1114 		return -EINVAL;
1115 
1116 	put_unaligned_be16(reg, addr_buf);
1117 	/* Write register address */
1118 	msgs[0].addr = client->addr;
1119 	msgs[0].flags = 0;
1120 	msgs[0].len = ARRAY_SIZE(addr_buf);
1121 	msgs[0].buf = addr_buf;
1122 
1123 	/* Read data from register */
1124 	msgs[1].addr = client->addr;
1125 	msgs[1].flags = I2C_M_RD;
1126 	msgs[1].len = len;
1127 	msgs[1].buf = &data_buf[4 - len];
1128 
1129 	ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
1130 	if (ret != ARRAY_SIZE(msgs))
1131 		return -EIO;
1132 
1133 	*val = get_unaligned_be32(data_buf);
1134 
1135 	return 0;
1136 }
1137 
1138 /* Write registers up to 4 at a time */
1139 static int imx355_write_reg(struct imx355 *imx355, u16 reg, u32 len, u32 val)
1140 {
1141 	struct i2c_client *client = v4l2_get_subdevdata(&imx355->sd);
1142 	u8 buf[6];
1143 
1144 	if (len > 4)
1145 		return -EINVAL;
1146 
1147 	put_unaligned_be16(reg, buf);
1148 	put_unaligned_be32(val << (8 * (4 - len)), buf + 2);
1149 	if (i2c_master_send(client, buf, len + 2) != len + 2)
1150 		return -EIO;
1151 
1152 	return 0;
1153 }
1154 
1155 /* Write a list of registers */
1156 static int imx355_write_regs(struct imx355 *imx355,
1157 			     const struct imx355_reg *regs, u32 len)
1158 {
1159 	int ret;
1160 	u32 i;
1161 
1162 	for (i = 0; i < len; i++) {
1163 		ret = imx355_write_reg(imx355, regs[i].address, 1, regs[i].val);
1164 		if (ret) {
1165 			dev_err_ratelimited(imx355->dev,
1166 					    "write reg 0x%4.4x return err %d",
1167 					    regs[i].address, ret);
1168 
1169 			return ret;
1170 		}
1171 	}
1172 
1173 	return 0;
1174 }
1175 
1176 /* Open sub-device */
1177 static int imx355_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1178 {
1179 	struct imx355 *imx355 = to_imx355(sd);
1180 	struct v4l2_mbus_framefmt *try_fmt =
1181 		v4l2_subdev_state_get_format(fh->state, 0);
1182 
1183 	mutex_lock(&imx355->mutex);
1184 
1185 	/* Initialize try_fmt */
1186 	try_fmt->width = imx355->cur_mode->width;
1187 	try_fmt->height = imx355->cur_mode->height;
1188 	try_fmt->code = imx355_get_format_code(imx355);
1189 	try_fmt->field = V4L2_FIELD_NONE;
1190 
1191 	mutex_unlock(&imx355->mutex);
1192 
1193 	return 0;
1194 }
1195 
1196 static int imx355_set_ctrl(struct v4l2_ctrl *ctrl)
1197 {
1198 	struct imx355 *imx355 = container_of(ctrl->handler,
1199 					     struct imx355, ctrl_handler);
1200 	s64 max;
1201 	int ret;
1202 
1203 	/* Propagate change of current control to all related controls */
1204 	switch (ctrl->id) {
1205 	case V4L2_CID_VBLANK:
1206 		/* Update max exposure while meeting expected vblanking */
1207 		max = imx355->cur_mode->height + ctrl->val - 10;
1208 		__v4l2_ctrl_modify_range(imx355->exposure,
1209 					 imx355->exposure->minimum,
1210 					 max, imx355->exposure->step, max);
1211 		break;
1212 	}
1213 
1214 	/*
1215 	 * Applying V4L2 control value only happens
1216 	 * when power is up for streaming
1217 	 */
1218 	if (!pm_runtime_get_if_in_use(imx355->dev))
1219 		return 0;
1220 
1221 	switch (ctrl->id) {
1222 	case V4L2_CID_ANALOGUE_GAIN:
1223 		/* Analog gain = 1024/(1024 - ctrl->val) times */
1224 		ret = imx355_write_reg(imx355, IMX355_REG_ANALOG_GAIN, 2,
1225 				       ctrl->val);
1226 		break;
1227 	case V4L2_CID_DIGITAL_GAIN:
1228 		ret = imx355_write_reg(imx355, IMX355_REG_DIG_GAIN_GLOBAL, 2,
1229 				       ctrl->val);
1230 		break;
1231 	case V4L2_CID_EXPOSURE:
1232 		ret = imx355_write_reg(imx355, IMX355_REG_EXPOSURE, 2,
1233 				       ctrl->val);
1234 		break;
1235 	case V4L2_CID_VBLANK:
1236 		/* Update FLL that meets expected vertical blanking */
1237 		ret = imx355_write_reg(imx355, IMX355_REG_FLL, 2,
1238 				       imx355->cur_mode->height + ctrl->val);
1239 		break;
1240 	case V4L2_CID_TEST_PATTERN:
1241 		ret = imx355_write_reg(imx355, IMX355_REG_TEST_PATTERN,
1242 				       2, ctrl->val);
1243 		break;
1244 	case V4L2_CID_HFLIP:
1245 	case V4L2_CID_VFLIP:
1246 		ret = imx355_write_reg(imx355, IMX355_REG_ORIENTATION, 1,
1247 				       imx355->hflip->val |
1248 				       imx355->vflip->val << 1);
1249 		break;
1250 	default:
1251 		ret = -EINVAL;
1252 		dev_info(imx355->dev, "ctrl(id:0x%x,val:0x%x) is not handled",
1253 			 ctrl->id, ctrl->val);
1254 		break;
1255 	}
1256 
1257 	pm_runtime_put(imx355->dev);
1258 
1259 	return ret;
1260 }
1261 
1262 static const struct v4l2_ctrl_ops imx355_ctrl_ops = {
1263 	.s_ctrl = imx355_set_ctrl,
1264 };
1265 
1266 static int imx355_enum_mbus_code(struct v4l2_subdev *sd,
1267 				 struct v4l2_subdev_state *sd_state,
1268 				 struct v4l2_subdev_mbus_code_enum *code)
1269 {
1270 	struct imx355 *imx355 = to_imx355(sd);
1271 
1272 	if (code->index > 0)
1273 		return -EINVAL;
1274 
1275 	mutex_lock(&imx355->mutex);
1276 	code->code = imx355_get_format_code(imx355);
1277 	mutex_unlock(&imx355->mutex);
1278 
1279 	return 0;
1280 }
1281 
1282 static int imx355_enum_frame_size(struct v4l2_subdev *sd,
1283 				  struct v4l2_subdev_state *sd_state,
1284 				  struct v4l2_subdev_frame_size_enum *fse)
1285 {
1286 	struct imx355 *imx355 = to_imx355(sd);
1287 
1288 	if (fse->index >= ARRAY_SIZE(supported_modes))
1289 		return -EINVAL;
1290 
1291 	mutex_lock(&imx355->mutex);
1292 	if (fse->code != imx355_get_format_code(imx355)) {
1293 		mutex_unlock(&imx355->mutex);
1294 		return -EINVAL;
1295 	}
1296 	mutex_unlock(&imx355->mutex);
1297 
1298 	fse->min_width = supported_modes[fse->index].width;
1299 	fse->max_width = fse->min_width;
1300 	fse->min_height = supported_modes[fse->index].height;
1301 	fse->max_height = fse->min_height;
1302 
1303 	return 0;
1304 }
1305 
1306 static void imx355_update_pad_format(struct imx355 *imx355,
1307 				     const struct imx355_mode *mode,
1308 				     struct v4l2_subdev_format *fmt)
1309 {
1310 	fmt->format.width = mode->width;
1311 	fmt->format.height = mode->height;
1312 	fmt->format.code = imx355_get_format_code(imx355);
1313 	fmt->format.field = V4L2_FIELD_NONE;
1314 }
1315 
1316 static int imx355_do_get_pad_format(struct imx355 *imx355,
1317 				    struct v4l2_subdev_state *sd_state,
1318 				    struct v4l2_subdev_format *fmt)
1319 {
1320 	struct v4l2_mbus_framefmt *framefmt;
1321 
1322 	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1323 		framefmt = v4l2_subdev_state_get_format(sd_state, fmt->pad);
1324 		fmt->format = *framefmt;
1325 	} else {
1326 		imx355_update_pad_format(imx355, imx355->cur_mode, fmt);
1327 	}
1328 
1329 	return 0;
1330 }
1331 
1332 static int imx355_get_pad_format(struct v4l2_subdev *sd,
1333 				 struct v4l2_subdev_state *sd_state,
1334 				 struct v4l2_subdev_format *fmt)
1335 {
1336 	struct imx355 *imx355 = to_imx355(sd);
1337 	int ret;
1338 
1339 	mutex_lock(&imx355->mutex);
1340 	ret = imx355_do_get_pad_format(imx355, sd_state, fmt);
1341 	mutex_unlock(&imx355->mutex);
1342 
1343 	return ret;
1344 }
1345 
1346 static int
1347 imx355_set_pad_format(struct v4l2_subdev *sd,
1348 		      struct v4l2_subdev_state *sd_state,
1349 		      struct v4l2_subdev_format *fmt)
1350 {
1351 	struct imx355 *imx355 = to_imx355(sd);
1352 	const struct imx355_mode *mode;
1353 	struct v4l2_mbus_framefmt *framefmt;
1354 	s32 vblank_def;
1355 	s32 vblank_min;
1356 	s64 h_blank;
1357 	u64 pixel_rate;
1358 	u32 height;
1359 
1360 	mutex_lock(&imx355->mutex);
1361 
1362 	/*
1363 	 * Only one bayer order is supported.
1364 	 * It depends on the flip settings.
1365 	 */
1366 	fmt->format.code = imx355_get_format_code(imx355);
1367 
1368 	mode = v4l2_find_nearest_size(supported_modes,
1369 				      ARRAY_SIZE(supported_modes),
1370 				      width, height,
1371 				      fmt->format.width, fmt->format.height);
1372 	imx355_update_pad_format(imx355, mode, fmt);
1373 	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1374 		framefmt = v4l2_subdev_state_get_format(sd_state, fmt->pad);
1375 		*framefmt = fmt->format;
1376 	} else {
1377 		imx355->cur_mode = mode;
1378 		pixel_rate = IMX355_LINK_FREQ_DEFAULT * 2 * 4;
1379 		do_div(pixel_rate, 10);
1380 		__v4l2_ctrl_s_ctrl_int64(imx355->pixel_rate, pixel_rate);
1381 		/* Update limits and set FPS to default */
1382 		height = imx355->cur_mode->height;
1383 		vblank_def = imx355->cur_mode->fll_def - height;
1384 		vblank_min = imx355->cur_mode->fll_min - height;
1385 		height = IMX355_FLL_MAX - height;
1386 		__v4l2_ctrl_modify_range(imx355->vblank, vblank_min, height, 1,
1387 					 vblank_def);
1388 		__v4l2_ctrl_s_ctrl(imx355->vblank, vblank_def);
1389 		h_blank = mode->llp - imx355->cur_mode->width;
1390 		/*
1391 		 * Currently hblank is not changeable.
1392 		 * So FPS control is done only by vblank.
1393 		 */
1394 		__v4l2_ctrl_modify_range(imx355->hblank, h_blank,
1395 					 h_blank, 1, h_blank);
1396 	}
1397 
1398 	mutex_unlock(&imx355->mutex);
1399 
1400 	return 0;
1401 }
1402 
1403 /* Start streaming */
1404 static int imx355_start_streaming(struct imx355 *imx355)
1405 {
1406 	const struct imx355_reg_list *reg_list;
1407 	int ret;
1408 
1409 	/* Global Setting */
1410 	reg_list = &imx355_global_setting;
1411 	ret = imx355_write_regs(imx355, reg_list->regs, reg_list->num_of_regs);
1412 	if (ret) {
1413 		dev_err(imx355->dev, "failed to set global settings");
1414 		return ret;
1415 	}
1416 
1417 	/* Apply default values of current mode */
1418 	reg_list = &imx355->cur_mode->reg_list;
1419 	ret = imx355_write_regs(imx355, reg_list->regs, reg_list->num_of_regs);
1420 	if (ret) {
1421 		dev_err(imx355->dev, "failed to set mode");
1422 		return ret;
1423 	}
1424 
1425 	/* set digital gain control to all color mode */
1426 	ret = imx355_write_reg(imx355, IMX355_REG_DPGA_USE_GLOBAL_GAIN, 1, 1);
1427 	if (ret)
1428 		return ret;
1429 
1430 	/* Apply customized values from user */
1431 	ret =  __v4l2_ctrl_handler_setup(imx355->sd.ctrl_handler);
1432 	if (ret)
1433 		return ret;
1434 
1435 	return imx355_write_reg(imx355, IMX355_REG_MODE_SELECT,
1436 				1, IMX355_MODE_STREAMING);
1437 }
1438 
1439 /* Stop streaming */
1440 static int imx355_stop_streaming(struct imx355 *imx355)
1441 {
1442 	return imx355_write_reg(imx355, IMX355_REG_MODE_SELECT,
1443 				1, IMX355_MODE_STANDBY);
1444 }
1445 
1446 static int imx355_set_stream(struct v4l2_subdev *sd, int enable)
1447 {
1448 	struct imx355 *imx355 = to_imx355(sd);
1449 	int ret = 0;
1450 
1451 	mutex_lock(&imx355->mutex);
1452 
1453 	if (enable) {
1454 		ret = pm_runtime_resume_and_get(imx355->dev);
1455 		if (ret < 0)
1456 			goto err_unlock;
1457 
1458 		/*
1459 		 * Apply default & customized values
1460 		 * and then start streaming.
1461 		 */
1462 		ret = imx355_start_streaming(imx355);
1463 		if (ret)
1464 			goto err_rpm_put;
1465 	} else {
1466 		imx355_stop_streaming(imx355);
1467 		pm_runtime_put(imx355->dev);
1468 	}
1469 
1470 	/* vflip and hflip cannot change during streaming */
1471 	__v4l2_ctrl_grab(imx355->vflip, enable);
1472 	__v4l2_ctrl_grab(imx355->hflip, enable);
1473 
1474 	mutex_unlock(&imx355->mutex);
1475 
1476 	return ret;
1477 
1478 err_rpm_put:
1479 	pm_runtime_put(imx355->dev);
1480 err_unlock:
1481 	mutex_unlock(&imx355->mutex);
1482 
1483 	return ret;
1484 }
1485 
1486 /* Verify chip ID */
1487 static int imx355_identify_module(struct imx355 *imx355)
1488 {
1489 	int ret;
1490 	u32 val;
1491 
1492 	ret = imx355_read_reg(imx355, IMX355_REG_CHIP_ID, 2, &val);
1493 	if (ret)
1494 		return ret;
1495 
1496 	if (val != IMX355_CHIP_ID) {
1497 		dev_err(imx355->dev, "chip id mismatch: %x!=%x",
1498 			IMX355_CHIP_ID, val);
1499 		return -EIO;
1500 	}
1501 	return 0;
1502 }
1503 
1504 static const struct v4l2_subdev_core_ops imx355_subdev_core_ops = {
1505 	.subscribe_event = v4l2_ctrl_subdev_subscribe_event,
1506 	.unsubscribe_event = v4l2_event_subdev_unsubscribe,
1507 };
1508 
1509 static const struct v4l2_subdev_video_ops imx355_video_ops = {
1510 	.s_stream = imx355_set_stream,
1511 };
1512 
1513 static const struct v4l2_subdev_pad_ops imx355_pad_ops = {
1514 	.enum_mbus_code = imx355_enum_mbus_code,
1515 	.get_fmt = imx355_get_pad_format,
1516 	.set_fmt = imx355_set_pad_format,
1517 	.enum_frame_size = imx355_enum_frame_size,
1518 };
1519 
1520 static const struct v4l2_subdev_ops imx355_subdev_ops = {
1521 	.core = &imx355_subdev_core_ops,
1522 	.video = &imx355_video_ops,
1523 	.pad = &imx355_pad_ops,
1524 };
1525 
1526 static const struct media_entity_operations imx355_subdev_entity_ops = {
1527 	.link_validate = v4l2_subdev_link_validate,
1528 };
1529 
1530 static const struct v4l2_subdev_internal_ops imx355_internal_ops = {
1531 	.open = imx355_open,
1532 };
1533 
1534 static int imx355_power_off(struct device *dev)
1535 {
1536 	struct i2c_client *client = container_of(dev, struct i2c_client, dev);
1537 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1538 	struct imx355 *imx355 = to_imx355(sd);
1539 
1540 	gpiod_set_value_cansleep(imx355->reset_gpio, 1);
1541 
1542 	regulator_bulk_disable(ARRAY_SIZE(imx355_supplies), imx355->supplies);
1543 	clk_disable_unprepare(imx355->clk);
1544 
1545 	return 0;
1546 }
1547 
1548 static int imx355_power_on(struct device *dev)
1549 {
1550 	struct i2c_client *client = container_of(dev, struct i2c_client, dev);
1551 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1552 	struct imx355 *imx355 = to_imx355(sd);
1553 	int ret;
1554 
1555 	ret = clk_prepare_enable(imx355->clk);
1556 	if (ret)
1557 		return dev_err_probe(dev, ret, "failed to enable clocks");
1558 
1559 	ret = regulator_bulk_enable(ARRAY_SIZE(imx355_supplies),
1560 				    imx355->supplies);
1561 	if (ret) {
1562 		dev_err_probe(dev, ret, "failed to enable regulators");
1563 		goto error_disable_clocks;
1564 	}
1565 
1566 	usleep_range(1000, 2000);
1567 	gpiod_set_value_cansleep(imx355->reset_gpio, 0);
1568 	usleep_range(10000, 11000);
1569 
1570 	return 0;
1571 
1572 error_disable_clocks:
1573 	clk_disable_unprepare(imx355->clk);
1574 	return ret;
1575 }
1576 
1577 static DEFINE_RUNTIME_DEV_PM_OPS(imx355_pm_ops, imx355_power_off,
1578 				 imx355_power_on, NULL);
1579 
1580 /* Initialize control handlers */
1581 static int imx355_init_controls(struct imx355 *imx355)
1582 {
1583 	struct v4l2_fwnode_device_properties props;
1584 	struct v4l2_ctrl_handler *ctrl_hdlr;
1585 	s64 exposure_max;
1586 	s64 vblank_def;
1587 	s64 vblank_min;
1588 	s64 hblank;
1589 	u64 pixel_rate;
1590 	const struct imx355_mode *mode;
1591 	u32 max;
1592 	int ret;
1593 
1594 	ctrl_hdlr = &imx355->ctrl_handler;
1595 	ret = v4l2_ctrl_handler_init(ctrl_hdlr, 12);
1596 	if (ret)
1597 		return ret;
1598 
1599 	ctrl_hdlr->lock = &imx355->mutex;
1600 	max = ARRAY_SIZE(link_freq_menu_items) - 1;
1601 	imx355->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &imx355_ctrl_ops,
1602 						   V4L2_CID_LINK_FREQ, max, 0,
1603 						   link_freq_menu_items);
1604 	if (imx355->link_freq)
1605 		imx355->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1606 
1607 	/* pixel_rate = link_freq * 2 * nr_of_lanes / bits_per_sample */
1608 	pixel_rate = IMX355_LINK_FREQ_DEFAULT * 2 * 4;
1609 	do_div(pixel_rate, 10);
1610 	/* By default, PIXEL_RATE is read only */
1611 	imx355->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &imx355_ctrl_ops,
1612 					       V4L2_CID_PIXEL_RATE, pixel_rate,
1613 					       pixel_rate, 1, pixel_rate);
1614 
1615 	/* Initialize vblank/hblank/exposure parameters based on current mode */
1616 	mode = imx355->cur_mode;
1617 	vblank_def = mode->fll_def - mode->height;
1618 	vblank_min = mode->fll_min - mode->height;
1619 	imx355->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx355_ctrl_ops,
1620 					   V4L2_CID_VBLANK, vblank_min,
1621 					   IMX355_FLL_MAX - mode->height,
1622 					   1, vblank_def);
1623 
1624 	hblank = mode->llp - mode->width;
1625 	imx355->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx355_ctrl_ops,
1626 					   V4L2_CID_HBLANK, hblank, hblank,
1627 					   1, hblank);
1628 	if (imx355->hblank)
1629 		imx355->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1630 
1631 	/* fll >= exposure time + adjust parameter (default value is 10) */
1632 	exposure_max = mode->fll_def - 10;
1633 	imx355->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &imx355_ctrl_ops,
1634 					     V4L2_CID_EXPOSURE,
1635 					     IMX355_EXPOSURE_MIN, exposure_max,
1636 					     IMX355_EXPOSURE_STEP,
1637 					     IMX355_EXPOSURE_DEFAULT);
1638 
1639 	imx355->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx355_ctrl_ops,
1640 					  V4L2_CID_HFLIP, 0, 1, 1, 0);
1641 	if (imx355->hflip)
1642 		imx355->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
1643 	imx355->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx355_ctrl_ops,
1644 					  V4L2_CID_VFLIP, 0, 1, 1, 0);
1645 	if (imx355->vflip)
1646 		imx355->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
1647 
1648 	v4l2_ctrl_new_std(ctrl_hdlr, &imx355_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
1649 			  IMX355_ANA_GAIN_MIN, IMX355_ANA_GAIN_MAX,
1650 			  IMX355_ANA_GAIN_STEP, IMX355_ANA_GAIN_DEFAULT);
1651 
1652 	/* Digital gain */
1653 	v4l2_ctrl_new_std(ctrl_hdlr, &imx355_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
1654 			  IMX355_DGTL_GAIN_MIN, IMX355_DGTL_GAIN_MAX,
1655 			  IMX355_DGTL_GAIN_STEP, IMX355_DGTL_GAIN_DEFAULT);
1656 
1657 	v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &imx355_ctrl_ops,
1658 				     V4L2_CID_TEST_PATTERN,
1659 				     ARRAY_SIZE(imx355_test_pattern_menu) - 1,
1660 				     0, 0, imx355_test_pattern_menu);
1661 	if (ctrl_hdlr->error) {
1662 		ret = ctrl_hdlr->error;
1663 		dev_err(imx355->dev, "control init failed: %d", ret);
1664 		goto error;
1665 	}
1666 
1667 	ret = v4l2_fwnode_device_parse(imx355->dev, &props);
1668 	if (ret)
1669 		goto error;
1670 
1671 	ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &imx355_ctrl_ops,
1672 					      &props);
1673 	if (ret)
1674 		goto error;
1675 
1676 	imx355->sd.ctrl_handler = ctrl_hdlr;
1677 
1678 	return 0;
1679 
1680 error:
1681 	v4l2_ctrl_handler_free(ctrl_hdlr);
1682 
1683 	return ret;
1684 }
1685 
1686 static struct imx355_hwcfg *imx355_get_hwcfg(struct device *dev)
1687 {
1688 	struct imx355_hwcfg *cfg;
1689 	struct v4l2_fwnode_endpoint bus_cfg = {
1690 		.bus_type = V4L2_MBUS_CSI2_DPHY
1691 	};
1692 	struct fwnode_handle *ep;
1693 	struct fwnode_handle *fwnode = dev_fwnode(dev);
1694 	int ret;
1695 
1696 	if (!fwnode)
1697 		return NULL;
1698 
1699 	ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
1700 	if (!ep)
1701 		return NULL;
1702 
1703 	ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
1704 	if (ret)
1705 		goto out_err;
1706 
1707 	cfg = devm_kzalloc(dev, sizeof(*cfg), GFP_KERNEL);
1708 	if (!cfg)
1709 		goto out_err;
1710 
1711 	if (bus_cfg.bus.mipi_csi2.num_data_lanes != IMX355_DATA_LANES)
1712 		goto out_err;
1713 
1714 	ret = v4l2_link_freq_to_bitmap(dev, bus_cfg.link_frequencies,
1715 				       bus_cfg.nr_of_link_frequencies,
1716 				       link_freq_menu_items,
1717 				       ARRAY_SIZE(link_freq_menu_items),
1718 				       &cfg->link_freq_bitmap);
1719 	if (ret)
1720 		goto out_err;
1721 
1722 	v4l2_fwnode_endpoint_free(&bus_cfg);
1723 	fwnode_handle_put(ep);
1724 	return cfg;
1725 
1726 out_err:
1727 	v4l2_fwnode_endpoint_free(&bus_cfg);
1728 	fwnode_handle_put(ep);
1729 	return NULL;
1730 }
1731 
1732 static int imx355_probe(struct i2c_client *client)
1733 {
1734 	struct imx355 *imx355;
1735 	unsigned long freq;
1736 	int ret;
1737 
1738 	imx355 = devm_kzalloc(&client->dev, sizeof(*imx355), GFP_KERNEL);
1739 	if (!imx355)
1740 		return -ENOMEM;
1741 
1742 	imx355->dev = &client->dev;
1743 
1744 	mutex_init(&imx355->mutex);
1745 
1746 	imx355->clk = devm_v4l2_sensor_clk_get(imx355->dev, NULL);
1747 	if (IS_ERR(imx355->clk))
1748 		return dev_err_probe(imx355->dev, PTR_ERR(imx355->clk),
1749 				     "failed to get clock\n");
1750 
1751 	freq = clk_get_rate(imx355->clk);
1752 	if (freq != IMX355_EXT_CLK)
1753 		return dev_err_probe(imx355->dev, -EINVAL,
1754 				     "external clock %lu is not supported\n",
1755 				     freq);
1756 
1757 	ret = devm_regulator_bulk_get_const(imx355->dev,
1758 					    ARRAY_SIZE(imx355_supplies),
1759 					    imx355_supplies,
1760 					    &imx355->supplies);
1761 	if (ret) {
1762 		dev_err_probe(imx355->dev, ret, "could not get regulators");
1763 		goto error_probe;
1764 	}
1765 
1766 	imx355->reset_gpio = devm_gpiod_get_optional(imx355->dev, "reset",
1767 						     GPIOD_OUT_HIGH);
1768 	if (IS_ERR(imx355->reset_gpio)) {
1769 		ret = dev_err_probe(imx355->dev, PTR_ERR(imx355->reset_gpio),
1770 				    "failed to get gpios");
1771 		goto error_probe;
1772 	}
1773 
1774 	/* Initialize subdev */
1775 	v4l2_i2c_subdev_init(&imx355->sd, client, &imx355_subdev_ops);
1776 
1777 	imx355->hwcfg = imx355_get_hwcfg(imx355->dev);
1778 	if (!imx355->hwcfg) {
1779 		dev_err(imx355->dev, "failed to get hwcfg");
1780 		ret = -ENODEV;
1781 		goto error_probe;
1782 	}
1783 
1784 	ret = imx355_power_on(imx355->dev);
1785 	if (ret)
1786 		goto error_probe;
1787 
1788 	/* Check module identity */
1789 	ret = imx355_identify_module(imx355);
1790 	if (ret) {
1791 		dev_err(imx355->dev, "failed to find sensor: %d", ret);
1792 		goto error_power_off;
1793 	}
1794 
1795 	/* Set default mode to max resolution */
1796 	imx355->cur_mode = &supported_modes[0];
1797 
1798 	ret = imx355_init_controls(imx355);
1799 	if (ret) {
1800 		dev_err(imx355->dev, "failed to init controls: %d", ret);
1801 		goto error_power_off;
1802 	}
1803 
1804 	/* Initialize subdev */
1805 	imx355->sd.internal_ops = &imx355_internal_ops;
1806 	imx355->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1807 		V4L2_SUBDEV_FL_HAS_EVENTS;
1808 	imx355->sd.entity.ops = &imx355_subdev_entity_ops;
1809 	imx355->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1810 
1811 	/* Initialize source pad */
1812 	imx355->pad.flags = MEDIA_PAD_FL_SOURCE;
1813 	ret = media_entity_pads_init(&imx355->sd.entity, 1, &imx355->pad);
1814 	if (ret) {
1815 		dev_err(imx355->dev, "failed to init entity pads: %d", ret);
1816 		goto error_handler_free;
1817 	}
1818 
1819 	/*
1820 	 * Device is already turned on by i2c-core with ACPI domain PM.
1821 	 * Enable runtime PM and turn off the device.
1822 	 */
1823 	pm_runtime_set_active(imx355->dev);
1824 	pm_runtime_enable(imx355->dev);
1825 	pm_runtime_idle(imx355->dev);
1826 
1827 	ret = v4l2_async_register_subdev_sensor(&imx355->sd);
1828 	if (ret < 0)
1829 		goto error_media_entity_runtime_pm;
1830 
1831 	return 0;
1832 
1833 error_media_entity_runtime_pm:
1834 	pm_runtime_disable(imx355->dev);
1835 	pm_runtime_set_suspended(imx355->dev);
1836 	media_entity_cleanup(&imx355->sd.entity);
1837 
1838 error_handler_free:
1839 	v4l2_ctrl_handler_free(imx355->sd.ctrl_handler);
1840 
1841 error_power_off:
1842 	imx355_power_off(imx355->dev);
1843 
1844 error_probe:
1845 	mutex_destroy(&imx355->mutex);
1846 
1847 	return ret;
1848 }
1849 
1850 static void imx355_remove(struct i2c_client *client)
1851 {
1852 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1853 	struct imx355 *imx355 = to_imx355(sd);
1854 
1855 	v4l2_async_unregister_subdev(sd);
1856 	media_entity_cleanup(&sd->entity);
1857 	v4l2_ctrl_handler_free(sd->ctrl_handler);
1858 
1859 	pm_runtime_disable(imx355->dev);
1860 
1861 	if (!pm_runtime_status_suspended(imx355->dev)) {
1862 		imx355_power_off(imx355->dev);
1863 		pm_runtime_set_suspended(imx355->dev);
1864 	}
1865 
1866 	mutex_destroy(&imx355->mutex);
1867 }
1868 
1869 static const struct acpi_device_id imx355_acpi_ids[] __maybe_unused = {
1870 	{ "SONY355A" },
1871 	{ /* sentinel */ }
1872 };
1873 MODULE_DEVICE_TABLE(acpi, imx355_acpi_ids);
1874 
1875 static const struct of_device_id imx355_match_table[] = {
1876 	{ .compatible = "sony,imx355", },
1877 	{ /* sentinel */ }
1878 };
1879 MODULE_DEVICE_TABLE(of, imx355_match_table);
1880 
1881 static struct i2c_driver imx355_i2c_driver = {
1882 	.driver = {
1883 		.name = "imx355",
1884 		.acpi_match_table = ACPI_PTR(imx355_acpi_ids),
1885 		.of_match_table = imx355_match_table,
1886 		.pm = &imx355_pm_ops,
1887 	},
1888 	.probe = imx355_probe,
1889 	.remove = imx355_remove,
1890 };
1891 module_i2c_driver(imx355_i2c_driver);
1892 
1893 MODULE_AUTHOR("Qiu, Tianshu <tian.shu.qiu@intel.com>");
1894 MODULE_AUTHOR("Rapolu, Chiranjeevi");
1895 MODULE_AUTHOR("Bingbu Cao <bingbu.cao@intel.com>");
1896 MODULE_AUTHOR("Yang, Hyungwoo");
1897 MODULE_DESCRIPTION("Sony imx355 sensor driver");
1898 MODULE_LICENSE("GPL v2");
1899