xref: /linux/drivers/media/i2c/imx355.c (revision 12cdc242c3faaa66399a01fb40c151ee236e6bbf) 
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2018 Intel Corporation
3 
4 #include <linux/acpi.h>
5 #include <linux/clk.h>
6 #include <linux/delay.h>
7 #include <linux/gpio/consumer.h>
8 #include <linux/i2c.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/pm_runtime.h>
12 #include <linux/regulator/consumer.h>
13 #include <linux/unaligned.h>
14 
15 #include <media/v4l2-ctrls.h>
16 #include <media/v4l2-device.h>
17 #include <media/v4l2-event.h>
18 #include <media/v4l2-fwnode.h>
19 
20 #define IMX355_REG_MODE_SELECT		0x0100
21 #define IMX355_MODE_STANDBY		0x00
22 #define IMX355_MODE_STREAMING		0x01
23 
24 /* Chip ID */
25 #define IMX355_REG_CHIP_ID		0x0016
26 #define IMX355_CHIP_ID			0x0355
27 
28 /* V_TIMING internal */
29 #define IMX355_REG_FLL			0x0340
30 #define IMX355_FLL_MAX			0xffff
31 
32 /* Exposure control */
33 #define IMX355_REG_EXPOSURE		0x0202
34 #define IMX355_EXPOSURE_MIN		1
35 #define IMX355_EXPOSURE_STEP		1
36 #define IMX355_EXPOSURE_DEFAULT		0x0282
37 
38 /* Analog gain control */
39 #define IMX355_REG_ANALOG_GAIN		0x0204
40 #define IMX355_ANA_GAIN_MIN		0
41 #define IMX355_ANA_GAIN_MAX		960
42 #define IMX355_ANA_GAIN_STEP		1
43 #define IMX355_ANA_GAIN_DEFAULT		0
44 
45 /* Digital gain control */
46 #define IMX355_REG_DPGA_USE_GLOBAL_GAIN	0x3070
47 #define IMX355_REG_DIG_GAIN_GLOBAL	0x020e
48 #define IMX355_DGTL_GAIN_MIN		256
49 #define IMX355_DGTL_GAIN_MAX		4095
50 #define IMX355_DGTL_GAIN_STEP		1
51 #define IMX355_DGTL_GAIN_DEFAULT	256
52 
53 /* Test Pattern Control */
54 #define IMX355_REG_TEST_PATTERN		0x0600
55 #define IMX355_TEST_PATTERN_DISABLED		0
56 #define IMX355_TEST_PATTERN_SOLID_COLOR		1
57 #define IMX355_TEST_PATTERN_COLOR_BARS		2
58 #define IMX355_TEST_PATTERN_GRAY_COLOR_BARS	3
59 #define IMX355_TEST_PATTERN_PN9			4
60 
61 /* Flip Control */
62 #define IMX355_REG_ORIENTATION		0x0101
63 
64 /* default link frequency and external clock */
65 #define IMX355_LINK_FREQ_DEFAULT	360000000LL
66 #define IMX355_EXT_CLK			19200000
67 #define IMX355_LINK_FREQ_INDEX		0
68 
69 struct imx355_reg {
70 	u16 address;
71 	u8 val;
72 };
73 
74 struct imx355_reg_list {
75 	u32 num_of_regs;
76 	const struct imx355_reg *regs;
77 };
78 
79 /* Mode : resolution and related config&values */
80 struct imx355_mode {
81 	/* Frame width */
82 	u32 width;
83 	/* Frame height */
84 	u32 height;
85 
86 	/* V-timing */
87 	u32 fll_def;
88 	u32 fll_min;
89 
90 	/* H-timing */
91 	u32 llp;
92 
93 	/* index of link frequency */
94 	u32 link_freq_index;
95 
96 	/* Default register values */
97 	struct imx355_reg_list reg_list;
98 };
99 
100 struct imx355_hwcfg {
101 	unsigned long link_freq_bitmap;
102 };
103 
104 struct imx355 {
105 	struct device *dev;
106 	struct clk *clk;
107 
108 	struct v4l2_subdev sd;
109 	struct media_pad pad;
110 
111 	struct v4l2_ctrl_handler ctrl_handler;
112 	/* V4L2 Controls */
113 	struct v4l2_ctrl *link_freq;
114 	struct v4l2_ctrl *pixel_rate;
115 	struct v4l2_ctrl *vblank;
116 	struct v4l2_ctrl *hblank;
117 	struct v4l2_ctrl *exposure;
118 	struct v4l2_ctrl *vflip;
119 	struct v4l2_ctrl *hflip;
120 
121 	/* Current mode */
122 	const struct imx355_mode *cur_mode;
123 
124 	struct imx355_hwcfg *hwcfg;
125 
126 	/*
127 	 * Mutex for serialized access:
128 	 * Protect sensor set pad format and start/stop streaming safely.
129 	 * Protect access to sensor v4l2 controls.
130 	 */
131 	struct mutex mutex;
132 
133 	struct gpio_desc *reset_gpio;
134 	struct regulator_bulk_data *supplies;
135 };
136 
137 static const struct regulator_bulk_data imx355_supplies[] = {
138 	{ .supply = "avdd" },
139 	{ .supply = "dvdd" },
140 	{ .supply = "dovdd" },
141 };
142 
143 static const struct imx355_reg imx355_global_regs[] = {
144 	{ 0x0136, 0x13 },
145 	{ 0x0137, 0x33 },
146 	{ 0x304e, 0x03 },
147 	{ 0x4348, 0x16 },
148 	{ 0x4350, 0x19 },
149 	{ 0x4408, 0x0a },
150 	{ 0x440c, 0x0b },
151 	{ 0x4411, 0x5f },
152 	{ 0x4412, 0x2c },
153 	{ 0x4623, 0x00 },
154 	{ 0x462c, 0x0f },
155 	{ 0x462d, 0x00 },
156 	{ 0x462e, 0x00 },
157 	{ 0x4684, 0x54 },
158 	{ 0x480a, 0x07 },
159 	{ 0x4908, 0x07 },
160 	{ 0x4909, 0x07 },
161 	{ 0x490d, 0x0a },
162 	{ 0x491e, 0x0f },
163 	{ 0x4921, 0x06 },
164 	{ 0x4923, 0x28 },
165 	{ 0x4924, 0x28 },
166 	{ 0x4925, 0x29 },
167 	{ 0x4926, 0x29 },
168 	{ 0x4927, 0x1f },
169 	{ 0x4928, 0x20 },
170 	{ 0x4929, 0x20 },
171 	{ 0x492a, 0x20 },
172 	{ 0x492c, 0x05 },
173 	{ 0x492d, 0x06 },
174 	{ 0x492e, 0x06 },
175 	{ 0x492f, 0x06 },
176 	{ 0x4930, 0x03 },
177 	{ 0x4931, 0x04 },
178 	{ 0x4932, 0x04 },
179 	{ 0x4933, 0x05 },
180 	{ 0x595e, 0x01 },
181 	{ 0x5963, 0x01 },
182 	{ 0x3030, 0x01 },
183 	{ 0x3031, 0x01 },
184 	{ 0x3045, 0x01 },
185 	{ 0x4010, 0x00 },
186 	{ 0x4011, 0x00 },
187 	{ 0x4012, 0x00 },
188 	{ 0x4013, 0x01 },
189 	{ 0x68a8, 0xfe },
190 	{ 0x68a9, 0xff },
191 	{ 0x6888, 0x00 },
192 	{ 0x6889, 0x00 },
193 	{ 0x68b0, 0x00 },
194 	{ 0x3058, 0x00 },
195 	{ 0x305a, 0x00 },
196 };
197 
198 static const struct imx355_reg_list imx355_global_setting = {
199 	.num_of_regs = ARRAY_SIZE(imx355_global_regs),
200 	.regs = imx355_global_regs,
201 };
202 
203 static const struct imx355_reg mode_3268x2448_regs[] = {
204 	{ 0x0112, 0x0a },
205 	{ 0x0113, 0x0a },
206 	{ 0x0114, 0x03 },
207 	{ 0x0342, 0x0e },
208 	{ 0x0343, 0x58 },
209 	{ 0x0340, 0x0a },
210 	{ 0x0341, 0x37 },
211 	{ 0x0344, 0x00 },
212 	{ 0x0345, 0x08 },
213 	{ 0x0346, 0x00 },
214 	{ 0x0347, 0x08 },
215 	{ 0x0348, 0x0c },
216 	{ 0x0349, 0xcb },
217 	{ 0x034a, 0x09 },
218 	{ 0x034b, 0x97 },
219 	{ 0x0220, 0x00 },
220 	{ 0x0222, 0x01 },
221 	{ 0x0900, 0x00 },
222 	{ 0x0901, 0x11 },
223 	{ 0x0902, 0x00 },
224 	{ 0x034c, 0x0c },
225 	{ 0x034d, 0xc4 },
226 	{ 0x034e, 0x09 },
227 	{ 0x034f, 0x90 },
228 	{ 0x0301, 0x05 },
229 	{ 0x0303, 0x01 },
230 	{ 0x0305, 0x02 },
231 	{ 0x0306, 0x00 },
232 	{ 0x0307, 0x78 },
233 	{ 0x030b, 0x01 },
234 	{ 0x030d, 0x02 },
235 	{ 0x030e, 0x00 },
236 	{ 0x030f, 0x4b },
237 	{ 0x0310, 0x00 },
238 	{ 0x0700, 0x00 },
239 	{ 0x0701, 0x10 },
240 	{ 0x0820, 0x0b },
241 	{ 0x0821, 0x40 },
242 	{ 0x3088, 0x04 },
243 	{ 0x6813, 0x02 },
244 	{ 0x6835, 0x07 },
245 	{ 0x6836, 0x01 },
246 	{ 0x6837, 0x04 },
247 	{ 0x684d, 0x07 },
248 	{ 0x684e, 0x01 },
249 	{ 0x684f, 0x04 },
250 };
251 
252 static const struct imx355_reg mode_3264x2448_regs[] = {
253 	{ 0x0112, 0x0a },
254 	{ 0x0113, 0x0a },
255 	{ 0x0114, 0x03 },
256 	{ 0x0342, 0x0e },
257 	{ 0x0343, 0x58 },
258 	{ 0x0340, 0x0a },
259 	{ 0x0341, 0x37 },
260 	{ 0x0344, 0x00 },
261 	{ 0x0345, 0x08 },
262 	{ 0x0346, 0x00 },
263 	{ 0x0347, 0x08 },
264 	{ 0x0348, 0x0c },
265 	{ 0x0349, 0xc7 },
266 	{ 0x034a, 0x09 },
267 	{ 0x034b, 0x97 },
268 	{ 0x0220, 0x00 },
269 	{ 0x0222, 0x01 },
270 	{ 0x0900, 0x00 },
271 	{ 0x0901, 0x11 },
272 	{ 0x0902, 0x00 },
273 	{ 0x034c, 0x0c },
274 	{ 0x034d, 0xc0 },
275 	{ 0x034e, 0x09 },
276 	{ 0x034f, 0x90 },
277 	{ 0x0301, 0x05 },
278 	{ 0x0303, 0x01 },
279 	{ 0x0305, 0x02 },
280 	{ 0x0306, 0x00 },
281 	{ 0x0307, 0x78 },
282 	{ 0x030b, 0x01 },
283 	{ 0x030d, 0x02 },
284 	{ 0x030e, 0x00 },
285 	{ 0x030f, 0x4b },
286 	{ 0x0310, 0x00 },
287 	{ 0x0700, 0x00 },
288 	{ 0x0701, 0x10 },
289 	{ 0x0820, 0x0b },
290 	{ 0x0821, 0x40 },
291 	{ 0x3088, 0x04 },
292 	{ 0x6813, 0x02 },
293 	{ 0x6835, 0x07 },
294 	{ 0x6836, 0x01 },
295 	{ 0x6837, 0x04 },
296 	{ 0x684d, 0x07 },
297 	{ 0x684e, 0x01 },
298 	{ 0x684f, 0x04 },
299 };
300 
301 static const struct imx355_reg mode_3280x2464_regs[] = {
302 	{ 0x0112, 0x0a },
303 	{ 0x0113, 0x0a },
304 	{ 0x0114, 0x03 },
305 	{ 0x0342, 0x0e },
306 	{ 0x0343, 0x58 },
307 	{ 0x0340, 0x0a },
308 	{ 0x0341, 0x37 },
309 	{ 0x0344, 0x00 },
310 	{ 0x0345, 0x00 },
311 	{ 0x0346, 0x00 },
312 	{ 0x0347, 0x00 },
313 	{ 0x0348, 0x0c },
314 	{ 0x0349, 0xcf },
315 	{ 0x034a, 0x09 },
316 	{ 0x034b, 0x9f },
317 	{ 0x0220, 0x00 },
318 	{ 0x0222, 0x01 },
319 	{ 0x0900, 0x00 },
320 	{ 0x0901, 0x11 },
321 	{ 0x0902, 0x00 },
322 	{ 0x034c, 0x0c },
323 	{ 0x034d, 0xd0 },
324 	{ 0x034e, 0x09 },
325 	{ 0x034f, 0xa0 },
326 	{ 0x0301, 0x05 },
327 	{ 0x0303, 0x01 },
328 	{ 0x0305, 0x02 },
329 	{ 0x0306, 0x00 },
330 	{ 0x0307, 0x78 },
331 	{ 0x030b, 0x01 },
332 	{ 0x030d, 0x02 },
333 	{ 0x030e, 0x00 },
334 	{ 0x030f, 0x4b },
335 	{ 0x0310, 0x00 },
336 	{ 0x0700, 0x00 },
337 	{ 0x0701, 0x10 },
338 	{ 0x0820, 0x0b },
339 	{ 0x0821, 0x40 },
340 	{ 0x3088, 0x04 },
341 	{ 0x6813, 0x02 },
342 	{ 0x6835, 0x07 },
343 	{ 0x6836, 0x01 },
344 	{ 0x6837, 0x04 },
345 	{ 0x684d, 0x07 },
346 	{ 0x684e, 0x01 },
347 	{ 0x684f, 0x04 },
348 };
349 
350 static const struct imx355_reg mode_1940x1096_regs[] = {
351 	{ 0x0112, 0x0a },
352 	{ 0x0113, 0x0a },
353 	{ 0x0114, 0x03 },
354 	{ 0x0342, 0x0e },
355 	{ 0x0343, 0x58 },
356 	{ 0x0340, 0x05 },
357 	{ 0x0341, 0x1a },
358 	{ 0x0344, 0x02 },
359 	{ 0x0345, 0xa0 },
360 	{ 0x0346, 0x02 },
361 	{ 0x0347, 0xac },
362 	{ 0x0348, 0x0a },
363 	{ 0x0349, 0x33 },
364 	{ 0x034a, 0x06 },
365 	{ 0x034b, 0xf3 },
366 	{ 0x0220, 0x00 },
367 	{ 0x0222, 0x01 },
368 	{ 0x0900, 0x00 },
369 	{ 0x0901, 0x11 },
370 	{ 0x0902, 0x00 },
371 	{ 0x034c, 0x07 },
372 	{ 0x034d, 0x94 },
373 	{ 0x034e, 0x04 },
374 	{ 0x034f, 0x48 },
375 	{ 0x0301, 0x05 },
376 	{ 0x0303, 0x01 },
377 	{ 0x0305, 0x02 },
378 	{ 0x0306, 0x00 },
379 	{ 0x0307, 0x78 },
380 	{ 0x030b, 0x01 },
381 	{ 0x030d, 0x02 },
382 	{ 0x030e, 0x00 },
383 	{ 0x030f, 0x4b },
384 	{ 0x0310, 0x00 },
385 	{ 0x0700, 0x00 },
386 	{ 0x0701, 0x10 },
387 	{ 0x0820, 0x0b },
388 	{ 0x0821, 0x40 },
389 	{ 0x3088, 0x04 },
390 	{ 0x6813, 0x02 },
391 	{ 0x6835, 0x07 },
392 	{ 0x6836, 0x01 },
393 	{ 0x6837, 0x04 },
394 	{ 0x684d, 0x07 },
395 	{ 0x684e, 0x01 },
396 	{ 0x684f, 0x04 },
397 };
398 
399 static const struct imx355_reg mode_1936x1096_regs[] = {
400 	{ 0x0112, 0x0a },
401 	{ 0x0113, 0x0a },
402 	{ 0x0114, 0x03 },
403 	{ 0x0342, 0x0e },
404 	{ 0x0343, 0x58 },
405 	{ 0x0340, 0x05 },
406 	{ 0x0341, 0x1a },
407 	{ 0x0344, 0x02 },
408 	{ 0x0345, 0xa0 },
409 	{ 0x0346, 0x02 },
410 	{ 0x0347, 0xac },
411 	{ 0x0348, 0x0a },
412 	{ 0x0349, 0x2f },
413 	{ 0x034a, 0x06 },
414 	{ 0x034b, 0xf3 },
415 	{ 0x0220, 0x00 },
416 	{ 0x0222, 0x01 },
417 	{ 0x0900, 0x00 },
418 	{ 0x0901, 0x11 },
419 	{ 0x0902, 0x00 },
420 	{ 0x034c, 0x07 },
421 	{ 0x034d, 0x90 },
422 	{ 0x034e, 0x04 },
423 	{ 0x034f, 0x48 },
424 	{ 0x0301, 0x05 },
425 	{ 0x0303, 0x01 },
426 	{ 0x0305, 0x02 },
427 	{ 0x0306, 0x00 },
428 	{ 0x0307, 0x78 },
429 	{ 0x030b, 0x01 },
430 	{ 0x030d, 0x02 },
431 	{ 0x030e, 0x00 },
432 	{ 0x030f, 0x4b },
433 	{ 0x0310, 0x00 },
434 	{ 0x0700, 0x00 },
435 	{ 0x0701, 0x10 },
436 	{ 0x0820, 0x0b },
437 	{ 0x0821, 0x40 },
438 	{ 0x3088, 0x04 },
439 	{ 0x6813, 0x02 },
440 	{ 0x6835, 0x07 },
441 	{ 0x6836, 0x01 },
442 	{ 0x6837, 0x04 },
443 	{ 0x684d, 0x07 },
444 	{ 0x684e, 0x01 },
445 	{ 0x684f, 0x04 },
446 };
447 
448 static const struct imx355_reg mode_1924x1080_regs[] = {
449 	{ 0x0112, 0x0a },
450 	{ 0x0113, 0x0a },
451 	{ 0x0114, 0x03 },
452 	{ 0x0342, 0x0e },
453 	{ 0x0343, 0x58 },
454 	{ 0x0340, 0x05 },
455 	{ 0x0341, 0x1a },
456 	{ 0x0344, 0x02 },
457 	{ 0x0345, 0xa8 },
458 	{ 0x0346, 0x02 },
459 	{ 0x0347, 0xb4 },
460 	{ 0x0348, 0x0a },
461 	{ 0x0349, 0x2b },
462 	{ 0x034a, 0x06 },
463 	{ 0x034b, 0xeb },
464 	{ 0x0220, 0x00 },
465 	{ 0x0222, 0x01 },
466 	{ 0x0900, 0x00 },
467 	{ 0x0901, 0x11 },
468 	{ 0x0902, 0x00 },
469 	{ 0x034c, 0x07 },
470 	{ 0x034d, 0x84 },
471 	{ 0x034e, 0x04 },
472 	{ 0x034f, 0x38 },
473 	{ 0x0301, 0x05 },
474 	{ 0x0303, 0x01 },
475 	{ 0x0305, 0x02 },
476 	{ 0x0306, 0x00 },
477 	{ 0x0307, 0x78 },
478 	{ 0x030b, 0x01 },
479 	{ 0x030d, 0x02 },
480 	{ 0x030e, 0x00 },
481 	{ 0x030f, 0x4b },
482 	{ 0x0310, 0x00 },
483 	{ 0x0700, 0x00 },
484 	{ 0x0701, 0x10 },
485 	{ 0x0820, 0x0b },
486 	{ 0x0821, 0x40 },
487 	{ 0x3088, 0x04 },
488 	{ 0x6813, 0x02 },
489 	{ 0x6835, 0x07 },
490 	{ 0x6836, 0x01 },
491 	{ 0x6837, 0x04 },
492 	{ 0x684d, 0x07 },
493 	{ 0x684e, 0x01 },
494 	{ 0x684f, 0x04 },
495 };
496 
497 static const struct imx355_reg mode_1920x1080_regs[] = {
498 	{ 0x0112, 0x0a },
499 	{ 0x0113, 0x0a },
500 	{ 0x0114, 0x03 },
501 	{ 0x0342, 0x0e },
502 	{ 0x0343, 0x58 },
503 	{ 0x0340, 0x05 },
504 	{ 0x0341, 0x1a },
505 	{ 0x0344, 0x02 },
506 	{ 0x0345, 0xa8 },
507 	{ 0x0346, 0x02 },
508 	{ 0x0347, 0xb4 },
509 	{ 0x0348, 0x0a },
510 	{ 0x0349, 0x27 },
511 	{ 0x034a, 0x06 },
512 	{ 0x034b, 0xeb },
513 	{ 0x0220, 0x00 },
514 	{ 0x0222, 0x01 },
515 	{ 0x0900, 0x00 },
516 	{ 0x0901, 0x11 },
517 	{ 0x0902, 0x00 },
518 	{ 0x034c, 0x07 },
519 	{ 0x034d, 0x80 },
520 	{ 0x034e, 0x04 },
521 	{ 0x034f, 0x38 },
522 	{ 0x0301, 0x05 },
523 	{ 0x0303, 0x01 },
524 	{ 0x0305, 0x02 },
525 	{ 0x0306, 0x00 },
526 	{ 0x0307, 0x78 },
527 	{ 0x030b, 0x01 },
528 	{ 0x030d, 0x02 },
529 	{ 0x030e, 0x00 },
530 	{ 0x030f, 0x4b },
531 	{ 0x0310, 0x00 },
532 	{ 0x0700, 0x00 },
533 	{ 0x0701, 0x10 },
534 	{ 0x0820, 0x0b },
535 	{ 0x0821, 0x40 },
536 	{ 0x3088, 0x04 },
537 	{ 0x6813, 0x02 },
538 	{ 0x6835, 0x07 },
539 	{ 0x6836, 0x01 },
540 	{ 0x6837, 0x04 },
541 	{ 0x684d, 0x07 },
542 	{ 0x684e, 0x01 },
543 	{ 0x684f, 0x04 },
544 };
545 
546 static const struct imx355_reg mode_1640x1232_regs[] = {
547 	{ 0x0112, 0x0a },
548 	{ 0x0113, 0x0a },
549 	{ 0x0114, 0x03 },
550 	{ 0x0342, 0x07 },
551 	{ 0x0343, 0x2c },
552 	{ 0x0340, 0x05 },
553 	{ 0x0341, 0x1a },
554 	{ 0x0344, 0x00 },
555 	{ 0x0345, 0x00 },
556 	{ 0x0346, 0x00 },
557 	{ 0x0347, 0x00 },
558 	{ 0x0348, 0x0c },
559 	{ 0x0349, 0xcf },
560 	{ 0x034a, 0x09 },
561 	{ 0x034b, 0x9f },
562 	{ 0x0220, 0x00 },
563 	{ 0x0222, 0x01 },
564 	{ 0x0900, 0x01 },
565 	{ 0x0901, 0x22 },
566 	{ 0x0902, 0x00 },
567 	{ 0x034c, 0x06 },
568 	{ 0x034d, 0x68 },
569 	{ 0x034e, 0x04 },
570 	{ 0x034f, 0xd0 },
571 	{ 0x0301, 0x05 },
572 	{ 0x0303, 0x01 },
573 	{ 0x0305, 0x02 },
574 	{ 0x0306, 0x00 },
575 	{ 0x0307, 0x78 },
576 	{ 0x030b, 0x01 },
577 	{ 0x030d, 0x02 },
578 	{ 0x030e, 0x00 },
579 	{ 0x030f, 0x4b },
580 	{ 0x0310, 0x00 },
581 	{ 0x0700, 0x00 },
582 	{ 0x0701, 0x10 },
583 	{ 0x0820, 0x0b },
584 	{ 0x0821, 0x40 },
585 	{ 0x3088, 0x04 },
586 	{ 0x6813, 0x02 },
587 	{ 0x6835, 0x07 },
588 	{ 0x6836, 0x01 },
589 	{ 0x6837, 0x04 },
590 	{ 0x684d, 0x07 },
591 	{ 0x684e, 0x01 },
592 	{ 0x684f, 0x04 },
593 };
594 
595 static const struct imx355_reg mode_1640x922_regs[] = {
596 	{ 0x0112, 0x0a },
597 	{ 0x0113, 0x0a },
598 	{ 0x0114, 0x03 },
599 	{ 0x0342, 0x07 },
600 	{ 0x0343, 0x2c },
601 	{ 0x0340, 0x05 },
602 	{ 0x0341, 0x1a },
603 	{ 0x0344, 0x00 },
604 	{ 0x0345, 0x00 },
605 	{ 0x0346, 0x01 },
606 	{ 0x0347, 0x30 },
607 	{ 0x0348, 0x0c },
608 	{ 0x0349, 0xcf },
609 	{ 0x034a, 0x08 },
610 	{ 0x034b, 0x63 },
611 	{ 0x0220, 0x00 },
612 	{ 0x0222, 0x01 },
613 	{ 0x0900, 0x01 },
614 	{ 0x0901, 0x22 },
615 	{ 0x0902, 0x00 },
616 	{ 0x034c, 0x06 },
617 	{ 0x034d, 0x68 },
618 	{ 0x034e, 0x03 },
619 	{ 0x034f, 0x9a },
620 	{ 0x0301, 0x05 },
621 	{ 0x0303, 0x01 },
622 	{ 0x0305, 0x02 },
623 	{ 0x0306, 0x00 },
624 	{ 0x0307, 0x78 },
625 	{ 0x030b, 0x01 },
626 	{ 0x030d, 0x02 },
627 	{ 0x030e, 0x00 },
628 	{ 0x030f, 0x4b },
629 	{ 0x0310, 0x00 },
630 	{ 0x0700, 0x00 },
631 	{ 0x0701, 0x10 },
632 	{ 0x0820, 0x0b },
633 	{ 0x0821, 0x40 },
634 	{ 0x3088, 0x04 },
635 	{ 0x6813, 0x02 },
636 	{ 0x6835, 0x07 },
637 	{ 0x6836, 0x01 },
638 	{ 0x6837, 0x04 },
639 	{ 0x684d, 0x07 },
640 	{ 0x684e, 0x01 },
641 	{ 0x684f, 0x04 },
642 };
643 
644 static const struct imx355_reg mode_1300x736_regs[] = {
645 	{ 0x0112, 0x0a },
646 	{ 0x0113, 0x0a },
647 	{ 0x0114, 0x03 },
648 	{ 0x0342, 0x07 },
649 	{ 0x0343, 0x2c },
650 	{ 0x0340, 0x05 },
651 	{ 0x0341, 0x1a },
652 	{ 0x0344, 0x01 },
653 	{ 0x0345, 0x58 },
654 	{ 0x0346, 0x01 },
655 	{ 0x0347, 0xf0 },
656 	{ 0x0348, 0x0b },
657 	{ 0x0349, 0x7f },
658 	{ 0x034a, 0x07 },
659 	{ 0x034b, 0xaf },
660 	{ 0x0220, 0x00 },
661 	{ 0x0222, 0x01 },
662 	{ 0x0900, 0x01 },
663 	{ 0x0901, 0x22 },
664 	{ 0x0902, 0x00 },
665 	{ 0x034c, 0x05 },
666 	{ 0x034d, 0x14 },
667 	{ 0x034e, 0x02 },
668 	{ 0x034f, 0xe0 },
669 	{ 0x0301, 0x05 },
670 	{ 0x0303, 0x01 },
671 	{ 0x0305, 0x02 },
672 	{ 0x0306, 0x00 },
673 	{ 0x0307, 0x78 },
674 	{ 0x030b, 0x01 },
675 	{ 0x030d, 0x02 },
676 	{ 0x030e, 0x00 },
677 	{ 0x030f, 0x4b },
678 	{ 0x0310, 0x00 },
679 	{ 0x0700, 0x00 },
680 	{ 0x0701, 0x10 },
681 	{ 0x0820, 0x0b },
682 	{ 0x0821, 0x40 },
683 	{ 0x3088, 0x04 },
684 	{ 0x6813, 0x02 },
685 	{ 0x6835, 0x07 },
686 	{ 0x6836, 0x01 },
687 	{ 0x6837, 0x04 },
688 	{ 0x684d, 0x07 },
689 	{ 0x684e, 0x01 },
690 	{ 0x684f, 0x04 },
691 };
692 
693 static const struct imx355_reg mode_1296x736_regs[] = {
694 	{ 0x0112, 0x0a },
695 	{ 0x0113, 0x0a },
696 	{ 0x0114, 0x03 },
697 	{ 0x0342, 0x07 },
698 	{ 0x0343, 0x2c },
699 	{ 0x0340, 0x05 },
700 	{ 0x0341, 0x1a },
701 	{ 0x0344, 0x01 },
702 	{ 0x0345, 0x58 },
703 	{ 0x0346, 0x01 },
704 	{ 0x0347, 0xf0 },
705 	{ 0x0348, 0x0b },
706 	{ 0x0349, 0x77 },
707 	{ 0x034a, 0x07 },
708 	{ 0x034b, 0xaf },
709 	{ 0x0220, 0x00 },
710 	{ 0x0222, 0x01 },
711 	{ 0x0900, 0x01 },
712 	{ 0x0901, 0x22 },
713 	{ 0x0902, 0x00 },
714 	{ 0x034c, 0x05 },
715 	{ 0x034d, 0x10 },
716 	{ 0x034e, 0x02 },
717 	{ 0x034f, 0xe0 },
718 	{ 0x0301, 0x05 },
719 	{ 0x0303, 0x01 },
720 	{ 0x0305, 0x02 },
721 	{ 0x0306, 0x00 },
722 	{ 0x0307, 0x78 },
723 	{ 0x030b, 0x01 },
724 	{ 0x030d, 0x02 },
725 	{ 0x030e, 0x00 },
726 	{ 0x030f, 0x4b },
727 	{ 0x0310, 0x00 },
728 	{ 0x0700, 0x00 },
729 	{ 0x0701, 0x10 },
730 	{ 0x0820, 0x0b },
731 	{ 0x0821, 0x40 },
732 	{ 0x3088, 0x04 },
733 	{ 0x6813, 0x02 },
734 	{ 0x6835, 0x07 },
735 	{ 0x6836, 0x01 },
736 	{ 0x6837, 0x04 },
737 	{ 0x684d, 0x07 },
738 	{ 0x684e, 0x01 },
739 	{ 0x684f, 0x04 },
740 };
741 
742 static const struct imx355_reg mode_1284x720_regs[] = {
743 	{ 0x0112, 0x0a },
744 	{ 0x0113, 0x0a },
745 	{ 0x0114, 0x03 },
746 	{ 0x0342, 0x07 },
747 	{ 0x0343, 0x2c },
748 	{ 0x0340, 0x05 },
749 	{ 0x0341, 0x1a },
750 	{ 0x0344, 0x01 },
751 	{ 0x0345, 0x68 },
752 	{ 0x0346, 0x02 },
753 	{ 0x0347, 0x00 },
754 	{ 0x0348, 0x0b },
755 	{ 0x0349, 0x6f },
756 	{ 0x034a, 0x07 },
757 	{ 0x034b, 0x9f },
758 	{ 0x0220, 0x00 },
759 	{ 0x0222, 0x01 },
760 	{ 0x0900, 0x01 },
761 	{ 0x0901, 0x22 },
762 	{ 0x0902, 0x00 },
763 	{ 0x034c, 0x05 },
764 	{ 0x034d, 0x04 },
765 	{ 0x034e, 0x02 },
766 	{ 0x034f, 0xd0 },
767 	{ 0x0301, 0x05 },
768 	{ 0x0303, 0x01 },
769 	{ 0x0305, 0x02 },
770 	{ 0x0306, 0x00 },
771 	{ 0x0307, 0x78 },
772 	{ 0x030b, 0x01 },
773 	{ 0x030d, 0x02 },
774 	{ 0x030e, 0x00 },
775 	{ 0x030f, 0x4b },
776 	{ 0x0310, 0x00 },
777 	{ 0x0700, 0x00 },
778 	{ 0x0701, 0x10 },
779 	{ 0x0820, 0x0b },
780 	{ 0x0821, 0x40 },
781 	{ 0x3088, 0x04 },
782 	{ 0x6813, 0x02 },
783 	{ 0x6835, 0x07 },
784 	{ 0x6836, 0x01 },
785 	{ 0x6837, 0x04 },
786 	{ 0x684d, 0x07 },
787 	{ 0x684e, 0x01 },
788 	{ 0x684f, 0x04 },
789 };
790 
791 static const struct imx355_reg mode_1280x720_regs[] = {
792 	{ 0x0112, 0x0a },
793 	{ 0x0113, 0x0a },
794 	{ 0x0114, 0x03 },
795 	{ 0x0342, 0x07 },
796 	{ 0x0343, 0x2c },
797 	{ 0x0340, 0x05 },
798 	{ 0x0341, 0x1a },
799 	{ 0x0344, 0x01 },
800 	{ 0x0345, 0x68 },
801 	{ 0x0346, 0x02 },
802 	{ 0x0347, 0x00 },
803 	{ 0x0348, 0x0b },
804 	{ 0x0349, 0x67 },
805 	{ 0x034a, 0x07 },
806 	{ 0x034b, 0x9f },
807 	{ 0x0220, 0x00 },
808 	{ 0x0222, 0x01 },
809 	{ 0x0900, 0x01 },
810 	{ 0x0901, 0x22 },
811 	{ 0x0902, 0x00 },
812 	{ 0x034c, 0x05 },
813 	{ 0x034d, 0x00 },
814 	{ 0x034e, 0x02 },
815 	{ 0x034f, 0xd0 },
816 	{ 0x0301, 0x05 },
817 	{ 0x0303, 0x01 },
818 	{ 0x0305, 0x02 },
819 	{ 0x0306, 0x00 },
820 	{ 0x0307, 0x78 },
821 	{ 0x030b, 0x01 },
822 	{ 0x030d, 0x02 },
823 	{ 0x030e, 0x00 },
824 	{ 0x030f, 0x4b },
825 	{ 0x0310, 0x00 },
826 	{ 0x0700, 0x00 },
827 	{ 0x0701, 0x10 },
828 	{ 0x0820, 0x0b },
829 	{ 0x0821, 0x40 },
830 	{ 0x3088, 0x04 },
831 	{ 0x6813, 0x02 },
832 	{ 0x6835, 0x07 },
833 	{ 0x6836, 0x01 },
834 	{ 0x6837, 0x04 },
835 	{ 0x684d, 0x07 },
836 	{ 0x684e, 0x01 },
837 	{ 0x684f, 0x04 },
838 };
839 
840 static const struct imx355_reg mode_820x616_regs[] = {
841 	{ 0x0112, 0x0a },
842 	{ 0x0113, 0x0a },
843 	{ 0x0114, 0x03 },
844 	{ 0x0342, 0x0e },
845 	{ 0x0343, 0x58 },
846 	{ 0x0340, 0x02 },
847 	{ 0x0341, 0x8c },
848 	{ 0x0344, 0x00 },
849 	{ 0x0345, 0x00 },
850 	{ 0x0346, 0x00 },
851 	{ 0x0347, 0x00 },
852 	{ 0x0348, 0x0c },
853 	{ 0x0349, 0xcf },
854 	{ 0x034a, 0x09 },
855 	{ 0x034b, 0x9f },
856 	{ 0x0220, 0x00 },
857 	{ 0x0222, 0x01 },
858 	{ 0x0900, 0x01 },
859 	{ 0x0901, 0x44 },
860 	{ 0x0902, 0x00 },
861 	{ 0x034c, 0x03 },
862 	{ 0x034d, 0x34 },
863 	{ 0x034e, 0x02 },
864 	{ 0x034f, 0x68 },
865 	{ 0x0301, 0x05 },
866 	{ 0x0303, 0x01 },
867 	{ 0x0305, 0x02 },
868 	{ 0x0306, 0x00 },
869 	{ 0x0307, 0x78 },
870 	{ 0x030b, 0x01 },
871 	{ 0x030d, 0x02 },
872 	{ 0x030e, 0x00 },
873 	{ 0x030f, 0x4b },
874 	{ 0x0310, 0x00 },
875 	{ 0x0700, 0x02 },
876 	{ 0x0701, 0x78 },
877 	{ 0x0820, 0x0b },
878 	{ 0x0821, 0x40 },
879 	{ 0x3088, 0x04 },
880 	{ 0x6813, 0x02 },
881 	{ 0x6835, 0x07 },
882 	{ 0x6836, 0x01 },
883 	{ 0x6837, 0x04 },
884 	{ 0x684d, 0x07 },
885 	{ 0x684e, 0x01 },
886 	{ 0x684f, 0x04 },
887 };
888 
889 static const char * const imx355_test_pattern_menu[] = {
890 	"Disabled",
891 	"Solid Colour",
892 	"Eight Vertical Colour Bars",
893 	"Colour Bars With Fade to Grey",
894 	"Pseudorandom Sequence (PN9)",
895 };
896 
897 /*
898  * When adding more than the one below, make sure the disallowed ones will
899  * actually be disabled in the LINK_FREQ control.
900  */
901 static const s64 link_freq_menu_items[] = {
902 	IMX355_LINK_FREQ_DEFAULT,
903 };
904 
905 /* Mode configs */
906 static const struct imx355_mode supported_modes[] = {
907 	{
908 		.width = 3280,
909 		.height = 2464,
910 		.fll_def = 2615,
911 		.fll_min = 2615,
912 		.llp = 3672,
913 		.link_freq_index = IMX355_LINK_FREQ_INDEX,
914 		.reg_list = {
915 			.num_of_regs = ARRAY_SIZE(mode_3280x2464_regs),
916 			.regs = mode_3280x2464_regs,
917 		},
918 	},
919 	{
920 		.width = 3268,
921 		.height = 2448,
922 		.fll_def = 2615,
923 		.fll_min = 2615,
924 		.llp = 3672,
925 		.link_freq_index = IMX355_LINK_FREQ_INDEX,
926 		.reg_list = {
927 			.num_of_regs = ARRAY_SIZE(mode_3268x2448_regs),
928 			.regs = mode_3268x2448_regs,
929 		},
930 	},
931 	{
932 		.width = 3264,
933 		.height = 2448,
934 		.fll_def = 2615,
935 		.fll_min = 2615,
936 		.llp = 3672,
937 		.link_freq_index = IMX355_LINK_FREQ_INDEX,
938 		.reg_list = {
939 			.num_of_regs = ARRAY_SIZE(mode_3264x2448_regs),
940 			.regs = mode_3264x2448_regs,
941 		},
942 	},
943 	{
944 		.width = 1940,
945 		.height = 1096,
946 		.fll_def = 1306,
947 		.fll_min = 1306,
948 		.llp = 3672,
949 		.link_freq_index = IMX355_LINK_FREQ_INDEX,
950 		.reg_list = {
951 			.num_of_regs = ARRAY_SIZE(mode_1940x1096_regs),
952 			.regs = mode_1940x1096_regs,
953 		},
954 	},
955 	{
956 		.width = 1936,
957 		.height = 1096,
958 		.fll_def = 1306,
959 		.fll_min = 1306,
960 		.llp = 3672,
961 		.link_freq_index = IMX355_LINK_FREQ_INDEX,
962 		.reg_list = {
963 			.num_of_regs = ARRAY_SIZE(mode_1936x1096_regs),
964 			.regs = mode_1936x1096_regs,
965 		},
966 	},
967 	{
968 		.width = 1924,
969 		.height = 1080,
970 		.fll_def = 1306,
971 		.fll_min = 1306,
972 		.llp = 3672,
973 		.link_freq_index = IMX355_LINK_FREQ_INDEX,
974 		.reg_list = {
975 			.num_of_regs = ARRAY_SIZE(mode_1924x1080_regs),
976 			.regs = mode_1924x1080_regs,
977 		},
978 	},
979 	{
980 		.width = 1920,
981 		.height = 1080,
982 		.fll_def = 1306,
983 		.fll_min = 1306,
984 		.llp = 3672,
985 		.link_freq_index = IMX355_LINK_FREQ_INDEX,
986 		.reg_list = {
987 			.num_of_regs = ARRAY_SIZE(mode_1920x1080_regs),
988 			.regs = mode_1920x1080_regs,
989 		},
990 	},
991 	{
992 		.width = 1640,
993 		.height = 1232,
994 		.fll_def = 1306,
995 		.fll_min = 1306,
996 		.llp = 1836,
997 		.link_freq_index = IMX355_LINK_FREQ_INDEX,
998 		.reg_list = {
999 			.num_of_regs = ARRAY_SIZE(mode_1640x1232_regs),
1000 			.regs = mode_1640x1232_regs,
1001 		},
1002 	},
1003 	{
1004 		.width = 1640,
1005 		.height = 922,
1006 		.fll_def = 1306,
1007 		.fll_min = 1306,
1008 		.llp = 1836,
1009 		.link_freq_index = IMX355_LINK_FREQ_INDEX,
1010 		.reg_list = {
1011 			.num_of_regs = ARRAY_SIZE(mode_1640x922_regs),
1012 			.regs = mode_1640x922_regs,
1013 		},
1014 	},
1015 	{
1016 		.width = 1300,
1017 		.height = 736,
1018 		.fll_def = 1306,
1019 		.fll_min = 1306,
1020 		.llp = 1836,
1021 		.link_freq_index = IMX355_LINK_FREQ_INDEX,
1022 		.reg_list = {
1023 			.num_of_regs = ARRAY_SIZE(mode_1300x736_regs),
1024 			.regs = mode_1300x736_regs,
1025 		},
1026 	},
1027 	{
1028 		.width = 1296,
1029 		.height = 736,
1030 		.fll_def = 1306,
1031 		.fll_min = 1306,
1032 		.llp = 1836,
1033 		.link_freq_index = IMX355_LINK_FREQ_INDEX,
1034 		.reg_list = {
1035 			.num_of_regs = ARRAY_SIZE(mode_1296x736_regs),
1036 			.regs = mode_1296x736_regs,
1037 		},
1038 	},
1039 	{
1040 		.width = 1284,
1041 		.height = 720,
1042 		.fll_def = 1306,
1043 		.fll_min = 1306,
1044 		.llp = 1836,
1045 		.link_freq_index = IMX355_LINK_FREQ_INDEX,
1046 		.reg_list = {
1047 			.num_of_regs = ARRAY_SIZE(mode_1284x720_regs),
1048 			.regs = mode_1284x720_regs,
1049 		},
1050 	},
1051 	{
1052 		.width = 1280,
1053 		.height = 720,
1054 		.fll_def = 1306,
1055 		.fll_min = 1306,
1056 		.llp = 1836,
1057 		.link_freq_index = IMX355_LINK_FREQ_INDEX,
1058 		.reg_list = {
1059 			.num_of_regs = ARRAY_SIZE(mode_1280x720_regs),
1060 			.regs = mode_1280x720_regs,
1061 		},
1062 	},
1063 	{
1064 		.width = 820,
1065 		.height = 616,
1066 		.fll_def = 652,
1067 		.fll_min = 652,
1068 		.llp = 3672,
1069 		.link_freq_index = IMX355_LINK_FREQ_INDEX,
1070 		.reg_list = {
1071 			.num_of_regs = ARRAY_SIZE(mode_820x616_regs),
1072 			.regs = mode_820x616_regs,
1073 		},
1074 	},
1075 };
1076 
1077 static inline struct imx355 *to_imx355(struct v4l2_subdev *_sd)
1078 {
1079 	return container_of(_sd, struct imx355, sd);
1080 }
1081 
1082 /* Get bayer order based on flip setting. */
1083 static u32 imx355_get_format_code(struct imx355 *imx355)
1084 {
1085 	/*
1086 	 * Only one bayer order is supported.
1087 	 * It depends on the flip settings.
1088 	 */
1089 	u32 code;
1090 	static const u32 codes[2][2] = {
1091 		{ MEDIA_BUS_FMT_SRGGB10_1X10, MEDIA_BUS_FMT_SGRBG10_1X10, },
1092 		{ MEDIA_BUS_FMT_SGBRG10_1X10, MEDIA_BUS_FMT_SBGGR10_1X10, },
1093 	};
1094 
1095 	lockdep_assert_held(&imx355->mutex);
1096 	code = codes[imx355->vflip->val][imx355->hflip->val];
1097 
1098 	return code;
1099 }
1100 
1101 /* Read registers up to 4 at a time */
1102 static int imx355_read_reg(struct imx355 *imx355, u16 reg, u32 len, u32 *val)
1103 {
1104 	struct i2c_client *client = v4l2_get_subdevdata(&imx355->sd);
1105 	struct i2c_msg msgs[2];
1106 	u8 addr_buf[2];
1107 	u8 data_buf[4] = { 0 };
1108 	int ret;
1109 
1110 	if (len > 4)
1111 		return -EINVAL;
1112 
1113 	put_unaligned_be16(reg, addr_buf);
1114 	/* Write register address */
1115 	msgs[0].addr = client->addr;
1116 	msgs[0].flags = 0;
1117 	msgs[0].len = ARRAY_SIZE(addr_buf);
1118 	msgs[0].buf = addr_buf;
1119 
1120 	/* Read data from register */
1121 	msgs[1].addr = client->addr;
1122 	msgs[1].flags = I2C_M_RD;
1123 	msgs[1].len = len;
1124 	msgs[1].buf = &data_buf[4 - len];
1125 
1126 	ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
1127 	if (ret != ARRAY_SIZE(msgs))
1128 		return -EIO;
1129 
1130 	*val = get_unaligned_be32(data_buf);
1131 
1132 	return 0;
1133 }
1134 
1135 /* Write registers up to 4 at a time */
1136 static int imx355_write_reg(struct imx355 *imx355, u16 reg, u32 len, u32 val)
1137 {
1138 	struct i2c_client *client = v4l2_get_subdevdata(&imx355->sd);
1139 	u8 buf[6];
1140 
1141 	if (len > 4)
1142 		return -EINVAL;
1143 
1144 	put_unaligned_be16(reg, buf);
1145 	put_unaligned_be32(val << (8 * (4 - len)), buf + 2);
1146 	if (i2c_master_send(client, buf, len + 2) != len + 2)
1147 		return -EIO;
1148 
1149 	return 0;
1150 }
1151 
1152 /* Write a list of registers */
1153 static int imx355_write_regs(struct imx355 *imx355,
1154 			     const struct imx355_reg *regs, u32 len)
1155 {
1156 	int ret;
1157 	u32 i;
1158 
1159 	for (i = 0; i < len; i++) {
1160 		ret = imx355_write_reg(imx355, regs[i].address, 1, regs[i].val);
1161 		if (ret) {
1162 			dev_err_ratelimited(imx355->dev,
1163 					    "write reg 0x%4.4x return err %d",
1164 					    regs[i].address, ret);
1165 
1166 			return ret;
1167 		}
1168 	}
1169 
1170 	return 0;
1171 }
1172 
1173 /* Open sub-device */
1174 static int imx355_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1175 {
1176 	struct imx355 *imx355 = to_imx355(sd);
1177 	struct v4l2_mbus_framefmt *try_fmt =
1178 		v4l2_subdev_state_get_format(fh->state, 0);
1179 
1180 	mutex_lock(&imx355->mutex);
1181 
1182 	/* Initialize try_fmt */
1183 	try_fmt->width = imx355->cur_mode->width;
1184 	try_fmt->height = imx355->cur_mode->height;
1185 	try_fmt->code = imx355_get_format_code(imx355);
1186 	try_fmt->field = V4L2_FIELD_NONE;
1187 
1188 	mutex_unlock(&imx355->mutex);
1189 
1190 	return 0;
1191 }
1192 
1193 static int imx355_set_ctrl(struct v4l2_ctrl *ctrl)
1194 {
1195 	struct imx355 *imx355 = container_of(ctrl->handler,
1196 					     struct imx355, ctrl_handler);
1197 	s64 max;
1198 	int ret;
1199 
1200 	/* Propagate change of current control to all related controls */
1201 	switch (ctrl->id) {
1202 	case V4L2_CID_VBLANK:
1203 		/* Update max exposure while meeting expected vblanking */
1204 		max = imx355->cur_mode->height + ctrl->val - 10;
1205 		__v4l2_ctrl_modify_range(imx355->exposure,
1206 					 imx355->exposure->minimum,
1207 					 max, imx355->exposure->step, max);
1208 		break;
1209 	}
1210 
1211 	/*
1212 	 * Applying V4L2 control value only happens
1213 	 * when power is up for streaming
1214 	 */
1215 	if (!pm_runtime_get_if_in_use(imx355->dev))
1216 		return 0;
1217 
1218 	switch (ctrl->id) {
1219 	case V4L2_CID_ANALOGUE_GAIN:
1220 		/* Analog gain = 1024/(1024 - ctrl->val) times */
1221 		ret = imx355_write_reg(imx355, IMX355_REG_ANALOG_GAIN, 2,
1222 				       ctrl->val);
1223 		break;
1224 	case V4L2_CID_DIGITAL_GAIN:
1225 		ret = imx355_write_reg(imx355, IMX355_REG_DIG_GAIN_GLOBAL, 2,
1226 				       ctrl->val);
1227 		break;
1228 	case V4L2_CID_EXPOSURE:
1229 		ret = imx355_write_reg(imx355, IMX355_REG_EXPOSURE, 2,
1230 				       ctrl->val);
1231 		break;
1232 	case V4L2_CID_VBLANK:
1233 		/* Update FLL that meets expected vertical blanking */
1234 		ret = imx355_write_reg(imx355, IMX355_REG_FLL, 2,
1235 				       imx355->cur_mode->height + ctrl->val);
1236 		break;
1237 	case V4L2_CID_TEST_PATTERN:
1238 		ret = imx355_write_reg(imx355, IMX355_REG_TEST_PATTERN,
1239 				       2, ctrl->val);
1240 		break;
1241 	case V4L2_CID_HFLIP:
1242 	case V4L2_CID_VFLIP:
1243 		ret = imx355_write_reg(imx355, IMX355_REG_ORIENTATION, 1,
1244 				       imx355->hflip->val |
1245 				       imx355->vflip->val << 1);
1246 		break;
1247 	default:
1248 		ret = -EINVAL;
1249 		dev_info(imx355->dev, "ctrl(id:0x%x,val:0x%x) is not handled",
1250 			 ctrl->id, ctrl->val);
1251 		break;
1252 	}
1253 
1254 	pm_runtime_put(imx355->dev);
1255 
1256 	return ret;
1257 }
1258 
1259 static const struct v4l2_ctrl_ops imx355_ctrl_ops = {
1260 	.s_ctrl = imx355_set_ctrl,
1261 };
1262 
1263 static int imx355_enum_mbus_code(struct v4l2_subdev *sd,
1264 				 struct v4l2_subdev_state *sd_state,
1265 				 struct v4l2_subdev_mbus_code_enum *code)
1266 {
1267 	struct imx355 *imx355 = to_imx355(sd);
1268 
1269 	if (code->index > 0)
1270 		return -EINVAL;
1271 
1272 	mutex_lock(&imx355->mutex);
1273 	code->code = imx355_get_format_code(imx355);
1274 	mutex_unlock(&imx355->mutex);
1275 
1276 	return 0;
1277 }
1278 
1279 static int imx355_enum_frame_size(struct v4l2_subdev *sd,
1280 				  struct v4l2_subdev_state *sd_state,
1281 				  struct v4l2_subdev_frame_size_enum *fse)
1282 {
1283 	struct imx355 *imx355 = to_imx355(sd);
1284 
1285 	if (fse->index >= ARRAY_SIZE(supported_modes))
1286 		return -EINVAL;
1287 
1288 	mutex_lock(&imx355->mutex);
1289 	if (fse->code != imx355_get_format_code(imx355)) {
1290 		mutex_unlock(&imx355->mutex);
1291 		return -EINVAL;
1292 	}
1293 	mutex_unlock(&imx355->mutex);
1294 
1295 	fse->min_width = supported_modes[fse->index].width;
1296 	fse->max_width = fse->min_width;
1297 	fse->min_height = supported_modes[fse->index].height;
1298 	fse->max_height = fse->min_height;
1299 
1300 	return 0;
1301 }
1302 
1303 static void imx355_update_pad_format(struct imx355 *imx355,
1304 				     const struct imx355_mode *mode,
1305 				     struct v4l2_subdev_format *fmt)
1306 {
1307 	fmt->format.width = mode->width;
1308 	fmt->format.height = mode->height;
1309 	fmt->format.code = imx355_get_format_code(imx355);
1310 	fmt->format.field = V4L2_FIELD_NONE;
1311 }
1312 
1313 static int imx355_do_get_pad_format(struct imx355 *imx355,
1314 				    struct v4l2_subdev_state *sd_state,
1315 				    struct v4l2_subdev_format *fmt)
1316 {
1317 	struct v4l2_mbus_framefmt *framefmt;
1318 
1319 	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1320 		framefmt = v4l2_subdev_state_get_format(sd_state, fmt->pad);
1321 		fmt->format = *framefmt;
1322 	} else {
1323 		imx355_update_pad_format(imx355, imx355->cur_mode, fmt);
1324 	}
1325 
1326 	return 0;
1327 }
1328 
1329 static int imx355_get_pad_format(struct v4l2_subdev *sd,
1330 				 struct v4l2_subdev_state *sd_state,
1331 				 struct v4l2_subdev_format *fmt)
1332 {
1333 	struct imx355 *imx355 = to_imx355(sd);
1334 	int ret;
1335 
1336 	mutex_lock(&imx355->mutex);
1337 	ret = imx355_do_get_pad_format(imx355, sd_state, fmt);
1338 	mutex_unlock(&imx355->mutex);
1339 
1340 	return ret;
1341 }
1342 
1343 static int
1344 imx355_set_pad_format(struct v4l2_subdev *sd,
1345 		      struct v4l2_subdev_state *sd_state,
1346 		      struct v4l2_subdev_format *fmt)
1347 {
1348 	struct imx355 *imx355 = to_imx355(sd);
1349 	const struct imx355_mode *mode;
1350 	struct v4l2_mbus_framefmt *framefmt;
1351 	s32 vblank_def;
1352 	s32 vblank_min;
1353 	s64 h_blank;
1354 	u64 pixel_rate;
1355 	u32 height;
1356 
1357 	mutex_lock(&imx355->mutex);
1358 
1359 	/*
1360 	 * Only one bayer order is supported.
1361 	 * It depends on the flip settings.
1362 	 */
1363 	fmt->format.code = imx355_get_format_code(imx355);
1364 
1365 	mode = v4l2_find_nearest_size(supported_modes,
1366 				      ARRAY_SIZE(supported_modes),
1367 				      width, height,
1368 				      fmt->format.width, fmt->format.height);
1369 	imx355_update_pad_format(imx355, mode, fmt);
1370 	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1371 		framefmt = v4l2_subdev_state_get_format(sd_state, fmt->pad);
1372 		*framefmt = fmt->format;
1373 	} else {
1374 		imx355->cur_mode = mode;
1375 		pixel_rate = IMX355_LINK_FREQ_DEFAULT * 2 * 4;
1376 		do_div(pixel_rate, 10);
1377 		__v4l2_ctrl_s_ctrl_int64(imx355->pixel_rate, pixel_rate);
1378 		/* Update limits and set FPS to default */
1379 		height = imx355->cur_mode->height;
1380 		vblank_def = imx355->cur_mode->fll_def - height;
1381 		vblank_min = imx355->cur_mode->fll_min - height;
1382 		height = IMX355_FLL_MAX - height;
1383 		__v4l2_ctrl_modify_range(imx355->vblank, vblank_min, height, 1,
1384 					 vblank_def);
1385 		__v4l2_ctrl_s_ctrl(imx355->vblank, vblank_def);
1386 		h_blank = mode->llp - imx355->cur_mode->width;
1387 		/*
1388 		 * Currently hblank is not changeable.
1389 		 * So FPS control is done only by vblank.
1390 		 */
1391 		__v4l2_ctrl_modify_range(imx355->hblank, h_blank,
1392 					 h_blank, 1, h_blank);
1393 	}
1394 
1395 	mutex_unlock(&imx355->mutex);
1396 
1397 	return 0;
1398 }
1399 
1400 /* Start streaming */
1401 static int imx355_start_streaming(struct imx355 *imx355)
1402 {
1403 	const struct imx355_reg_list *reg_list;
1404 	int ret;
1405 
1406 	/* Global Setting */
1407 	reg_list = &imx355_global_setting;
1408 	ret = imx355_write_regs(imx355, reg_list->regs, reg_list->num_of_regs);
1409 	if (ret) {
1410 		dev_err(imx355->dev, "failed to set global settings");
1411 		return ret;
1412 	}
1413 
1414 	/* Apply default values of current mode */
1415 	reg_list = &imx355->cur_mode->reg_list;
1416 	ret = imx355_write_regs(imx355, reg_list->regs, reg_list->num_of_regs);
1417 	if (ret) {
1418 		dev_err(imx355->dev, "failed to set mode");
1419 		return ret;
1420 	}
1421 
1422 	/* set digital gain control to all color mode */
1423 	ret = imx355_write_reg(imx355, IMX355_REG_DPGA_USE_GLOBAL_GAIN, 1, 1);
1424 	if (ret)
1425 		return ret;
1426 
1427 	/* Apply customized values from user */
1428 	ret =  __v4l2_ctrl_handler_setup(imx355->sd.ctrl_handler);
1429 	if (ret)
1430 		return ret;
1431 
1432 	return imx355_write_reg(imx355, IMX355_REG_MODE_SELECT,
1433 				1, IMX355_MODE_STREAMING);
1434 }
1435 
1436 /* Stop streaming */
1437 static int imx355_stop_streaming(struct imx355 *imx355)
1438 {
1439 	return imx355_write_reg(imx355, IMX355_REG_MODE_SELECT,
1440 				1, IMX355_MODE_STANDBY);
1441 }
1442 
1443 static int imx355_set_stream(struct v4l2_subdev *sd, int enable)
1444 {
1445 	struct imx355 *imx355 = to_imx355(sd);
1446 	int ret = 0;
1447 
1448 	mutex_lock(&imx355->mutex);
1449 
1450 	if (enable) {
1451 		ret = pm_runtime_resume_and_get(imx355->dev);
1452 		if (ret < 0)
1453 			goto err_unlock;
1454 
1455 		/*
1456 		 * Apply default & customized values
1457 		 * and then start streaming.
1458 		 */
1459 		ret = imx355_start_streaming(imx355);
1460 		if (ret)
1461 			goto err_rpm_put;
1462 	} else {
1463 		imx355_stop_streaming(imx355);
1464 		pm_runtime_put(imx355->dev);
1465 	}
1466 
1467 	/* vflip and hflip cannot change during streaming */
1468 	__v4l2_ctrl_grab(imx355->vflip, enable);
1469 	__v4l2_ctrl_grab(imx355->hflip, enable);
1470 
1471 	mutex_unlock(&imx355->mutex);
1472 
1473 	return ret;
1474 
1475 err_rpm_put:
1476 	pm_runtime_put(imx355->dev);
1477 err_unlock:
1478 	mutex_unlock(&imx355->mutex);
1479 
1480 	return ret;
1481 }
1482 
1483 /* Verify chip ID */
1484 static int imx355_identify_module(struct imx355 *imx355)
1485 {
1486 	int ret;
1487 	u32 val;
1488 
1489 	ret = imx355_read_reg(imx355, IMX355_REG_CHIP_ID, 2, &val);
1490 	if (ret)
1491 		return ret;
1492 
1493 	if (val != IMX355_CHIP_ID) {
1494 		dev_err(imx355->dev, "chip id mismatch: %x!=%x",
1495 			IMX355_CHIP_ID, val);
1496 		return -EIO;
1497 	}
1498 	return 0;
1499 }
1500 
1501 static const struct v4l2_subdev_core_ops imx355_subdev_core_ops = {
1502 	.subscribe_event = v4l2_ctrl_subdev_subscribe_event,
1503 	.unsubscribe_event = v4l2_event_subdev_unsubscribe,
1504 };
1505 
1506 static const struct v4l2_subdev_video_ops imx355_video_ops = {
1507 	.s_stream = imx355_set_stream,
1508 };
1509 
1510 static const struct v4l2_subdev_pad_ops imx355_pad_ops = {
1511 	.enum_mbus_code = imx355_enum_mbus_code,
1512 	.get_fmt = imx355_get_pad_format,
1513 	.set_fmt = imx355_set_pad_format,
1514 	.enum_frame_size = imx355_enum_frame_size,
1515 };
1516 
1517 static const struct v4l2_subdev_ops imx355_subdev_ops = {
1518 	.core = &imx355_subdev_core_ops,
1519 	.video = &imx355_video_ops,
1520 	.pad = &imx355_pad_ops,
1521 };
1522 
1523 static const struct media_entity_operations imx355_subdev_entity_ops = {
1524 	.link_validate = v4l2_subdev_link_validate,
1525 };
1526 
1527 static const struct v4l2_subdev_internal_ops imx355_internal_ops = {
1528 	.open = imx355_open,
1529 };
1530 
1531 static int imx355_power_off(struct device *dev)
1532 {
1533 	struct i2c_client *client = container_of(dev, struct i2c_client, dev);
1534 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1535 	struct imx355 *imx355 = to_imx355(sd);
1536 
1537 	gpiod_set_value_cansleep(imx355->reset_gpio, 1);
1538 
1539 	regulator_bulk_disable(ARRAY_SIZE(imx355_supplies), imx355->supplies);
1540 	clk_disable_unprepare(imx355->clk);
1541 
1542 	return 0;
1543 }
1544 
1545 static int imx355_power_on(struct device *dev)
1546 {
1547 	struct i2c_client *client = container_of(dev, struct i2c_client, dev);
1548 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1549 	struct imx355 *imx355 = to_imx355(sd);
1550 	int ret;
1551 
1552 	ret = clk_prepare_enable(imx355->clk);
1553 	if (ret)
1554 		return dev_err_probe(dev, ret, "failed to enable clocks");
1555 
1556 	ret = regulator_bulk_enable(ARRAY_SIZE(imx355_supplies),
1557 				    imx355->supplies);
1558 	if (ret) {
1559 		dev_err_probe(dev, ret, "failed to enable regulators");
1560 		goto error_disable_clocks;
1561 	}
1562 
1563 	usleep_range(1000, 2000);
1564 	gpiod_set_value_cansleep(imx355->reset_gpio, 0);
1565 	usleep_range(10000, 11000);
1566 
1567 	return 0;
1568 
1569 error_disable_clocks:
1570 	clk_disable_unprepare(imx355->clk);
1571 	return ret;
1572 }
1573 
1574 static DEFINE_RUNTIME_DEV_PM_OPS(imx355_pm_ops, imx355_power_off,
1575 				 imx355_power_on, NULL);
1576 
1577 /* Initialize control handlers */
1578 static int imx355_init_controls(struct imx355 *imx355)
1579 {
1580 	struct v4l2_fwnode_device_properties props;
1581 	struct v4l2_ctrl_handler *ctrl_hdlr;
1582 	s64 exposure_max;
1583 	s64 vblank_def;
1584 	s64 vblank_min;
1585 	s64 hblank;
1586 	u64 pixel_rate;
1587 	const struct imx355_mode *mode;
1588 	u32 max;
1589 	int ret;
1590 
1591 	ctrl_hdlr = &imx355->ctrl_handler;
1592 	ret = v4l2_ctrl_handler_init(ctrl_hdlr, 12);
1593 	if (ret)
1594 		return ret;
1595 
1596 	ctrl_hdlr->lock = &imx355->mutex;
1597 	max = ARRAY_SIZE(link_freq_menu_items) - 1;
1598 	imx355->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &imx355_ctrl_ops,
1599 						   V4L2_CID_LINK_FREQ, max, 0,
1600 						   link_freq_menu_items);
1601 	if (imx355->link_freq)
1602 		imx355->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1603 
1604 	/* pixel_rate = link_freq * 2 * nr_of_lanes / bits_per_sample */
1605 	pixel_rate = IMX355_LINK_FREQ_DEFAULT * 2 * 4;
1606 	do_div(pixel_rate, 10);
1607 	/* By default, PIXEL_RATE is read only */
1608 	imx355->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &imx355_ctrl_ops,
1609 					       V4L2_CID_PIXEL_RATE, pixel_rate,
1610 					       pixel_rate, 1, pixel_rate);
1611 
1612 	/* Initialize vblank/hblank/exposure parameters based on current mode */
1613 	mode = imx355->cur_mode;
1614 	vblank_def = mode->fll_def - mode->height;
1615 	vblank_min = mode->fll_min - mode->height;
1616 	imx355->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx355_ctrl_ops,
1617 					   V4L2_CID_VBLANK, vblank_min,
1618 					   IMX355_FLL_MAX - mode->height,
1619 					   1, vblank_def);
1620 
1621 	hblank = mode->llp - mode->width;
1622 	imx355->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx355_ctrl_ops,
1623 					   V4L2_CID_HBLANK, hblank, hblank,
1624 					   1, hblank);
1625 	if (imx355->hblank)
1626 		imx355->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1627 
1628 	/* fll >= exposure time + adjust parameter (default value is 10) */
1629 	exposure_max = mode->fll_def - 10;
1630 	imx355->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &imx355_ctrl_ops,
1631 					     V4L2_CID_EXPOSURE,
1632 					     IMX355_EXPOSURE_MIN, exposure_max,
1633 					     IMX355_EXPOSURE_STEP,
1634 					     IMX355_EXPOSURE_DEFAULT);
1635 
1636 	imx355->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx355_ctrl_ops,
1637 					  V4L2_CID_HFLIP, 0, 1, 1, 0);
1638 	if (imx355->hflip)
1639 		imx355->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
1640 	imx355->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx355_ctrl_ops,
1641 					  V4L2_CID_VFLIP, 0, 1, 1, 0);
1642 	if (imx355->vflip)
1643 		imx355->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
1644 
1645 	v4l2_ctrl_new_std(ctrl_hdlr, &imx355_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
1646 			  IMX355_ANA_GAIN_MIN, IMX355_ANA_GAIN_MAX,
1647 			  IMX355_ANA_GAIN_STEP, IMX355_ANA_GAIN_DEFAULT);
1648 
1649 	/* Digital gain */
1650 	v4l2_ctrl_new_std(ctrl_hdlr, &imx355_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
1651 			  IMX355_DGTL_GAIN_MIN, IMX355_DGTL_GAIN_MAX,
1652 			  IMX355_DGTL_GAIN_STEP, IMX355_DGTL_GAIN_DEFAULT);
1653 
1654 	v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &imx355_ctrl_ops,
1655 				     V4L2_CID_TEST_PATTERN,
1656 				     ARRAY_SIZE(imx355_test_pattern_menu) - 1,
1657 				     0, 0, imx355_test_pattern_menu);
1658 	if (ctrl_hdlr->error) {
1659 		ret = ctrl_hdlr->error;
1660 		dev_err(imx355->dev, "control init failed: %d", ret);
1661 		goto error;
1662 	}
1663 
1664 	ret = v4l2_fwnode_device_parse(imx355->dev, &props);
1665 	if (ret)
1666 		goto error;
1667 
1668 	ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &imx355_ctrl_ops,
1669 					      &props);
1670 	if (ret)
1671 		goto error;
1672 
1673 	imx355->sd.ctrl_handler = ctrl_hdlr;
1674 
1675 	return 0;
1676 
1677 error:
1678 	v4l2_ctrl_handler_free(ctrl_hdlr);
1679 
1680 	return ret;
1681 }
1682 
1683 static struct imx355_hwcfg *imx355_get_hwcfg(struct device *dev)
1684 {
1685 	struct imx355_hwcfg *cfg;
1686 	struct v4l2_fwnode_endpoint bus_cfg = {
1687 		.bus_type = V4L2_MBUS_CSI2_DPHY
1688 	};
1689 	struct fwnode_handle *ep;
1690 	struct fwnode_handle *fwnode = dev_fwnode(dev);
1691 	int ret;
1692 
1693 	if (!fwnode)
1694 		return NULL;
1695 
1696 	ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
1697 	if (!ep)
1698 		return NULL;
1699 
1700 	ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
1701 	if (ret)
1702 		goto out_err;
1703 
1704 	cfg = devm_kzalloc(dev, sizeof(*cfg), GFP_KERNEL);
1705 	if (!cfg)
1706 		goto out_err;
1707 
1708 	ret = v4l2_link_freq_to_bitmap(dev, bus_cfg.link_frequencies,
1709 				       bus_cfg.nr_of_link_frequencies,
1710 				       link_freq_menu_items,
1711 				       ARRAY_SIZE(link_freq_menu_items),
1712 				       &cfg->link_freq_bitmap);
1713 	if (ret)
1714 		goto out_err;
1715 
1716 	v4l2_fwnode_endpoint_free(&bus_cfg);
1717 	fwnode_handle_put(ep);
1718 	return cfg;
1719 
1720 out_err:
1721 	v4l2_fwnode_endpoint_free(&bus_cfg);
1722 	fwnode_handle_put(ep);
1723 	return NULL;
1724 }
1725 
1726 static int imx355_probe(struct i2c_client *client)
1727 {
1728 	struct imx355 *imx355;
1729 	unsigned long freq;
1730 	int ret;
1731 
1732 	imx355 = devm_kzalloc(&client->dev, sizeof(*imx355), GFP_KERNEL);
1733 	if (!imx355)
1734 		return -ENOMEM;
1735 
1736 	imx355->dev = &client->dev;
1737 
1738 	mutex_init(&imx355->mutex);
1739 
1740 	imx355->clk = devm_v4l2_sensor_clk_get(imx355->dev, NULL);
1741 	if (IS_ERR(imx355->clk))
1742 		return dev_err_probe(imx355->dev, PTR_ERR(imx355->clk),
1743 				     "failed to get clock\n");
1744 
1745 	freq = clk_get_rate(imx355->clk);
1746 	if (freq != IMX355_EXT_CLK)
1747 		return dev_err_probe(imx355->dev, -EINVAL,
1748 				     "external clock %lu is not supported\n",
1749 				     freq);
1750 
1751 	ret = devm_regulator_bulk_get_const(imx355->dev,
1752 					    ARRAY_SIZE(imx355_supplies),
1753 					    imx355_supplies,
1754 					    &imx355->supplies);
1755 	if (ret) {
1756 		dev_err_probe(imx355->dev, ret, "could not get regulators");
1757 		goto error_probe;
1758 	}
1759 
1760 	imx355->reset_gpio = devm_gpiod_get_optional(imx355->dev, "reset",
1761 						     GPIOD_OUT_HIGH);
1762 	if (IS_ERR(imx355->reset_gpio)) {
1763 		ret = dev_err_probe(imx355->dev, PTR_ERR(imx355->reset_gpio),
1764 				    "failed to get gpios");
1765 		goto error_probe;
1766 	}
1767 
1768 	/* Initialize subdev */
1769 	v4l2_i2c_subdev_init(&imx355->sd, client, &imx355_subdev_ops);
1770 
1771 	imx355->hwcfg = imx355_get_hwcfg(imx355->dev);
1772 	if (!imx355->hwcfg) {
1773 		dev_err(imx355->dev, "failed to get hwcfg");
1774 		ret = -ENODEV;
1775 		goto error_probe;
1776 	}
1777 
1778 	ret = imx355_power_on(imx355->dev);
1779 	if (ret)
1780 		goto error_probe;
1781 
1782 	/* Check module identity */
1783 	ret = imx355_identify_module(imx355);
1784 	if (ret) {
1785 		dev_err(imx355->dev, "failed to find sensor: %d", ret);
1786 		goto error_power_off;
1787 	}
1788 
1789 	/* Set default mode to max resolution */
1790 	imx355->cur_mode = &supported_modes[0];
1791 
1792 	ret = imx355_init_controls(imx355);
1793 	if (ret) {
1794 		dev_err(imx355->dev, "failed to init controls: %d", ret);
1795 		goto error_power_off;
1796 	}
1797 
1798 	/* Initialize subdev */
1799 	imx355->sd.internal_ops = &imx355_internal_ops;
1800 	imx355->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1801 		V4L2_SUBDEV_FL_HAS_EVENTS;
1802 	imx355->sd.entity.ops = &imx355_subdev_entity_ops;
1803 	imx355->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1804 
1805 	/* Initialize source pad */
1806 	imx355->pad.flags = MEDIA_PAD_FL_SOURCE;
1807 	ret = media_entity_pads_init(&imx355->sd.entity, 1, &imx355->pad);
1808 	if (ret) {
1809 		dev_err(imx355->dev, "failed to init entity pads: %d", ret);
1810 		goto error_handler_free;
1811 	}
1812 
1813 	/*
1814 	 * Device is already turned on by i2c-core with ACPI domain PM.
1815 	 * Enable runtime PM and turn off the device.
1816 	 */
1817 	pm_runtime_set_active(imx355->dev);
1818 	pm_runtime_enable(imx355->dev);
1819 	pm_runtime_idle(imx355->dev);
1820 
1821 	ret = v4l2_async_register_subdev_sensor(&imx355->sd);
1822 	if (ret < 0)
1823 		goto error_media_entity_runtime_pm;
1824 
1825 	return 0;
1826 
1827 error_media_entity_runtime_pm:
1828 	pm_runtime_disable(imx355->dev);
1829 	pm_runtime_set_suspended(imx355->dev);
1830 	media_entity_cleanup(&imx355->sd.entity);
1831 
1832 error_handler_free:
1833 	v4l2_ctrl_handler_free(imx355->sd.ctrl_handler);
1834 
1835 error_power_off:
1836 	imx355_power_off(imx355->dev);
1837 
1838 error_probe:
1839 	mutex_destroy(&imx355->mutex);
1840 
1841 	return ret;
1842 }
1843 
1844 static void imx355_remove(struct i2c_client *client)
1845 {
1846 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1847 	struct imx355 *imx355 = to_imx355(sd);
1848 
1849 	v4l2_async_unregister_subdev(sd);
1850 	media_entity_cleanup(&sd->entity);
1851 	v4l2_ctrl_handler_free(sd->ctrl_handler);
1852 
1853 	pm_runtime_disable(imx355->dev);
1854 
1855 	if (!pm_runtime_status_suspended(imx355->dev)) {
1856 		imx355_power_off(imx355->dev);
1857 		pm_runtime_set_suspended(imx355->dev);
1858 	}
1859 
1860 	mutex_destroy(&imx355->mutex);
1861 }
1862 
1863 static const struct acpi_device_id imx355_acpi_ids[] __maybe_unused = {
1864 	{ "SONY355A" },
1865 	{ /* sentinel */ }
1866 };
1867 MODULE_DEVICE_TABLE(acpi, imx355_acpi_ids);
1868 
1869 static const struct of_device_id imx355_match_table[] = {
1870 	{ .compatible = "sony,imx355", },
1871 	{ /* sentinel */ }
1872 };
1873 MODULE_DEVICE_TABLE(of, imx355_match_table);
1874 
1875 static struct i2c_driver imx355_i2c_driver = {
1876 	.driver = {
1877 		.name = "imx355",
1878 		.acpi_match_table = ACPI_PTR(imx355_acpi_ids),
1879 		.of_match_table = imx355_match_table,
1880 		.pm = &imx355_pm_ops,
1881 	},
1882 	.probe = imx355_probe,
1883 	.remove = imx355_remove,
1884 };
1885 module_i2c_driver(imx355_i2c_driver);
1886 
1887 MODULE_AUTHOR("Qiu, Tianshu <tian.shu.qiu@intel.com>");
1888 MODULE_AUTHOR("Rapolu, Chiranjeevi");
1889 MODULE_AUTHOR("Bingbu Cao <bingbu.cao@intel.com>");
1890 MODULE_AUTHOR("Yang, Hyungwoo");
1891 MODULE_DESCRIPTION("Sony imx355 sensor driver");
1892 MODULE_LICENSE("GPL v2");
1893