1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (C) 2018 Intel Corporation 3 4 #include <linux/acpi.h> 5 #include <linux/clk.h> 6 #include <linux/delay.h> 7 #include <linux/gpio/consumer.h> 8 #include <linux/i2c.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/regmap.h> 13 #include <linux/regulator/consumer.h> 14 #include <linux/unaligned.h> 15 16 #include <media/v4l2-cci.h> 17 #include <media/v4l2-ctrls.h> 18 #include <media/v4l2-device.h> 19 #include <media/v4l2-event.h> 20 #include <media/v4l2-fwnode.h> 21 22 #define IMX355_REG_MODE_SELECT CCI_REG8(0x0100) 23 #define IMX355_MODE_STANDBY 0x00 24 #define IMX355_MODE_STREAMING 0x01 25 26 /* Chip ID */ 27 #define IMX355_REG_CHIP_ID CCI_REG16(0x0016) 28 #define IMX355_CHIP_ID 0x0355 29 30 #define IMX355_REG_LANE_SEL CCI_REG8(0x0114) 31 32 /* PLL registers that depend on the external clock frequency */ 33 #define IMX355_REG_EXTCLK_FREQ CCI_REG16(0x0136) 34 #define IMX355_REG_PLL_OP_PREDIV CCI_REG8(0x030d) 35 #define IMX355_REG_PLL_OP_MUL CCI_REG16(0x030e) 36 #define IMX355_REG_PLL_IVT_PCK_DIV CCI_REG8(0x0301) 37 #define IMX355_REG_PLL_IVT_SYSCK_DIV CCI_REG8(0x0303) 38 #define IMX355_PLL_OP_PREDIV 2 39 #define IMX355_PLL_IVT_PCK_DIV 5 40 41 /* V_TIMING internal */ 42 #define IMX355_REG_FLL CCI_REG16(0x0340) 43 #define IMX355_FLL_MAX 0xffff 44 #define IMX355_VBLANK_MIN 20 45 46 #define IMX355_REG_LLP CCI_REG16(0x0342) 47 #define IMX355_LLP_MAX 0xffff 48 49 #define IMX355_REG_X_ADD_START CCI_REG16(0x0344) 50 #define IMX355_REG_Y_ADD_START CCI_REG16(0x0346) 51 #define IMX355_REG_X_ADD_END CCI_REG16(0x0348) 52 #define IMX355_REG_Y_ADD_END CCI_REG16(0x034a) 53 #define IMX355_REG_X_OUT_SIZE CCI_REG16(0x034c) 54 #define IMX355_REG_Y_OUT_SIZE CCI_REG16(0x034e) 55 56 /* Exposure control */ 57 #define IMX355_REG_EXPOSURE CCI_REG16(0x0202) 58 #define IMX355_EXPOSURE_MIN 1 59 #define IMX355_EXPOSURE_STEP 1 60 #define IMX355_EXPOSURE_DEFAULT 0x0282 61 #define IMX355_EXPOSURE_OFFSET 10 62 63 /* Analog gain control */ 64 #define IMX355_REG_ANALOG_GAIN CCI_REG16(0x0204) 65 #define IMX355_ANA_GAIN_MIN 0 66 #define IMX355_ANA_GAIN_MAX 960 67 #define IMX355_ANA_GAIN_STEP 1 68 #define IMX355_ANA_GAIN_DEFAULT 0 69 70 /* Digital gain control */ 71 #define IMX355_REG_DPGA_USE_GLOBAL_GAIN CCI_REG8(0x3070) 72 #define IMX355_REG_DIG_GAIN_GLOBAL CCI_REG16(0x020e) 73 #define IMX355_DGTL_GAIN_MIN 256 74 #define IMX355_DGTL_GAIN_MAX 4095 75 #define IMX355_DGTL_GAIN_STEP 1 76 #define IMX355_DGTL_GAIN_DEFAULT 256 77 78 /* Test Pattern Control */ 79 #define IMX355_REG_TEST_PATTERN CCI_REG16(0x0600) 80 #define IMX355_TEST_PATTERN_DISABLED 0 81 #define IMX355_TEST_PATTERN_SOLID_COLOR 1 82 #define IMX355_TEST_PATTERN_COLOR_BARS 2 83 #define IMX355_TEST_PATTERN_GRAY_COLOR_BARS 3 84 #define IMX355_TEST_PATTERN_PN9 4 85 86 #define IMX355_REG_REQ_LINK_BIT_RATE CCI_REG16(0x0820) 87 88 #define IMX355_REG_BINNING_MODE CCI_REG8(0x0900) 89 #define IMX355_REG_BINNING_TYPE CCI_REG8(0x0901) 90 #define IMX355_REG_BINNING_WEIGHTING CCI_REG8(0x0902) 91 92 /* Flip Control */ 93 #define IMX355_REG_ORIENTATION CCI_REG8(0x0101) 94 95 #define IMX355_PIXEL_ARRAY_TOP 0 96 #define IMX355_PIXEL_ARRAY_LEFT 0 97 #define IMX355_PIXEL_ARRAY_WIDTH 3280 98 #define IMX355_PIXEL_ARRAY_HEIGHT 2464 99 100 struct imx355_reg_list { 101 u32 num_of_regs; 102 const struct cci_reg_sequence *regs; 103 }; 104 105 /* Mode : resolution and related config&values */ 106 struct imx355_mode { 107 /* Frame width */ 108 u32 width; 109 /* Frame height */ 110 u32 height; 111 struct v4l2_rect crop; 112 113 /* V-timing */ 114 u32 fll_def; 115 116 /* H-timing */ 117 u32 llp; 118 119 /* Default register values */ 120 struct imx355_reg_list reg_list; 121 }; 122 123 struct imx355_clk_params { 124 u32 ext_clk; 125 u16 extclk_freq; /* External clock (MHz) in 8.8 fixed point) */ 126 u16 pll_op_mpy[2]; /* OP system PLL multiplier */ 127 u8 pll_op_prediv[2]; /* OP system pre PLL d */ 128 }; 129 130 /* 131 * The clock tree is in single PLL mode, so PREDIV_VT and MPY_IVT do nothing. 132 * In 4 lane mode the MIPI rate is 360Mhz (720Mbit/s) and pixel rate is 133 * 288MPix/s. 134 * In 2 lane mode the MIPI rate is 444MHz (888Mbit/s) and pixel rate 135 * 177.6MPix/s with a 24MHz clock, and 441.6MHz (883.2Mbit/s) and 176.6MPix/s 136 * with a 19.2MHz clock. 137 */ 138 static const struct imx355_clk_params imx355_clk_params[] = { 139 { 140 .ext_clk = 19200000, 141 .extclk_freq = 0x1333, 142 .pll_op_mpy = { 75, 92 }, 143 .pll_op_prediv = { 2, 2 } 144 }, 145 { 146 .ext_clk = 24000000, 147 .extclk_freq = 0x1800, 148 .pll_op_mpy = { 60, 111 }, 149 .pll_op_prediv = { 2, 3 } 150 }, 151 }; 152 153 struct imx355_hwcfg { 154 s64 link_freq_menu; 155 unsigned long link_freq_bitmap; 156 unsigned int num_lanes; 157 }; 158 159 struct imx355 { 160 struct device *dev; 161 struct clk *clk; 162 struct regmap *regmap; 163 164 struct v4l2_subdev sd; 165 struct media_pad pad; 166 167 struct v4l2_ctrl_handler ctrl_handler; 168 /* V4L2 Controls */ 169 struct v4l2_ctrl *link_freq; 170 struct v4l2_ctrl *vblank; 171 struct v4l2_ctrl *hblank; 172 struct v4l2_ctrl *exposure; 173 struct v4l2_ctrl *vflip; 174 struct v4l2_ctrl *hflip; 175 176 struct imx355_hwcfg *hwcfg; 177 const struct imx355_clk_params *clk_params; 178 179 struct gpio_desc *reset_gpio; 180 struct regulator_bulk_data *supplies; 181 }; 182 183 static const struct regulator_bulk_data imx355_supplies[] = { 184 { .supply = "avdd" }, 185 { .supply = "dvdd" }, 186 { .supply = "dovdd" }, 187 }; 188 189 static const struct cci_reg_sequence imx355_global_regs[] = { 190 { CCI_REG8(0x304e), 0x03 }, 191 { CCI_REG8(0x4348), 0x16 }, 192 { CCI_REG8(0x4350), 0x19 }, 193 { CCI_REG8(0x4408), 0x0a }, 194 { CCI_REG8(0x440c), 0x0b }, 195 { CCI_REG8(0x4411), 0x5f }, 196 { CCI_REG8(0x4412), 0x2c }, 197 { CCI_REG8(0x4623), 0x00 }, 198 { CCI_REG8(0x462c), 0x0f }, 199 { CCI_REG8(0x462d), 0x00 }, 200 { CCI_REG8(0x462e), 0x00 }, 201 { CCI_REG8(0x4684), 0x54 }, 202 { CCI_REG8(0x480a), 0x07 }, 203 { CCI_REG8(0x4908), 0x07 }, 204 { CCI_REG8(0x4909), 0x07 }, 205 { CCI_REG8(0x490d), 0x0a }, 206 { CCI_REG8(0x491e), 0x0f }, 207 { CCI_REG8(0x4921), 0x06 }, 208 { CCI_REG8(0x4923), 0x28 }, 209 { CCI_REG8(0x4924), 0x28 }, 210 { CCI_REG8(0x4925), 0x29 }, 211 { CCI_REG8(0x4926), 0x29 }, 212 { CCI_REG8(0x4927), 0x1f }, 213 { CCI_REG8(0x4928), 0x20 }, 214 { CCI_REG8(0x4929), 0x20 }, 215 { CCI_REG8(0x492a), 0x20 }, 216 { CCI_REG8(0x492c), 0x05 }, 217 { CCI_REG8(0x492d), 0x06 }, 218 { CCI_REG8(0x492e), 0x06 }, 219 { CCI_REG8(0x492f), 0x06 }, 220 { CCI_REG8(0x4930), 0x03 }, 221 { CCI_REG8(0x4931), 0x04 }, 222 { CCI_REG8(0x4932), 0x04 }, 223 { CCI_REG8(0x4933), 0x05 }, 224 { CCI_REG8(0x595e), 0x01 }, 225 { CCI_REG8(0x5963), 0x01 }, 226 { CCI_REG8(0x3030), 0x01 }, 227 { CCI_REG8(0x3031), 0x01 }, 228 { CCI_REG8(0x3045), 0x01 }, 229 { CCI_REG8(0x4010), 0x00 }, 230 { CCI_REG8(0x4011), 0x00 }, 231 { CCI_REG8(0x4012), 0x00 }, 232 { CCI_REG8(0x4013), 0x01 }, 233 { CCI_REG8(0x68a8), 0xfe }, 234 { CCI_REG8(0x68a9), 0xff }, 235 { CCI_REG8(0x6888), 0x00 }, 236 { CCI_REG8(0x6889), 0x00 }, 237 { CCI_REG8(0x68b0), 0x00 }, 238 { CCI_REG8(0x3058), 0x00 }, 239 { CCI_REG8(0x305a), 0x00 }, 240 { CCI_REG8(0x0112), 0x0a }, 241 { CCI_REG8(0x0113), 0x0a }, 242 { IMX355_REG_PLL_IVT_PCK_DIV, IMX355_PLL_IVT_PCK_DIV }, 243 { CCI_REG8(0x0303), 0x01 }, 244 { CCI_REG8(0x0305), 0x02 }, 245 { CCI_REG8(0x0306), 0x00 }, 246 { CCI_REG8(0x0307), 0x78 }, 247 { CCI_REG8(0x030b), 0x01 }, 248 { IMX355_REG_PLL_OP_PREDIV, IMX355_PLL_OP_PREDIV }, 249 { CCI_REG8(0x0310), 0x00 }, 250 { CCI_REG8(0x0220), 0x00 }, 251 { CCI_REG8(0x0222), 0x01 }, 252 { CCI_REG8(0x3088), 0x04 }, 253 { CCI_REG8(0x6813), 0x02 }, 254 { CCI_REG8(0x6835), 0x07 }, 255 { CCI_REG8(0x6836), 0x01 }, 256 { CCI_REG8(0x6837), 0x04 }, 257 { CCI_REG8(0x684d), 0x07 }, 258 { CCI_REG8(0x684e), 0x01 }, 259 { CCI_REG8(0x684f), 0x04 }, 260 }; 261 262 static const struct cci_reg_sequence mode_3268x2448_regs[] = { 263 { CCI_REG8(0x0700), 0x00 }, 264 { CCI_REG8(0x0701), 0x10 }, 265 }; 266 267 static const struct cci_reg_sequence mode_3264x2448_regs[] = { 268 { CCI_REG8(0x0700), 0x00 }, 269 { CCI_REG8(0x0701), 0x10 }, 270 }; 271 272 static const struct cci_reg_sequence mode_3280x2464_regs[] = { 273 { CCI_REG8(0x0700), 0x00 }, 274 { CCI_REG8(0x0701), 0x10 }, 275 }; 276 277 static const struct cci_reg_sequence mode_1940x1096_regs[] = { 278 { CCI_REG8(0x0700), 0x00 }, 279 { CCI_REG8(0x0701), 0x10 }, 280 }; 281 282 static const struct cci_reg_sequence mode_1936x1096_regs[] = { 283 { CCI_REG8(0x0700), 0x00 }, 284 { CCI_REG8(0x0701), 0x10 }, 285 }; 286 287 static const struct cci_reg_sequence mode_1924x1080_regs[] = { 288 { CCI_REG8(0x0700), 0x00 }, 289 { CCI_REG8(0x0701), 0x10 }, 290 }; 291 292 static const struct cci_reg_sequence mode_1920x1080_regs[] = { 293 { CCI_REG8(0x0700), 0x00 }, 294 { CCI_REG8(0x0701), 0x10 }, 295 }; 296 297 static const struct cci_reg_sequence mode_1640x1232_regs[] = { 298 { CCI_REG8(0x0700), 0x00 }, 299 { CCI_REG8(0x0701), 0x10 }, 300 }; 301 302 static const struct cci_reg_sequence mode_1640x922_regs[] = { 303 { CCI_REG8(0x0700), 0x00 }, 304 { CCI_REG8(0x0701), 0x10 }, 305 }; 306 307 static const struct cci_reg_sequence mode_1300x736_regs[] = { 308 { CCI_REG8(0x0700), 0x00 }, 309 { CCI_REG8(0x0701), 0x10 }, 310 }; 311 312 static const struct cci_reg_sequence mode_1296x736_regs[] = { 313 { CCI_REG8(0x0700), 0x00 }, 314 { CCI_REG8(0x0701), 0x10 }, 315 }; 316 317 static const struct cci_reg_sequence mode_1284x720_regs[] = { 318 { CCI_REG8(0x0700), 0x00 }, 319 { CCI_REG8(0x0701), 0x10 }, 320 }; 321 322 static const struct cci_reg_sequence mode_1280x720_regs[] = { 323 { CCI_REG8(0x0700), 0x00 }, 324 { CCI_REG8(0x0701), 0x10 }, 325 }; 326 327 static const struct cci_reg_sequence mode_820x616_regs[] = { 328 { CCI_REG8(0x0700), 0x02 }, 329 { CCI_REG8(0x0701), 0x78 }, 330 }; 331 332 static const char * const imx355_test_pattern_menu[] = { 333 "Disabled", 334 "Solid Colour", 335 "Eight Vertical Colour Bars", 336 "Colour Bars With Fade to Grey", 337 "Pseudorandom Sequence (PN9)", 338 }; 339 340 /* Mode configs */ 341 static const struct imx355_mode supported_modes[] = { 342 { 343 .width = 3280, 344 .height = 2464, 345 .crop = { 346 .width = 3280, 347 .height = 2464, 348 .left = 0, 349 .top = 0, 350 }, 351 .fll_def = 2615, 352 .llp = 3672, 353 .reg_list = { 354 .num_of_regs = ARRAY_SIZE(mode_3280x2464_regs), 355 .regs = mode_3280x2464_regs, 356 }, 357 }, 358 { 359 .width = 3268, 360 .height = 2448, 361 .crop = { 362 .width = 3268, 363 .height = 2448, 364 .left = 8, 365 .top = 8, 366 }, 367 .fll_def = 2615, 368 .llp = 3672, 369 .reg_list = { 370 .num_of_regs = ARRAY_SIZE(mode_3268x2448_regs), 371 .regs = mode_3268x2448_regs, 372 }, 373 }, 374 { 375 .width = 3264, 376 .height = 2448, 377 .crop = { 378 .width = 3264, 379 .height = 2448, 380 .left = 8, 381 .top = 8, 382 }, 383 .fll_def = 2615, 384 .llp = 3672, 385 .reg_list = { 386 .num_of_regs = ARRAY_SIZE(mode_3264x2448_regs), 387 .regs = mode_3264x2448_regs, 388 }, 389 }, 390 { 391 .width = 1940, 392 .height = 1096, 393 .crop = { 394 .width = 1940, 395 .height = 1096, 396 .left = 672, 397 .top = 684, 398 }, 399 .fll_def = 1306, 400 .llp = 3672, 401 .reg_list = { 402 .num_of_regs = ARRAY_SIZE(mode_1940x1096_regs), 403 .regs = mode_1940x1096_regs, 404 }, 405 }, 406 { 407 .width = 1936, 408 .height = 1096, 409 .crop = { 410 .width = 1936, 411 .height = 1096, 412 .left = 672, 413 .top = 684, 414 }, 415 .fll_def = 1306, 416 .llp = 3672, 417 .reg_list = { 418 .num_of_regs = ARRAY_SIZE(mode_1936x1096_regs), 419 .regs = mode_1936x1096_regs, 420 }, 421 }, 422 { 423 .width = 1924, 424 .height = 1080, 425 .crop = { 426 .width = 1924, 427 .height = 1080, 428 .left = 680, 429 .top = 692, 430 }, 431 .fll_def = 1306, 432 .llp = 3672, 433 .reg_list = { 434 .num_of_regs = ARRAY_SIZE(mode_1924x1080_regs), 435 .regs = mode_1924x1080_regs, 436 }, 437 }, 438 { 439 .width = 1920, 440 .height = 1080, 441 .crop = { 442 .width = 1920, 443 .height = 1080, 444 .left = 680, 445 .top = 692, 446 }, 447 .fll_def = 1306, 448 .llp = 3672, 449 .reg_list = { 450 .num_of_regs = ARRAY_SIZE(mode_1920x1080_regs), 451 .regs = mode_1920x1080_regs, 452 }, 453 }, 454 { 455 .width = 1640, 456 .height = 1232, 457 .crop = { 458 .width = 3280, 459 .height = 2464, 460 .left = 0, 461 .top = 0, 462 }, 463 .fll_def = 1306, 464 .llp = 1836, 465 .reg_list = { 466 .num_of_regs = ARRAY_SIZE(mode_1640x1232_regs), 467 .regs = mode_1640x1232_regs, 468 }, 469 }, 470 { 471 .width = 1640, 472 .height = 922, 473 .crop = { 474 .width = 3280, 475 .height = 1844, 476 .left = 0, 477 .top = 304, 478 }, 479 .fll_def = 1306, 480 .llp = 1836, 481 .reg_list = { 482 .num_of_regs = ARRAY_SIZE(mode_1640x922_regs), 483 .regs = mode_1640x922_regs, 484 }, 485 }, 486 { 487 .width = 1300, 488 .height = 736, 489 .crop = { 490 .width = 2600, 491 .height = 1472, 492 .left = 344, 493 .top = 496, 494 }, 495 .fll_def = 1306, 496 .llp = 1836, 497 .reg_list = { 498 .num_of_regs = ARRAY_SIZE(mode_1300x736_regs), 499 .regs = mode_1300x736_regs, 500 }, 501 }, 502 { 503 .width = 1296, 504 .height = 736, 505 .crop = { 506 .width = 2592, 507 .height = 1472, 508 .left = 344, 509 .top = 496, 510 }, 511 .fll_def = 1306, 512 .llp = 1836, 513 .reg_list = { 514 .num_of_regs = ARRAY_SIZE(mode_1296x736_regs), 515 .regs = mode_1296x736_regs, 516 }, 517 }, 518 { 519 .width = 1284, 520 .height = 720, 521 .crop = { 522 .width = 2568, 523 .height = 1440, 524 .left = 360, 525 .top = 512, 526 }, 527 .fll_def = 1306, 528 .llp = 1836, 529 .reg_list = { 530 .num_of_regs = ARRAY_SIZE(mode_1284x720_regs), 531 .regs = mode_1284x720_regs, 532 }, 533 }, 534 { 535 .width = 1280, 536 .height = 720, 537 .crop = { 538 .width = 2560, 539 .height = 1440, 540 .left = 360, 541 .top = 512, 542 }, 543 .fll_def = 1306, 544 .llp = 1836, 545 .reg_list = { 546 .num_of_regs = ARRAY_SIZE(mode_1280x720_regs), 547 .regs = mode_1280x720_regs, 548 }, 549 }, 550 { 551 .width = 820, 552 .height = 616, 553 .crop = { 554 .width = 3280, 555 .height = 2464, 556 .left = 0, 557 .top = 0, 558 }, 559 .fll_def = 652, 560 .llp = 3672, 561 .reg_list = { 562 .num_of_regs = ARRAY_SIZE(mode_820x616_regs), 563 .regs = mode_820x616_regs, 564 }, 565 }, 566 }; 567 568 static inline struct imx355 *to_imx355(struct v4l2_subdev *_sd) 569 { 570 return container_of(_sd, struct imx355, sd); 571 } 572 573 /* Get bayer order based on flip setting. */ 574 static u32 imx355_get_format_code(struct imx355 *imx355) 575 { 576 /* 577 * Only one bayer order is supported. 578 * It depends on the flip settings. 579 */ 580 u32 code; 581 static const u32 codes[2][2] = { 582 { MEDIA_BUS_FMT_SRGGB10_1X10, MEDIA_BUS_FMT_SGRBG10_1X10, }, 583 { MEDIA_BUS_FMT_SGBRG10_1X10, MEDIA_BUS_FMT_SBGGR10_1X10, }, 584 }; 585 586 code = codes[imx355->vflip->val][imx355->hflip->val]; 587 588 return code; 589 } 590 591 static int imx355_set_ctrl(struct v4l2_ctrl *ctrl) 592 { 593 struct imx355 *imx355 = container_of(ctrl->handler, 594 struct imx355, ctrl_handler); 595 const struct v4l2_mbus_framefmt *format = NULL; 596 struct v4l2_subdev_state *state; 597 s64 max; 598 int ret; 599 600 state = v4l2_subdev_get_locked_active_state(&imx355->sd); 601 format = v4l2_subdev_state_get_format(state, 0); 602 603 /* Propagate change of current control to all related controls */ 604 switch (ctrl->id) { 605 case V4L2_CID_VBLANK: 606 /* Update max exposure while meeting expected vblanking */ 607 max = format->height + ctrl->val - IMX355_EXPOSURE_OFFSET; 608 __v4l2_ctrl_modify_range(imx355->exposure, 609 imx355->exposure->minimum, 610 max, imx355->exposure->step, max); 611 break; 612 } 613 614 /* 615 * Applying V4L2 control value only happens 616 * when power is up for streaming 617 */ 618 if (!pm_runtime_get_if_in_use(imx355->dev)) 619 return 0; 620 621 switch (ctrl->id) { 622 case V4L2_CID_ANALOGUE_GAIN: 623 /* Analog gain = 1024/(1024 - ctrl->val) times */ 624 ret = cci_write(imx355->regmap, IMX355_REG_ANALOG_GAIN, 625 ctrl->val, NULL); 626 break; 627 case V4L2_CID_DIGITAL_GAIN: 628 ret = cci_write(imx355->regmap, IMX355_REG_DIG_GAIN_GLOBAL, 629 ctrl->val, NULL); 630 break; 631 case V4L2_CID_EXPOSURE: 632 ret = cci_write(imx355->regmap, IMX355_REG_EXPOSURE, 633 ctrl->val, NULL); 634 break; 635 case V4L2_CID_VBLANK: 636 /* Update FLL that meets expected vertical blanking */ 637 ret = cci_write(imx355->regmap, IMX355_REG_FLL, 638 format->height + ctrl->val, NULL); 639 break; 640 case V4L2_CID_TEST_PATTERN: 641 ret = cci_write(imx355->regmap, IMX355_REG_TEST_PATTERN, 642 ctrl->val, NULL); 643 break; 644 case V4L2_CID_HFLIP: 645 case V4L2_CID_VFLIP: 646 ret = cci_write(imx355->regmap, IMX355_REG_ORIENTATION, 647 imx355->hflip->val | imx355->vflip->val << 1, 648 NULL); 649 break; 650 default: 651 ret = -EINVAL; 652 dev_info(imx355->dev, "ctrl(id:0x%x,val:0x%x) is not handled", 653 ctrl->id, ctrl->val); 654 break; 655 } 656 657 pm_runtime_put(imx355->dev); 658 659 return ret; 660 } 661 662 static const struct v4l2_ctrl_ops imx355_ctrl_ops = { 663 .s_ctrl = imx355_set_ctrl, 664 }; 665 666 static int imx355_enum_mbus_code(struct v4l2_subdev *sd, 667 struct v4l2_subdev_state *sd_state, 668 struct v4l2_subdev_mbus_code_enum *code) 669 { 670 struct imx355 *imx355 = to_imx355(sd); 671 672 if (code->index > 0) 673 return -EINVAL; 674 675 code->code = imx355_get_format_code(imx355); 676 677 return 0; 678 } 679 680 static int imx355_enum_frame_size(struct v4l2_subdev *sd, 681 struct v4l2_subdev_state *sd_state, 682 struct v4l2_subdev_frame_size_enum *fse) 683 { 684 struct imx355 *imx355 = to_imx355(sd); 685 686 if (fse->index >= ARRAY_SIZE(supported_modes)) 687 return -EINVAL; 688 689 if (fse->code != imx355_get_format_code(imx355)) { 690 return -EINVAL; 691 } 692 693 fse->min_width = supported_modes[fse->index].width; 694 fse->max_width = fse->min_width; 695 fse->min_height = supported_modes[fse->index].height; 696 fse->max_height = fse->min_height; 697 698 return 0; 699 } 700 701 static void imx355_update_pad_format(struct imx355 *imx355, 702 const struct imx355_mode *mode, 703 struct v4l2_subdev_format *fmt) 704 { 705 fmt->format.width = mode->width; 706 fmt->format.height = mode->height; 707 fmt->format.code = imx355_get_format_code(imx355); 708 fmt->format.field = V4L2_FIELD_NONE; 709 fmt->format.colorspace = V4L2_COLORSPACE_RAW; 710 fmt->format.ycbcr_enc = V4L2_YCBCR_ENC_601; 711 fmt->format.quantization = V4L2_QUANTIZATION_FULL_RANGE; 712 fmt->format.xfer_func = V4L2_XFER_FUNC_NONE; 713 } 714 715 static int 716 imx355_set_pad_format(struct v4l2_subdev *sd, 717 struct v4l2_subdev_state *sd_state, 718 struct v4l2_subdev_format *fmt) 719 { 720 struct imx355 *imx355 = to_imx355(sd); 721 const struct imx355_mode *mode; 722 struct v4l2_mbus_framefmt *framefmt; 723 struct v4l2_rect *crop; 724 s64 h_blank; 725 726 /* 727 * Only one bayer order is supported. 728 * It depends on the flip settings. 729 */ 730 fmt->format.code = imx355_get_format_code(imx355); 731 732 mode = v4l2_find_nearest_size(supported_modes, 733 ARRAY_SIZE(supported_modes), 734 width, height, 735 fmt->format.width, fmt->format.height); 736 imx355_update_pad_format(imx355, mode, fmt); 737 framefmt = v4l2_subdev_state_get_format(sd_state, 0); 738 739 *framefmt = fmt->format; 740 741 crop = v4l2_subdev_state_get_crop(sd_state, 0); 742 crop->width = mode->crop.width; 743 crop->height = mode->crop.height; 744 crop->left = mode->crop.left; 745 crop->top = mode->crop.top; 746 747 if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 748 /* Update limits and set FPS to default */ 749 __v4l2_ctrl_modify_range(imx355->vblank, IMX355_VBLANK_MIN, 750 IMX355_FLL_MAX - mode->height, 1, 751 mode->fll_def - mode->height); 752 __v4l2_ctrl_s_ctrl(imx355->vblank, mode->fll_def - mode->height); 753 754 h_blank = mode->llp - mode->width; 755 756 /* 757 * Currently hblank is not changeable. 758 * So FPS control is done only by vblank. 759 */ 760 __v4l2_ctrl_modify_range(imx355->hblank, h_blank, 761 h_blank, 1, h_blank); 762 } 763 764 return 0; 765 } 766 767 static int imx355_get_selection(struct v4l2_subdev *sd, 768 struct v4l2_subdev_state *sd_state, 769 struct v4l2_subdev_selection *sel) 770 { 771 switch (sel->target) { 772 case V4L2_SEL_TGT_CROP: 773 sel->r = *v4l2_subdev_state_get_crop(sd_state, 0); 774 return 0; 775 case V4L2_SEL_TGT_CROP_DEFAULT: 776 case V4L2_SEL_TGT_CROP_BOUNDS: 777 case V4L2_SEL_TGT_NATIVE_SIZE: 778 sel->r.top = IMX355_PIXEL_ARRAY_TOP; 779 sel->r.left = IMX355_PIXEL_ARRAY_LEFT; 780 sel->r.width = IMX355_PIXEL_ARRAY_WIDTH; 781 sel->r.height = IMX355_PIXEL_ARRAY_HEIGHT; 782 783 return 0; 784 } 785 786 return -EINVAL; 787 } 788 789 static int imx355_entity_init_state(struct v4l2_subdev *subdev, 790 struct v4l2_subdev_state *sd_state) 791 { 792 struct v4l2_subdev_format fmt = { }; 793 794 fmt.which = sd_state ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE; 795 fmt.format.code = MEDIA_BUS_FMT_SRGGB10_1X10; 796 fmt.format.width = supported_modes[0].width; 797 fmt.format.height = supported_modes[0].height; 798 799 imx355_set_pad_format(subdev, sd_state, &fmt); 800 801 return 0; 802 } 803 804 /* Start streaming */ 805 static int imx355_start_streaming(struct imx355 *imx355) 806 { 807 const struct v4l2_mbus_framefmt *fmt; 808 struct v4l2_subdev_state *state; 809 const struct imx355_mode *mode; 810 int lane_idx = imx355->hwcfg->num_lanes == 4 ? 0 : 1; 811 struct v4l2_rect *crop; 812 u64 link_bitrate; 813 u8 binning_mode; 814 int ret = 0; 815 816 /* Global Setting */ 817 cci_multi_reg_write(imx355->regmap, imx355_global_regs, 818 ARRAY_SIZE(imx355_global_regs), &ret); 819 820 /* Apply values of current mode */ 821 state = v4l2_subdev_get_locked_active_state(&imx355->sd); 822 fmt = v4l2_subdev_state_get_format(state, 0); 823 crop = v4l2_subdev_state_get_crop(state, 0); 824 mode = v4l2_find_nearest_size(supported_modes, 825 ARRAY_SIZE(supported_modes), 826 width, height, fmt->width, fmt->height); 827 cci_multi_reg_write(imx355->regmap, mode->reg_list.regs, 828 mode->reg_list.num_of_regs, &ret); 829 830 /* Set readout crop and size registers */ 831 cci_write(imx355->regmap, IMX355_REG_X_ADD_START, crop->left, 832 &ret); 833 cci_write(imx355->regmap, IMX355_REG_Y_ADD_START, crop->top, &ret); 834 cci_write(imx355->regmap, IMX355_REG_X_ADD_END, 835 crop->width + crop->left - 1, &ret); 836 cci_write(imx355->regmap, IMX355_REG_Y_ADD_END, 837 crop->height + crop->top - 1, &ret); 838 cci_write(imx355->regmap, IMX355_REG_X_OUT_SIZE, fmt->width, &ret); 839 cci_write(imx355->regmap, IMX355_REG_Y_OUT_SIZE, fmt->height, &ret); 840 841 binning_mode = ((crop->width / fmt->width) << 4) | 842 (crop->height / fmt->height); 843 cci_write(imx355->regmap, IMX355_REG_BINNING_MODE, 844 binning_mode == 0x11 ? 0x00 : 0x01, &ret); 845 cci_write(imx355->regmap, IMX355_REG_BINNING_TYPE, binning_mode, &ret); 846 cci_write(imx355->regmap, IMX355_REG_BINNING_WEIGHTING, 0x00, &ret); 847 848 /* Set PLL registers for the external clock frequency */ 849 cci_write(imx355->regmap, IMX355_REG_EXTCLK_FREQ, 850 imx355->clk_params->extclk_freq, &ret); 851 cci_write(imx355->regmap, IMX355_REG_PLL_OP_MUL, 852 imx355->clk_params->pll_op_mpy[lane_idx], &ret); 853 cci_write(imx355->regmap, IMX355_REG_PLL_OP_PREDIV, 854 imx355->clk_params->pll_op_prediv[lane_idx], &ret); 855 cci_write(imx355->regmap, IMX355_REG_PLL_IVT_SYSCK_DIV, 856 lane_idx ? 2 : 1, &ret); 857 858 /* Set MIPI configuration */ 859 cci_write(imx355->regmap, IMX355_REG_LANE_SEL, 860 imx355->hwcfg->num_lanes - 1, &ret); 861 862 link_bitrate = imx355->link_freq->qmenu_int[imx355->link_freq->val] * 863 imx355->hwcfg->num_lanes * 2; 864 do_div(link_bitrate, 1000000); 865 cci_write(imx355->regmap, IMX355_REG_REQ_LINK_BIT_RATE, link_bitrate, 866 &ret); 867 868 /* set digital gain control to all color mode */ 869 cci_write(imx355->regmap, IMX355_REG_DPGA_USE_GLOBAL_GAIN, 1, &ret); 870 871 /* set line length */ 872 cci_write(imx355->regmap, IMX355_REG_LLP, 873 imx355->hblank->val + fmt->width, &ret); 874 875 /* Apply customized values from user */ 876 if (!ret) 877 ret = __v4l2_ctrl_handler_setup(imx355->sd.ctrl_handler); 878 879 cci_write(imx355->regmap, IMX355_REG_MODE_SELECT, IMX355_MODE_STREAMING, 880 &ret); 881 882 return ret; 883 } 884 885 /* Stop streaming */ 886 static int imx355_stop_streaming(struct imx355 *imx355) 887 { 888 return cci_write(imx355->regmap, IMX355_REG_MODE_SELECT, 889 IMX355_MODE_STANDBY, NULL); 890 } 891 892 static int imx355_set_stream(struct v4l2_subdev *sd, int enable) 893 { 894 struct imx355 *imx355 = to_imx355(sd); 895 struct v4l2_subdev_state *state; 896 int ret = 0; 897 898 state = v4l2_subdev_lock_and_get_active_state(sd); 899 900 if (enable) { 901 ret = pm_runtime_resume_and_get(imx355->dev); 902 if (ret < 0) 903 goto err_unlock; 904 905 /* 906 * Apply default & customized values 907 * and then start streaming. 908 */ 909 ret = imx355_start_streaming(imx355); 910 if (ret) 911 goto err_rpm_put; 912 } else { 913 imx355_stop_streaming(imx355); 914 pm_runtime_put_autosuspend(imx355->dev); 915 } 916 917 /* vflip and hflip cannot change during streaming */ 918 __v4l2_ctrl_grab(imx355->vflip, enable); 919 __v4l2_ctrl_grab(imx355->hflip, enable); 920 921 v4l2_subdev_unlock_state(state); 922 923 return ret; 924 925 err_rpm_put: 926 pm_runtime_put_autosuspend(imx355->dev); 927 err_unlock: 928 v4l2_subdev_unlock_state(state); 929 930 return ret; 931 } 932 933 /* Verify chip ID */ 934 static int imx355_identify_module(struct imx355 *imx355) 935 { 936 int ret; 937 u64 val; 938 939 ret = cci_read(imx355->regmap, IMX355_REG_CHIP_ID, &val, NULL); 940 if (ret) 941 return ret; 942 943 if (val != IMX355_CHIP_ID) { 944 dev_err(imx355->dev, "chip id mismatch: %x!=%llx", 945 IMX355_CHIP_ID, val); 946 return -EIO; 947 } 948 return 0; 949 } 950 951 static const struct v4l2_subdev_core_ops imx355_subdev_core_ops = { 952 .subscribe_event = v4l2_ctrl_subdev_subscribe_event, 953 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 954 }; 955 956 static const struct v4l2_subdev_video_ops imx355_video_ops = { 957 .s_stream = imx355_set_stream, 958 }; 959 960 static const struct v4l2_subdev_pad_ops imx355_pad_ops = { 961 .enum_mbus_code = imx355_enum_mbus_code, 962 .get_fmt = v4l2_subdev_get_fmt, 963 .set_fmt = imx355_set_pad_format, 964 .enum_frame_size = imx355_enum_frame_size, 965 .get_selection = imx355_get_selection, 966 }; 967 968 static const struct v4l2_subdev_ops imx355_subdev_ops = { 969 .core = &imx355_subdev_core_ops, 970 .video = &imx355_video_ops, 971 .pad = &imx355_pad_ops, 972 }; 973 974 static const struct media_entity_operations imx355_subdev_entity_ops = { 975 .link_validate = v4l2_subdev_link_validate, 976 }; 977 978 static const struct v4l2_subdev_internal_ops imx355_internal_ops = { 979 .init_state = imx355_entity_init_state, 980 }; 981 982 static int imx355_power_off(struct device *dev) 983 { 984 struct i2c_client *client = container_of(dev, struct i2c_client, dev); 985 struct v4l2_subdev *sd = i2c_get_clientdata(client); 986 struct imx355 *imx355 = to_imx355(sd); 987 988 gpiod_set_value_cansleep(imx355->reset_gpio, 1); 989 990 regulator_bulk_disable(ARRAY_SIZE(imx355_supplies), imx355->supplies); 991 clk_disable_unprepare(imx355->clk); 992 993 return 0; 994 } 995 996 static int imx355_power_on(struct device *dev) 997 { 998 struct i2c_client *client = container_of(dev, struct i2c_client, dev); 999 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1000 struct imx355 *imx355 = to_imx355(sd); 1001 int ret; 1002 1003 ret = clk_prepare_enable(imx355->clk); 1004 if (ret) 1005 return dev_err_probe(dev, ret, "failed to enable clocks"); 1006 1007 ret = regulator_bulk_enable(ARRAY_SIZE(imx355_supplies), 1008 imx355->supplies); 1009 if (ret) { 1010 dev_err_probe(dev, ret, "failed to enable regulators"); 1011 goto error_disable_clocks; 1012 } 1013 1014 usleep_range(1000, 2000); 1015 gpiod_set_value_cansleep(imx355->reset_gpio, 0); 1016 usleep_range(10000, 11000); 1017 1018 return 0; 1019 1020 error_disable_clocks: 1021 clk_disable_unprepare(imx355->clk); 1022 return ret; 1023 } 1024 1025 static DEFINE_RUNTIME_DEV_PM_OPS(imx355_pm_ops, imx355_power_off, 1026 imx355_power_on, NULL); 1027 1028 /* Initialize control handlers */ 1029 static int imx355_init_controls(struct imx355 *imx355) 1030 { 1031 struct v4l2_fwnode_device_properties props; 1032 struct v4l2_ctrl_handler *ctrl_hdlr; 1033 const struct imx355_mode *mode = &supported_modes[0]; 1034 s64 exposure_max; 1035 s64 vblank_def; 1036 s64 hblank; 1037 u64 pixel_rate; 1038 int ret; 1039 1040 ctrl_hdlr = &imx355->ctrl_handler; 1041 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 12); 1042 if (ret) 1043 return ret; 1044 1045 imx355->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &imx355_ctrl_ops, 1046 V4L2_CID_LINK_FREQ, 0, 0, 1047 &imx355->hwcfg->link_freq_menu); 1048 if (imx355->link_freq) 1049 imx355->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1050 1051 /* pixel_rate = link_freq * 2 * nr_of_lanes / bits_per_sample */ 1052 pixel_rate = imx355->hwcfg->link_freq_menu * 2 * imx355->hwcfg->num_lanes; 1053 do_div(pixel_rate, 10); 1054 1055 v4l2_ctrl_new_std(ctrl_hdlr, &imx355_ctrl_ops, V4L2_CID_PIXEL_RATE, 1056 pixel_rate, pixel_rate, 1, pixel_rate); 1057 1058 /* Initialize vblank/hblank/exposure parameters based on current mode */ 1059 vblank_def = mode->fll_def - mode->height; 1060 imx355->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx355_ctrl_ops, 1061 V4L2_CID_VBLANK, IMX355_VBLANK_MIN, 1062 IMX355_FLL_MAX - mode->height, 1063 1, vblank_def); 1064 1065 hblank = mode->llp - mode->width; 1066 imx355->hblank = v4l2_ctrl_new_std(ctrl_hdlr, NULL, V4L2_CID_HBLANK, 1067 hblank, hblank, 1, hblank); 1068 if (imx355->hblank) 1069 imx355->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1070 1071 /* fll >= exposure time + adjust parameter (default value is 10) */ 1072 exposure_max = mode->fll_def - IMX355_EXPOSURE_OFFSET; 1073 imx355->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &imx355_ctrl_ops, 1074 V4L2_CID_EXPOSURE, 1075 IMX355_EXPOSURE_MIN, exposure_max, 1076 IMX355_EXPOSURE_STEP, 1077 IMX355_EXPOSURE_DEFAULT); 1078 1079 imx355->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx355_ctrl_ops, 1080 V4L2_CID_HFLIP, 0, 1, 1, 0); 1081 if (imx355->hflip) 1082 imx355->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; 1083 imx355->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx355_ctrl_ops, 1084 V4L2_CID_VFLIP, 0, 1, 1, 0); 1085 if (imx355->vflip) 1086 imx355->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; 1087 1088 v4l2_ctrl_new_std(ctrl_hdlr, &imx355_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 1089 IMX355_ANA_GAIN_MIN, IMX355_ANA_GAIN_MAX, 1090 IMX355_ANA_GAIN_STEP, IMX355_ANA_GAIN_DEFAULT); 1091 1092 /* Digital gain */ 1093 v4l2_ctrl_new_std(ctrl_hdlr, &imx355_ctrl_ops, V4L2_CID_DIGITAL_GAIN, 1094 IMX355_DGTL_GAIN_MIN, IMX355_DGTL_GAIN_MAX, 1095 IMX355_DGTL_GAIN_STEP, IMX355_DGTL_GAIN_DEFAULT); 1096 1097 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &imx355_ctrl_ops, 1098 V4L2_CID_TEST_PATTERN, 1099 ARRAY_SIZE(imx355_test_pattern_menu) - 1, 1100 0, 0, imx355_test_pattern_menu); 1101 if (ctrl_hdlr->error) { 1102 ret = ctrl_hdlr->error; 1103 dev_err(imx355->dev, "control init failed: %d", ret); 1104 goto error; 1105 } 1106 1107 ret = v4l2_fwnode_device_parse(imx355->dev, &props); 1108 if (ret) 1109 goto error; 1110 1111 ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &imx355_ctrl_ops, 1112 &props); 1113 if (ret) 1114 goto error; 1115 1116 imx355->sd.ctrl_handler = ctrl_hdlr; 1117 1118 return 0; 1119 1120 error: 1121 v4l2_ctrl_handler_free(ctrl_hdlr); 1122 1123 return ret; 1124 } 1125 1126 static struct imx355_hwcfg *imx355_get_hwcfg(struct imx355 *imx355) 1127 { 1128 struct device *dev = imx355->dev; 1129 struct imx355_hwcfg *cfg; 1130 struct v4l2_fwnode_endpoint bus_cfg = { 1131 .bus_type = V4L2_MBUS_CSI2_DPHY 1132 }; 1133 const struct imx355_clk_params *clk = imx355->clk_params; 1134 struct fwnode_handle *ep; 1135 struct fwnode_handle *fwnode = dev_fwnode(dev); 1136 int lane_idx; 1137 int ret; 1138 1139 if (!fwnode) 1140 return NULL; 1141 1142 ep = fwnode_graph_get_next_endpoint(fwnode, NULL); 1143 if (!ep) 1144 return NULL; 1145 1146 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); 1147 if (ret) 1148 goto out_err; 1149 1150 cfg = devm_kzalloc(dev, sizeof(*cfg), GFP_KERNEL); 1151 if (!cfg) 1152 goto out_err; 1153 1154 if (bus_cfg.bus.mipi_csi2.num_data_lanes != 2 && 1155 bus_cfg.bus.mipi_csi2.num_data_lanes != 4) 1156 goto out_err; 1157 1158 cfg->num_lanes = bus_cfg.bus.mipi_csi2.num_data_lanes; 1159 1160 lane_idx = cfg->num_lanes == 4 ? 0 : 1; 1161 cfg->link_freq_menu = (clk->ext_clk * clk->pll_op_mpy[lane_idx]) / 1162 (clk->pll_op_prediv[lane_idx] * 2); 1163 ret = v4l2_link_freq_to_bitmap(dev, bus_cfg.link_frequencies, 1164 bus_cfg.nr_of_link_frequencies, 1165 &cfg->link_freq_menu, 1, 1166 &cfg->link_freq_bitmap); 1167 if (ret) 1168 goto out_err; 1169 1170 v4l2_fwnode_endpoint_free(&bus_cfg); 1171 fwnode_handle_put(ep); 1172 return cfg; 1173 1174 out_err: 1175 v4l2_fwnode_endpoint_free(&bus_cfg); 1176 fwnode_handle_put(ep); 1177 return NULL; 1178 } 1179 1180 static int imx355_probe(struct i2c_client *client) 1181 { 1182 struct imx355 *imx355; 1183 unsigned long freq; 1184 int ret; 1185 1186 imx355 = devm_kzalloc(&client->dev, sizeof(*imx355), GFP_KERNEL); 1187 if (!imx355) 1188 return -ENOMEM; 1189 1190 imx355->dev = &client->dev; 1191 1192 imx355->regmap = devm_cci_regmap_init_i2c(client, 16); 1193 if (IS_ERR(imx355->regmap)) 1194 return dev_err_probe(imx355->dev, PTR_ERR(imx355->regmap), 1195 "Unable to initialize I2C\n"); 1196 1197 imx355->clk = devm_v4l2_sensor_clk_get(imx355->dev, NULL); 1198 if (IS_ERR(imx355->clk)) 1199 return dev_err_probe(imx355->dev, PTR_ERR(imx355->clk), 1200 "failed to get clock\n"); 1201 1202 freq = clk_get_rate(imx355->clk); 1203 for (unsigned int i = 0; i < ARRAY_SIZE(imx355_clk_params); i++) { 1204 if (freq == imx355_clk_params[i].ext_clk) { 1205 imx355->clk_params = &imx355_clk_params[i]; 1206 break; 1207 } 1208 } 1209 if (!imx355->clk_params) 1210 return dev_err_probe(imx355->dev, -EINVAL, 1211 "external clock %lu is not supported\n", 1212 freq); 1213 1214 ret = devm_regulator_bulk_get_const(imx355->dev, 1215 ARRAY_SIZE(imx355_supplies), 1216 imx355_supplies, 1217 &imx355->supplies); 1218 if (ret) { 1219 dev_err_probe(imx355->dev, ret, "could not get regulators"); 1220 return ret; 1221 } 1222 1223 imx355->reset_gpio = devm_gpiod_get_optional(imx355->dev, "reset", 1224 GPIOD_OUT_HIGH); 1225 if (IS_ERR(imx355->reset_gpio)) { 1226 ret = dev_err_probe(imx355->dev, PTR_ERR(imx355->reset_gpio), 1227 "failed to get gpios"); 1228 return ret; 1229 } 1230 1231 /* Initialize subdev */ 1232 v4l2_i2c_subdev_init(&imx355->sd, client, &imx355_subdev_ops); 1233 1234 imx355->hwcfg = imx355_get_hwcfg(imx355); 1235 if (!imx355->hwcfg) { 1236 dev_err(imx355->dev, "failed to get hwcfg"); 1237 return -ENODEV; 1238 } 1239 1240 ret = imx355_power_on(imx355->dev); 1241 if (ret) 1242 return ret; 1243 1244 /* Check module identity */ 1245 ret = imx355_identify_module(imx355); 1246 if (ret) { 1247 dev_err(imx355->dev, "failed to find sensor: %d", ret); 1248 goto error_power_off; 1249 } 1250 1251 ret = imx355_init_controls(imx355); 1252 if (ret) { 1253 dev_err(imx355->dev, "failed to init controls: %d", ret); 1254 goto error_power_off; 1255 } 1256 1257 /* Initialize subdev */ 1258 imx355->sd.internal_ops = &imx355_internal_ops; 1259 imx355->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | 1260 V4L2_SUBDEV_FL_HAS_EVENTS; 1261 imx355->sd.entity.ops = &imx355_subdev_entity_ops; 1262 imx355->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1263 1264 /* Initialize source pad */ 1265 imx355->pad.flags = MEDIA_PAD_FL_SOURCE; 1266 ret = media_entity_pads_init(&imx355->sd.entity, 1, &imx355->pad); 1267 if (ret) { 1268 dev_err(imx355->dev, "failed to init entity pads: %d", ret); 1269 goto error_handler_free; 1270 } 1271 1272 imx355->sd.state_lock = imx355->ctrl_handler.lock; 1273 ret = v4l2_subdev_init_finalize(&imx355->sd); 1274 if (ret < 0) { 1275 dev_err_probe(imx355->dev, ret, "subdev init error\n"); 1276 goto error_media_entity_free; 1277 } 1278 1279 /* 1280 * Device is already turned on by i2c-core with ACPI domain PM. 1281 * Enable runtime PM and turn off the device. 1282 */ 1283 pm_runtime_set_active(imx355->dev); 1284 pm_runtime_enable(imx355->dev); 1285 pm_runtime_set_autosuspend_delay(imx355->dev, 1000); 1286 pm_runtime_use_autosuspend(imx355->dev); 1287 1288 ret = v4l2_async_register_subdev_sensor(&imx355->sd); 1289 if (ret < 0) 1290 goto error_subdev_cleanup_runtime_pm; 1291 1292 pm_runtime_idle(imx355->dev); 1293 1294 return 0; 1295 1296 error_subdev_cleanup_runtime_pm: 1297 pm_runtime_disable(imx355->dev); 1298 pm_runtime_set_suspended(imx355->dev); 1299 pm_runtime_dont_use_autosuspend(imx355->dev); 1300 v4l2_subdev_cleanup(&imx355->sd); 1301 error_media_entity_free: 1302 media_entity_cleanup(&imx355->sd.entity); 1303 1304 error_handler_free: 1305 v4l2_ctrl_handler_free(imx355->sd.ctrl_handler); 1306 1307 error_power_off: 1308 imx355_power_off(imx355->dev); 1309 1310 return ret; 1311 } 1312 1313 static void imx355_remove(struct i2c_client *client) 1314 { 1315 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1316 struct imx355 *imx355 = to_imx355(sd); 1317 1318 v4l2_async_unregister_subdev(sd); 1319 v4l2_subdev_cleanup(sd); 1320 media_entity_cleanup(&sd->entity); 1321 v4l2_ctrl_handler_free(sd->ctrl_handler); 1322 1323 pm_runtime_disable(imx355->dev); 1324 1325 if (!pm_runtime_status_suspended(imx355->dev)) { 1326 imx355_power_off(imx355->dev); 1327 pm_runtime_set_suspended(imx355->dev); 1328 } 1329 1330 pm_runtime_dont_use_autosuspend(imx355->dev); 1331 } 1332 1333 static const struct acpi_device_id imx355_acpi_ids[] __maybe_unused = { 1334 { "SONY355A" }, 1335 { /* sentinel */ } 1336 }; 1337 MODULE_DEVICE_TABLE(acpi, imx355_acpi_ids); 1338 1339 static const struct of_device_id imx355_match_table[] = { 1340 { .compatible = "sony,imx355", }, 1341 { /* sentinel */ } 1342 }; 1343 MODULE_DEVICE_TABLE(of, imx355_match_table); 1344 1345 static struct i2c_driver imx355_i2c_driver = { 1346 .driver = { 1347 .name = "imx355", 1348 .acpi_match_table = ACPI_PTR(imx355_acpi_ids), 1349 .of_match_table = imx355_match_table, 1350 .pm = &imx355_pm_ops, 1351 }, 1352 .probe = imx355_probe, 1353 .remove = imx355_remove, 1354 }; 1355 module_i2c_driver(imx355_i2c_driver); 1356 1357 MODULE_AUTHOR("Qiu, Tianshu <tian.shu.qiu@intel.com>"); 1358 MODULE_AUTHOR("Rapolu, Chiranjeevi"); 1359 MODULE_AUTHOR("Bingbu Cao <bingbu.cao@intel.com>"); 1360 MODULE_AUTHOR("Yang, Hyungwoo"); 1361 MODULE_DESCRIPTION("Sony imx355 sensor driver"); 1362 MODULE_LICENSE("GPL v2"); 1363