1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Sony IMX290 CMOS Image Sensor Driver 4 * 5 * Copyright (C) 2019 FRAMOS GmbH. 6 * 7 * Copyright (C) 2019 Linaro Ltd. 8 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/i2c.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 21 #include <linux/unaligned.h> 22 23 #include <media/media-entity.h> 24 #include <media/v4l2-cci.h> 25 #include <media/v4l2-ctrls.h> 26 #include <media/v4l2-device.h> 27 #include <media/v4l2-fwnode.h> 28 #include <media/v4l2-subdev.h> 29 30 #define IMX290_STANDBY CCI_REG8(0x3000) 31 #define IMX290_REGHOLD CCI_REG8(0x3001) 32 #define IMX290_XMSTA CCI_REG8(0x3002) 33 #define IMX290_ADBIT CCI_REG8(0x3005) 34 #define IMX290_ADBIT_10BIT (0 << 0) 35 #define IMX290_ADBIT_12BIT (1 << 0) 36 #define IMX290_CTRL_07 CCI_REG8(0x3007) 37 #define IMX290_VREVERSE BIT(0) 38 #define IMX290_HREVERSE BIT(1) 39 #define IMX290_WINMODE_1080P (0 << 4) 40 #define IMX290_WINMODE_720P (1 << 4) 41 #define IMX290_WINMODE_CROP (4 << 4) 42 #define IMX290_FR_FDG_SEL CCI_REG8(0x3009) 43 #define IMX290_BLKLEVEL CCI_REG16_LE(0x300a) 44 #define IMX290_GAIN CCI_REG8(0x3014) 45 #define IMX290_VMAX CCI_REG24_LE(0x3018) 46 #define IMX290_VMAX_MAX 0x3ffff 47 #define IMX290_HMAX CCI_REG16_LE(0x301c) 48 #define IMX290_HMAX_MAX 0xffff 49 #define IMX290_SHS1 CCI_REG24_LE(0x3020) 50 #define IMX290_WINWV_OB CCI_REG8(0x303a) 51 #define IMX290_WINPV CCI_REG16_LE(0x303c) 52 #define IMX290_WINWV CCI_REG16_LE(0x303e) 53 #define IMX290_WINPH CCI_REG16_LE(0x3040) 54 #define IMX290_WINWH CCI_REG16_LE(0x3042) 55 #define IMX290_OUT_CTRL CCI_REG8(0x3046) 56 #define IMX290_ODBIT_10BIT (0 << 0) 57 #define IMX290_ODBIT_12BIT (1 << 0) 58 #define IMX290_OPORTSEL_PARALLEL (0x0 << 4) 59 #define IMX290_OPORTSEL_LVDS_2CH (0xd << 4) 60 #define IMX290_OPORTSEL_LVDS_4CH (0xe << 4) 61 #define IMX290_OPORTSEL_LVDS_8CH (0xf << 4) 62 #define IMX290_XSOUTSEL CCI_REG8(0x304b) 63 #define IMX290_XSOUTSEL_XVSOUTSEL_HIGH (0 << 0) 64 #define IMX290_XSOUTSEL_XVSOUTSEL_VSYNC (2 << 0) 65 #define IMX290_XSOUTSEL_XHSOUTSEL_HIGH (0 << 2) 66 #define IMX290_XSOUTSEL_XHSOUTSEL_HSYNC (2 << 2) 67 #define IMX290_INCKSEL1 CCI_REG8(0x305c) 68 #define IMX290_INCKSEL2 CCI_REG8(0x305d) 69 #define IMX290_INCKSEL3 CCI_REG8(0x305e) 70 #define IMX290_INCKSEL4 CCI_REG8(0x305f) 71 #define IMX290_PGCTRL CCI_REG8(0x308c) 72 #define IMX290_ADBIT1 CCI_REG8(0x3129) 73 #define IMX290_ADBIT1_10BIT 0x1d 74 #define IMX290_ADBIT1_12BIT 0x00 75 #define IMX290_INCKSEL5 CCI_REG8(0x315e) 76 #define IMX290_INCKSEL6 CCI_REG8(0x3164) 77 #define IMX290_ADBIT2 CCI_REG8(0x317c) 78 #define IMX290_ADBIT2_10BIT 0x12 79 #define IMX290_ADBIT2_12BIT 0x00 80 #define IMX290_ADBIT3 CCI_REG8(0x31ec) 81 #define IMX290_ADBIT3_10BIT 0x37 82 #define IMX290_ADBIT3_12BIT 0x0e 83 #define IMX290_REPETITION CCI_REG8(0x3405) 84 #define IMX290_PHY_LANE_NUM CCI_REG8(0x3407) 85 #define IMX290_OPB_SIZE_V CCI_REG8(0x3414) 86 #define IMX290_Y_OUT_SIZE CCI_REG16_LE(0x3418) 87 #define IMX290_CSI_DT_FMT CCI_REG16_LE(0x3441) 88 #define IMX290_CSI_DT_FMT_RAW10 0x0a0a 89 #define IMX290_CSI_DT_FMT_RAW12 0x0c0c 90 #define IMX290_CSI_LANE_MODE CCI_REG8(0x3443) 91 #define IMX290_EXTCK_FREQ CCI_REG16_LE(0x3444) 92 #define IMX290_TCLKPOST CCI_REG16_LE(0x3446) 93 #define IMX290_THSZERO CCI_REG16_LE(0x3448) 94 #define IMX290_THSPREPARE CCI_REG16_LE(0x344a) 95 #define IMX290_TCLKTRAIL CCI_REG16_LE(0x344c) 96 #define IMX290_THSTRAIL CCI_REG16_LE(0x344e) 97 #define IMX290_TCLKZERO CCI_REG16_LE(0x3450) 98 #define IMX290_TCLKPREPARE CCI_REG16_LE(0x3452) 99 #define IMX290_TLPX CCI_REG16_LE(0x3454) 100 #define IMX290_X_OUT_SIZE CCI_REG16_LE(0x3472) 101 #define IMX290_INCKSEL7 CCI_REG8(0x3480) 102 103 #define IMX290_PGCTRL_REGEN BIT(0) 104 #define IMX290_PGCTRL_THRU BIT(1) 105 #define IMX290_PGCTRL_MODE(n) ((n) << 4) 106 107 /* Number of lines by which exposure must be less than VMAX */ 108 #define IMX290_EXPOSURE_OFFSET 2 109 110 #define IMX290_PIXEL_RATE 148500000 111 112 /* 113 * The IMX290 pixel array is organized as follows: 114 * 115 * +------------------------------------+ 116 * | Optical Black | } Vertical effective optical black (10) 117 * +---+------------------------------------+---+ 118 * | | | | } Effective top margin (8) 119 * | | +----------------------------+ | | \ 120 * | | | | | | | 121 * | | | | | | | 122 * | | | | | | | 123 * | | | Recording Pixel Area | | | | Recommended height (1080) 124 * | | | | | | | 125 * | | | | | | | 126 * | | | | | | | 127 * | | +----------------------------+ | | / 128 * | | | | } Effective bottom margin (9) 129 * +---+------------------------------------+---+ 130 * <-> <-> <--------------------------> <-> <-> 131 * \---- Ignored right margin (4) 132 * \-------- Effective right margin (9) 133 * \------------------------- Recommended width (1920) 134 * \----------------------------------------- Effective left margin (8) 135 * \--------------------------------------------- Ignored left margin (4) 136 * 137 * The optical black lines are output over CSI-2 with a separate data type. 138 * 139 * The pixel array is meant to have 1920x1080 usable pixels after image 140 * processing in an ISP. It has 8 (9) extra active pixels usable for color 141 * processing in the ISP on the top and left (bottom and right) sides of the 142 * image. In addition, 4 additional pixels are present on the left and right 143 * sides of the image, documented as "ignored area". 144 * 145 * As far as is understood, all pixels of the pixel array (ignored area, color 146 * processing margins and recording area) can be output by the sensor. 147 */ 148 149 #define IMX290_PIXEL_ARRAY_WIDTH 1945 150 #define IMX290_PIXEL_ARRAY_HEIGHT 1097 151 #define IMX290_PIXEL_ARRAY_MARGIN_LEFT 12 152 #define IMX290_PIXEL_ARRAY_MARGIN_RIGHT 13 153 #define IMX290_PIXEL_ARRAY_MARGIN_TOP 8 154 #define IMX290_PIXEL_ARRAY_MARGIN_BOTTOM 9 155 #define IMX290_PIXEL_ARRAY_RECORDING_WIDTH 1920 156 #define IMX290_PIXEL_ARRAY_RECORDING_HEIGHT 1080 157 158 /* Equivalent value for 16bpp */ 159 #define IMX290_BLACK_LEVEL_DEFAULT 3840 160 161 #define IMX290_NUM_SUPPLIES 3 162 163 enum imx290_colour_variant { 164 IMX290_VARIANT_COLOUR, 165 IMX290_VARIANT_MONO, 166 IMX290_VARIANT_MAX 167 }; 168 169 enum imx290_model { 170 IMX290_MODEL_IMX290LQR, 171 IMX290_MODEL_IMX290LLR, 172 IMX290_MODEL_IMX327LQR, 173 }; 174 175 struct imx290_model_info { 176 enum imx290_colour_variant colour_variant; 177 const struct cci_reg_sequence *init_regs; 178 size_t init_regs_num; 179 const char *name; 180 }; 181 182 enum imx290_clk_freq { 183 IMX290_CLK_37_125, 184 IMX290_CLK_74_25, 185 IMX290_NUM_CLK 186 }; 187 188 /* 189 * Clock configuration for registers INCKSEL1 to INCKSEL6. 190 */ 191 struct imx290_clk_cfg { 192 u8 incksel1; 193 u8 incksel2; 194 u8 incksel3; 195 u8 incksel4; 196 u8 incksel5; 197 u8 incksel6; 198 }; 199 200 struct imx290_mode { 201 u32 width; 202 u32 height; 203 u32 hmax_min; 204 u32 vmax_min; 205 u8 link_freq_index; 206 u8 ctrl_07; 207 208 const struct cci_reg_sequence *data; 209 u32 data_size; 210 211 const struct imx290_clk_cfg *clk_cfg; 212 }; 213 214 struct imx290_csi_cfg { 215 u16 repetition; 216 u16 tclkpost; 217 u16 thszero; 218 u16 thsprepare; 219 u16 tclktrail; 220 u16 thstrail; 221 u16 tclkzero; 222 u16 tclkprepare; 223 u16 tlpx; 224 }; 225 226 struct imx290 { 227 struct device *dev; 228 struct clk *xclk; 229 struct regmap *regmap; 230 enum imx290_clk_freq xclk_idx; 231 u8 nlanes; 232 const struct imx290_model_info *model; 233 234 struct v4l2_subdev sd; 235 struct media_pad pad; 236 237 const struct imx290_mode *current_mode; 238 239 struct regulator_bulk_data supplies[IMX290_NUM_SUPPLIES]; 240 struct gpio_desc *rst_gpio; 241 242 struct v4l2_ctrl_handler ctrls; 243 struct v4l2_ctrl *link_freq; 244 struct v4l2_ctrl *hblank; 245 struct v4l2_ctrl *vblank; 246 struct v4l2_ctrl *exposure; 247 struct { 248 struct v4l2_ctrl *hflip; 249 struct v4l2_ctrl *vflip; 250 }; 251 }; 252 253 static inline struct imx290 *to_imx290(struct v4l2_subdev *_sd) 254 { 255 return container_of(_sd, struct imx290, sd); 256 } 257 258 /* ----------------------------------------------------------------------------- 259 * Modes and formats 260 */ 261 262 static const struct cci_reg_sequence imx290_global_init_settings[] = { 263 { IMX290_WINWV_OB, 12 }, 264 { IMX290_WINPH, 0 }, 265 { IMX290_WINPV, 0 }, 266 { IMX290_WINWH, 1948 }, 267 { IMX290_WINWV, 1097 }, 268 { IMX290_XSOUTSEL, IMX290_XSOUTSEL_XVSOUTSEL_VSYNC | 269 IMX290_XSOUTSEL_XHSOUTSEL_HSYNC }, 270 { CCI_REG8(0x3011), 0x02 }, 271 { CCI_REG8(0x3012), 0x64 }, 272 { CCI_REG8(0x3013), 0x00 }, 273 }; 274 275 static const struct cci_reg_sequence imx290_global_init_settings_290[] = { 276 { CCI_REG8(0x300f), 0x00 }, 277 { CCI_REG8(0x3010), 0x21 }, 278 { CCI_REG8(0x3016), 0x09 }, 279 { CCI_REG8(0x3070), 0x02 }, 280 { CCI_REG8(0x3071), 0x11 }, 281 { CCI_REG8(0x309b), 0x10 }, 282 { CCI_REG8(0x309c), 0x22 }, 283 { CCI_REG8(0x30a2), 0x02 }, 284 { CCI_REG8(0x30a6), 0x20 }, 285 { CCI_REG8(0x30a8), 0x20 }, 286 { CCI_REG8(0x30aa), 0x20 }, 287 { CCI_REG8(0x30ac), 0x20 }, 288 { CCI_REG8(0x30b0), 0x43 }, 289 { CCI_REG8(0x3119), 0x9e }, 290 { CCI_REG8(0x311c), 0x1e }, 291 { CCI_REG8(0x311e), 0x08 }, 292 { CCI_REG8(0x3128), 0x05 }, 293 { CCI_REG8(0x313d), 0x83 }, 294 { CCI_REG8(0x3150), 0x03 }, 295 { CCI_REG8(0x317e), 0x00 }, 296 { CCI_REG8(0x32b8), 0x50 }, 297 { CCI_REG8(0x32b9), 0x10 }, 298 { CCI_REG8(0x32ba), 0x00 }, 299 { CCI_REG8(0x32bb), 0x04 }, 300 { CCI_REG8(0x32c8), 0x50 }, 301 { CCI_REG8(0x32c9), 0x10 }, 302 { CCI_REG8(0x32ca), 0x00 }, 303 { CCI_REG8(0x32cb), 0x04 }, 304 { CCI_REG8(0x332c), 0xd3 }, 305 { CCI_REG8(0x332d), 0x10 }, 306 { CCI_REG8(0x332e), 0x0d }, 307 { CCI_REG8(0x3358), 0x06 }, 308 { CCI_REG8(0x3359), 0xe1 }, 309 { CCI_REG8(0x335a), 0x11 }, 310 { CCI_REG8(0x3360), 0x1e }, 311 { CCI_REG8(0x3361), 0x61 }, 312 { CCI_REG8(0x3362), 0x10 }, 313 { CCI_REG8(0x33b0), 0x50 }, 314 { CCI_REG8(0x33b2), 0x1a }, 315 { CCI_REG8(0x33b3), 0x04 }, 316 }; 317 318 #define IMX290_NUM_CLK_REGS 2 319 static const struct cci_reg_sequence xclk_regs[][IMX290_NUM_CLK_REGS] = { 320 [IMX290_CLK_37_125] = { 321 { IMX290_EXTCK_FREQ, (37125 * 256) / 1000 }, 322 { IMX290_INCKSEL7, 0x49 }, 323 }, 324 [IMX290_CLK_74_25] = { 325 { IMX290_EXTCK_FREQ, (74250 * 256) / 1000 }, 326 { IMX290_INCKSEL7, 0x92 }, 327 }, 328 }; 329 330 static const struct cci_reg_sequence imx290_global_init_settings_327[] = { 331 { CCI_REG8(0x309e), 0x4A }, 332 { CCI_REG8(0x309f), 0x4A }, 333 { CCI_REG8(0x313b), 0x61 }, 334 }; 335 336 static const struct cci_reg_sequence imx290_1080p_settings[] = { 337 /* mode settings */ 338 { IMX290_WINWV_OB, 12 }, 339 { IMX290_OPB_SIZE_V, 10 }, 340 { IMX290_X_OUT_SIZE, 1920 }, 341 { IMX290_Y_OUT_SIZE, 1080 }, 342 }; 343 344 static const struct cci_reg_sequence imx290_720p_settings[] = { 345 /* mode settings */ 346 { IMX290_WINWV_OB, 6 }, 347 { IMX290_OPB_SIZE_V, 4 }, 348 { IMX290_X_OUT_SIZE, 1280 }, 349 { IMX290_Y_OUT_SIZE, 720 }, 350 }; 351 352 static const struct cci_reg_sequence imx290_10bit_settings[] = { 353 { IMX290_ADBIT, IMX290_ADBIT_10BIT }, 354 { IMX290_OUT_CTRL, IMX290_ODBIT_10BIT }, 355 { IMX290_ADBIT1, IMX290_ADBIT1_10BIT }, 356 { IMX290_ADBIT2, IMX290_ADBIT2_10BIT }, 357 { IMX290_ADBIT3, IMX290_ADBIT3_10BIT }, 358 { IMX290_CSI_DT_FMT, IMX290_CSI_DT_FMT_RAW10 }, 359 }; 360 361 static const struct cci_reg_sequence imx290_12bit_settings[] = { 362 { IMX290_ADBIT, IMX290_ADBIT_12BIT }, 363 { IMX290_OUT_CTRL, IMX290_ODBIT_12BIT }, 364 { IMX290_ADBIT1, IMX290_ADBIT1_12BIT }, 365 { IMX290_ADBIT2, IMX290_ADBIT2_12BIT }, 366 { IMX290_ADBIT3, IMX290_ADBIT3_12BIT }, 367 { IMX290_CSI_DT_FMT, IMX290_CSI_DT_FMT_RAW12 }, 368 }; 369 370 static const struct imx290_csi_cfg imx290_csi_222_75mhz = { 371 /* 222.75MHz or 445.5Mbit/s per lane */ 372 .repetition = 0x10, 373 .tclkpost = 87, 374 .thszero = 55, 375 .thsprepare = 31, 376 .tclktrail = 31, 377 .thstrail = 31, 378 .tclkzero = 119, 379 .tclkprepare = 31, 380 .tlpx = 23, 381 }; 382 383 static const struct imx290_csi_cfg imx290_csi_445_5mhz = { 384 /* 445.5MHz or 891Mbit/s per lane */ 385 .repetition = 0x00, 386 .tclkpost = 119, 387 .thszero = 103, 388 .thsprepare = 71, 389 .tclktrail = 55, 390 .thstrail = 63, 391 .tclkzero = 255, 392 .tclkprepare = 63, 393 .tlpx = 55, 394 }; 395 396 static const struct imx290_csi_cfg imx290_csi_148_5mhz = { 397 /* 148.5MHz or 297Mbit/s per lane */ 398 .repetition = 0x10, 399 .tclkpost = 79, 400 .thszero = 47, 401 .thsprepare = 23, 402 .tclktrail = 23, 403 .thstrail = 23, 404 .tclkzero = 87, 405 .tclkprepare = 23, 406 .tlpx = 23, 407 }; 408 409 static const struct imx290_csi_cfg imx290_csi_297mhz = { 410 /* 297MHz or 594Mbit/s per lane */ 411 .repetition = 0x00, 412 .tclkpost = 103, 413 .thszero = 87, 414 .thsprepare = 47, 415 .tclktrail = 39, 416 .thstrail = 47, 417 .tclkzero = 191, 418 .tclkprepare = 47, 419 .tlpx = 39, 420 }; 421 422 /* supported link frequencies */ 423 #define FREQ_INDEX_1080P 0 424 #define FREQ_INDEX_720P 1 425 static const s64 imx290_link_freq_2lanes[] = { 426 [FREQ_INDEX_1080P] = 445500000, 427 [FREQ_INDEX_720P] = 297000000, 428 }; 429 430 static const s64 imx290_link_freq_4lanes[] = { 431 [FREQ_INDEX_1080P] = 222750000, 432 [FREQ_INDEX_720P] = 148500000, 433 }; 434 435 /* 436 * In this function and in the similar ones below We rely on imx290_probe() 437 * to ensure that nlanes is either 2 or 4. 438 */ 439 static inline const s64 *imx290_link_freqs_ptr(const struct imx290 *imx290) 440 { 441 if (imx290->nlanes == 2) 442 return imx290_link_freq_2lanes; 443 else 444 return imx290_link_freq_4lanes; 445 } 446 447 static inline int imx290_link_freqs_num(const struct imx290 *imx290) 448 { 449 if (imx290->nlanes == 2) 450 return ARRAY_SIZE(imx290_link_freq_2lanes); 451 else 452 return ARRAY_SIZE(imx290_link_freq_4lanes); 453 } 454 455 static const struct imx290_clk_cfg imx290_1080p_clock_config[] = { 456 [IMX290_CLK_37_125] = { 457 /* 37.125MHz clock config */ 458 .incksel1 = 0x18, 459 .incksel2 = 0x03, 460 .incksel3 = 0x20, 461 .incksel4 = 0x01, 462 .incksel5 = 0x1a, 463 .incksel6 = 0x1a, 464 }, 465 [IMX290_CLK_74_25] = { 466 /* 74.25MHz clock config */ 467 .incksel1 = 0x0c, 468 .incksel2 = 0x03, 469 .incksel3 = 0x10, 470 .incksel4 = 0x01, 471 .incksel5 = 0x1b, 472 .incksel6 = 0x1b, 473 }, 474 }; 475 476 static const struct imx290_clk_cfg imx290_720p_clock_config[] = { 477 [IMX290_CLK_37_125] = { 478 /* 37.125MHz clock config */ 479 .incksel1 = 0x20, 480 .incksel2 = 0x00, 481 .incksel3 = 0x20, 482 .incksel4 = 0x01, 483 .incksel5 = 0x1a, 484 .incksel6 = 0x1a, 485 }, 486 [IMX290_CLK_74_25] = { 487 /* 74.25MHz clock config */ 488 .incksel1 = 0x10, 489 .incksel2 = 0x00, 490 .incksel3 = 0x10, 491 .incksel4 = 0x01, 492 .incksel5 = 0x1b, 493 .incksel6 = 0x1b, 494 }, 495 }; 496 497 /* Mode configs */ 498 static const struct imx290_mode imx290_modes_2lanes[] = { 499 { 500 .width = 1920, 501 .height = 1080, 502 .hmax_min = 2200, 503 .vmax_min = 1125, 504 .link_freq_index = FREQ_INDEX_1080P, 505 .ctrl_07 = IMX290_WINMODE_1080P, 506 .data = imx290_1080p_settings, 507 .data_size = ARRAY_SIZE(imx290_1080p_settings), 508 .clk_cfg = imx290_1080p_clock_config, 509 }, 510 { 511 .width = 1280, 512 .height = 720, 513 .hmax_min = 3300, 514 .vmax_min = 750, 515 .link_freq_index = FREQ_INDEX_720P, 516 .ctrl_07 = IMX290_WINMODE_720P, 517 .data = imx290_720p_settings, 518 .data_size = ARRAY_SIZE(imx290_720p_settings), 519 .clk_cfg = imx290_720p_clock_config, 520 }, 521 }; 522 523 static const struct imx290_mode imx290_modes_4lanes[] = { 524 { 525 .width = 1920, 526 .height = 1080, 527 .hmax_min = 2200, 528 .vmax_min = 1125, 529 .link_freq_index = FREQ_INDEX_1080P, 530 .ctrl_07 = IMX290_WINMODE_1080P, 531 .data = imx290_1080p_settings, 532 .data_size = ARRAY_SIZE(imx290_1080p_settings), 533 .clk_cfg = imx290_1080p_clock_config, 534 }, 535 { 536 .width = 1280, 537 .height = 720, 538 .hmax_min = 3300, 539 .vmax_min = 750, 540 .link_freq_index = FREQ_INDEX_720P, 541 .ctrl_07 = IMX290_WINMODE_720P, 542 .data = imx290_720p_settings, 543 .data_size = ARRAY_SIZE(imx290_720p_settings), 544 .clk_cfg = imx290_720p_clock_config, 545 }, 546 }; 547 548 static inline const struct imx290_mode *imx290_modes_ptr(const struct imx290 *imx290) 549 { 550 if (imx290->nlanes == 2) 551 return imx290_modes_2lanes; 552 else 553 return imx290_modes_4lanes; 554 } 555 556 static inline int imx290_modes_num(const struct imx290 *imx290) 557 { 558 if (imx290->nlanes == 2) 559 return ARRAY_SIZE(imx290_modes_2lanes); 560 else 561 return ARRAY_SIZE(imx290_modes_4lanes); 562 } 563 564 struct imx290_format_info { 565 u32 code[IMX290_VARIANT_MAX]; 566 u8 bpp; 567 const struct cci_reg_sequence *regs; 568 unsigned int num_regs; 569 }; 570 571 static const struct imx290_format_info imx290_formats[] = { 572 { 573 .code = { 574 [IMX290_VARIANT_COLOUR] = MEDIA_BUS_FMT_SRGGB10_1X10, 575 [IMX290_VARIANT_MONO] = MEDIA_BUS_FMT_Y10_1X10 576 }, 577 .bpp = 10, 578 .regs = imx290_10bit_settings, 579 .num_regs = ARRAY_SIZE(imx290_10bit_settings), 580 }, { 581 .code = { 582 [IMX290_VARIANT_COLOUR] = MEDIA_BUS_FMT_SRGGB12_1X12, 583 [IMX290_VARIANT_MONO] = MEDIA_BUS_FMT_Y12_1X12 584 }, 585 .bpp = 12, 586 .regs = imx290_12bit_settings, 587 .num_regs = ARRAY_SIZE(imx290_12bit_settings), 588 } 589 }; 590 591 static const struct imx290_format_info * 592 imx290_format_info(const struct imx290 *imx290, u32 code) 593 { 594 unsigned int i; 595 596 for (i = 0; i < ARRAY_SIZE(imx290_formats); ++i) { 597 const struct imx290_format_info *info = &imx290_formats[i]; 598 599 if (info->code[imx290->model->colour_variant] == code) 600 return info; 601 } 602 603 return NULL; 604 } 605 606 static int imx290_set_register_array(struct imx290 *imx290, 607 const struct cci_reg_sequence *settings, 608 unsigned int num_settings) 609 { 610 int ret; 611 612 ret = cci_multi_reg_write(imx290->regmap, settings, num_settings, NULL); 613 if (ret < 0) 614 return ret; 615 616 /* Provide 10ms settle time */ 617 usleep_range(10000, 11000); 618 619 return 0; 620 } 621 622 static int imx290_set_clock(struct imx290 *imx290) 623 { 624 const struct imx290_mode *mode = imx290->current_mode; 625 enum imx290_clk_freq clk_idx = imx290->xclk_idx; 626 const struct imx290_clk_cfg *clk_cfg = &mode->clk_cfg[clk_idx]; 627 int ret; 628 629 ret = imx290_set_register_array(imx290, xclk_regs[clk_idx], 630 IMX290_NUM_CLK_REGS); 631 632 cci_write(imx290->regmap, IMX290_INCKSEL1, clk_cfg->incksel1, &ret); 633 cci_write(imx290->regmap, IMX290_INCKSEL2, clk_cfg->incksel2, &ret); 634 cci_write(imx290->regmap, IMX290_INCKSEL3, clk_cfg->incksel3, &ret); 635 cci_write(imx290->regmap, IMX290_INCKSEL4, clk_cfg->incksel4, &ret); 636 cci_write(imx290->regmap, IMX290_INCKSEL5, clk_cfg->incksel5, &ret); 637 cci_write(imx290->regmap, IMX290_INCKSEL6, clk_cfg->incksel6, &ret); 638 639 return ret; 640 } 641 642 static int imx290_set_data_lanes(struct imx290 *imx290) 643 { 644 int ret = 0; 645 646 cci_write(imx290->regmap, IMX290_PHY_LANE_NUM, imx290->nlanes - 1, 647 &ret); 648 cci_write(imx290->regmap, IMX290_CSI_LANE_MODE, imx290->nlanes - 1, 649 &ret); 650 cci_write(imx290->regmap, IMX290_FR_FDG_SEL, 0x01, &ret); 651 652 return ret; 653 } 654 655 static int imx290_set_black_level(struct imx290 *imx290, 656 const struct v4l2_mbus_framefmt *format, 657 unsigned int black_level, int *err) 658 { 659 unsigned int bpp = imx290_format_info(imx290, format->code)->bpp; 660 661 return cci_write(imx290->regmap, IMX290_BLKLEVEL, 662 black_level >> (16 - bpp), err); 663 } 664 665 static int imx290_set_csi_config(struct imx290 *imx290) 666 { 667 const s64 *link_freqs = imx290_link_freqs_ptr(imx290); 668 const struct imx290_csi_cfg *csi_cfg; 669 int ret = 0; 670 671 switch (link_freqs[imx290->current_mode->link_freq_index]) { 672 case 445500000: 673 csi_cfg = &imx290_csi_445_5mhz; 674 break; 675 case 297000000: 676 csi_cfg = &imx290_csi_297mhz; 677 break; 678 case 222750000: 679 csi_cfg = &imx290_csi_222_75mhz; 680 break; 681 case 148500000: 682 csi_cfg = &imx290_csi_148_5mhz; 683 break; 684 default: 685 return -EINVAL; 686 } 687 688 cci_write(imx290->regmap, IMX290_REPETITION, csi_cfg->repetition, &ret); 689 cci_write(imx290->regmap, IMX290_TCLKPOST, csi_cfg->tclkpost, &ret); 690 cci_write(imx290->regmap, IMX290_THSZERO, csi_cfg->thszero, &ret); 691 cci_write(imx290->regmap, IMX290_THSPREPARE, csi_cfg->thsprepare, &ret); 692 cci_write(imx290->regmap, IMX290_TCLKTRAIL, csi_cfg->tclktrail, &ret); 693 cci_write(imx290->regmap, IMX290_THSTRAIL, csi_cfg->thstrail, &ret); 694 cci_write(imx290->regmap, IMX290_TCLKZERO, csi_cfg->tclkzero, &ret); 695 cci_write(imx290->regmap, IMX290_TCLKPREPARE, csi_cfg->tclkprepare, 696 &ret); 697 cci_write(imx290->regmap, IMX290_TLPX, csi_cfg->tlpx, &ret); 698 699 return ret; 700 } 701 702 static int imx290_setup_format(struct imx290 *imx290, 703 const struct v4l2_mbus_framefmt *format) 704 { 705 const struct imx290_format_info *info; 706 int ret; 707 708 info = imx290_format_info(imx290, format->code); 709 710 ret = imx290_set_register_array(imx290, info->regs, info->num_regs); 711 if (ret < 0) { 712 dev_err(imx290->dev, "Could not set format registers\n"); 713 return ret; 714 } 715 716 return imx290_set_black_level(imx290, format, 717 IMX290_BLACK_LEVEL_DEFAULT, &ret); 718 } 719 720 /* ---------------------------------------------------------------------------- 721 * Controls 722 */ 723 static void imx290_exposure_update(struct imx290 *imx290, 724 const struct imx290_mode *mode) 725 { 726 unsigned int exposure_max; 727 728 exposure_max = imx290->vblank->val + mode->height - 729 IMX290_EXPOSURE_OFFSET; 730 __v4l2_ctrl_modify_range(imx290->exposure, 1, exposure_max, 1, 731 exposure_max); 732 } 733 734 static int imx290_set_ctrl(struct v4l2_ctrl *ctrl) 735 { 736 struct imx290 *imx290 = container_of(ctrl->handler, 737 struct imx290, ctrls); 738 const struct v4l2_mbus_framefmt *format; 739 struct v4l2_subdev_state *state; 740 int ret = 0, vmax; 741 742 /* 743 * Return immediately for controls that don't need to be applied to the 744 * device. 745 */ 746 if (ctrl->flags & V4L2_CTRL_FLAG_READ_ONLY) 747 return 0; 748 749 if (ctrl->id == V4L2_CID_VBLANK) { 750 /* Changing vblank changes the allowed range for exposure. */ 751 imx290_exposure_update(imx290, imx290->current_mode); 752 } 753 754 /* V4L2 controls values will be applied only when power is already up */ 755 if (!pm_runtime_get_if_in_use(imx290->dev)) 756 return 0; 757 758 state = v4l2_subdev_get_locked_active_state(&imx290->sd); 759 format = v4l2_subdev_state_get_format(state, 0); 760 761 switch (ctrl->id) { 762 case V4L2_CID_ANALOGUE_GAIN: 763 ret = cci_write(imx290->regmap, IMX290_GAIN, ctrl->val, NULL); 764 break; 765 766 case V4L2_CID_VBLANK: 767 ret = cci_write(imx290->regmap, IMX290_VMAX, 768 ctrl->val + imx290->current_mode->height, NULL); 769 /* 770 * Due to the way that exposure is programmed in this sensor in 771 * relation to VMAX, we have to reprogramme it whenever VMAX is 772 * changed. 773 * Update ctrl so that the V4L2_CID_EXPOSURE case can refer to 774 * it. 775 */ 776 ctrl = imx290->exposure; 777 fallthrough; 778 case V4L2_CID_EXPOSURE: 779 vmax = imx290->vblank->val + imx290->current_mode->height; 780 ret = cci_write(imx290->regmap, IMX290_SHS1, 781 vmax - ctrl->val - 1, NULL); 782 break; 783 784 case V4L2_CID_TEST_PATTERN: 785 if (ctrl->val) { 786 imx290_set_black_level(imx290, format, 0, &ret); 787 usleep_range(10000, 11000); 788 cci_write(imx290->regmap, IMX290_PGCTRL, 789 (u8)(IMX290_PGCTRL_REGEN | 790 IMX290_PGCTRL_THRU | 791 IMX290_PGCTRL_MODE(ctrl->val)), &ret); 792 } else { 793 cci_write(imx290->regmap, IMX290_PGCTRL, 0x00, &ret); 794 usleep_range(10000, 11000); 795 imx290_set_black_level(imx290, format, 796 IMX290_BLACK_LEVEL_DEFAULT, &ret); 797 } 798 break; 799 800 case V4L2_CID_HBLANK: 801 ret = cci_write(imx290->regmap, IMX290_HMAX, 802 ctrl->val + imx290->current_mode->width, NULL); 803 break; 804 805 case V4L2_CID_HFLIP: 806 case V4L2_CID_VFLIP: 807 { 808 u32 reg; 809 810 reg = imx290->current_mode->ctrl_07; 811 if (imx290->hflip->val) 812 reg |= IMX290_HREVERSE; 813 if (imx290->vflip->val) 814 reg |= IMX290_VREVERSE; 815 ret = cci_write(imx290->regmap, IMX290_CTRL_07, reg, NULL); 816 break; 817 } 818 819 default: 820 ret = -EINVAL; 821 break; 822 } 823 824 pm_runtime_mark_last_busy(imx290->dev); 825 pm_runtime_put_autosuspend(imx290->dev); 826 827 return ret; 828 } 829 830 static const struct v4l2_ctrl_ops imx290_ctrl_ops = { 831 .s_ctrl = imx290_set_ctrl, 832 }; 833 834 static const char * const imx290_test_pattern_menu[] = { 835 "Disabled", 836 "Sequence Pattern 1", 837 "Horizontal Color-bar Chart", 838 "Vertical Color-bar Chart", 839 "Sequence Pattern 2", 840 "Gradation Pattern 1", 841 "Gradation Pattern 2", 842 "000/555h Toggle Pattern", 843 }; 844 845 static void imx290_ctrl_update(struct imx290 *imx290, 846 const struct imx290_mode *mode) 847 { 848 unsigned int hblank_min = mode->hmax_min - mode->width; 849 unsigned int hblank_max = IMX290_HMAX_MAX - mode->width; 850 unsigned int vblank_min = mode->vmax_min - mode->height; 851 unsigned int vblank_max = IMX290_VMAX_MAX - mode->height; 852 853 __v4l2_ctrl_s_ctrl(imx290->link_freq, mode->link_freq_index); 854 855 __v4l2_ctrl_modify_range(imx290->hblank, hblank_min, hblank_max, 1, 856 hblank_min); 857 __v4l2_ctrl_modify_range(imx290->vblank, vblank_min, vblank_max, 1, 858 vblank_min); 859 } 860 861 static int imx290_ctrl_init(struct imx290 *imx290) 862 { 863 struct v4l2_fwnode_device_properties props; 864 int ret; 865 866 ret = v4l2_fwnode_device_parse(imx290->dev, &props); 867 if (ret < 0) 868 return ret; 869 870 v4l2_ctrl_handler_init(&imx290->ctrls, 11); 871 872 /* 873 * The sensor has an analog gain and a digital gain, both controlled 874 * through a single gain value, expressed in 0.3dB increments. Values 875 * from 0.0dB (0) to 30.0dB (100) apply analog gain only, higher values 876 * up to 72.0dB (240) add further digital gain. Limit the range to 877 * analog gain only, support for digital gain can be added separately 878 * if needed. 879 * 880 * The IMX327 and IMX462 are largely compatible with the IMX290, but 881 * have an analog gain range of 0.0dB to 29.4dB and 42dB of digital 882 * gain. When support for those sensors gets added to the driver, the 883 * gain control should be adjusted accordingly. 884 */ 885 v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 886 V4L2_CID_ANALOGUE_GAIN, 0, 100, 1, 0); 887 888 /* 889 * Correct range will be determined through imx290_ctrl_update setting 890 * V4L2_CID_VBLANK. 891 */ 892 imx290->exposure = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 893 V4L2_CID_EXPOSURE, 1, 65535, 1, 894 65535); 895 896 /* 897 * Set the link frequency, pixel rate, horizontal blanking and vertical 898 * blanking to hardcoded values, they will be updated by 899 * imx290_ctrl_update(). 900 */ 901 imx290->link_freq = 902 v4l2_ctrl_new_int_menu(&imx290->ctrls, &imx290_ctrl_ops, 903 V4L2_CID_LINK_FREQ, 904 imx290_link_freqs_num(imx290) - 1, 0, 905 imx290_link_freqs_ptr(imx290)); 906 if (imx290->link_freq) 907 imx290->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 908 909 v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, V4L2_CID_PIXEL_RATE, 910 IMX290_PIXEL_RATE, IMX290_PIXEL_RATE, 1, 911 IMX290_PIXEL_RATE); 912 913 v4l2_ctrl_new_std_menu_items(&imx290->ctrls, &imx290_ctrl_ops, 914 V4L2_CID_TEST_PATTERN, 915 ARRAY_SIZE(imx290_test_pattern_menu) - 1, 916 0, 0, imx290_test_pattern_menu); 917 918 /* 919 * Actual range will be set from imx290_ctrl_update later in the probe. 920 */ 921 imx290->hblank = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 922 V4L2_CID_HBLANK, 1, 1, 1, 1); 923 924 imx290->vblank = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 925 V4L2_CID_VBLANK, 1, 1, 1, 1); 926 927 imx290->hflip = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 928 V4L2_CID_HFLIP, 0, 1, 1, 0); 929 imx290->vflip = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 930 V4L2_CID_VFLIP, 0, 1, 1, 0); 931 v4l2_ctrl_cluster(2, &imx290->hflip); 932 933 v4l2_ctrl_new_fwnode_properties(&imx290->ctrls, &imx290_ctrl_ops, 934 &props); 935 936 imx290->sd.ctrl_handler = &imx290->ctrls; 937 938 if (imx290->ctrls.error) { 939 ret = imx290->ctrls.error; 940 v4l2_ctrl_handler_free(&imx290->ctrls); 941 return ret; 942 } 943 944 return 0; 945 } 946 947 /* ---------------------------------------------------------------------------- 948 * Subdev operations 949 */ 950 951 /* Start streaming */ 952 static int imx290_start_streaming(struct imx290 *imx290, 953 struct v4l2_subdev_state *state) 954 { 955 const struct v4l2_mbus_framefmt *format; 956 int ret; 957 958 /* Set init register settings */ 959 ret = imx290_set_register_array(imx290, imx290_global_init_settings, 960 ARRAY_SIZE(imx290_global_init_settings)); 961 if (ret < 0) { 962 dev_err(imx290->dev, "Could not set init registers\n"); 963 return ret; 964 } 965 966 /* Set mdel specific init register settings */ 967 ret = imx290_set_register_array(imx290, imx290->model->init_regs, 968 imx290->model->init_regs_num); 969 if (ret < 0) { 970 dev_err(imx290->dev, "Could not set model specific init registers\n"); 971 return ret; 972 } 973 974 /* Set clock parameters based on mode and xclk */ 975 ret = imx290_set_clock(imx290); 976 if (ret < 0) { 977 dev_err(imx290->dev, "Could not set clocks - %d\n", ret); 978 return ret; 979 } 980 981 /* Set data lane count */ 982 ret = imx290_set_data_lanes(imx290); 983 if (ret < 0) { 984 dev_err(imx290->dev, "Could not set data lanes - %d\n", ret); 985 return ret; 986 } 987 988 ret = imx290_set_csi_config(imx290); 989 if (ret < 0) { 990 dev_err(imx290->dev, "Could not set csi cfg - %d\n", ret); 991 return ret; 992 } 993 994 /* Apply the register values related to current frame format */ 995 format = v4l2_subdev_state_get_format(state, 0); 996 ret = imx290_setup_format(imx290, format); 997 if (ret < 0) { 998 dev_err(imx290->dev, "Could not set frame format - %d\n", ret); 999 return ret; 1000 } 1001 1002 /* Apply default values of current mode */ 1003 ret = imx290_set_register_array(imx290, imx290->current_mode->data, 1004 imx290->current_mode->data_size); 1005 if (ret < 0) { 1006 dev_err(imx290->dev, "Could not set current mode - %d\n", ret); 1007 return ret; 1008 } 1009 1010 /* Apply customized values from user */ 1011 ret = __v4l2_ctrl_handler_setup(imx290->sd.ctrl_handler); 1012 if (ret) { 1013 dev_err(imx290->dev, "Could not sync v4l2 controls - %d\n", ret); 1014 return ret; 1015 } 1016 1017 cci_write(imx290->regmap, IMX290_STANDBY, 0x00, &ret); 1018 1019 msleep(30); 1020 1021 /* Start streaming */ 1022 return cci_write(imx290->regmap, IMX290_XMSTA, 0x00, &ret); 1023 } 1024 1025 /* Stop streaming */ 1026 static int imx290_stop_streaming(struct imx290 *imx290) 1027 { 1028 int ret = 0; 1029 1030 cci_write(imx290->regmap, IMX290_STANDBY, 0x01, &ret); 1031 1032 msleep(30); 1033 1034 return cci_write(imx290->regmap, IMX290_XMSTA, 0x01, &ret); 1035 } 1036 1037 static int imx290_set_stream(struct v4l2_subdev *sd, int enable) 1038 { 1039 struct imx290 *imx290 = to_imx290(sd); 1040 struct v4l2_subdev_state *state; 1041 int ret = 0; 1042 1043 state = v4l2_subdev_lock_and_get_active_state(sd); 1044 1045 if (enable) { 1046 ret = pm_runtime_resume_and_get(imx290->dev); 1047 if (ret < 0) 1048 goto unlock; 1049 1050 ret = imx290_start_streaming(imx290, state); 1051 if (ret) { 1052 dev_err(imx290->dev, "Start stream failed\n"); 1053 pm_runtime_put_sync(imx290->dev); 1054 goto unlock; 1055 } 1056 } else { 1057 imx290_stop_streaming(imx290); 1058 pm_runtime_mark_last_busy(imx290->dev); 1059 pm_runtime_put_autosuspend(imx290->dev); 1060 } 1061 1062 /* 1063 * vflip and hflip should not be changed during streaming as the sensor 1064 * will produce an invalid frame. 1065 */ 1066 __v4l2_ctrl_grab(imx290->vflip, enable); 1067 __v4l2_ctrl_grab(imx290->hflip, enable); 1068 1069 unlock: 1070 v4l2_subdev_unlock_state(state); 1071 return ret; 1072 } 1073 1074 static int imx290_enum_mbus_code(struct v4l2_subdev *sd, 1075 struct v4l2_subdev_state *sd_state, 1076 struct v4l2_subdev_mbus_code_enum *code) 1077 { 1078 const struct imx290 *imx290 = to_imx290(sd); 1079 1080 if (code->index >= ARRAY_SIZE(imx290_formats)) 1081 return -EINVAL; 1082 1083 code->code = imx290_formats[code->index].code[imx290->model->colour_variant]; 1084 1085 return 0; 1086 } 1087 1088 static int imx290_enum_frame_size(struct v4l2_subdev *sd, 1089 struct v4l2_subdev_state *sd_state, 1090 struct v4l2_subdev_frame_size_enum *fse) 1091 { 1092 const struct imx290 *imx290 = to_imx290(sd); 1093 const struct imx290_mode *imx290_modes = imx290_modes_ptr(imx290); 1094 1095 if (!imx290_format_info(imx290, fse->code)) 1096 return -EINVAL; 1097 1098 if (fse->index >= imx290_modes_num(imx290)) 1099 return -EINVAL; 1100 1101 fse->min_width = imx290_modes[fse->index].width; 1102 fse->max_width = imx290_modes[fse->index].width; 1103 fse->min_height = imx290_modes[fse->index].height; 1104 fse->max_height = imx290_modes[fse->index].height; 1105 1106 return 0; 1107 } 1108 1109 static int imx290_set_fmt(struct v4l2_subdev *sd, 1110 struct v4l2_subdev_state *sd_state, 1111 struct v4l2_subdev_format *fmt) 1112 { 1113 struct imx290 *imx290 = to_imx290(sd); 1114 const struct imx290_mode *mode; 1115 struct v4l2_mbus_framefmt *format; 1116 1117 mode = v4l2_find_nearest_size(imx290_modes_ptr(imx290), 1118 imx290_modes_num(imx290), width, height, 1119 fmt->format.width, fmt->format.height); 1120 1121 fmt->format.width = mode->width; 1122 fmt->format.height = mode->height; 1123 1124 if (!imx290_format_info(imx290, fmt->format.code)) 1125 fmt->format.code = imx290_formats[0].code[imx290->model->colour_variant]; 1126 1127 fmt->format.field = V4L2_FIELD_NONE; 1128 fmt->format.colorspace = V4L2_COLORSPACE_RAW; 1129 fmt->format.ycbcr_enc = V4L2_YCBCR_ENC_601; 1130 fmt->format.quantization = V4L2_QUANTIZATION_FULL_RANGE; 1131 fmt->format.xfer_func = V4L2_XFER_FUNC_NONE; 1132 1133 format = v4l2_subdev_state_get_format(sd_state, 0); 1134 1135 if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 1136 imx290->current_mode = mode; 1137 1138 imx290_ctrl_update(imx290, mode); 1139 imx290_exposure_update(imx290, mode); 1140 } 1141 1142 *format = fmt->format; 1143 1144 return 0; 1145 } 1146 1147 static int imx290_get_selection(struct v4l2_subdev *sd, 1148 struct v4l2_subdev_state *sd_state, 1149 struct v4l2_subdev_selection *sel) 1150 { 1151 struct imx290 *imx290 = to_imx290(sd); 1152 struct v4l2_mbus_framefmt *format; 1153 1154 switch (sel->target) { 1155 case V4L2_SEL_TGT_CROP: { 1156 format = v4l2_subdev_state_get_format(sd_state, 0); 1157 1158 /* 1159 * The sensor moves the readout by 1 pixel based on flips to 1160 * keep the Bayer order the same. 1161 */ 1162 sel->r.top = IMX290_PIXEL_ARRAY_MARGIN_TOP 1163 + (IMX290_PIXEL_ARRAY_RECORDING_HEIGHT - format->height) / 2 1164 + imx290->vflip->val; 1165 sel->r.left = IMX290_PIXEL_ARRAY_MARGIN_LEFT 1166 + (IMX290_PIXEL_ARRAY_RECORDING_WIDTH - format->width) / 2 1167 + imx290->hflip->val; 1168 sel->r.width = format->width; 1169 sel->r.height = format->height; 1170 1171 return 0; 1172 } 1173 1174 case V4L2_SEL_TGT_NATIVE_SIZE: 1175 case V4L2_SEL_TGT_CROP_BOUNDS: 1176 sel->r.top = 0; 1177 sel->r.left = 0; 1178 sel->r.width = IMX290_PIXEL_ARRAY_WIDTH; 1179 sel->r.height = IMX290_PIXEL_ARRAY_HEIGHT; 1180 1181 return 0; 1182 1183 case V4L2_SEL_TGT_CROP_DEFAULT: 1184 sel->r.top = IMX290_PIXEL_ARRAY_MARGIN_TOP; 1185 sel->r.left = IMX290_PIXEL_ARRAY_MARGIN_LEFT; 1186 sel->r.width = IMX290_PIXEL_ARRAY_RECORDING_WIDTH; 1187 sel->r.height = IMX290_PIXEL_ARRAY_RECORDING_HEIGHT; 1188 1189 return 0; 1190 1191 default: 1192 return -EINVAL; 1193 } 1194 } 1195 1196 static int imx290_entity_init_state(struct v4l2_subdev *subdev, 1197 struct v4l2_subdev_state *sd_state) 1198 { 1199 struct v4l2_subdev_format fmt = { 1200 .which = V4L2_SUBDEV_FORMAT_TRY, 1201 .format = { 1202 .width = 1920, 1203 .height = 1080, 1204 }, 1205 }; 1206 1207 imx290_set_fmt(subdev, sd_state, &fmt); 1208 1209 return 0; 1210 } 1211 1212 static const struct v4l2_subdev_video_ops imx290_video_ops = { 1213 .s_stream = imx290_set_stream, 1214 }; 1215 1216 static const struct v4l2_subdev_pad_ops imx290_pad_ops = { 1217 .enum_mbus_code = imx290_enum_mbus_code, 1218 .enum_frame_size = imx290_enum_frame_size, 1219 .get_fmt = v4l2_subdev_get_fmt, 1220 .set_fmt = imx290_set_fmt, 1221 .get_selection = imx290_get_selection, 1222 }; 1223 1224 static const struct v4l2_subdev_ops imx290_subdev_ops = { 1225 .video = &imx290_video_ops, 1226 .pad = &imx290_pad_ops, 1227 }; 1228 1229 static const struct v4l2_subdev_internal_ops imx290_internal_ops = { 1230 .init_state = imx290_entity_init_state, 1231 }; 1232 1233 static const struct media_entity_operations imx290_subdev_entity_ops = { 1234 .link_validate = v4l2_subdev_link_validate, 1235 }; 1236 1237 static int imx290_subdev_init(struct imx290 *imx290) 1238 { 1239 struct i2c_client *client = to_i2c_client(imx290->dev); 1240 struct v4l2_subdev_state *state; 1241 int ret; 1242 1243 imx290->current_mode = &imx290_modes_ptr(imx290)[0]; 1244 1245 /* 1246 * After linking the subdev with the imx290 instance, we are allowed to 1247 * use the pm_runtime functions. Decrease the PM usage count. The device 1248 * will get suspended after the autosuspend delay, turning the power 1249 * off. However, the communication happening in imx290_ctrl_update() 1250 * will already be prevented even before the delay. 1251 */ 1252 v4l2_i2c_subdev_init(&imx290->sd, client, &imx290_subdev_ops); 1253 imx290->sd.dev = imx290->dev; 1254 pm_runtime_mark_last_busy(imx290->dev); 1255 pm_runtime_put_autosuspend(imx290->dev); 1256 1257 imx290->sd.internal_ops = &imx290_internal_ops; 1258 imx290->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1259 imx290->sd.entity.ops = &imx290_subdev_entity_ops; 1260 imx290->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1261 1262 imx290->pad.flags = MEDIA_PAD_FL_SOURCE; 1263 ret = media_entity_pads_init(&imx290->sd.entity, 1, &imx290->pad); 1264 if (ret < 0) { 1265 dev_err(imx290->dev, "Could not register media entity\n"); 1266 return ret; 1267 } 1268 1269 ret = imx290_ctrl_init(imx290); 1270 if (ret < 0) { 1271 dev_err(imx290->dev, "Control initialization error %d\n", ret); 1272 goto err_media; 1273 } 1274 1275 imx290->sd.state_lock = imx290->ctrls.lock; 1276 1277 ret = v4l2_subdev_init_finalize(&imx290->sd); 1278 if (ret < 0) { 1279 dev_err(imx290->dev, "subdev initialization error %d\n", ret); 1280 goto err_ctrls; 1281 } 1282 1283 state = v4l2_subdev_lock_and_get_active_state(&imx290->sd); 1284 imx290_ctrl_update(imx290, imx290->current_mode); 1285 v4l2_subdev_unlock_state(state); 1286 1287 return 0; 1288 1289 err_ctrls: 1290 v4l2_ctrl_handler_free(&imx290->ctrls); 1291 err_media: 1292 media_entity_cleanup(&imx290->sd.entity); 1293 return ret; 1294 } 1295 1296 static void imx290_subdev_cleanup(struct imx290 *imx290) 1297 { 1298 v4l2_subdev_cleanup(&imx290->sd); 1299 media_entity_cleanup(&imx290->sd.entity); 1300 v4l2_ctrl_handler_free(&imx290->ctrls); 1301 } 1302 1303 /* ---------------------------------------------------------------------------- 1304 * Power management 1305 */ 1306 1307 static int imx290_power_on(struct imx290 *imx290) 1308 { 1309 int ret; 1310 1311 ret = clk_prepare_enable(imx290->xclk); 1312 if (ret) { 1313 dev_err(imx290->dev, "Failed to enable clock\n"); 1314 return ret; 1315 } 1316 1317 ret = regulator_bulk_enable(ARRAY_SIZE(imx290->supplies), 1318 imx290->supplies); 1319 if (ret) { 1320 dev_err(imx290->dev, "Failed to enable regulators\n"); 1321 clk_disable_unprepare(imx290->xclk); 1322 return ret; 1323 } 1324 1325 usleep_range(1, 2); 1326 gpiod_set_value_cansleep(imx290->rst_gpio, 0); 1327 usleep_range(30000, 31000); 1328 1329 return 0; 1330 } 1331 1332 static void imx290_power_off(struct imx290 *imx290) 1333 { 1334 clk_disable_unprepare(imx290->xclk); 1335 gpiod_set_value_cansleep(imx290->rst_gpio, 1); 1336 regulator_bulk_disable(ARRAY_SIZE(imx290->supplies), imx290->supplies); 1337 } 1338 1339 static int imx290_runtime_resume(struct device *dev) 1340 { 1341 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1342 struct imx290 *imx290 = to_imx290(sd); 1343 1344 return imx290_power_on(imx290); 1345 } 1346 1347 static int imx290_runtime_suspend(struct device *dev) 1348 { 1349 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1350 struct imx290 *imx290 = to_imx290(sd); 1351 1352 imx290_power_off(imx290); 1353 1354 return 0; 1355 } 1356 1357 static const struct dev_pm_ops imx290_pm_ops = { 1358 RUNTIME_PM_OPS(imx290_runtime_suspend, imx290_runtime_resume, NULL) 1359 }; 1360 1361 /* ---------------------------------------------------------------------------- 1362 * Probe & remove 1363 */ 1364 1365 static const char * const imx290_supply_name[IMX290_NUM_SUPPLIES] = { 1366 "vdda", 1367 "vddd", 1368 "vdddo", 1369 }; 1370 1371 static int imx290_get_regulators(struct device *dev, struct imx290 *imx290) 1372 { 1373 unsigned int i; 1374 1375 for (i = 0; i < ARRAY_SIZE(imx290->supplies); i++) 1376 imx290->supplies[i].supply = imx290_supply_name[i]; 1377 1378 return devm_regulator_bulk_get(dev, ARRAY_SIZE(imx290->supplies), 1379 imx290->supplies); 1380 } 1381 1382 static int imx290_init_clk(struct imx290 *imx290) 1383 { 1384 u32 xclk_freq; 1385 int ret; 1386 1387 ret = device_property_read_u32(imx290->dev, "clock-frequency", 1388 &xclk_freq); 1389 if (ret) { 1390 dev_err(imx290->dev, "Could not get xclk frequency\n"); 1391 return ret; 1392 } 1393 1394 /* external clock must be 37.125 MHz or 74.25MHz */ 1395 switch (xclk_freq) { 1396 case 37125000: 1397 imx290->xclk_idx = IMX290_CLK_37_125; 1398 break; 1399 case 74250000: 1400 imx290->xclk_idx = IMX290_CLK_74_25; 1401 break; 1402 default: 1403 dev_err(imx290->dev, "External clock frequency %u is not supported\n", 1404 xclk_freq); 1405 return -EINVAL; 1406 } 1407 1408 ret = clk_set_rate(imx290->xclk, xclk_freq); 1409 if (ret) { 1410 dev_err(imx290->dev, "Could not set xclk frequency\n"); 1411 return ret; 1412 } 1413 1414 return 0; 1415 } 1416 1417 /* 1418 * Returns 0 if all link frequencies used by the driver for the given number 1419 * of MIPI data lanes are mentioned in the device tree, or the value of the 1420 * first missing frequency otherwise. 1421 */ 1422 static s64 imx290_check_link_freqs(const struct imx290 *imx290, 1423 const struct v4l2_fwnode_endpoint *ep) 1424 { 1425 int i, j; 1426 const s64 *freqs = imx290_link_freqs_ptr(imx290); 1427 int freqs_count = imx290_link_freqs_num(imx290); 1428 1429 for (i = 0; i < freqs_count; i++) { 1430 for (j = 0; j < ep->nr_of_link_frequencies; j++) 1431 if (freqs[i] == ep->link_frequencies[j]) 1432 break; 1433 if (j == ep->nr_of_link_frequencies) 1434 return freqs[i]; 1435 } 1436 return 0; 1437 } 1438 1439 static const struct imx290_model_info imx290_models[] = { 1440 [IMX290_MODEL_IMX290LQR] = { 1441 .colour_variant = IMX290_VARIANT_COLOUR, 1442 .init_regs = imx290_global_init_settings_290, 1443 .init_regs_num = ARRAY_SIZE(imx290_global_init_settings_290), 1444 .name = "imx290", 1445 }, 1446 [IMX290_MODEL_IMX290LLR] = { 1447 .colour_variant = IMX290_VARIANT_MONO, 1448 .init_regs = imx290_global_init_settings_290, 1449 .init_regs_num = ARRAY_SIZE(imx290_global_init_settings_290), 1450 .name = "imx290", 1451 }, 1452 [IMX290_MODEL_IMX327LQR] = { 1453 .colour_variant = IMX290_VARIANT_COLOUR, 1454 .init_regs = imx290_global_init_settings_327, 1455 .init_regs_num = ARRAY_SIZE(imx290_global_init_settings_327), 1456 .name = "imx327", 1457 }, 1458 }; 1459 1460 static int imx290_parse_dt(struct imx290 *imx290) 1461 { 1462 /* Only CSI2 is supported for now: */ 1463 struct v4l2_fwnode_endpoint ep = { 1464 .bus_type = V4L2_MBUS_CSI2_DPHY 1465 }; 1466 struct fwnode_handle *endpoint; 1467 int ret; 1468 s64 fq; 1469 1470 imx290->model = of_device_get_match_data(imx290->dev); 1471 1472 endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(imx290->dev), NULL); 1473 if (!endpoint) { 1474 dev_err(imx290->dev, "Endpoint node not found\n"); 1475 return -EINVAL; 1476 } 1477 1478 ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &ep); 1479 fwnode_handle_put(endpoint); 1480 if (ret == -ENXIO) { 1481 dev_err(imx290->dev, "Unsupported bus type, should be CSI2\n"); 1482 goto done; 1483 } else if (ret) { 1484 dev_err(imx290->dev, "Parsing endpoint node failed\n"); 1485 goto done; 1486 } 1487 1488 /* Get number of data lanes */ 1489 imx290->nlanes = ep.bus.mipi_csi2.num_data_lanes; 1490 if (imx290->nlanes != 2 && imx290->nlanes != 4) { 1491 dev_err(imx290->dev, "Invalid data lanes: %d\n", imx290->nlanes); 1492 ret = -EINVAL; 1493 goto done; 1494 } 1495 1496 dev_dbg(imx290->dev, "Using %u data lanes\n", imx290->nlanes); 1497 1498 if (!ep.nr_of_link_frequencies) { 1499 dev_err(imx290->dev, "link-frequency property not found in DT\n"); 1500 ret = -EINVAL; 1501 goto done; 1502 } 1503 1504 /* Check that link frequences for all the modes are in device tree */ 1505 fq = imx290_check_link_freqs(imx290, &ep); 1506 if (fq) { 1507 dev_err(imx290->dev, "Link frequency of %lld is not supported\n", 1508 fq); 1509 ret = -EINVAL; 1510 goto done; 1511 } 1512 1513 ret = 0; 1514 1515 done: 1516 v4l2_fwnode_endpoint_free(&ep); 1517 return ret; 1518 } 1519 1520 static int imx290_probe(struct i2c_client *client) 1521 { 1522 struct device *dev = &client->dev; 1523 struct imx290 *imx290; 1524 int ret; 1525 1526 imx290 = devm_kzalloc(dev, sizeof(*imx290), GFP_KERNEL); 1527 if (!imx290) 1528 return -ENOMEM; 1529 1530 imx290->dev = dev; 1531 imx290->regmap = devm_cci_regmap_init_i2c(client, 16); 1532 if (IS_ERR(imx290->regmap)) { 1533 dev_err(dev, "Unable to initialize I2C\n"); 1534 return -ENODEV; 1535 } 1536 1537 ret = imx290_parse_dt(imx290); 1538 if (ret) 1539 return ret; 1540 1541 /* Acquire resources. */ 1542 imx290->xclk = devm_clk_get(dev, "xclk"); 1543 if (IS_ERR(imx290->xclk)) 1544 return dev_err_probe(dev, PTR_ERR(imx290->xclk), 1545 "Could not get xclk\n"); 1546 1547 ret = imx290_get_regulators(dev, imx290); 1548 if (ret < 0) 1549 return dev_err_probe(dev, ret, "Cannot get regulators\n"); 1550 1551 imx290->rst_gpio = devm_gpiod_get_optional(dev, "reset", 1552 GPIOD_OUT_HIGH); 1553 if (IS_ERR(imx290->rst_gpio)) 1554 return dev_err_probe(dev, PTR_ERR(imx290->rst_gpio), 1555 "Cannot get reset gpio\n"); 1556 1557 /* Initialize external clock frequency. */ 1558 ret = imx290_init_clk(imx290); 1559 if (ret) 1560 return ret; 1561 1562 /* 1563 * Enable power management. The driver supports runtime PM, but needs to 1564 * work when runtime PM is disabled in the kernel. To that end, power 1565 * the sensor on manually here. 1566 */ 1567 ret = imx290_power_on(imx290); 1568 if (ret < 0) { 1569 dev_err(dev, "Could not power on the device\n"); 1570 return ret; 1571 } 1572 1573 /* 1574 * Enable runtime PM with autosuspend. As the device has been powered 1575 * manually, mark it as active, and increase the usage count without 1576 * resuming the device. 1577 */ 1578 pm_runtime_set_active(dev); 1579 pm_runtime_get_noresume(dev); 1580 pm_runtime_enable(dev); 1581 pm_runtime_set_autosuspend_delay(dev, 1000); 1582 pm_runtime_use_autosuspend(dev); 1583 1584 /* 1585 * Make sure the sensor is available, in STANDBY and not streaming 1586 * before the V4L2 subdev is initialized. 1587 */ 1588 ret = imx290_stop_streaming(imx290); 1589 if (ret) { 1590 ret = dev_err_probe(dev, ret, "Could not initialize device\n"); 1591 goto err_pm; 1592 } 1593 1594 /* Initialize the V4L2 subdev. */ 1595 ret = imx290_subdev_init(imx290); 1596 if (ret) 1597 goto err_pm; 1598 1599 v4l2_i2c_subdev_set_name(&imx290->sd, client, 1600 imx290->model->name, NULL); 1601 1602 /* 1603 * Finally, register the V4L2 subdev. This must be done after 1604 * initializing everything as the subdev can be used immediately after 1605 * being registered. 1606 */ 1607 ret = v4l2_async_register_subdev(&imx290->sd); 1608 if (ret < 0) { 1609 dev_err(dev, "Could not register v4l2 device\n"); 1610 goto err_subdev; 1611 } 1612 1613 return 0; 1614 1615 err_subdev: 1616 imx290_subdev_cleanup(imx290); 1617 err_pm: 1618 pm_runtime_disable(dev); 1619 pm_runtime_put_noidle(dev); 1620 imx290_power_off(imx290); 1621 return ret; 1622 } 1623 1624 static void imx290_remove(struct i2c_client *client) 1625 { 1626 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1627 struct imx290 *imx290 = to_imx290(sd); 1628 1629 v4l2_async_unregister_subdev(sd); 1630 imx290_subdev_cleanup(imx290); 1631 1632 /* 1633 * Disable runtime PM. In case runtime PM is disabled in the kernel, 1634 * make sure to turn power off manually. 1635 */ 1636 pm_runtime_disable(imx290->dev); 1637 if (!pm_runtime_status_suspended(imx290->dev)) 1638 imx290_power_off(imx290); 1639 pm_runtime_set_suspended(imx290->dev); 1640 } 1641 1642 static const struct of_device_id imx290_of_match[] = { 1643 { 1644 /* Deprecated - synonym for "sony,imx290lqr" */ 1645 .compatible = "sony,imx290", 1646 .data = &imx290_models[IMX290_MODEL_IMX290LQR], 1647 }, { 1648 .compatible = "sony,imx290lqr", 1649 .data = &imx290_models[IMX290_MODEL_IMX290LQR], 1650 }, { 1651 .compatible = "sony,imx290llr", 1652 .data = &imx290_models[IMX290_MODEL_IMX290LLR], 1653 }, { 1654 .compatible = "sony,imx327lqr", 1655 .data = &imx290_models[IMX290_MODEL_IMX327LQR], 1656 }, 1657 { /* sentinel */ }, 1658 }; 1659 MODULE_DEVICE_TABLE(of, imx290_of_match); 1660 1661 static struct i2c_driver imx290_i2c_driver = { 1662 .probe = imx290_probe, 1663 .remove = imx290_remove, 1664 .driver = { 1665 .name = "imx290", 1666 .pm = pm_ptr(&imx290_pm_ops), 1667 .of_match_table = imx290_of_match, 1668 }, 1669 }; 1670 1671 module_i2c_driver(imx290_i2c_driver); 1672 1673 MODULE_DESCRIPTION("Sony IMX290 CMOS Image Sensor Driver"); 1674 MODULE_AUTHOR("FRAMOS GmbH"); 1675 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>"); 1676 MODULE_LICENSE("GPL v2"); 1677