1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Sony IMX290 CMOS Image Sensor Driver 4 * 5 * Copyright (C) 2019 FRAMOS GmbH. 6 * 7 * Copyright (C) 2019 Linaro Ltd. 8 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/i2c.h> 15 #include <linux/module.h> 16 #include <linux/of_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 21 #include <asm/unaligned.h> 22 23 #include <media/media-entity.h> 24 #include <media/v4l2-ctrls.h> 25 #include <media/v4l2-device.h> 26 #include <media/v4l2-event.h> 27 #include <media/v4l2-fwnode.h> 28 #include <media/v4l2-subdev.h> 29 30 #define IMX290_REG_SIZE_SHIFT 16 31 #define IMX290_REG_ADDR_MASK 0xffff 32 #define IMX290_REG_8BIT(n) ((1U << IMX290_REG_SIZE_SHIFT) | (n)) 33 #define IMX290_REG_16BIT(n) ((2U << IMX290_REG_SIZE_SHIFT) | (n)) 34 #define IMX290_REG_24BIT(n) ((3U << IMX290_REG_SIZE_SHIFT) | (n)) 35 36 #define IMX290_STANDBY IMX290_REG_8BIT(0x3000) 37 #define IMX290_REGHOLD IMX290_REG_8BIT(0x3001) 38 #define IMX290_XMSTA IMX290_REG_8BIT(0x3002) 39 #define IMX290_ADBIT IMX290_REG_8BIT(0x3005) 40 #define IMX290_ADBIT_10BIT (0 << 0) 41 #define IMX290_ADBIT_12BIT (1 << 0) 42 #define IMX290_CTRL_07 IMX290_REG_8BIT(0x3007) 43 #define IMX290_VREVERSE BIT(0) 44 #define IMX290_HREVERSE BIT(1) 45 #define IMX290_WINMODE_1080P (0 << 4) 46 #define IMX290_WINMODE_720P (1 << 4) 47 #define IMX290_WINMODE_CROP (4 << 4) 48 #define IMX290_FR_FDG_SEL IMX290_REG_8BIT(0x3009) 49 #define IMX290_BLKLEVEL IMX290_REG_16BIT(0x300a) 50 #define IMX290_GAIN IMX290_REG_8BIT(0x3014) 51 #define IMX290_VMAX IMX290_REG_24BIT(0x3018) 52 #define IMX290_VMAX_MAX 0x3ffff 53 #define IMX290_HMAX IMX290_REG_16BIT(0x301c) 54 #define IMX290_HMAX_MAX 0xffff 55 #define IMX290_SHS1 IMX290_REG_24BIT(0x3020) 56 #define IMX290_WINWV_OB IMX290_REG_8BIT(0x303a) 57 #define IMX290_WINPV IMX290_REG_16BIT(0x303c) 58 #define IMX290_WINWV IMX290_REG_16BIT(0x303e) 59 #define IMX290_WINPH IMX290_REG_16BIT(0x3040) 60 #define IMX290_WINWH IMX290_REG_16BIT(0x3042) 61 #define IMX290_OUT_CTRL IMX290_REG_8BIT(0x3046) 62 #define IMX290_ODBIT_10BIT (0 << 0) 63 #define IMX290_ODBIT_12BIT (1 << 0) 64 #define IMX290_OPORTSEL_PARALLEL (0x0 << 4) 65 #define IMX290_OPORTSEL_LVDS_2CH (0xd << 4) 66 #define IMX290_OPORTSEL_LVDS_4CH (0xe << 4) 67 #define IMX290_OPORTSEL_LVDS_8CH (0xf << 4) 68 #define IMX290_XSOUTSEL IMX290_REG_8BIT(0x304b) 69 #define IMX290_XSOUTSEL_XVSOUTSEL_HIGH (0 << 0) 70 #define IMX290_XSOUTSEL_XVSOUTSEL_VSYNC (2 << 0) 71 #define IMX290_XSOUTSEL_XHSOUTSEL_HIGH (0 << 2) 72 #define IMX290_XSOUTSEL_XHSOUTSEL_HSYNC (2 << 2) 73 #define IMX290_INCKSEL1 IMX290_REG_8BIT(0x305c) 74 #define IMX290_INCKSEL2 IMX290_REG_8BIT(0x305d) 75 #define IMX290_INCKSEL3 IMX290_REG_8BIT(0x305e) 76 #define IMX290_INCKSEL4 IMX290_REG_8BIT(0x305f) 77 #define IMX290_PGCTRL IMX290_REG_8BIT(0x308c) 78 #define IMX290_ADBIT1 IMX290_REG_8BIT(0x3129) 79 #define IMX290_ADBIT1_10BIT 0x1d 80 #define IMX290_ADBIT1_12BIT 0x00 81 #define IMX290_INCKSEL5 IMX290_REG_8BIT(0x315e) 82 #define IMX290_INCKSEL6 IMX290_REG_8BIT(0x3164) 83 #define IMX290_ADBIT2 IMX290_REG_8BIT(0x317c) 84 #define IMX290_ADBIT2_10BIT 0x12 85 #define IMX290_ADBIT2_12BIT 0x00 86 #define IMX290_CHIP_ID IMX290_REG_16BIT(0x319a) 87 #define IMX290_ADBIT3 IMX290_REG_8BIT(0x31ec) 88 #define IMX290_ADBIT3_10BIT 0x37 89 #define IMX290_ADBIT3_12BIT 0x0e 90 #define IMX290_REPETITION IMX290_REG_8BIT(0x3405) 91 #define IMX290_PHY_LANE_NUM IMX290_REG_8BIT(0x3407) 92 #define IMX290_OPB_SIZE_V IMX290_REG_8BIT(0x3414) 93 #define IMX290_Y_OUT_SIZE IMX290_REG_16BIT(0x3418) 94 #define IMX290_CSI_DT_FMT IMX290_REG_16BIT(0x3441) 95 #define IMX290_CSI_DT_FMT_RAW10 0x0a0a 96 #define IMX290_CSI_DT_FMT_RAW12 0x0c0c 97 #define IMX290_CSI_LANE_MODE IMX290_REG_8BIT(0x3443) 98 #define IMX290_EXTCK_FREQ IMX290_REG_16BIT(0x3444) 99 #define IMX290_TCLKPOST IMX290_REG_16BIT(0x3446) 100 #define IMX290_THSZERO IMX290_REG_16BIT(0x3448) 101 #define IMX290_THSPREPARE IMX290_REG_16BIT(0x344a) 102 #define IMX290_TCLKTRAIL IMX290_REG_16BIT(0x344c) 103 #define IMX290_THSTRAIL IMX290_REG_16BIT(0x344e) 104 #define IMX290_TCLKZERO IMX290_REG_16BIT(0x3450) 105 #define IMX290_TCLKPREPARE IMX290_REG_16BIT(0x3452) 106 #define IMX290_TLPX IMX290_REG_16BIT(0x3454) 107 #define IMX290_X_OUT_SIZE IMX290_REG_16BIT(0x3472) 108 #define IMX290_INCKSEL7 IMX290_REG_8BIT(0x3480) 109 110 #define IMX290_PGCTRL_REGEN BIT(0) 111 #define IMX290_PGCTRL_THRU BIT(1) 112 #define IMX290_PGCTRL_MODE(n) ((n) << 4) 113 114 /* Number of lines by which exposure must be less than VMAX */ 115 #define IMX290_EXPOSURE_OFFSET 2 116 117 #define IMX290_PIXEL_RATE 148500000 118 119 /* 120 * The IMX290 pixel array is organized as follows: 121 * 122 * +------------------------------------+ 123 * | Optical Black | } Vertical effective optical black (10) 124 * +---+------------------------------------+---+ 125 * | | | | } Effective top margin (8) 126 * | | +----------------------------+ | | \ 127 * | | | | | | | 128 * | | | | | | | 129 * | | | | | | | 130 * | | | Recording Pixel Area | | | | Recommended height (1080) 131 * | | | | | | | 132 * | | | | | | | 133 * | | | | | | | 134 * | | +----------------------------+ | | / 135 * | | | | } Effective bottom margin (9) 136 * +---+------------------------------------+---+ 137 * <-> <-> <--------------------------> <-> <-> 138 * \---- Ignored right margin (4) 139 * \-------- Effective right margin (9) 140 * \------------------------- Recommended width (1920) 141 * \----------------------------------------- Effective left margin (8) 142 * \--------------------------------------------- Ignored left margin (4) 143 * 144 * The optical black lines are output over CSI-2 with a separate data type. 145 * 146 * The pixel array is meant to have 1920x1080 usable pixels after image 147 * processing in an ISP. It has 8 (9) extra active pixels usable for color 148 * processing in the ISP on the top and left (bottom and right) sides of the 149 * image. In addition, 4 additional pixels are present on the left and right 150 * sides of the image, documented as "ignored area". 151 * 152 * As far as is understood, all pixels of the pixel array (ignored area, color 153 * processing margins and recording area) can be output by the sensor. 154 */ 155 156 #define IMX290_PIXEL_ARRAY_WIDTH 1945 157 #define IMX290_PIXEL_ARRAY_HEIGHT 1097 158 #define IMX920_PIXEL_ARRAY_MARGIN_LEFT 12 159 #define IMX920_PIXEL_ARRAY_MARGIN_RIGHT 13 160 #define IMX920_PIXEL_ARRAY_MARGIN_TOP 8 161 #define IMX920_PIXEL_ARRAY_MARGIN_BOTTOM 9 162 #define IMX290_PIXEL_ARRAY_RECORDING_WIDTH 1920 163 #define IMX290_PIXEL_ARRAY_RECORDING_HEIGHT 1080 164 165 /* Equivalent value for 16bpp */ 166 #define IMX290_BLACK_LEVEL_DEFAULT 3840 167 168 #define IMX290_NUM_SUPPLIES 3 169 170 enum imx290_colour_variant { 171 IMX290_VARIANT_COLOUR, 172 IMX290_VARIANT_MONO, 173 IMX290_VARIANT_MAX 174 }; 175 176 enum imx290_model { 177 IMX290_MODEL_IMX290LQR, 178 IMX290_MODEL_IMX290LLR, 179 IMX290_MODEL_IMX327LQR, 180 }; 181 182 struct imx290_model_info { 183 enum imx290_colour_variant colour_variant; 184 const struct imx290_regval *init_regs; 185 size_t init_regs_num; 186 const char *name; 187 }; 188 189 enum imx290_clk_freq { 190 IMX290_CLK_37_125, 191 IMX290_CLK_74_25, 192 IMX290_NUM_CLK 193 }; 194 195 struct imx290_regval { 196 u32 reg; 197 u32 val; 198 }; 199 200 /* 201 * Clock configuration for registers INCKSEL1 to INCKSEL6. 202 */ 203 struct imx290_clk_cfg { 204 u8 incksel1; 205 u8 incksel2; 206 u8 incksel3; 207 u8 incksel4; 208 u8 incksel5; 209 u8 incksel6; 210 }; 211 212 struct imx290_mode { 213 u32 width; 214 u32 height; 215 u32 hmax_min; 216 u32 vmax_min; 217 u8 link_freq_index; 218 u8 ctrl_07; 219 220 const struct imx290_regval *data; 221 u32 data_size; 222 223 const struct imx290_clk_cfg *clk_cfg; 224 }; 225 226 struct imx290_csi_cfg { 227 u16 repetition; 228 u16 tclkpost; 229 u16 thszero; 230 u16 thsprepare; 231 u16 tclktrail; 232 u16 thstrail; 233 u16 tclkzero; 234 u16 tclkprepare; 235 u16 tlpx; 236 }; 237 238 struct imx290 { 239 struct device *dev; 240 struct clk *xclk; 241 struct regmap *regmap; 242 enum imx290_clk_freq xclk_idx; 243 u8 nlanes; 244 const struct imx290_model_info *model; 245 246 struct v4l2_subdev sd; 247 struct media_pad pad; 248 249 const struct imx290_mode *current_mode; 250 251 struct regulator_bulk_data supplies[IMX290_NUM_SUPPLIES]; 252 struct gpio_desc *rst_gpio; 253 254 struct v4l2_ctrl_handler ctrls; 255 struct v4l2_ctrl *link_freq; 256 struct v4l2_ctrl *hblank; 257 struct v4l2_ctrl *vblank; 258 struct v4l2_ctrl *exposure; 259 struct { 260 struct v4l2_ctrl *hflip; 261 struct v4l2_ctrl *vflip; 262 }; 263 }; 264 265 static inline struct imx290 *to_imx290(struct v4l2_subdev *_sd) 266 { 267 return container_of(_sd, struct imx290, sd); 268 } 269 270 /* ----------------------------------------------------------------------------- 271 * Modes and formats 272 */ 273 274 static const struct imx290_regval imx290_global_init_settings[] = { 275 { IMX290_WINWV_OB, 12 }, 276 { IMX290_WINPH, 0 }, 277 { IMX290_WINPV, 0 }, 278 { IMX290_WINWH, 1948 }, 279 { IMX290_WINWV, 1097 }, 280 { IMX290_XSOUTSEL, IMX290_XSOUTSEL_XVSOUTSEL_VSYNC | 281 IMX290_XSOUTSEL_XHSOUTSEL_HSYNC }, 282 { IMX290_REG_8BIT(0x3011), 0x02 }, 283 { IMX290_REG_8BIT(0x3012), 0x64 }, 284 { IMX290_REG_8BIT(0x3013), 0x00 }, 285 }; 286 287 static const struct imx290_regval imx290_global_init_settings_290[] = { 288 { IMX290_REG_8BIT(0x300f), 0x00 }, 289 { IMX290_REG_8BIT(0x3010), 0x21 }, 290 { IMX290_REG_8BIT(0x3016), 0x09 }, 291 { IMX290_REG_8BIT(0x3070), 0x02 }, 292 { IMX290_REG_8BIT(0x3071), 0x11 }, 293 { IMX290_REG_8BIT(0x309b), 0x10 }, 294 { IMX290_REG_8BIT(0x309c), 0x22 }, 295 { IMX290_REG_8BIT(0x30a2), 0x02 }, 296 { IMX290_REG_8BIT(0x30a6), 0x20 }, 297 { IMX290_REG_8BIT(0x30a8), 0x20 }, 298 { IMX290_REG_8BIT(0x30aa), 0x20 }, 299 { IMX290_REG_8BIT(0x30ac), 0x20 }, 300 { IMX290_REG_8BIT(0x30b0), 0x43 }, 301 { IMX290_REG_8BIT(0x3119), 0x9e }, 302 { IMX290_REG_8BIT(0x311c), 0x1e }, 303 { IMX290_REG_8BIT(0x311e), 0x08 }, 304 { IMX290_REG_8BIT(0x3128), 0x05 }, 305 { IMX290_REG_8BIT(0x313d), 0x83 }, 306 { IMX290_REG_8BIT(0x3150), 0x03 }, 307 { IMX290_REG_8BIT(0x317e), 0x00 }, 308 { IMX290_REG_8BIT(0x32b8), 0x50 }, 309 { IMX290_REG_8BIT(0x32b9), 0x10 }, 310 { IMX290_REG_8BIT(0x32ba), 0x00 }, 311 { IMX290_REG_8BIT(0x32bb), 0x04 }, 312 { IMX290_REG_8BIT(0x32c8), 0x50 }, 313 { IMX290_REG_8BIT(0x32c9), 0x10 }, 314 { IMX290_REG_8BIT(0x32ca), 0x00 }, 315 { IMX290_REG_8BIT(0x32cb), 0x04 }, 316 { IMX290_REG_8BIT(0x332c), 0xd3 }, 317 { IMX290_REG_8BIT(0x332d), 0x10 }, 318 { IMX290_REG_8BIT(0x332e), 0x0d }, 319 { IMX290_REG_8BIT(0x3358), 0x06 }, 320 { IMX290_REG_8BIT(0x3359), 0xe1 }, 321 { IMX290_REG_8BIT(0x335a), 0x11 }, 322 { IMX290_REG_8BIT(0x3360), 0x1e }, 323 { IMX290_REG_8BIT(0x3361), 0x61 }, 324 { IMX290_REG_8BIT(0x3362), 0x10 }, 325 { IMX290_REG_8BIT(0x33b0), 0x50 }, 326 { IMX290_REG_8BIT(0x33b2), 0x1a }, 327 { IMX290_REG_8BIT(0x33b3), 0x04 }, 328 }; 329 330 #define IMX290_NUM_CLK_REGS 2 331 static const struct imx290_regval xclk_regs[][IMX290_NUM_CLK_REGS] = { 332 [IMX290_CLK_37_125] = { 333 { IMX290_EXTCK_FREQ, (37125 * 256) / 1000 }, 334 { IMX290_INCKSEL7, 0x49 }, 335 }, 336 [IMX290_CLK_74_25] = { 337 { IMX290_EXTCK_FREQ, (74250 * 256) / 1000 }, 338 { IMX290_INCKSEL7, 0x92 }, 339 }, 340 }; 341 342 static const struct imx290_regval imx290_global_init_settings_327[] = { 343 { IMX290_REG_8BIT(0x309e), 0x4A }, 344 { IMX290_REG_8BIT(0x309f), 0x4A }, 345 { IMX290_REG_8BIT(0x313b), 0x61 }, 346 }; 347 348 static const struct imx290_regval imx290_1080p_settings[] = { 349 /* mode settings */ 350 { IMX290_WINWV_OB, 12 }, 351 { IMX290_OPB_SIZE_V, 10 }, 352 { IMX290_X_OUT_SIZE, 1920 }, 353 { IMX290_Y_OUT_SIZE, 1080 }, 354 }; 355 356 static const struct imx290_regval imx290_720p_settings[] = { 357 /* mode settings */ 358 { IMX290_WINWV_OB, 6 }, 359 { IMX290_OPB_SIZE_V, 4 }, 360 { IMX290_X_OUT_SIZE, 1280 }, 361 { IMX290_Y_OUT_SIZE, 720 }, 362 }; 363 364 static const struct imx290_regval imx290_10bit_settings[] = { 365 { IMX290_ADBIT, IMX290_ADBIT_10BIT }, 366 { IMX290_OUT_CTRL, IMX290_ODBIT_10BIT }, 367 { IMX290_ADBIT1, IMX290_ADBIT1_10BIT }, 368 { IMX290_ADBIT2, IMX290_ADBIT2_10BIT }, 369 { IMX290_ADBIT3, IMX290_ADBIT3_10BIT }, 370 { IMX290_CSI_DT_FMT, IMX290_CSI_DT_FMT_RAW10 }, 371 }; 372 373 static const struct imx290_regval imx290_12bit_settings[] = { 374 { IMX290_ADBIT, IMX290_ADBIT_12BIT }, 375 { IMX290_OUT_CTRL, IMX290_ODBIT_12BIT }, 376 { IMX290_ADBIT1, IMX290_ADBIT1_12BIT }, 377 { IMX290_ADBIT2, IMX290_ADBIT2_12BIT }, 378 { IMX290_ADBIT3, IMX290_ADBIT3_12BIT }, 379 { IMX290_CSI_DT_FMT, IMX290_CSI_DT_FMT_RAW12 }, 380 }; 381 382 static const struct imx290_csi_cfg imx290_csi_222_75mhz = { 383 /* 222.75MHz or 445.5Mbit/s per lane */ 384 .repetition = 0x10, 385 .tclkpost = 87, 386 .thszero = 55, 387 .thsprepare = 31, 388 .tclktrail = 31, 389 .thstrail = 31, 390 .tclkzero = 119, 391 .tclkprepare = 31, 392 .tlpx = 23, 393 }; 394 395 static const struct imx290_csi_cfg imx290_csi_445_5mhz = { 396 /* 445.5MHz or 891Mbit/s per lane */ 397 .repetition = 0x00, 398 .tclkpost = 119, 399 .thszero = 103, 400 .thsprepare = 71, 401 .tclktrail = 55, 402 .thstrail = 63, 403 .tclkzero = 255, 404 .tclkprepare = 63, 405 .tlpx = 55, 406 }; 407 408 static const struct imx290_csi_cfg imx290_csi_148_5mhz = { 409 /* 148.5MHz or 297Mbit/s per lane */ 410 .repetition = 0x10, 411 .tclkpost = 79, 412 .thszero = 47, 413 .thsprepare = 23, 414 .tclktrail = 23, 415 .thstrail = 23, 416 .tclkzero = 87, 417 .tclkprepare = 23, 418 .tlpx = 23, 419 }; 420 421 static const struct imx290_csi_cfg imx290_csi_297mhz = { 422 /* 297MHz or 594Mbit/s per lane */ 423 .repetition = 0x00, 424 .tclkpost = 103, 425 .thszero = 87, 426 .thsprepare = 47, 427 .tclktrail = 39, 428 .thstrail = 47, 429 .tclkzero = 191, 430 .tclkprepare = 47, 431 .tlpx = 39, 432 }; 433 434 /* supported link frequencies */ 435 #define FREQ_INDEX_1080P 0 436 #define FREQ_INDEX_720P 1 437 static const s64 imx290_link_freq_2lanes[] = { 438 [FREQ_INDEX_1080P] = 445500000, 439 [FREQ_INDEX_720P] = 297000000, 440 }; 441 442 static const s64 imx290_link_freq_4lanes[] = { 443 [FREQ_INDEX_1080P] = 222750000, 444 [FREQ_INDEX_720P] = 148500000, 445 }; 446 447 /* 448 * In this function and in the similar ones below We rely on imx290_probe() 449 * to ensure that nlanes is either 2 or 4. 450 */ 451 static inline const s64 *imx290_link_freqs_ptr(const struct imx290 *imx290) 452 { 453 if (imx290->nlanes == 2) 454 return imx290_link_freq_2lanes; 455 else 456 return imx290_link_freq_4lanes; 457 } 458 459 static inline int imx290_link_freqs_num(const struct imx290 *imx290) 460 { 461 if (imx290->nlanes == 2) 462 return ARRAY_SIZE(imx290_link_freq_2lanes); 463 else 464 return ARRAY_SIZE(imx290_link_freq_4lanes); 465 } 466 467 static const struct imx290_clk_cfg imx290_1080p_clock_config[] = { 468 [IMX290_CLK_37_125] = { 469 /* 37.125MHz clock config */ 470 .incksel1 = 0x18, 471 .incksel2 = 0x03, 472 .incksel3 = 0x20, 473 .incksel4 = 0x01, 474 .incksel5 = 0x1a, 475 .incksel6 = 0x1a, 476 }, 477 [IMX290_CLK_74_25] = { 478 /* 74.25MHz clock config */ 479 .incksel1 = 0x0c, 480 .incksel2 = 0x03, 481 .incksel3 = 0x10, 482 .incksel4 = 0x01, 483 .incksel5 = 0x1b, 484 .incksel6 = 0x1b, 485 }, 486 }; 487 488 static const struct imx290_clk_cfg imx290_720p_clock_config[] = { 489 [IMX290_CLK_37_125] = { 490 /* 37.125MHz clock config */ 491 .incksel1 = 0x20, 492 .incksel2 = 0x00, 493 .incksel3 = 0x20, 494 .incksel4 = 0x01, 495 .incksel5 = 0x1a, 496 .incksel6 = 0x1a, 497 }, 498 [IMX290_CLK_74_25] = { 499 /* 74.25MHz clock config */ 500 .incksel1 = 0x10, 501 .incksel2 = 0x00, 502 .incksel3 = 0x10, 503 .incksel4 = 0x01, 504 .incksel5 = 0x1b, 505 .incksel6 = 0x1b, 506 }, 507 }; 508 509 /* Mode configs */ 510 static const struct imx290_mode imx290_modes_2lanes[] = { 511 { 512 .width = 1920, 513 .height = 1080, 514 .hmax_min = 2200, 515 .vmax_min = 1125, 516 .link_freq_index = FREQ_INDEX_1080P, 517 .ctrl_07 = IMX290_WINMODE_1080P, 518 .data = imx290_1080p_settings, 519 .data_size = ARRAY_SIZE(imx290_1080p_settings), 520 .clk_cfg = imx290_1080p_clock_config, 521 }, 522 { 523 .width = 1280, 524 .height = 720, 525 .hmax_min = 3300, 526 .vmax_min = 750, 527 .link_freq_index = FREQ_INDEX_720P, 528 .ctrl_07 = IMX290_WINMODE_720P, 529 .data = imx290_720p_settings, 530 .data_size = ARRAY_SIZE(imx290_720p_settings), 531 .clk_cfg = imx290_720p_clock_config, 532 }, 533 }; 534 535 static const struct imx290_mode imx290_modes_4lanes[] = { 536 { 537 .width = 1920, 538 .height = 1080, 539 .hmax_min = 2200, 540 .vmax_min = 1125, 541 .link_freq_index = FREQ_INDEX_1080P, 542 .ctrl_07 = IMX290_WINMODE_1080P, 543 .data = imx290_1080p_settings, 544 .data_size = ARRAY_SIZE(imx290_1080p_settings), 545 .clk_cfg = imx290_1080p_clock_config, 546 }, 547 { 548 .width = 1280, 549 .height = 720, 550 .hmax_min = 3300, 551 .vmax_min = 750, 552 .link_freq_index = FREQ_INDEX_720P, 553 .ctrl_07 = IMX290_WINMODE_720P, 554 .data = imx290_720p_settings, 555 .data_size = ARRAY_SIZE(imx290_720p_settings), 556 .clk_cfg = imx290_720p_clock_config, 557 }, 558 }; 559 560 static inline const struct imx290_mode *imx290_modes_ptr(const struct imx290 *imx290) 561 { 562 if (imx290->nlanes == 2) 563 return imx290_modes_2lanes; 564 else 565 return imx290_modes_4lanes; 566 } 567 568 static inline int imx290_modes_num(const struct imx290 *imx290) 569 { 570 if (imx290->nlanes == 2) 571 return ARRAY_SIZE(imx290_modes_2lanes); 572 else 573 return ARRAY_SIZE(imx290_modes_4lanes); 574 } 575 576 struct imx290_format_info { 577 u32 code[IMX290_VARIANT_MAX]; 578 u8 bpp; 579 const struct imx290_regval *regs; 580 unsigned int num_regs; 581 }; 582 583 static const struct imx290_format_info imx290_formats[] = { 584 { 585 .code = { 586 [IMX290_VARIANT_COLOUR] = MEDIA_BUS_FMT_SRGGB10_1X10, 587 [IMX290_VARIANT_MONO] = MEDIA_BUS_FMT_Y10_1X10 588 }, 589 .bpp = 10, 590 .regs = imx290_10bit_settings, 591 .num_regs = ARRAY_SIZE(imx290_10bit_settings), 592 }, { 593 .code = { 594 [IMX290_VARIANT_COLOUR] = MEDIA_BUS_FMT_SRGGB12_1X12, 595 [IMX290_VARIANT_MONO] = MEDIA_BUS_FMT_Y12_1X12 596 }, 597 .bpp = 12, 598 .regs = imx290_12bit_settings, 599 .num_regs = ARRAY_SIZE(imx290_12bit_settings), 600 } 601 }; 602 603 static const struct imx290_format_info * 604 imx290_format_info(const struct imx290 *imx290, u32 code) 605 { 606 unsigned int i; 607 608 for (i = 0; i < ARRAY_SIZE(imx290_formats); ++i) { 609 const struct imx290_format_info *info = &imx290_formats[i]; 610 611 if (info->code[imx290->model->colour_variant] == code) 612 return info; 613 } 614 615 return NULL; 616 } 617 618 /* ----------------------------------------------------------------------------- 619 * Register access 620 */ 621 622 static int __always_unused imx290_read(struct imx290 *imx290, u32 addr, u32 *value) 623 { 624 u8 data[3] = { 0, 0, 0 }; 625 int ret; 626 627 ret = regmap_raw_read(imx290->regmap, addr & IMX290_REG_ADDR_MASK, 628 data, (addr >> IMX290_REG_SIZE_SHIFT) & 3); 629 if (ret < 0) { 630 dev_err(imx290->dev, "%u-bit read from 0x%04x failed: %d\n", 631 ((addr >> IMX290_REG_SIZE_SHIFT) & 3) * 8, 632 addr & IMX290_REG_ADDR_MASK, ret); 633 return ret; 634 } 635 636 *value = get_unaligned_le24(data); 637 return 0; 638 } 639 640 static int imx290_write(struct imx290 *imx290, u32 addr, u32 value, int *err) 641 { 642 u8 data[3]; 643 int ret; 644 645 if (err && *err) 646 return *err; 647 648 put_unaligned_le24(value, data); 649 650 ret = regmap_raw_write(imx290->regmap, addr & IMX290_REG_ADDR_MASK, 651 data, (addr >> IMX290_REG_SIZE_SHIFT) & 3); 652 if (ret < 0) { 653 dev_err(imx290->dev, "%u-bit write to 0x%04x failed: %d\n", 654 ((addr >> IMX290_REG_SIZE_SHIFT) & 3) * 8, 655 addr & IMX290_REG_ADDR_MASK, ret); 656 if (err) 657 *err = ret; 658 } 659 660 return ret; 661 } 662 663 static int imx290_set_register_array(struct imx290 *imx290, 664 const struct imx290_regval *settings, 665 unsigned int num_settings) 666 { 667 unsigned int i; 668 int ret; 669 670 for (i = 0; i < num_settings; ++i, ++settings) { 671 ret = imx290_write(imx290, settings->reg, settings->val, NULL); 672 if (ret < 0) 673 return ret; 674 } 675 676 /* Provide 10ms settle time */ 677 usleep_range(10000, 11000); 678 679 return 0; 680 } 681 682 static int imx290_set_clock(struct imx290 *imx290) 683 { 684 const struct imx290_mode *mode = imx290->current_mode; 685 enum imx290_clk_freq clk_idx = imx290->xclk_idx; 686 const struct imx290_clk_cfg *clk_cfg = &mode->clk_cfg[clk_idx]; 687 int ret; 688 689 ret = imx290_set_register_array(imx290, xclk_regs[clk_idx], 690 IMX290_NUM_CLK_REGS); 691 692 imx290_write(imx290, IMX290_INCKSEL1, clk_cfg->incksel1, &ret); 693 imx290_write(imx290, IMX290_INCKSEL2, clk_cfg->incksel2, &ret); 694 imx290_write(imx290, IMX290_INCKSEL3, clk_cfg->incksel3, &ret); 695 imx290_write(imx290, IMX290_INCKSEL4, clk_cfg->incksel4, &ret); 696 imx290_write(imx290, IMX290_INCKSEL5, clk_cfg->incksel5, &ret); 697 imx290_write(imx290, IMX290_INCKSEL6, clk_cfg->incksel6, &ret); 698 699 return ret; 700 } 701 702 static int imx290_set_data_lanes(struct imx290 *imx290) 703 { 704 int ret = 0; 705 706 imx290_write(imx290, IMX290_PHY_LANE_NUM, imx290->nlanes - 1, &ret); 707 imx290_write(imx290, IMX290_CSI_LANE_MODE, imx290->nlanes - 1, &ret); 708 imx290_write(imx290, IMX290_FR_FDG_SEL, 0x01, &ret); 709 710 return ret; 711 } 712 713 static int imx290_set_black_level(struct imx290 *imx290, 714 const struct v4l2_mbus_framefmt *format, 715 unsigned int black_level, int *err) 716 { 717 unsigned int bpp = imx290_format_info(imx290, format->code)->bpp; 718 719 return imx290_write(imx290, IMX290_BLKLEVEL, 720 black_level >> (16 - bpp), err); 721 } 722 723 static int imx290_set_csi_config(struct imx290 *imx290) 724 { 725 const s64 *link_freqs = imx290_link_freqs_ptr(imx290); 726 const struct imx290_csi_cfg *csi_cfg; 727 int ret = 0; 728 729 switch (link_freqs[imx290->current_mode->link_freq_index]) { 730 case 445500000: 731 csi_cfg = &imx290_csi_445_5mhz; 732 break; 733 case 297000000: 734 csi_cfg = &imx290_csi_297mhz; 735 break; 736 case 222750000: 737 csi_cfg = &imx290_csi_222_75mhz; 738 break; 739 case 148500000: 740 csi_cfg = &imx290_csi_148_5mhz; 741 break; 742 default: 743 return -EINVAL; 744 } 745 746 imx290_write(imx290, IMX290_REPETITION, csi_cfg->repetition, &ret); 747 imx290_write(imx290, IMX290_TCLKPOST, csi_cfg->tclkpost, &ret); 748 imx290_write(imx290, IMX290_THSZERO, csi_cfg->thszero, &ret); 749 imx290_write(imx290, IMX290_THSPREPARE, csi_cfg->thsprepare, &ret); 750 imx290_write(imx290, IMX290_TCLKTRAIL, csi_cfg->tclktrail, &ret); 751 imx290_write(imx290, IMX290_THSTRAIL, csi_cfg->thstrail, &ret); 752 imx290_write(imx290, IMX290_TCLKZERO, csi_cfg->tclkzero, &ret); 753 imx290_write(imx290, IMX290_TCLKPREPARE, csi_cfg->tclkprepare, &ret); 754 imx290_write(imx290, IMX290_TLPX, csi_cfg->tlpx, &ret); 755 756 return ret; 757 } 758 759 static int imx290_setup_format(struct imx290 *imx290, 760 const struct v4l2_mbus_framefmt *format) 761 { 762 const struct imx290_format_info *info; 763 int ret; 764 765 info = imx290_format_info(imx290, format->code); 766 767 ret = imx290_set_register_array(imx290, info->regs, info->num_regs); 768 if (ret < 0) { 769 dev_err(imx290->dev, "Could not set format registers\n"); 770 return ret; 771 } 772 773 return imx290_set_black_level(imx290, format, 774 IMX290_BLACK_LEVEL_DEFAULT, &ret); 775 } 776 777 /* ---------------------------------------------------------------------------- 778 * Controls 779 */ 780 static void imx290_exposure_update(struct imx290 *imx290, 781 const struct imx290_mode *mode) 782 { 783 unsigned int exposure_max; 784 785 exposure_max = imx290->vblank->val + mode->height - 786 IMX290_EXPOSURE_OFFSET; 787 __v4l2_ctrl_modify_range(imx290->exposure, 1, exposure_max, 1, 788 exposure_max); 789 } 790 791 static int imx290_set_ctrl(struct v4l2_ctrl *ctrl) 792 { 793 struct imx290 *imx290 = container_of(ctrl->handler, 794 struct imx290, ctrls); 795 const struct v4l2_mbus_framefmt *format; 796 struct v4l2_subdev_state *state; 797 int ret = 0, vmax; 798 799 /* 800 * Return immediately for controls that don't need to be applied to the 801 * device. 802 */ 803 if (ctrl->flags & V4L2_CTRL_FLAG_READ_ONLY) 804 return 0; 805 806 if (ctrl->id == V4L2_CID_VBLANK) { 807 /* Changing vblank changes the allowed range for exposure. */ 808 imx290_exposure_update(imx290, imx290->current_mode); 809 } 810 811 /* V4L2 controls values will be applied only when power is already up */ 812 if (!pm_runtime_get_if_in_use(imx290->dev)) 813 return 0; 814 815 state = v4l2_subdev_get_locked_active_state(&imx290->sd); 816 format = v4l2_subdev_get_pad_format(&imx290->sd, state, 0); 817 818 switch (ctrl->id) { 819 case V4L2_CID_ANALOGUE_GAIN: 820 ret = imx290_write(imx290, IMX290_GAIN, ctrl->val, NULL); 821 break; 822 823 case V4L2_CID_VBLANK: 824 ret = imx290_write(imx290, IMX290_VMAX, 825 ctrl->val + imx290->current_mode->height, 826 NULL); 827 /* 828 * Due to the way that exposure is programmed in this sensor in 829 * relation to VMAX, we have to reprogramme it whenever VMAX is 830 * changed. 831 * Update ctrl so that the V4L2_CID_EXPOSURE case can refer to 832 * it. 833 */ 834 ctrl = imx290->exposure; 835 fallthrough; 836 case V4L2_CID_EXPOSURE: 837 vmax = imx290->vblank->val + imx290->current_mode->height; 838 ret = imx290_write(imx290, IMX290_SHS1, 839 vmax - ctrl->val - 1, NULL); 840 break; 841 842 case V4L2_CID_TEST_PATTERN: 843 if (ctrl->val) { 844 imx290_set_black_level(imx290, format, 0, &ret); 845 usleep_range(10000, 11000); 846 imx290_write(imx290, IMX290_PGCTRL, 847 (u8)(IMX290_PGCTRL_REGEN | 848 IMX290_PGCTRL_THRU | 849 IMX290_PGCTRL_MODE(ctrl->val)), &ret); 850 } else { 851 imx290_write(imx290, IMX290_PGCTRL, 0x00, &ret); 852 usleep_range(10000, 11000); 853 imx290_set_black_level(imx290, format, 854 IMX290_BLACK_LEVEL_DEFAULT, &ret); 855 } 856 break; 857 858 case V4L2_CID_HBLANK: 859 ret = imx290_write(imx290, IMX290_HMAX, 860 ctrl->val + imx290->current_mode->width, 861 NULL); 862 break; 863 864 case V4L2_CID_HFLIP: 865 case V4L2_CID_VFLIP: 866 { 867 u32 reg; 868 869 reg = imx290->current_mode->ctrl_07; 870 if (imx290->hflip->val) 871 reg |= IMX290_HREVERSE; 872 if (imx290->vflip->val) 873 reg |= IMX290_VREVERSE; 874 ret = imx290_write(imx290, IMX290_CTRL_07, reg, NULL); 875 break; 876 } 877 878 default: 879 ret = -EINVAL; 880 break; 881 } 882 883 pm_runtime_mark_last_busy(imx290->dev); 884 pm_runtime_put_autosuspend(imx290->dev); 885 886 return ret; 887 } 888 889 static const struct v4l2_ctrl_ops imx290_ctrl_ops = { 890 .s_ctrl = imx290_set_ctrl, 891 }; 892 893 static const char * const imx290_test_pattern_menu[] = { 894 "Disabled", 895 "Sequence Pattern 1", 896 "Horizontal Color-bar Chart", 897 "Vertical Color-bar Chart", 898 "Sequence Pattern 2", 899 "Gradation Pattern 1", 900 "Gradation Pattern 2", 901 "000/555h Toggle Pattern", 902 }; 903 904 static void imx290_ctrl_update(struct imx290 *imx290, 905 const struct v4l2_mbus_framefmt *format, 906 const struct imx290_mode *mode) 907 { 908 unsigned int hblank_min = mode->hmax_min - mode->width; 909 unsigned int hblank_max = IMX290_HMAX_MAX - mode->width; 910 unsigned int vblank_min = mode->vmax_min - mode->height; 911 unsigned int vblank_max = IMX290_VMAX_MAX - mode->height; 912 913 __v4l2_ctrl_s_ctrl(imx290->link_freq, mode->link_freq_index); 914 915 __v4l2_ctrl_modify_range(imx290->hblank, hblank_min, hblank_max, 1, 916 hblank_min); 917 __v4l2_ctrl_modify_range(imx290->vblank, vblank_min, vblank_max, 1, 918 vblank_min); 919 } 920 921 static int imx290_ctrl_init(struct imx290 *imx290) 922 { 923 struct v4l2_fwnode_device_properties props; 924 int ret; 925 926 ret = v4l2_fwnode_device_parse(imx290->dev, &props); 927 if (ret < 0) 928 return ret; 929 930 v4l2_ctrl_handler_init(&imx290->ctrls, 11); 931 932 /* 933 * The sensor has an analog gain and a digital gain, both controlled 934 * through a single gain value, expressed in 0.3dB increments. Values 935 * from 0.0dB (0) to 30.0dB (100) apply analog gain only, higher values 936 * up to 72.0dB (240) add further digital gain. Limit the range to 937 * analog gain only, support for digital gain can be added separately 938 * if needed. 939 * 940 * The IMX327 and IMX462 are largely compatible with the IMX290, but 941 * have an analog gain range of 0.0dB to 29.4dB and 42dB of digital 942 * gain. When support for those sensors gets added to the driver, the 943 * gain control should be adjusted accordingly. 944 */ 945 v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 946 V4L2_CID_ANALOGUE_GAIN, 0, 100, 1, 0); 947 948 /* 949 * Correct range will be determined through imx290_ctrl_update setting 950 * V4L2_CID_VBLANK. 951 */ 952 imx290->exposure = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 953 V4L2_CID_EXPOSURE, 1, 65535, 1, 954 65535); 955 956 /* 957 * Set the link frequency, pixel rate, horizontal blanking and vertical 958 * blanking to hardcoded values, they will be updated by 959 * imx290_ctrl_update(). 960 */ 961 imx290->link_freq = 962 v4l2_ctrl_new_int_menu(&imx290->ctrls, &imx290_ctrl_ops, 963 V4L2_CID_LINK_FREQ, 964 imx290_link_freqs_num(imx290) - 1, 0, 965 imx290_link_freqs_ptr(imx290)); 966 if (imx290->link_freq) 967 imx290->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 968 969 v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, V4L2_CID_PIXEL_RATE, 970 IMX290_PIXEL_RATE, IMX290_PIXEL_RATE, 1, 971 IMX290_PIXEL_RATE); 972 973 v4l2_ctrl_new_std_menu_items(&imx290->ctrls, &imx290_ctrl_ops, 974 V4L2_CID_TEST_PATTERN, 975 ARRAY_SIZE(imx290_test_pattern_menu) - 1, 976 0, 0, imx290_test_pattern_menu); 977 978 /* 979 * Actual range will be set from imx290_ctrl_update later in the probe. 980 */ 981 imx290->hblank = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 982 V4L2_CID_HBLANK, 1, 1, 1, 1); 983 984 imx290->vblank = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 985 V4L2_CID_VBLANK, 1, 1, 1, 1); 986 987 imx290->hflip = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 988 V4L2_CID_HFLIP, 0, 1, 1, 0); 989 imx290->vflip = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 990 V4L2_CID_VFLIP, 0, 1, 1, 0); 991 v4l2_ctrl_cluster(2, &imx290->hflip); 992 993 v4l2_ctrl_new_fwnode_properties(&imx290->ctrls, &imx290_ctrl_ops, 994 &props); 995 996 imx290->sd.ctrl_handler = &imx290->ctrls; 997 998 if (imx290->ctrls.error) { 999 ret = imx290->ctrls.error; 1000 v4l2_ctrl_handler_free(&imx290->ctrls); 1001 return ret; 1002 } 1003 1004 return 0; 1005 } 1006 1007 /* ---------------------------------------------------------------------------- 1008 * Subdev operations 1009 */ 1010 1011 /* Start streaming */ 1012 static int imx290_start_streaming(struct imx290 *imx290, 1013 struct v4l2_subdev_state *state) 1014 { 1015 const struct v4l2_mbus_framefmt *format; 1016 int ret; 1017 1018 /* Set init register settings */ 1019 ret = imx290_set_register_array(imx290, imx290_global_init_settings, 1020 ARRAY_SIZE(imx290_global_init_settings)); 1021 if (ret < 0) { 1022 dev_err(imx290->dev, "Could not set init registers\n"); 1023 return ret; 1024 } 1025 1026 /* Set mdel specific init register settings */ 1027 ret = imx290_set_register_array(imx290, imx290->model->init_regs, 1028 imx290->model->init_regs_num); 1029 if (ret < 0) { 1030 dev_err(imx290->dev, "Could not set model specific init registers\n"); 1031 return ret; 1032 } 1033 1034 /* Set clock parameters based on mode and xclk */ 1035 ret = imx290_set_clock(imx290); 1036 if (ret < 0) { 1037 dev_err(imx290->dev, "Could not set clocks - %d\n", ret); 1038 return ret; 1039 } 1040 1041 /* Set data lane count */ 1042 ret = imx290_set_data_lanes(imx290); 1043 if (ret < 0) { 1044 dev_err(imx290->dev, "Could not set data lanes - %d\n", ret); 1045 return ret; 1046 } 1047 1048 ret = imx290_set_csi_config(imx290); 1049 if (ret < 0) { 1050 dev_err(imx290->dev, "Could not set csi cfg - %d\n", ret); 1051 return ret; 1052 } 1053 1054 /* Apply the register values related to current frame format */ 1055 format = v4l2_subdev_get_pad_format(&imx290->sd, state, 0); 1056 ret = imx290_setup_format(imx290, format); 1057 if (ret < 0) { 1058 dev_err(imx290->dev, "Could not set frame format - %d\n", ret); 1059 return ret; 1060 } 1061 1062 /* Apply default values of current mode */ 1063 ret = imx290_set_register_array(imx290, imx290->current_mode->data, 1064 imx290->current_mode->data_size); 1065 if (ret < 0) { 1066 dev_err(imx290->dev, "Could not set current mode - %d\n", ret); 1067 return ret; 1068 } 1069 1070 /* Apply customized values from user */ 1071 ret = __v4l2_ctrl_handler_setup(imx290->sd.ctrl_handler); 1072 if (ret) { 1073 dev_err(imx290->dev, "Could not sync v4l2 controls - %d\n", ret); 1074 return ret; 1075 } 1076 1077 imx290_write(imx290, IMX290_STANDBY, 0x00, &ret); 1078 1079 msleep(30); 1080 1081 /* Start streaming */ 1082 return imx290_write(imx290, IMX290_XMSTA, 0x00, &ret); 1083 } 1084 1085 /* Stop streaming */ 1086 static int imx290_stop_streaming(struct imx290 *imx290) 1087 { 1088 int ret = 0; 1089 1090 imx290_write(imx290, IMX290_STANDBY, 0x01, &ret); 1091 1092 msleep(30); 1093 1094 return imx290_write(imx290, IMX290_XMSTA, 0x01, &ret); 1095 } 1096 1097 static int imx290_set_stream(struct v4l2_subdev *sd, int enable) 1098 { 1099 struct imx290 *imx290 = to_imx290(sd); 1100 struct v4l2_subdev_state *state; 1101 int ret = 0; 1102 1103 state = v4l2_subdev_lock_and_get_active_state(sd); 1104 1105 if (enable) { 1106 ret = pm_runtime_resume_and_get(imx290->dev); 1107 if (ret < 0) 1108 goto unlock; 1109 1110 ret = imx290_start_streaming(imx290, state); 1111 if (ret) { 1112 dev_err(imx290->dev, "Start stream failed\n"); 1113 pm_runtime_put_sync(imx290->dev); 1114 goto unlock; 1115 } 1116 } else { 1117 imx290_stop_streaming(imx290); 1118 pm_runtime_mark_last_busy(imx290->dev); 1119 pm_runtime_put_autosuspend(imx290->dev); 1120 } 1121 1122 /* 1123 * vflip and hflip should not be changed during streaming as the sensor 1124 * will produce an invalid frame. 1125 */ 1126 __v4l2_ctrl_grab(imx290->vflip, enable); 1127 __v4l2_ctrl_grab(imx290->hflip, enable); 1128 1129 unlock: 1130 v4l2_subdev_unlock_state(state); 1131 return ret; 1132 } 1133 1134 static int imx290_enum_mbus_code(struct v4l2_subdev *sd, 1135 struct v4l2_subdev_state *sd_state, 1136 struct v4l2_subdev_mbus_code_enum *code) 1137 { 1138 const struct imx290 *imx290 = to_imx290(sd); 1139 1140 if (code->index >= ARRAY_SIZE(imx290_formats)) 1141 return -EINVAL; 1142 1143 code->code = imx290_formats[code->index].code[imx290->model->colour_variant]; 1144 1145 return 0; 1146 } 1147 1148 static int imx290_enum_frame_size(struct v4l2_subdev *sd, 1149 struct v4l2_subdev_state *sd_state, 1150 struct v4l2_subdev_frame_size_enum *fse) 1151 { 1152 const struct imx290 *imx290 = to_imx290(sd); 1153 const struct imx290_mode *imx290_modes = imx290_modes_ptr(imx290); 1154 1155 if (!imx290_format_info(imx290, fse->code)) 1156 return -EINVAL; 1157 1158 if (fse->index >= imx290_modes_num(imx290)) 1159 return -EINVAL; 1160 1161 fse->min_width = imx290_modes[fse->index].width; 1162 fse->max_width = imx290_modes[fse->index].width; 1163 fse->min_height = imx290_modes[fse->index].height; 1164 fse->max_height = imx290_modes[fse->index].height; 1165 1166 return 0; 1167 } 1168 1169 static int imx290_set_fmt(struct v4l2_subdev *sd, 1170 struct v4l2_subdev_state *sd_state, 1171 struct v4l2_subdev_format *fmt) 1172 { 1173 struct imx290 *imx290 = to_imx290(sd); 1174 const struct imx290_mode *mode; 1175 struct v4l2_mbus_framefmt *format; 1176 1177 mode = v4l2_find_nearest_size(imx290_modes_ptr(imx290), 1178 imx290_modes_num(imx290), width, height, 1179 fmt->format.width, fmt->format.height); 1180 1181 fmt->format.width = mode->width; 1182 fmt->format.height = mode->height; 1183 1184 if (!imx290_format_info(imx290, fmt->format.code)) 1185 fmt->format.code = imx290_formats[0].code[imx290->model->colour_variant]; 1186 1187 fmt->format.field = V4L2_FIELD_NONE; 1188 fmt->format.colorspace = V4L2_COLORSPACE_RAW; 1189 fmt->format.ycbcr_enc = V4L2_YCBCR_ENC_601; 1190 fmt->format.quantization = V4L2_QUANTIZATION_FULL_RANGE; 1191 fmt->format.xfer_func = V4L2_XFER_FUNC_NONE; 1192 1193 format = v4l2_subdev_get_pad_format(sd, sd_state, 0); 1194 1195 if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 1196 imx290->current_mode = mode; 1197 1198 imx290_ctrl_update(imx290, &fmt->format, mode); 1199 imx290_exposure_update(imx290, mode); 1200 } 1201 1202 *format = fmt->format; 1203 1204 return 0; 1205 } 1206 1207 static int imx290_get_selection(struct v4l2_subdev *sd, 1208 struct v4l2_subdev_state *sd_state, 1209 struct v4l2_subdev_selection *sel) 1210 { 1211 struct imx290 *imx290 = to_imx290(sd); 1212 struct v4l2_mbus_framefmt *format; 1213 1214 switch (sel->target) { 1215 case V4L2_SEL_TGT_CROP: { 1216 format = v4l2_subdev_get_pad_format(sd, sd_state, 0); 1217 1218 /* 1219 * The sensor moves the readout by 1 pixel based on flips to 1220 * keep the Bayer order the same. 1221 */ 1222 sel->r.top = IMX920_PIXEL_ARRAY_MARGIN_TOP 1223 + (IMX290_PIXEL_ARRAY_RECORDING_HEIGHT - format->height) / 2 1224 + imx290->vflip->val; 1225 sel->r.left = IMX920_PIXEL_ARRAY_MARGIN_LEFT 1226 + (IMX290_PIXEL_ARRAY_RECORDING_WIDTH - format->width) / 2 1227 + imx290->hflip->val; 1228 sel->r.width = format->width; 1229 sel->r.height = format->height; 1230 1231 return 0; 1232 } 1233 1234 case V4L2_SEL_TGT_NATIVE_SIZE: 1235 case V4L2_SEL_TGT_CROP_BOUNDS: 1236 sel->r.top = 0; 1237 sel->r.left = 0; 1238 sel->r.width = IMX290_PIXEL_ARRAY_WIDTH; 1239 sel->r.height = IMX290_PIXEL_ARRAY_HEIGHT; 1240 1241 return 0; 1242 1243 case V4L2_SEL_TGT_CROP_DEFAULT: 1244 sel->r.top = IMX920_PIXEL_ARRAY_MARGIN_TOP; 1245 sel->r.left = IMX920_PIXEL_ARRAY_MARGIN_LEFT; 1246 sel->r.width = IMX290_PIXEL_ARRAY_RECORDING_WIDTH; 1247 sel->r.height = IMX290_PIXEL_ARRAY_RECORDING_HEIGHT; 1248 1249 return 0; 1250 1251 default: 1252 return -EINVAL; 1253 } 1254 } 1255 1256 static int imx290_entity_init_cfg(struct v4l2_subdev *subdev, 1257 struct v4l2_subdev_state *sd_state) 1258 { 1259 struct v4l2_subdev_format fmt = { 1260 .which = V4L2_SUBDEV_FORMAT_TRY, 1261 .format = { 1262 .width = 1920, 1263 .height = 1080, 1264 }, 1265 }; 1266 1267 imx290_set_fmt(subdev, sd_state, &fmt); 1268 1269 return 0; 1270 } 1271 1272 static const struct v4l2_subdev_core_ops imx290_core_ops = { 1273 .subscribe_event = v4l2_ctrl_subdev_subscribe_event, 1274 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 1275 }; 1276 1277 static const struct v4l2_subdev_video_ops imx290_video_ops = { 1278 .s_stream = imx290_set_stream, 1279 }; 1280 1281 static const struct v4l2_subdev_pad_ops imx290_pad_ops = { 1282 .init_cfg = imx290_entity_init_cfg, 1283 .enum_mbus_code = imx290_enum_mbus_code, 1284 .enum_frame_size = imx290_enum_frame_size, 1285 .get_fmt = v4l2_subdev_get_fmt, 1286 .set_fmt = imx290_set_fmt, 1287 .get_selection = imx290_get_selection, 1288 }; 1289 1290 static const struct v4l2_subdev_ops imx290_subdev_ops = { 1291 .core = &imx290_core_ops, 1292 .video = &imx290_video_ops, 1293 .pad = &imx290_pad_ops, 1294 }; 1295 1296 static const struct media_entity_operations imx290_subdev_entity_ops = { 1297 .link_validate = v4l2_subdev_link_validate, 1298 }; 1299 1300 static int imx290_subdev_init(struct imx290 *imx290) 1301 { 1302 struct i2c_client *client = to_i2c_client(imx290->dev); 1303 const struct v4l2_mbus_framefmt *format; 1304 struct v4l2_subdev_state *state; 1305 int ret; 1306 1307 imx290->current_mode = &imx290_modes_ptr(imx290)[0]; 1308 1309 v4l2_i2c_subdev_init(&imx290->sd, client, &imx290_subdev_ops); 1310 imx290->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | 1311 V4L2_SUBDEV_FL_HAS_EVENTS; 1312 imx290->sd.dev = imx290->dev; 1313 imx290->sd.entity.ops = &imx290_subdev_entity_ops; 1314 imx290->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1315 1316 imx290->pad.flags = MEDIA_PAD_FL_SOURCE; 1317 ret = media_entity_pads_init(&imx290->sd.entity, 1, &imx290->pad); 1318 if (ret < 0) { 1319 dev_err(imx290->dev, "Could not register media entity\n"); 1320 return ret; 1321 } 1322 1323 ret = imx290_ctrl_init(imx290); 1324 if (ret < 0) { 1325 dev_err(imx290->dev, "Control initialization error %d\n", ret); 1326 goto err_media; 1327 } 1328 1329 imx290->sd.state_lock = imx290->ctrls.lock; 1330 1331 ret = v4l2_subdev_init_finalize(&imx290->sd); 1332 if (ret < 0) { 1333 dev_err(imx290->dev, "subdev initialization error %d\n", ret); 1334 goto err_ctrls; 1335 } 1336 1337 state = v4l2_subdev_lock_and_get_active_state(&imx290->sd); 1338 format = v4l2_subdev_get_pad_format(&imx290->sd, state, 0); 1339 imx290_ctrl_update(imx290, format, imx290->current_mode); 1340 v4l2_subdev_unlock_state(state); 1341 1342 return 0; 1343 1344 err_ctrls: 1345 v4l2_ctrl_handler_free(&imx290->ctrls); 1346 err_media: 1347 media_entity_cleanup(&imx290->sd.entity); 1348 return ret; 1349 } 1350 1351 static void imx290_subdev_cleanup(struct imx290 *imx290) 1352 { 1353 v4l2_subdev_cleanup(&imx290->sd); 1354 media_entity_cleanup(&imx290->sd.entity); 1355 v4l2_ctrl_handler_free(&imx290->ctrls); 1356 } 1357 1358 /* ---------------------------------------------------------------------------- 1359 * Power management 1360 */ 1361 1362 static int imx290_power_on(struct imx290 *imx290) 1363 { 1364 int ret; 1365 1366 ret = clk_prepare_enable(imx290->xclk); 1367 if (ret) { 1368 dev_err(imx290->dev, "Failed to enable clock\n"); 1369 return ret; 1370 } 1371 1372 ret = regulator_bulk_enable(ARRAY_SIZE(imx290->supplies), 1373 imx290->supplies); 1374 if (ret) { 1375 dev_err(imx290->dev, "Failed to enable regulators\n"); 1376 clk_disable_unprepare(imx290->xclk); 1377 return ret; 1378 } 1379 1380 usleep_range(1, 2); 1381 gpiod_set_value_cansleep(imx290->rst_gpio, 0); 1382 usleep_range(30000, 31000); 1383 1384 return 0; 1385 } 1386 1387 static void imx290_power_off(struct imx290 *imx290) 1388 { 1389 clk_disable_unprepare(imx290->xclk); 1390 gpiod_set_value_cansleep(imx290->rst_gpio, 1); 1391 regulator_bulk_disable(ARRAY_SIZE(imx290->supplies), imx290->supplies); 1392 } 1393 1394 static int imx290_runtime_resume(struct device *dev) 1395 { 1396 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1397 struct imx290 *imx290 = to_imx290(sd); 1398 1399 return imx290_power_on(imx290); 1400 } 1401 1402 static int imx290_runtime_suspend(struct device *dev) 1403 { 1404 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1405 struct imx290 *imx290 = to_imx290(sd); 1406 1407 imx290_power_off(imx290); 1408 1409 return 0; 1410 } 1411 1412 static const struct dev_pm_ops imx290_pm_ops = { 1413 RUNTIME_PM_OPS(imx290_runtime_suspend, imx290_runtime_resume, NULL) 1414 }; 1415 1416 /* ---------------------------------------------------------------------------- 1417 * Probe & remove 1418 */ 1419 1420 static const struct regmap_config imx290_regmap_config = { 1421 .reg_bits = 16, 1422 .val_bits = 8, 1423 }; 1424 1425 static const char * const imx290_supply_name[IMX290_NUM_SUPPLIES] = { 1426 "vdda", 1427 "vddd", 1428 "vdddo", 1429 }; 1430 1431 static int imx290_get_regulators(struct device *dev, struct imx290 *imx290) 1432 { 1433 unsigned int i; 1434 1435 for (i = 0; i < ARRAY_SIZE(imx290->supplies); i++) 1436 imx290->supplies[i].supply = imx290_supply_name[i]; 1437 1438 return devm_regulator_bulk_get(dev, ARRAY_SIZE(imx290->supplies), 1439 imx290->supplies); 1440 } 1441 1442 static int imx290_init_clk(struct imx290 *imx290) 1443 { 1444 u32 xclk_freq; 1445 int ret; 1446 1447 ret = device_property_read_u32(imx290->dev, "clock-frequency", 1448 &xclk_freq); 1449 if (ret) { 1450 dev_err(imx290->dev, "Could not get xclk frequency\n"); 1451 return ret; 1452 } 1453 1454 /* external clock must be 37.125 MHz or 74.25MHz */ 1455 switch (xclk_freq) { 1456 case 37125000: 1457 imx290->xclk_idx = IMX290_CLK_37_125; 1458 break; 1459 case 74250000: 1460 imx290->xclk_idx = IMX290_CLK_74_25; 1461 break; 1462 default: 1463 dev_err(imx290->dev, "External clock frequency %u is not supported\n", 1464 xclk_freq); 1465 return -EINVAL; 1466 } 1467 1468 ret = clk_set_rate(imx290->xclk, xclk_freq); 1469 if (ret) { 1470 dev_err(imx290->dev, "Could not set xclk frequency\n"); 1471 return ret; 1472 } 1473 1474 return 0; 1475 } 1476 1477 /* 1478 * Returns 0 if all link frequencies used by the driver for the given number 1479 * of MIPI data lanes are mentioned in the device tree, or the value of the 1480 * first missing frequency otherwise. 1481 */ 1482 static s64 imx290_check_link_freqs(const struct imx290 *imx290, 1483 const struct v4l2_fwnode_endpoint *ep) 1484 { 1485 int i, j; 1486 const s64 *freqs = imx290_link_freqs_ptr(imx290); 1487 int freqs_count = imx290_link_freqs_num(imx290); 1488 1489 for (i = 0; i < freqs_count; i++) { 1490 for (j = 0; j < ep->nr_of_link_frequencies; j++) 1491 if (freqs[i] == ep->link_frequencies[j]) 1492 break; 1493 if (j == ep->nr_of_link_frequencies) 1494 return freqs[i]; 1495 } 1496 return 0; 1497 } 1498 1499 static const struct imx290_model_info imx290_models[] = { 1500 [IMX290_MODEL_IMX290LQR] = { 1501 .colour_variant = IMX290_VARIANT_COLOUR, 1502 .init_regs = imx290_global_init_settings_290, 1503 .init_regs_num = ARRAY_SIZE(imx290_global_init_settings_290), 1504 .name = "imx290", 1505 }, 1506 [IMX290_MODEL_IMX290LLR] = { 1507 .colour_variant = IMX290_VARIANT_MONO, 1508 .init_regs = imx290_global_init_settings_290, 1509 .init_regs_num = ARRAY_SIZE(imx290_global_init_settings_290), 1510 .name = "imx290", 1511 }, 1512 [IMX290_MODEL_IMX327LQR] = { 1513 .colour_variant = IMX290_VARIANT_COLOUR, 1514 .init_regs = imx290_global_init_settings_327, 1515 .init_regs_num = ARRAY_SIZE(imx290_global_init_settings_327), 1516 .name = "imx327", 1517 }, 1518 }; 1519 1520 static int imx290_parse_dt(struct imx290 *imx290) 1521 { 1522 /* Only CSI2 is supported for now: */ 1523 struct v4l2_fwnode_endpoint ep = { 1524 .bus_type = V4L2_MBUS_CSI2_DPHY 1525 }; 1526 struct fwnode_handle *endpoint; 1527 int ret; 1528 s64 fq; 1529 1530 imx290->model = of_device_get_match_data(imx290->dev); 1531 1532 endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(imx290->dev), NULL); 1533 if (!endpoint) { 1534 dev_err(imx290->dev, "Endpoint node not found\n"); 1535 return -EINVAL; 1536 } 1537 1538 ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &ep); 1539 fwnode_handle_put(endpoint); 1540 if (ret == -ENXIO) { 1541 dev_err(imx290->dev, "Unsupported bus type, should be CSI2\n"); 1542 goto done; 1543 } else if (ret) { 1544 dev_err(imx290->dev, "Parsing endpoint node failed\n"); 1545 goto done; 1546 } 1547 1548 /* Get number of data lanes */ 1549 imx290->nlanes = ep.bus.mipi_csi2.num_data_lanes; 1550 if (imx290->nlanes != 2 && imx290->nlanes != 4) { 1551 dev_err(imx290->dev, "Invalid data lanes: %d\n", imx290->nlanes); 1552 ret = -EINVAL; 1553 goto done; 1554 } 1555 1556 dev_dbg(imx290->dev, "Using %u data lanes\n", imx290->nlanes); 1557 1558 if (!ep.nr_of_link_frequencies) { 1559 dev_err(imx290->dev, "link-frequency property not found in DT\n"); 1560 ret = -EINVAL; 1561 goto done; 1562 } 1563 1564 /* Check that link frequences for all the modes are in device tree */ 1565 fq = imx290_check_link_freqs(imx290, &ep); 1566 if (fq) { 1567 dev_err(imx290->dev, "Link frequency of %lld is not supported\n", 1568 fq); 1569 ret = -EINVAL; 1570 goto done; 1571 } 1572 1573 ret = 0; 1574 1575 done: 1576 v4l2_fwnode_endpoint_free(&ep); 1577 return ret; 1578 } 1579 1580 static int imx290_probe(struct i2c_client *client) 1581 { 1582 struct device *dev = &client->dev; 1583 struct imx290 *imx290; 1584 int ret; 1585 1586 imx290 = devm_kzalloc(dev, sizeof(*imx290), GFP_KERNEL); 1587 if (!imx290) 1588 return -ENOMEM; 1589 1590 imx290->dev = dev; 1591 imx290->regmap = devm_regmap_init_i2c(client, &imx290_regmap_config); 1592 if (IS_ERR(imx290->regmap)) { 1593 dev_err(dev, "Unable to initialize I2C\n"); 1594 return -ENODEV; 1595 } 1596 1597 ret = imx290_parse_dt(imx290); 1598 if (ret) 1599 return ret; 1600 1601 /* Acquire resources. */ 1602 imx290->xclk = devm_clk_get(dev, "xclk"); 1603 if (IS_ERR(imx290->xclk)) 1604 return dev_err_probe(dev, PTR_ERR(imx290->xclk), 1605 "Could not get xclk\n"); 1606 1607 ret = imx290_get_regulators(dev, imx290); 1608 if (ret < 0) 1609 return dev_err_probe(dev, ret, "Cannot get regulators\n"); 1610 1611 imx290->rst_gpio = devm_gpiod_get_optional(dev, "reset", 1612 GPIOD_OUT_HIGH); 1613 if (IS_ERR(imx290->rst_gpio)) 1614 return dev_err_probe(dev, PTR_ERR(imx290->rst_gpio), 1615 "Cannot get reset gpio\n"); 1616 1617 /* Initialize external clock frequency. */ 1618 ret = imx290_init_clk(imx290); 1619 if (ret) 1620 return ret; 1621 1622 /* 1623 * Enable power management. The driver supports runtime PM, but needs to 1624 * work when runtime PM is disabled in the kernel. To that end, power 1625 * the sensor on manually here. 1626 */ 1627 ret = imx290_power_on(imx290); 1628 if (ret < 0) { 1629 dev_err(dev, "Could not power on the device\n"); 1630 return ret; 1631 } 1632 1633 /* 1634 * Enable runtime PM with autosuspend. As the device has been powered 1635 * manually, mark it as active, and increase the usage count without 1636 * resuming the device. 1637 */ 1638 pm_runtime_set_active(dev); 1639 pm_runtime_get_noresume(dev); 1640 pm_runtime_enable(dev); 1641 pm_runtime_set_autosuspend_delay(dev, 1000); 1642 pm_runtime_use_autosuspend(dev); 1643 1644 /* Initialize the V4L2 subdev. */ 1645 ret = imx290_subdev_init(imx290); 1646 if (ret) 1647 goto err_pm; 1648 1649 v4l2_i2c_subdev_set_name(&imx290->sd, client, 1650 imx290->model->name, NULL); 1651 1652 /* 1653 * Finally, register the V4L2 subdev. This must be done after 1654 * initializing everything as the subdev can be used immediately after 1655 * being registered. 1656 */ 1657 ret = v4l2_async_register_subdev(&imx290->sd); 1658 if (ret < 0) { 1659 dev_err(dev, "Could not register v4l2 device\n"); 1660 goto err_subdev; 1661 } 1662 1663 /* 1664 * Decrease the PM usage count. The device will get suspended after the 1665 * autosuspend delay, turning the power off. 1666 */ 1667 pm_runtime_mark_last_busy(dev); 1668 pm_runtime_put_autosuspend(dev); 1669 1670 return 0; 1671 1672 err_subdev: 1673 imx290_subdev_cleanup(imx290); 1674 err_pm: 1675 pm_runtime_disable(dev); 1676 pm_runtime_put_noidle(dev); 1677 imx290_power_off(imx290); 1678 return ret; 1679 } 1680 1681 static void imx290_remove(struct i2c_client *client) 1682 { 1683 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1684 struct imx290 *imx290 = to_imx290(sd); 1685 1686 v4l2_async_unregister_subdev(sd); 1687 imx290_subdev_cleanup(imx290); 1688 1689 /* 1690 * Disable runtime PM. In case runtime PM is disabled in the kernel, 1691 * make sure to turn power off manually. 1692 */ 1693 pm_runtime_disable(imx290->dev); 1694 if (!pm_runtime_status_suspended(imx290->dev)) 1695 imx290_power_off(imx290); 1696 pm_runtime_set_suspended(imx290->dev); 1697 } 1698 1699 static const struct of_device_id imx290_of_match[] = { 1700 { 1701 /* Deprecated - synonym for "sony,imx290lqr" */ 1702 .compatible = "sony,imx290", 1703 .data = &imx290_models[IMX290_MODEL_IMX290LQR], 1704 }, { 1705 .compatible = "sony,imx290lqr", 1706 .data = &imx290_models[IMX290_MODEL_IMX290LQR], 1707 }, { 1708 .compatible = "sony,imx290llr", 1709 .data = &imx290_models[IMX290_MODEL_IMX290LLR], 1710 }, { 1711 .compatible = "sony,imx327lqr", 1712 .data = &imx290_models[IMX290_MODEL_IMX327LQR], 1713 }, 1714 { /* sentinel */ }, 1715 }; 1716 MODULE_DEVICE_TABLE(of, imx290_of_match); 1717 1718 static struct i2c_driver imx290_i2c_driver = { 1719 .probe = imx290_probe, 1720 .remove = imx290_remove, 1721 .driver = { 1722 .name = "imx290", 1723 .pm = pm_ptr(&imx290_pm_ops), 1724 .of_match_table = imx290_of_match, 1725 }, 1726 }; 1727 1728 module_i2c_driver(imx290_i2c_driver); 1729 1730 MODULE_DESCRIPTION("Sony IMX290 CMOS Image Sensor Driver"); 1731 MODULE_AUTHOR("FRAMOS GmbH"); 1732 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>"); 1733 MODULE_LICENSE("GPL v2"); 1734