1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * V4L2 Support for the IMX283 4 * 5 * Diagonal 15.86 mm (Type 1) CMOS Image Sensor with Square Pixel for Color 6 * Cameras. 7 * 8 * Copyright (C) 2024 Ideas on Board Oy. 9 * 10 * Based on Sony IMX283 driver prepared by Will Whang 11 * 12 * Based on Sony imx477 camera driver 13 * Copyright (C) 2019-2020 Raspberry Pi (Trading) Ltd 14 */ 15 16 #include <linux/array_size.h> 17 #include <linux/bitops.h> 18 #include <linux/container_of.h> 19 #include <linux/clk.h> 20 #include <linux/delay.h> 21 #include <linux/err.h> 22 #include <linux/gpio/consumer.h> 23 #include <linux/i2c.h> 24 #include <linux/minmax.h> 25 #include <linux/module.h> 26 #include <linux/mutex.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/property.h> 29 #include <linux/regulator/consumer.h> 30 #include <linux/types.h> 31 #include <linux/units.h> 32 #include <media/v4l2-cci.h> 33 #include <media/v4l2-ctrls.h> 34 #include <media/v4l2-device.h> 35 #include <media/v4l2-fwnode.h> 36 #include <media/v4l2-mediabus.h> 37 38 /* Chip ID */ 39 #define IMX283_REG_CHIP_ID CCI_REG8(0x3000) 40 #define IMX283_CHIP_ID 0x0b // Default power on state 41 42 #define IMX283_REG_STANDBY CCI_REG8(0x3000) 43 #define IMX283_ACTIVE 0 44 #define IMX283_STANDBY BIT(0) 45 #define IMX283_STBLOGIC BIT(1) 46 #define IMX283_STBMIPI BIT(2) 47 #define IMX283_STBDV BIT(3) 48 #define IMX283_SLEEP BIT(4) 49 50 #define IMX283_REG_CLAMP CCI_REG8(0x3001) 51 #define IMX283_CLPSQRST BIT(4) 52 53 #define IMX283_REG_PLSTMG08 CCI_REG8(0x3003) 54 #define IMX283_PLSTMG08_VAL 0x77 55 56 #define IMX283_REG_MDSEL1 CCI_REG8(0x3004) 57 #define IMX283_REG_MDSEL2 CCI_REG8(0x3005) 58 #define IMX283_REG_MDSEL3 CCI_REG8(0x3006) 59 #define IMX283_MDSEL3_VCROP_EN BIT(5) 60 #define IMX283_REG_MDSEL4 CCI_REG8(0x3007) 61 #define IMX283_MDSEL4_VCROP_EN (BIT(4) | BIT(6)) 62 63 #define IMX283_REG_SVR CCI_REG16_LE(0x3009) 64 65 #define IMX283_REG_HTRIMMING CCI_REG8(0x300b) 66 #define IMX283_MDVREV BIT(0) /* VFLIP */ 67 #define IMX283_HTRIMMING_EN BIT(4) 68 69 #define IMX283_REG_VWINPOS CCI_REG16_LE(0x300f) 70 #define IMX283_REG_VWIDCUT CCI_REG16_LE(0x3011) 71 72 #define IMX283_REG_MDSEL7 CCI_REG16_LE(0x3013) 73 74 /* CSI Clock Configuration */ 75 #define IMX283_REG_TCLKPOST CCI_REG8(0x3018) 76 #define IMX283_REG_THSPREPARE CCI_REG8(0x301a) 77 #define IMX283_REG_THSZERO CCI_REG8(0x301c) 78 #define IMX283_REG_THSTRAIL CCI_REG8(0x301e) 79 #define IMX283_REG_TCLKTRAIL CCI_REG8(0x3020) 80 #define IMX283_REG_TCLKPREPARE CCI_REG8(0x3022) 81 #define IMX283_REG_TCLKZERO CCI_REG16_LE(0x3024) 82 #define IMX283_REG_TLPX CCI_REG8(0x3026) 83 #define IMX283_REG_THSEXIT CCI_REG8(0x3028) 84 #define IMX283_REG_TCLKPRE CCI_REG8(0x302a) 85 #define IMX283_REG_SYSMODE CCI_REG8(0x3104) 86 87 #define IMX283_REG_Y_OUT_SIZE CCI_REG16_LE(0x302f) 88 #define IMX283_REG_WRITE_VSIZE CCI_REG16_LE(0x3031) 89 #define IMX283_REG_OB_SIZE_V CCI_REG8(0x3033) 90 91 /* HMAX internal HBLANK */ 92 #define IMX283_REG_HMAX CCI_REG16_LE(0x3036) 93 #define IMX283_HMAX_MAX (BIT(16) - 1) 94 95 /* VMAX internal VBLANK */ 96 #define IMX283_REG_VMAX CCI_REG24_LE(0x3038) 97 #define IMX283_VMAX_MAX (BIT(16) - 1) 98 99 /* SHR internal */ 100 #define IMX283_REG_SHR CCI_REG16_LE(0x303b) 101 #define IMX283_SHR_MIN 11 102 103 /* 104 * Analog gain control 105 * Gain [dB] = -20log{(2048 - value [10:0]) /2048} 106 * Range: 0dB to approximately +27dB 107 */ 108 #define IMX283_REG_ANALOG_GAIN CCI_REG16_LE(0x3042) 109 #define IMX283_ANA_GAIN_MIN 0 110 #define IMX283_ANA_GAIN_MAX 1957 111 #define IMX283_ANA_GAIN_STEP 1 112 #define IMX283_ANA_GAIN_DEFAULT 0x0 113 114 /* 115 * Digital gain control 116 * Gain [dB] = value * 6 117 * Range: 0dB to +18db 118 */ 119 #define IMX283_REG_DIGITAL_GAIN CCI_REG8(0x3044) 120 #define IMX283_DGTL_GAIN_MIN 0 121 #define IMX283_DGTL_GAIN_MAX 3 122 #define IMX283_DGTL_GAIN_DEFAULT 0 123 #define IMX283_DGTL_GAIN_STEP 1 124 125 #define IMX283_REG_HTRIMMING_START CCI_REG16_LE(0x3058) 126 #define IMX283_REG_HTRIMMING_END CCI_REG16_LE(0x305a) 127 128 #define IMX283_REG_MDSEL18 CCI_REG16_LE(0x30f6) 129 130 /* Master Mode Operation Control */ 131 #define IMX283_REG_XMSTA CCI_REG8(0x3105) 132 #define IMX283_XMSTA_START 0 133 #define IMX283_XMSTA_STOP BIT(0) 134 135 #define IMX283_REG_SYNCDRV CCI_REG8(0x3107) 136 #define IMX283_SYNCDRV_XHS_XVS (0xa0 | 0x02) 137 #define IMX283_SYNCDRV_HIZ (0xa0 | 0x03) 138 139 /* PLL Standby */ 140 #define IMX283_REG_STBPL CCI_REG8(0x320b) 141 #define IMX283_STBPL_NORMAL 0x00 142 #define IMX283_STBPL_STANDBY 0x03 143 144 /* Input Frequency Setting */ 145 #define IMX283_REG_PLRD1 CCI_REG8(0x36c1) 146 #define IMX283_REG_PLRD2 CCI_REG16_LE(0x36c2) 147 #define IMX283_REG_PLRD3 CCI_REG8(0x36f7) 148 #define IMX283_REG_PLRD4 CCI_REG8(0x36f8) 149 150 #define IMX283_REG_PLSTMG02 CCI_REG8(0x36aa) 151 #define IMX283_PLSTMG02_VAL 0x00 152 153 #define IMX283_REG_MIPI_CLK CCI_REG8(0x3a43) 154 #define IMX283_MIPI_CLK_NONCONTINUOUS BIT(0) 155 156 #define IMX283_REG_EBD_X_OUT_SIZE CCI_REG16_LE(0x3a54) 157 158 /* Test pattern generator */ 159 #define IMX283_REG_TPG_CTRL CCI_REG8(0x3156) 160 #define IMX283_TPG_CTRL_CLKEN BIT(0) 161 #define IMX283_TPG_CTRL_PATEN BIT(4) 162 163 #define IMX283_REG_TPG_PAT CCI_REG8(0x3157) 164 #define IMX283_TPG_PAT_ALL_000 0x00 165 #define IMX283_TPG_PAT_ALL_FFF 0x01 166 #define IMX283_TPG_PAT_ALL_555 0x02 167 #define IMX283_TPG_PAT_ALL_AAA 0x03 168 #define IMX283_TPG_PAT_H_COLOR_BARS 0x0a 169 #define IMX283_TPG_PAT_V_COLOR_BARS 0x0b 170 171 /* Exposure control */ 172 #define IMX283_EXPOSURE_MIN 52 173 #define IMX283_EXPOSURE_STEP 1 174 #define IMX283_EXPOSURE_DEFAULT 1000 175 #define IMX283_EXPOSURE_MAX 49865 176 177 #define IMAGE_PAD 0 178 179 #define IMX283_XCLR_MIN_DELAY_US (1 * USEC_PER_MSEC) 180 #define IMX283_XCLR_DELAY_RANGE_US (1 * USEC_PER_MSEC) 181 182 /* IMX283 native and active pixel array size. */ 183 static const struct v4l2_rect imx283_native_area = { 184 .top = 0, 185 .left = 0, 186 .width = 5592, 187 .height = 3710, 188 }; 189 190 static const struct v4l2_rect imx283_active_area = { 191 .top = 40, 192 .left = 108, 193 .width = 5472, 194 .height = 3648, 195 }; 196 197 struct imx283_reg_list { 198 unsigned int num_of_regs; 199 const struct cci_reg_sequence *regs; 200 }; 201 202 /* Mode : resolution and related config values */ 203 struct imx283_mode { 204 unsigned int mode; 205 206 /* Bits per pixel */ 207 unsigned int bpp; 208 209 /* Frame width */ 210 unsigned int width; 211 212 /* Frame height */ 213 unsigned int height; 214 215 /* 216 * Minimum horizontal timing in pixel-units 217 * 218 * Note that HMAX is written in 72MHz units, and the datasheet assumes a 219 * 720MHz link frequency. Convert datasheet values with the following: 220 * 221 * For 12 bpp modes (480Mbps) convert with: 222 * hmax = [hmax in 72MHz units] * 480 / 72 223 * 224 * For 10 bpp modes (576Mbps) convert with: 225 * hmax = [hmax in 72MHz units] * 576 / 72 226 */ 227 u32 min_hmax; 228 229 /* minimum V-timing in lines */ 230 u32 min_vmax; 231 232 /* default H-timing */ 233 u32 default_hmax; 234 235 /* default V-timing */ 236 u32 default_vmax; 237 238 /* minimum SHR */ 239 u32 min_shr; 240 241 /* 242 * Per-mode vertical crop constants used to calculate values 243 * of IMX283REG_WIDCUT and IMX283_REG_VWINPOS. 244 */ 245 u32 veff; 246 u32 vst; 247 u32 vct; 248 249 /* Horizontal and vertical binning ratio */ 250 u8 hbin_ratio; 251 u8 vbin_ratio; 252 253 /* Optical Blanking */ 254 u32 horizontal_ob; 255 u32 vertical_ob; 256 257 /* Analog crop rectangle. */ 258 struct v4l2_rect crop; 259 }; 260 261 struct imx283_input_frequency { 262 unsigned int mhz; 263 unsigned int reg_count; 264 struct cci_reg_sequence regs[4]; 265 }; 266 267 static const struct imx283_input_frequency imx283_frequencies[] = { 268 { 269 .mhz = 6 * HZ_PER_MHZ, 270 .reg_count = 4, 271 .regs = { 272 { IMX283_REG_PLRD1, 0x00 }, 273 { IMX283_REG_PLRD2, 0x00f0 }, 274 { IMX283_REG_PLRD3, 0x00 }, 275 { IMX283_REG_PLRD4, 0xc0 }, 276 }, 277 }, 278 { 279 .mhz = 12 * HZ_PER_MHZ, 280 .reg_count = 4, 281 .regs = { 282 { IMX283_REG_PLRD1, 0x01 }, 283 { IMX283_REG_PLRD2, 0x00f0 }, 284 { IMX283_REG_PLRD3, 0x01 }, 285 { IMX283_REG_PLRD4, 0xc0 }, 286 }, 287 }, 288 { 289 .mhz = 18 * HZ_PER_MHZ, 290 .reg_count = 4, 291 .regs = { 292 { IMX283_REG_PLRD1, 0x01 }, 293 { IMX283_REG_PLRD2, 0x00a0 }, 294 { IMX283_REG_PLRD3, 0x01 }, 295 { IMX283_REG_PLRD4, 0x80 }, 296 }, 297 }, 298 { 299 .mhz = 24 * HZ_PER_MHZ, 300 .reg_count = 4, 301 .regs = { 302 { IMX283_REG_PLRD1, 0x02 }, 303 { IMX283_REG_PLRD2, 0x00f0 }, 304 { IMX283_REG_PLRD3, 0x02 }, 305 { IMX283_REG_PLRD4, 0xc0 }, 306 }, 307 }, 308 }; 309 310 enum imx283_modes { 311 IMX283_MODE_0, 312 IMX283_MODE_1, 313 IMX283_MODE_1A, 314 IMX283_MODE_1S, 315 IMX283_MODE_2, 316 IMX283_MODE_2A, 317 IMX283_MODE_3, 318 IMX283_MODE_4, 319 IMX283_MODE_5, 320 IMX283_MODE_6, 321 }; 322 323 struct imx283_readout_mode { 324 u8 mdsel1; 325 u8 mdsel2; 326 u8 mdsel3; 327 u8 mdsel4; 328 }; 329 330 static const struct imx283_readout_mode imx283_readout_modes[] = { 331 /* All pixel scan modes */ 332 [IMX283_MODE_0] = { 0x04, 0x03, 0x10, 0x00 }, /* 12 bit */ 333 [IMX283_MODE_1] = { 0x04, 0x01, 0x00, 0x00 }, /* 10 bit */ 334 [IMX283_MODE_1A] = { 0x04, 0x01, 0x20, 0x50 }, /* 10 bit */ 335 [IMX283_MODE_1S] = { 0x04, 0x41, 0x20, 0x50 }, /* 10 bit */ 336 337 /* Horizontal / Vertical 2/2-line binning */ 338 [IMX283_MODE_2] = { 0x0d, 0x11, 0x50, 0x00 }, /* 12 bit */ 339 [IMX283_MODE_2A] = { 0x0d, 0x11, 0x70, 0x50 }, /* 12 bit */ 340 341 /* Horizontal / Vertical 3/3-line binning */ 342 [IMX283_MODE_3] = { 0x1e, 0x18, 0x10, 0x00 }, /* 12 bit */ 343 344 /* Vertical 2/9 subsampling, horizontal 3 binning cropping */ 345 [IMX283_MODE_4] = { 0x29, 0x18, 0x30, 0x50 }, /* 12 bit */ 346 347 /* Vertical 2/19 subsampling binning, horizontal 3 binning */ 348 [IMX283_MODE_5] = { 0x2d, 0x18, 0x10, 0x00 }, /* 12 bit */ 349 350 /* Vertical 2 binning horizontal 2/4, subsampling 16:9 cropping */ 351 [IMX283_MODE_6] = { 0x18, 0x21, 0x00, 0x09 }, /* 10 bit */ 352 353 /* 354 * New modes should make sure the offset period is complied. 355 * See imx283_exposure() for reference. 356 */ 357 }; 358 359 static const struct cci_reg_sequence mipi_data_rate_1440Mbps[] = { 360 /* The default register settings provide the 1440Mbps rate */ 361 { CCI_REG8(0x36c5), 0x00 }, /* Undocumented */ 362 { CCI_REG8(0x3ac4), 0x00 }, /* Undocumented */ 363 364 { IMX283_REG_STBPL, 0x00 }, 365 { IMX283_REG_TCLKPOST, 0xa7 }, 366 { IMX283_REG_THSPREPARE, 0x6f }, 367 { IMX283_REG_THSZERO, 0x9f }, 368 { IMX283_REG_THSTRAIL, 0x5f }, 369 { IMX283_REG_TCLKTRAIL, 0x5f }, 370 { IMX283_REG_TCLKPREPARE, 0x6f }, 371 { IMX283_REG_TCLKZERO, 0x017f }, 372 { IMX283_REG_TLPX, 0x4f }, 373 { IMX283_REG_THSEXIT, 0x47 }, 374 { IMX283_REG_TCLKPRE, 0x07 }, 375 { IMX283_REG_SYSMODE, 0x02 }, 376 }; 377 378 static const struct cci_reg_sequence mipi_data_rate_720Mbps[] = { 379 /* Undocumented Additions "For 720MBps" Setting */ 380 { CCI_REG8(0x36c5), 0x01 }, /* Undocumented */ 381 { CCI_REG8(0x3ac4), 0x01 }, /* Undocumented */ 382 383 { IMX283_REG_STBPL, 0x00 }, 384 { IMX283_REG_TCLKPOST, 0x77 }, 385 { IMX283_REG_THSPREPARE, 0x37 }, 386 { IMX283_REG_THSZERO, 0x67 }, 387 { IMX283_REG_THSTRAIL, 0x37 }, 388 { IMX283_REG_TCLKTRAIL, 0x37 }, 389 { IMX283_REG_TCLKPREPARE, 0x37 }, 390 { IMX283_REG_TCLKZERO, 0xdf }, 391 { IMX283_REG_TLPX, 0x2f }, 392 { IMX283_REG_THSEXIT, 0x47 }, 393 { IMX283_REG_TCLKPRE, 0x0f }, 394 { IMX283_REG_SYSMODE, 0x02 }, 395 }; 396 397 static const s64 link_frequencies[] = { 398 720 * HZ_PER_MHZ, /* 1440 Mbps lane data rate */ 399 360 * HZ_PER_MHZ, /* 720 Mbps data lane rate */ 400 }; 401 402 static const struct imx283_reg_list link_freq_reglist[] = { 403 { /* 720 MHz */ 404 .num_of_regs = ARRAY_SIZE(mipi_data_rate_1440Mbps), 405 .regs = mipi_data_rate_1440Mbps, 406 }, 407 { /* 360 MHz */ 408 .num_of_regs = ARRAY_SIZE(mipi_data_rate_720Mbps), 409 .regs = mipi_data_rate_720Mbps, 410 }, 411 }; 412 413 /* Mode configs */ 414 static const struct imx283_mode supported_modes_12bit[] = { 415 { 416 /* 20MPix 21.40 fps readout mode 0 */ 417 .mode = IMX283_MODE_0, 418 .bpp = 12, 419 .width = 5472, 420 .height = 3648, 421 .min_hmax = 5914, /* 887 @ 480MHz/72MHz */ 422 .min_vmax = 3793, /* Lines */ 423 424 .veff = 3694, 425 .vst = 0, 426 .vct = 0, 427 428 .hbin_ratio = 1, 429 .vbin_ratio = 1, 430 431 /* 20.00 FPS */ 432 .default_hmax = 6000, /* 900 @ 480MHz/72MHz */ 433 .default_vmax = 4000, 434 435 .min_shr = 11, 436 .horizontal_ob = 96, 437 .vertical_ob = 16, 438 .crop = { 439 .top = 40, 440 .left = 108, 441 .width = 5472, 442 .height = 3648, 443 }, 444 }, 445 { 446 /* 447 * Readout mode 2 : 2/2 binned mode (2736x1824) 448 */ 449 .mode = IMX283_MODE_2, 450 .bpp = 12, 451 .width = 2736, 452 .height = 1824, 453 .min_hmax = 2414, /* Pixels (362 * 480MHz/72MHz + padding) */ 454 .min_vmax = 3840, /* Lines */ 455 456 /* 50.00 FPS */ 457 .default_hmax = 2500, /* 375 @ 480MHz/72Mhz */ 458 .default_vmax = 3840, 459 460 .veff = 1824, 461 .vst = 0, 462 .vct = 0, 463 464 .hbin_ratio = 2, 465 .vbin_ratio = 2, 466 467 .min_shr = 12, 468 .horizontal_ob = 48, 469 .vertical_ob = 4, 470 471 .crop = { 472 .top = 40, 473 .left = 108, 474 .width = 5472, 475 .height = 3648, 476 }, 477 }, 478 { 479 /* 480 * Readout mode 3 : 3/3 binned mode (1824x1216) 481 */ 482 .mode = IMX283_MODE_3, 483 .bpp = 12, 484 .width = 1824, 485 .height = 1216, 486 .min_hmax = 1894, /* Pixels (284 * 480MHz/72MHz + padding) */ 487 .min_vmax = 4200, /* Lines */ 488 489 /* 60.00 fps */ 490 .default_hmax = 1900, /* 285 @ 480MHz/72Mhz */ 491 .default_vmax = 4200, 492 493 .veff = 1234, 494 .vst = 0, 495 .vct = 0, 496 497 .hbin_ratio = 3, 498 .vbin_ratio = 3, 499 500 .min_shr = 16, 501 .horizontal_ob = 32, 502 .vertical_ob = 4, 503 504 .crop = { 505 .top = 40, 506 .left = 108, 507 .width = 5472, 508 .height = 3648, 509 }, 510 }, 511 }; 512 513 static const struct imx283_mode supported_modes_10bit[] = { 514 { 515 /* 20MPix 25.48 fps readout mode 1 */ 516 .mode = IMX283_MODE_1, 517 .bpp = 10, 518 .width = 5472, 519 .height = 3648, 520 .min_hmax = 5960, /* 745 @ 576MHz / 72MHz */ 521 .min_vmax = 3793, 522 523 /* 25.00 FPS */ 524 .default_hmax = 6000, /* 750 @ 576MHz / 72MHz */ 525 .default_vmax = 3840, 526 527 .min_shr = 10, 528 .horizontal_ob = 96, 529 .vertical_ob = 16, 530 .crop = { 531 .top = 40, 532 .left = 108, 533 .width = 5472, 534 .height = 3648, 535 }, 536 }, 537 }; 538 539 static const u32 imx283_mbus_codes[] = { 540 MEDIA_BUS_FMT_SRGGB12_1X12, 541 MEDIA_BUS_FMT_SRGGB10_1X10, 542 }; 543 544 /* regulator supplies */ 545 static const char *const imx283_supply_name[] = { 546 "vadd", /* Analog (2.9V) supply */ 547 "vdd1", /* Supply Voltage 2 (1.8V) supply */ 548 "vdd2", /* Supply Voltage 3 (1.2V) supply */ 549 }; 550 551 struct imx283 { 552 struct device *dev; 553 struct regmap *cci; 554 555 const struct imx283_input_frequency *freq; 556 557 struct v4l2_subdev sd; 558 struct media_pad pad; 559 560 struct clk *xclk; 561 562 struct gpio_desc *reset_gpio; 563 struct regulator_bulk_data supplies[ARRAY_SIZE(imx283_supply_name)]; 564 565 /* V4L2 Controls */ 566 struct v4l2_ctrl_handler ctrl_handler; 567 struct v4l2_ctrl *exposure; 568 struct v4l2_ctrl *vblank; 569 struct v4l2_ctrl *hblank; 570 struct v4l2_ctrl *vflip; 571 572 bool mipi_clk_noncontinuous; 573 unsigned long link_freq_bitmap; 574 575 u16 hmax; 576 u32 vmax; 577 }; 578 579 static inline struct imx283 *to_imx283(struct v4l2_subdev *sd) 580 { 581 return container_of_const(sd, struct imx283, sd); 582 } 583 584 static inline void get_mode_table(unsigned int code, 585 const struct imx283_mode **mode_list, 586 unsigned int *num_modes) 587 { 588 switch (code) { 589 case MEDIA_BUS_FMT_SRGGB12_1X12: 590 case MEDIA_BUS_FMT_SGRBG12_1X12: 591 case MEDIA_BUS_FMT_SGBRG12_1X12: 592 case MEDIA_BUS_FMT_SBGGR12_1X12: 593 *mode_list = supported_modes_12bit; 594 *num_modes = ARRAY_SIZE(supported_modes_12bit); 595 break; 596 597 case MEDIA_BUS_FMT_SRGGB10_1X10: 598 case MEDIA_BUS_FMT_SGRBG10_1X10: 599 case MEDIA_BUS_FMT_SGBRG10_1X10: 600 case MEDIA_BUS_FMT_SBGGR10_1X10: 601 *mode_list = supported_modes_10bit; 602 *num_modes = ARRAY_SIZE(supported_modes_10bit); 603 break; 604 default: 605 *mode_list = NULL; 606 *num_modes = 0; 607 break; 608 } 609 } 610 611 /* Calculate the Pixel Rate based on the current mode */ 612 static u64 imx283_pixel_rate(struct imx283 *imx283, 613 const struct imx283_mode *mode) 614 { 615 u64 link_frequency = link_frequencies[__ffs(imx283->link_freq_bitmap)]; 616 unsigned int bpp = mode->bpp; 617 const unsigned int ddr = 2; /* Double Data Rate */ 618 const unsigned int lanes = 4; /* Only 4 lane support */ 619 u64 numerator = link_frequency * ddr * lanes; 620 621 do_div(numerator, bpp); 622 623 return numerator; 624 } 625 626 /* Convert from a variable pixel_rate to 72 MHz clock cycles */ 627 static u64 imx283_internal_clock(unsigned int pixel_rate, unsigned int pixels) 628 { 629 /* 630 * Determine the following operation without overflow: 631 * pixels = 72 Mhz / pixel_rate 632 * 633 * The internal clock at 72MHz and Pixel Rate (between 240 and 576MHz) 634 * can easily overflow this calculation, so pre-divide to simplify. 635 */ 636 const u32 iclk_pre = 72; 637 const u32 pclk_pre = pixel_rate / HZ_PER_MHZ; 638 u64 numerator = pixels * iclk_pre; 639 640 do_div(numerator, pclk_pre); 641 642 return numerator; 643 } 644 645 /* Internal clock (72MHz) to Pixel Rate clock (Variable) */ 646 static u64 imx283_iclk_to_pix(unsigned int pixel_rate, unsigned int cycles) 647 { 648 /* 649 * Determine the following operation without overflow: 650 * cycles * pixel_rate / 72 MHz 651 * 652 * The internal clock at 72MHz and Pixel Rate (between 240 and 576MHz) 653 * can easily overflow this calculation, so pre-divide to simplify. 654 */ 655 const u32 iclk_pre = 72; 656 const u32 pclk_pre = pixel_rate / HZ_PER_MHZ; 657 u64 numerator = cycles * pclk_pre; 658 659 do_div(numerator, iclk_pre); 660 661 return numerator; 662 } 663 664 /* Determine the exposure based on current hmax, vmax and a given SHR */ 665 static u32 imx283_exposure(struct imx283 *imx283, 666 const struct imx283_mode *mode, u64 shr) 667 { 668 u32 svr = 0; /* SVR feature is not currently supported */ 669 u32 offset; 670 u64 numerator; 671 672 /* Number of clocks per internal offset period */ 673 offset = mode->mode == IMX283_MODE_0 ? 209 : 157; 674 numerator = (imx283->vmax * (svr + 1) - shr) * imx283->hmax + offset; 675 676 do_div(numerator, imx283->hmax); 677 678 return clamp(numerator, 0, U32_MAX); 679 } 680 681 static void imx283_exposure_limits(struct imx283 *imx283, 682 const struct imx283_mode *mode, 683 s64 *min_exposure, s64 *max_exposure) 684 { 685 u32 svr = 0; /* SVR feature is not currently supported */ 686 u64 min_shr = mode->min_shr; 687 /* Global Shutter is not supported */ 688 u64 max_shr = (svr + 1) * imx283->vmax - 4; 689 690 max_shr = min(max_shr, BIT(16) - 1); 691 692 *min_exposure = imx283_exposure(imx283, mode, max_shr); 693 *max_exposure = imx283_exposure(imx283, mode, min_shr); 694 } 695 696 /* 697 * Integration Time [s] = [ {VMAX x (SVR + 1) – (SHR)} x HMAX + offset ] 698 * / [ 72 x 10^6 ] 699 */ 700 static u32 imx283_shr(struct imx283 *imx283, const struct imx283_mode *mode, 701 u32 exposure) 702 { 703 u32 svr = 0; /* SVR feature is not currently supported */ 704 u32 offset; 705 u64 temp; 706 707 /* Number of clocks per internal offset period */ 708 offset = mode->mode == IMX283_MODE_0 ? 209 : 157; 709 temp = ((u64)exposure * imx283->hmax - offset); 710 do_div(temp, imx283->hmax); 711 712 return (imx283->vmax * (svr + 1) - temp); 713 } 714 715 static const char * const imx283_tpg_menu[] = { 716 "Disabled", 717 "All 000h", 718 "All FFFh", 719 "All 555h", 720 "All AAAh", 721 "Horizontal color bars", 722 "Vertical color bars", 723 }; 724 725 static const int imx283_tpg_val[] = { 726 IMX283_TPG_PAT_ALL_000, 727 IMX283_TPG_PAT_ALL_000, 728 IMX283_TPG_PAT_ALL_FFF, 729 IMX283_TPG_PAT_ALL_555, 730 IMX283_TPG_PAT_ALL_AAA, 731 IMX283_TPG_PAT_H_COLOR_BARS, 732 IMX283_TPG_PAT_V_COLOR_BARS, 733 }; 734 735 static int imx283_update_test_pattern(struct imx283 *imx283, u32 pattern_index) 736 { 737 int ret; 738 739 if (pattern_index >= ARRAY_SIZE(imx283_tpg_val)) 740 return -EINVAL; 741 742 if (!pattern_index) 743 return cci_write(imx283->cci, IMX283_REG_TPG_CTRL, 0x00, NULL); 744 745 ret = cci_write(imx283->cci, IMX283_REG_TPG_PAT, 746 imx283_tpg_val[pattern_index], NULL); 747 if (ret) 748 return ret; 749 750 return cci_write(imx283->cci, IMX283_REG_TPG_CTRL, 751 IMX283_TPG_CTRL_CLKEN | IMX283_TPG_CTRL_PATEN, NULL); 752 } 753 754 static int imx283_set_ctrl(struct v4l2_ctrl *ctrl) 755 { 756 struct imx283 *imx283 = container_of(ctrl->handler, struct imx283, 757 ctrl_handler); 758 const struct imx283_mode *mode; 759 struct v4l2_mbus_framefmt *fmt; 760 const struct imx283_mode *mode_list; 761 struct v4l2_subdev_state *state; 762 unsigned int num_modes; 763 u64 shr, pixel_rate; 764 int ret = 0; 765 766 state = v4l2_subdev_get_locked_active_state(&imx283->sd); 767 fmt = v4l2_subdev_state_get_format(state, 0); 768 769 get_mode_table(fmt->code, &mode_list, &num_modes); 770 mode = v4l2_find_nearest_size(mode_list, num_modes, width, height, 771 fmt->width, fmt->height); 772 773 /* 774 * The VBLANK control may change the limits of usable exposure, so check 775 * and adjust if necessary. 776 */ 777 if (ctrl->id == V4L2_CID_VBLANK) { 778 /* Honour the VBLANK limits when setting exposure. */ 779 s64 current_exposure, max_exposure, min_exposure; 780 781 imx283->vmax = mode->height + ctrl->val; 782 783 imx283_exposure_limits(imx283, mode, 784 &min_exposure, &max_exposure); 785 786 current_exposure = imx283->exposure->val; 787 current_exposure = clamp(current_exposure, min_exposure, 788 max_exposure); 789 790 __v4l2_ctrl_modify_range(imx283->exposure, min_exposure, 791 max_exposure, 1, current_exposure); 792 } 793 794 /* 795 * Applying V4L2 control value only happens 796 * when power is up for streaming 797 */ 798 if (!pm_runtime_get_if_active(imx283->dev)) 799 return 0; 800 801 switch (ctrl->id) { 802 case V4L2_CID_EXPOSURE: 803 shr = imx283_shr(imx283, mode, ctrl->val); 804 dev_dbg(imx283->dev, "V4L2_CID_EXPOSURE : %d - SHR: %lld\n", 805 ctrl->val, shr); 806 ret = cci_write(imx283->cci, IMX283_REG_SHR, shr, NULL); 807 break; 808 809 case V4L2_CID_HBLANK: 810 pixel_rate = imx283_pixel_rate(imx283, mode); 811 imx283->hmax = imx283_internal_clock(pixel_rate, mode->width + ctrl->val); 812 dev_dbg(imx283->dev, "V4L2_CID_HBLANK : %d HMAX : %u\n", 813 ctrl->val, imx283->hmax); 814 ret = cci_write(imx283->cci, IMX283_REG_HMAX, imx283->hmax, NULL); 815 break; 816 817 case V4L2_CID_VBLANK: 818 imx283->vmax = mode->height + ctrl->val; 819 dev_dbg(imx283->dev, "V4L2_CID_VBLANK : %d VMAX : %u\n", 820 ctrl->val, imx283->vmax); 821 ret = cci_write(imx283->cci, IMX283_REG_VMAX, imx283->vmax, NULL); 822 break; 823 824 case V4L2_CID_ANALOGUE_GAIN: 825 ret = cci_write(imx283->cci, IMX283_REG_ANALOG_GAIN, ctrl->val, NULL); 826 break; 827 828 case V4L2_CID_DIGITAL_GAIN: 829 ret = cci_write(imx283->cci, IMX283_REG_DIGITAL_GAIN, ctrl->val, NULL); 830 break; 831 832 case V4L2_CID_VFLIP: 833 /* 834 * VFLIP is managed by BIT(0) of IMX283_REG_HTRIMMING address, hence 835 * both need to be set simultaneously. 836 */ 837 if (ctrl->val) { 838 cci_write(imx283->cci, IMX283_REG_HTRIMMING, 839 IMX283_HTRIMMING_EN | IMX283_MDVREV, &ret); 840 } else { 841 cci_write(imx283->cci, IMX283_REG_HTRIMMING, 842 IMX283_HTRIMMING_EN, &ret); 843 } 844 break; 845 846 case V4L2_CID_TEST_PATTERN: 847 ret = imx283_update_test_pattern(imx283, ctrl->val); 848 break; 849 850 default: 851 dev_err(imx283->dev, "ctrl(id:0x%x, val:0x%x) is not handled\n", 852 ctrl->id, ctrl->val); 853 break; 854 } 855 856 pm_runtime_put(imx283->dev); 857 858 return ret; 859 } 860 861 static const struct v4l2_ctrl_ops imx283_ctrl_ops = { 862 .s_ctrl = imx283_set_ctrl, 863 }; 864 865 static int imx283_enum_mbus_code(struct v4l2_subdev *sd, 866 struct v4l2_subdev_state *sd_state, 867 struct v4l2_subdev_mbus_code_enum *code) 868 { 869 if (code->index >= ARRAY_SIZE(imx283_mbus_codes)) 870 return -EINVAL; 871 872 code->code = imx283_mbus_codes[code->index]; 873 874 return 0; 875 } 876 877 static int imx283_enum_frame_size(struct v4l2_subdev *sd, 878 struct v4l2_subdev_state *sd_state, 879 struct v4l2_subdev_frame_size_enum *fse) 880 { 881 const struct imx283_mode *mode_list; 882 unsigned int num_modes; 883 884 get_mode_table(fse->code, &mode_list, &num_modes); 885 886 if (fse->index >= num_modes) 887 return -EINVAL; 888 889 fse->min_width = mode_list[fse->index].width; 890 fse->max_width = fse->min_width; 891 fse->min_height = mode_list[fse->index].height; 892 fse->max_height = fse->min_height; 893 894 return 0; 895 } 896 897 static void imx283_update_image_pad_format(struct imx283 *imx283, 898 const struct imx283_mode *mode, 899 struct v4l2_mbus_framefmt *format) 900 { 901 format->width = mode->width; 902 format->height = mode->height; 903 format->field = V4L2_FIELD_NONE; 904 format->colorspace = V4L2_COLORSPACE_RAW; 905 format->ycbcr_enc = V4L2_YCBCR_ENC_601; 906 format->quantization = V4L2_QUANTIZATION_FULL_RANGE; 907 format->xfer_func = V4L2_XFER_FUNC_NONE; 908 } 909 910 static int imx283_init_state(struct v4l2_subdev *sd, 911 struct v4l2_subdev_state *state) 912 { 913 struct imx283 *imx283 = to_imx283(sd); 914 struct v4l2_mbus_framefmt *format; 915 const struct imx283_mode *mode; 916 struct v4l2_rect *crop; 917 918 /* Initialize try_fmt */ 919 format = v4l2_subdev_state_get_format(state, IMAGE_PAD); 920 921 mode = &supported_modes_12bit[0]; 922 format->code = MEDIA_BUS_FMT_SRGGB12_1X12; 923 imx283_update_image_pad_format(imx283, mode, format); 924 925 /* Initialize crop rectangle to mode default */ 926 crop = v4l2_subdev_state_get_crop(state, IMAGE_PAD); 927 *crop = mode->crop; 928 929 return 0; 930 } 931 932 static void imx283_set_framing_limits(struct imx283 *imx283, 933 const struct imx283_mode *mode) 934 { 935 u64 pixel_rate = imx283_pixel_rate(imx283, mode); 936 u64 min_hblank, max_hblank, def_hblank; 937 938 /* Initialise hmax and vmax for exposure calculations */ 939 imx283->hmax = imx283_internal_clock(pixel_rate, mode->default_hmax); 940 imx283->vmax = mode->default_vmax; 941 942 /* 943 * Horizontal Blanking 944 * Convert the HMAX_MAX (72MHz) to Pixel rate values for HBLANK_MAX 945 */ 946 min_hblank = mode->min_hmax - mode->width; 947 max_hblank = imx283_iclk_to_pix(pixel_rate, IMX283_HMAX_MAX) - mode->width; 948 def_hblank = mode->default_hmax - mode->width; 949 __v4l2_ctrl_modify_range(imx283->hblank, min_hblank, max_hblank, 1, 950 def_hblank); 951 __v4l2_ctrl_s_ctrl(imx283->hblank, def_hblank); 952 953 /* Vertical Blanking */ 954 __v4l2_ctrl_modify_range(imx283->vblank, mode->min_vmax - mode->height, 955 IMX283_VMAX_MAX - mode->height, 1, 956 mode->default_vmax - mode->height); 957 __v4l2_ctrl_s_ctrl(imx283->vblank, mode->default_vmax - mode->height); 958 } 959 960 static int imx283_set_pad_format(struct v4l2_subdev *sd, 961 struct v4l2_subdev_state *sd_state, 962 struct v4l2_subdev_format *fmt) 963 { 964 struct v4l2_mbus_framefmt *format; 965 const struct imx283_mode *mode; 966 struct imx283 *imx283 = to_imx283(sd); 967 const struct imx283_mode *mode_list; 968 unsigned int num_modes; 969 970 get_mode_table(fmt->format.code, &mode_list, &num_modes); 971 972 mode = v4l2_find_nearest_size(mode_list, num_modes, width, height, 973 fmt->format.width, fmt->format.height); 974 975 fmt->format.width = mode->width; 976 fmt->format.height = mode->height; 977 fmt->format.field = V4L2_FIELD_NONE; 978 fmt->format.colorspace = V4L2_COLORSPACE_RAW; 979 fmt->format.ycbcr_enc = V4L2_YCBCR_ENC_601; 980 fmt->format.quantization = V4L2_QUANTIZATION_FULL_RANGE; 981 fmt->format.xfer_func = V4L2_XFER_FUNC_NONE; 982 983 format = v4l2_subdev_state_get_format(sd_state, 0); 984 985 if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) 986 imx283_set_framing_limits(imx283, mode); 987 988 *format = fmt->format; 989 990 return 0; 991 } 992 993 static int imx283_standby_cancel(struct imx283 *imx283) 994 { 995 unsigned int link_freq_idx; 996 u8 mipi_clk; 997 int ret = 0; 998 999 cci_write(imx283->cci, IMX283_REG_STANDBY, 1000 IMX283_STBLOGIC | IMX283_STBDV, &ret); 1001 1002 /* Configure PLL clocks based on the xclk */ 1003 cci_multi_reg_write(imx283->cci, imx283->freq->regs, 1004 imx283->freq->reg_count, &ret); 1005 1006 dev_dbg(imx283->dev, "Using clk freq %ld MHz", 1007 imx283->freq->mhz / HZ_PER_MHZ); 1008 1009 /* Initialise communication */ 1010 cci_write(imx283->cci, IMX283_REG_PLSTMG08, IMX283_PLSTMG08_VAL, &ret); 1011 cci_write(imx283->cci, IMX283_REG_PLSTMG02, IMX283_PLSTMG02_VAL, &ret); 1012 1013 /* Enable PLL */ 1014 cci_write(imx283->cci, IMX283_REG_STBPL, IMX283_STBPL_NORMAL, &ret); 1015 1016 /* Configure MIPI clock mode */ 1017 mipi_clk = imx283->mipi_clk_noncontinuous ? IMX283_MIPI_CLK_NONCONTINUOUS : 0; 1018 cci_write(imx283->cci, IMX283_REG_MIPI_CLK, mipi_clk, &ret); 1019 1020 /* Configure the MIPI link speed */ 1021 link_freq_idx = __ffs(imx283->link_freq_bitmap); 1022 cci_multi_reg_write(imx283->cci, link_freq_reglist[link_freq_idx].regs, 1023 link_freq_reglist[link_freq_idx].num_of_regs, 1024 &ret); 1025 1026 /* 1st Stabilisation period of 1 ms or more */ 1027 usleep_range(1000, 2000); 1028 1029 /* Activate */ 1030 cci_write(imx283->cci, IMX283_REG_STANDBY, IMX283_ACTIVE, &ret); 1031 1032 /* 2nd Stabilisation period of 19ms or more */ 1033 usleep_range(19000, 20000); 1034 1035 cci_write(imx283->cci, IMX283_REG_CLAMP, IMX283_CLPSQRST, &ret); 1036 1037 return ret; 1038 } 1039 1040 /* Start streaming */ 1041 static int imx283_start_streaming(struct imx283 *imx283, 1042 struct v4l2_subdev_state *state) 1043 { 1044 const struct imx283_readout_mode *readout; 1045 const struct imx283_mode *mode; 1046 const struct v4l2_mbus_framefmt *fmt; 1047 const struct imx283_mode *mode_list; 1048 unsigned int num_modes; 1049 u32 v_widcut; 1050 s32 v_pos; 1051 u32 write_v_size; 1052 u32 y_out_size; 1053 int ret = 0; 1054 1055 fmt = v4l2_subdev_state_get_format(state, 0); 1056 get_mode_table(fmt->code, &mode_list, &num_modes); 1057 mode = v4l2_find_nearest_size(mode_list, num_modes, width, height, 1058 fmt->width, fmt->height); 1059 1060 ret = imx283_standby_cancel(imx283); 1061 if (ret) { 1062 dev_err(imx283->dev, "failed to cancel standby\n"); 1063 return ret; 1064 } 1065 1066 /* 1067 * Set the readout mode registers. 1068 * MDSEL3 and MDSEL4 are updated to enable Arbitrary Vertical Cropping. 1069 */ 1070 readout = &imx283_readout_modes[mode->mode]; 1071 cci_write(imx283->cci, IMX283_REG_MDSEL1, readout->mdsel1, &ret); 1072 cci_write(imx283->cci, IMX283_REG_MDSEL2, readout->mdsel2, &ret); 1073 cci_write(imx283->cci, IMX283_REG_MDSEL3, 1074 readout->mdsel3 | IMX283_MDSEL3_VCROP_EN, &ret); 1075 cci_write(imx283->cci, IMX283_REG_MDSEL4, 1076 readout->mdsel4 | IMX283_MDSEL4_VCROP_EN, &ret); 1077 1078 /* Mode 1S specific entries from the Readout Drive Mode Tables */ 1079 if (mode->mode == IMX283_MODE_1S) { 1080 cci_write(imx283->cci, IMX283_REG_MDSEL7, 0x01, &ret); 1081 cci_write(imx283->cci, IMX283_REG_MDSEL18, 0x1098, &ret); 1082 } 1083 1084 if (ret) { 1085 dev_err(imx283->dev, "failed to set readout\n"); 1086 return ret; 1087 } 1088 1089 /* Initialise SVR. Unsupported for now - Always 0 */ 1090 cci_write(imx283->cci, IMX283_REG_SVR, 0x00, &ret); 1091 1092 dev_dbg(imx283->dev, "Mode: Size %d x %d\n", mode->width, mode->height); 1093 dev_dbg(imx283->dev, "Analogue Crop (in the mode) (%d,%d)/%ux%u\n", 1094 mode->crop.left, 1095 mode->crop.top, 1096 mode->crop.width, 1097 mode->crop.height); 1098 1099 y_out_size = mode->crop.height / mode->vbin_ratio; 1100 write_v_size = y_out_size + mode->vertical_ob; 1101 /* 1102 * cropping start position = (VWINPOS – Vst) × 2 1103 * cropping width = Veff – (VWIDCUT – Vct) × 2 1104 */ 1105 v_pos = imx283->vflip->val ? 1106 ((-mode->crop.top / mode->vbin_ratio) / 2) + mode->vst : 1107 ((mode->crop.top / mode->vbin_ratio) / 2) + mode->vst; 1108 v_widcut = ((mode->veff - y_out_size) / 2) + mode->vct; 1109 1110 cci_write(imx283->cci, IMX283_REG_Y_OUT_SIZE, y_out_size, &ret); 1111 cci_write(imx283->cci, IMX283_REG_WRITE_VSIZE, write_v_size, &ret); 1112 cci_write(imx283->cci, IMX283_REG_VWIDCUT, v_widcut, &ret); 1113 cci_write(imx283->cci, IMX283_REG_VWINPOS, v_pos, &ret); 1114 1115 cci_write(imx283->cci, IMX283_REG_OB_SIZE_V, mode->vertical_ob, &ret); 1116 1117 /* TODO: Validate mode->crop is fully contained within imx283_native_area */ 1118 cci_write(imx283->cci, IMX283_REG_HTRIMMING_START, mode->crop.left, &ret); 1119 cci_write(imx283->cci, IMX283_REG_HTRIMMING_END, 1120 mode->crop.left + mode->crop.width, &ret); 1121 1122 /* Disable embedded data */ 1123 cci_write(imx283->cci, IMX283_REG_EBD_X_OUT_SIZE, 0, &ret); 1124 1125 /* Apply customized values from controls (HMAX/VMAX/SHR) */ 1126 ret = __v4l2_ctrl_handler_setup(imx283->sd.ctrl_handler); 1127 1128 /* Start master mode */ 1129 cci_write(imx283->cci, IMX283_REG_XMSTA, IMX283_XMSTA_START, &ret); 1130 cci_write(imx283->cci, IMX283_REG_SYNCDRV, IMX283_SYNCDRV_XHS_XVS, &ret); 1131 1132 return ret; 1133 } 1134 1135 static int imx283_enable_streams(struct v4l2_subdev *sd, 1136 struct v4l2_subdev_state *state, u32 pad, 1137 u64 streams_mask) 1138 { 1139 struct imx283 *imx283 = to_imx283(sd); 1140 int ret; 1141 1142 if (pad != IMAGE_PAD) 1143 return -EINVAL; 1144 1145 ret = pm_runtime_get_sync(imx283->dev); 1146 if (ret < 0) { 1147 pm_runtime_put_noidle(imx283->dev); 1148 return ret; 1149 } 1150 1151 ret = imx283_start_streaming(imx283, state); 1152 if (ret) 1153 goto err_rpm_put; 1154 1155 return 0; 1156 1157 err_rpm_put: 1158 pm_runtime_put_autosuspend(imx283->dev); 1159 1160 return ret; 1161 } 1162 1163 static int imx283_disable_streams(struct v4l2_subdev *sd, 1164 struct v4l2_subdev_state *state, u32 pad, 1165 u64 streams_mask) 1166 { 1167 struct imx283 *imx283 = to_imx283(sd); 1168 int ret = 0; 1169 1170 if (pad != IMAGE_PAD) 1171 return -EINVAL; 1172 1173 cci_write(imx283->cci, IMX283_REG_XMSTA, IMX283_XMSTA_STOP, &ret); 1174 cci_write(imx283->cci, IMX283_REG_STANDBY, IMX283_STANDBY, &ret); 1175 1176 if (ret) 1177 dev_err(imx283->dev, "Failed to stop stream\n"); 1178 1179 pm_runtime_put_autosuspend(imx283->dev); 1180 1181 return ret; 1182 } 1183 1184 /* Power/clock management functions */ 1185 static int imx283_power_on(struct device *dev) 1186 { 1187 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1188 struct imx283 *imx283 = to_imx283(sd); 1189 int ret; 1190 1191 ret = regulator_bulk_enable(ARRAY_SIZE(imx283_supply_name), 1192 imx283->supplies); 1193 if (ret) { 1194 dev_err(imx283->dev, "failed to enable regulators\n"); 1195 return ret; 1196 } 1197 1198 ret = clk_prepare_enable(imx283->xclk); 1199 if (ret) { 1200 dev_err(imx283->dev, "failed to enable clock\n"); 1201 goto reg_off; 1202 } 1203 1204 gpiod_set_value_cansleep(imx283->reset_gpio, 0); 1205 1206 usleep_range(IMX283_XCLR_MIN_DELAY_US, 1207 IMX283_XCLR_MIN_DELAY_US + IMX283_XCLR_DELAY_RANGE_US); 1208 1209 return 0; 1210 1211 reg_off: 1212 regulator_bulk_disable(ARRAY_SIZE(imx283_supply_name), imx283->supplies); 1213 return ret; 1214 } 1215 1216 static int imx283_power_off(struct device *dev) 1217 { 1218 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1219 struct imx283 *imx283 = to_imx283(sd); 1220 1221 gpiod_set_value_cansleep(imx283->reset_gpio, 1); 1222 regulator_bulk_disable(ARRAY_SIZE(imx283_supply_name), imx283->supplies); 1223 clk_disable_unprepare(imx283->xclk); 1224 1225 return 0; 1226 } 1227 1228 static int imx283_get_regulators(struct imx283 *imx283) 1229 { 1230 unsigned int i; 1231 1232 for (i = 0; i < ARRAY_SIZE(imx283_supply_name); i++) 1233 imx283->supplies[i].supply = imx283_supply_name[i]; 1234 1235 return devm_regulator_bulk_get(imx283->dev, 1236 ARRAY_SIZE(imx283_supply_name), 1237 imx283->supplies); 1238 } 1239 1240 /* Verify chip ID */ 1241 static int imx283_identify_module(struct imx283 *imx283) 1242 { 1243 int ret; 1244 u64 val; 1245 1246 ret = cci_read(imx283->cci, IMX283_REG_CHIP_ID, &val, NULL); 1247 if (ret) { 1248 dev_err(imx283->dev, "failed to read chip id %x, with error %d\n", 1249 IMX283_CHIP_ID, ret); 1250 return ret; 1251 } 1252 1253 if (val != IMX283_CHIP_ID) { 1254 dev_err(imx283->dev, "chip id mismatch: %x!=%llx\n", 1255 IMX283_CHIP_ID, val); 1256 return -EIO; 1257 } 1258 1259 return 0; 1260 } 1261 1262 static int imx283_get_selection(struct v4l2_subdev *sd, 1263 struct v4l2_subdev_state *sd_state, 1264 struct v4l2_subdev_selection *sel) 1265 { 1266 switch (sel->target) { 1267 case V4L2_SEL_TGT_CROP: { 1268 sel->r = *v4l2_subdev_state_get_crop(sd_state, 0); 1269 return 0; 1270 } 1271 1272 case V4L2_SEL_TGT_NATIVE_SIZE: 1273 sel->r = imx283_native_area; 1274 return 0; 1275 1276 case V4L2_SEL_TGT_CROP_DEFAULT: 1277 case V4L2_SEL_TGT_CROP_BOUNDS: 1278 sel->r = imx283_active_area; 1279 return 0; 1280 default: 1281 return -EINVAL; 1282 } 1283 } 1284 1285 static const struct v4l2_subdev_video_ops imx283_video_ops = { 1286 .s_stream = v4l2_subdev_s_stream_helper, 1287 }; 1288 1289 static const struct v4l2_subdev_pad_ops imx283_pad_ops = { 1290 .enum_mbus_code = imx283_enum_mbus_code, 1291 .get_fmt = v4l2_subdev_get_fmt, 1292 .set_fmt = imx283_set_pad_format, 1293 .get_selection = imx283_get_selection, 1294 .enum_frame_size = imx283_enum_frame_size, 1295 .enable_streams = imx283_enable_streams, 1296 .disable_streams = imx283_disable_streams, 1297 }; 1298 1299 static const struct v4l2_subdev_internal_ops imx283_internal_ops = { 1300 .init_state = imx283_init_state, 1301 }; 1302 1303 static const struct v4l2_subdev_ops imx283_subdev_ops = { 1304 .video = &imx283_video_ops, 1305 .pad = &imx283_pad_ops, 1306 }; 1307 1308 /* Initialize control handlers */ 1309 static int imx283_init_controls(struct imx283 *imx283) 1310 { 1311 struct v4l2_ctrl_handler *ctrl_hdlr; 1312 struct v4l2_fwnode_device_properties props; 1313 struct v4l2_ctrl *link_freq; 1314 const struct imx283_mode *mode = &supported_modes_12bit[0]; 1315 u64 min_hblank, max_hblank, def_hblank; 1316 u64 pixel_rate; 1317 int ret; 1318 1319 ctrl_hdlr = &imx283->ctrl_handler; 1320 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 16); 1321 if (ret) 1322 return ret; 1323 1324 /* 1325 * Create the controls here, but mode specific limits are setup 1326 * in the imx283_set_framing_limits() call below. 1327 */ 1328 1329 /* By default, PIXEL_RATE is read only */ 1330 pixel_rate = imx283_pixel_rate(imx283, mode); 1331 v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops, 1332 V4L2_CID_PIXEL_RATE, pixel_rate, 1333 pixel_rate, 1, pixel_rate); 1334 1335 link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &imx283_ctrl_ops, 1336 V4L2_CID_LINK_FREQ, 1337 __fls(imx283->link_freq_bitmap), 1338 __ffs(imx283->link_freq_bitmap), 1339 link_frequencies); 1340 if (link_freq) 1341 link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1342 1343 /* Initialise vblank/hblank/exposure based on the current mode. */ 1344 imx283->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops, 1345 V4L2_CID_VBLANK, 1346 mode->min_vmax - mode->height, 1347 IMX283_VMAX_MAX, 1, 1348 mode->default_vmax - mode->height); 1349 1350 min_hblank = mode->min_hmax - mode->width; 1351 max_hblank = imx283_iclk_to_pix(pixel_rate, IMX283_HMAX_MAX) - mode->width; 1352 def_hblank = mode->default_hmax - mode->width; 1353 imx283->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops, 1354 V4L2_CID_HBLANK, min_hblank, max_hblank, 1355 1, def_hblank); 1356 1357 imx283->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops, 1358 V4L2_CID_EXPOSURE, 1359 IMX283_EXPOSURE_MIN, 1360 IMX283_EXPOSURE_MAX, 1361 IMX283_EXPOSURE_STEP, 1362 IMX283_EXPOSURE_DEFAULT); 1363 1364 v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 1365 IMX283_ANA_GAIN_MIN, IMX283_ANA_GAIN_MAX, 1366 IMX283_ANA_GAIN_STEP, IMX283_ANA_GAIN_DEFAULT); 1367 1368 v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops, V4L2_CID_DIGITAL_GAIN, 1369 IMX283_DGTL_GAIN_MIN, IMX283_DGTL_GAIN_MAX, 1370 IMX283_DGTL_GAIN_STEP, IMX283_DGTL_GAIN_DEFAULT); 1371 1372 imx283->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops, V4L2_CID_VFLIP, 1373 0, 1, 1, 0); 1374 if (imx283->vflip) 1375 imx283->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; 1376 1377 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &imx283_ctrl_ops, 1378 V4L2_CID_TEST_PATTERN, 1379 ARRAY_SIZE(imx283_tpg_menu) - 1, 1380 0, 0, imx283_tpg_menu); 1381 1382 if (ctrl_hdlr->error) { 1383 ret = ctrl_hdlr->error; 1384 dev_err(imx283->dev, "control init failed (%d)\n", ret); 1385 goto error; 1386 } 1387 1388 ret = v4l2_fwnode_device_parse(imx283->dev, &props); 1389 if (ret) 1390 goto error; 1391 1392 ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &imx283_ctrl_ops, 1393 &props); 1394 if (ret) 1395 goto error; 1396 1397 imx283->sd.ctrl_handler = ctrl_hdlr; 1398 1399 mutex_lock(imx283->ctrl_handler.lock); 1400 1401 /* Setup exposure and frame/line length limits. */ 1402 imx283_set_framing_limits(imx283, mode); 1403 1404 mutex_unlock(imx283->ctrl_handler.lock); 1405 1406 return 0; 1407 1408 error: 1409 v4l2_ctrl_handler_free(ctrl_hdlr); 1410 1411 return ret; 1412 } 1413 1414 static int imx283_parse_endpoint(struct imx283 *imx283) 1415 { 1416 struct fwnode_handle *fwnode; 1417 struct v4l2_fwnode_endpoint bus_cfg = { 1418 .bus_type = V4L2_MBUS_CSI2_DPHY 1419 }; 1420 struct fwnode_handle *ep; 1421 int ret; 1422 1423 fwnode = dev_fwnode(imx283->dev); 1424 ep = fwnode_graph_get_next_endpoint(fwnode, NULL); 1425 if (!ep) { 1426 dev_err(imx283->dev, "Failed to get next endpoint\n"); 1427 return -ENXIO; 1428 } 1429 1430 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); 1431 fwnode_handle_put(ep); 1432 if (ret) 1433 return ret; 1434 1435 if (bus_cfg.bus.mipi_csi2.num_data_lanes != 4) { 1436 dev_err(imx283->dev, 1437 "number of CSI2 data lanes %d is not supported\n", 1438 bus_cfg.bus.mipi_csi2.num_data_lanes); 1439 ret = -EINVAL; 1440 goto done_endpoint_free; 1441 } 1442 1443 imx283->mipi_clk_noncontinuous = 1444 bus_cfg.bus.mipi_csi2.flags & V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK; 1445 1446 ret = v4l2_link_freq_to_bitmap(imx283->dev, bus_cfg.link_frequencies, 1447 bus_cfg.nr_of_link_frequencies, 1448 link_frequencies, ARRAY_SIZE(link_frequencies), 1449 &imx283->link_freq_bitmap); 1450 1451 done_endpoint_free: 1452 v4l2_fwnode_endpoint_free(&bus_cfg); 1453 1454 return ret; 1455 }; 1456 1457 static int imx283_probe(struct i2c_client *client) 1458 { 1459 struct imx283 *imx283; 1460 unsigned int i; 1461 unsigned int xclk_freq; 1462 int ret; 1463 1464 imx283 = devm_kzalloc(&client->dev, sizeof(*imx283), GFP_KERNEL); 1465 if (!imx283) 1466 return -ENOMEM; 1467 1468 imx283->dev = &client->dev; 1469 1470 v4l2_i2c_subdev_init(&imx283->sd, client, &imx283_subdev_ops); 1471 1472 imx283->cci = devm_cci_regmap_init_i2c(client, 16); 1473 if (IS_ERR(imx283->cci)) { 1474 ret = PTR_ERR(imx283->cci); 1475 dev_err(imx283->dev, "failed to initialize CCI: %d\n", ret); 1476 return ret; 1477 } 1478 1479 /* Get system clock (xclk) */ 1480 imx283->xclk = devm_v4l2_sensor_clk_get(imx283->dev, NULL); 1481 if (IS_ERR(imx283->xclk)) 1482 return dev_err_probe(imx283->dev, PTR_ERR(imx283->xclk), 1483 "failed to get xclk\n"); 1484 1485 xclk_freq = clk_get_rate(imx283->xclk); 1486 for (i = 0; i < ARRAY_SIZE(imx283_frequencies); i++) { 1487 if (xclk_freq == imx283_frequencies[i].mhz) { 1488 imx283->freq = &imx283_frequencies[i]; 1489 break; 1490 } 1491 } 1492 if (!imx283->freq) { 1493 dev_err(imx283->dev, "xclk frequency unsupported: %d Hz\n", xclk_freq); 1494 return -EINVAL; 1495 } 1496 1497 ret = imx283_get_regulators(imx283); 1498 if (ret) { 1499 return dev_err_probe(imx283->dev, ret, 1500 "failed to get regulators\n"); 1501 } 1502 1503 ret = imx283_parse_endpoint(imx283); 1504 if (ret) { 1505 dev_err(imx283->dev, "failed to parse endpoint configuration\n"); 1506 return ret; 1507 } 1508 1509 /* Request optional enable pin */ 1510 imx283->reset_gpio = devm_gpiod_get_optional(imx283->dev, "reset", 1511 GPIOD_OUT_LOW); 1512 if (IS_ERR(imx283->reset_gpio)) 1513 return dev_err_probe(imx283->dev, PTR_ERR(imx283->reset_gpio), 1514 "failed to get reset GPIO\n"); 1515 1516 /* 1517 * The sensor must be powered for imx283_identify_module() 1518 * to be able to read the CHIP_ID register 1519 */ 1520 ret = imx283_power_on(imx283->dev); 1521 if (ret) 1522 return ret; 1523 1524 ret = imx283_identify_module(imx283); 1525 if (ret) 1526 goto error_power_off; 1527 1528 /* 1529 * Enable runtime PM with autosuspend. As the device has been powered 1530 * manually, mark it as active, and increase the usage count without 1531 * resuming the device. 1532 */ 1533 pm_runtime_set_active(imx283->dev); 1534 pm_runtime_get_noresume(imx283->dev); 1535 pm_runtime_enable(imx283->dev); 1536 pm_runtime_set_autosuspend_delay(imx283->dev, 1000); 1537 pm_runtime_use_autosuspend(imx283->dev); 1538 1539 /* This needs the pm runtime to be registered. */ 1540 ret = imx283_init_controls(imx283); 1541 if (ret) 1542 goto error_pm; 1543 1544 /* Initialize subdev */ 1545 imx283->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1546 imx283->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1547 imx283->sd.internal_ops = &imx283_internal_ops; 1548 1549 /* Initialize source pads */ 1550 imx283->pad.flags = MEDIA_PAD_FL_SOURCE; 1551 1552 ret = media_entity_pads_init(&imx283->sd.entity, 1, &imx283->pad); 1553 if (ret) { 1554 dev_err(imx283->dev, "failed to init entity pads: %d\n", ret); 1555 goto error_handler_free; 1556 } 1557 1558 imx283->sd.state_lock = imx283->ctrl_handler.lock; 1559 ret = v4l2_subdev_init_finalize(&imx283->sd); 1560 if (ret < 0) { 1561 dev_err(imx283->dev, "subdev init error: %d\n", ret); 1562 goto error_media_entity; 1563 } 1564 1565 ret = v4l2_async_register_subdev_sensor(&imx283->sd); 1566 if (ret < 0) { 1567 dev_err(imx283->dev, "failed to register sensor sub-device: %d\n", ret); 1568 goto error_subdev_cleanup; 1569 } 1570 1571 /* 1572 * Decrease the PM usage count. The device will get suspended after the 1573 * autosuspend delay, turning the power off. 1574 */ 1575 pm_runtime_put_autosuspend(imx283->dev); 1576 1577 return 0; 1578 1579 error_subdev_cleanup: 1580 v4l2_subdev_cleanup(&imx283->sd); 1581 1582 error_media_entity: 1583 media_entity_cleanup(&imx283->sd.entity); 1584 1585 error_handler_free: 1586 v4l2_ctrl_handler_free(imx283->sd.ctrl_handler); 1587 1588 error_pm: 1589 pm_runtime_disable(imx283->dev); 1590 pm_runtime_set_suspended(imx283->dev); 1591 error_power_off: 1592 imx283_power_off(imx283->dev); 1593 1594 return ret; 1595 } 1596 1597 static void imx283_remove(struct i2c_client *client) 1598 { 1599 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1600 struct imx283 *imx283 = to_imx283(sd); 1601 1602 v4l2_async_unregister_subdev(sd); 1603 v4l2_subdev_cleanup(&imx283->sd); 1604 media_entity_cleanup(&sd->entity); 1605 v4l2_ctrl_handler_free(imx283->sd.ctrl_handler); 1606 1607 pm_runtime_disable(imx283->dev); 1608 if (!pm_runtime_status_suspended(imx283->dev)) 1609 imx283_power_off(imx283->dev); 1610 pm_runtime_set_suspended(imx283->dev); 1611 } 1612 1613 static DEFINE_RUNTIME_DEV_PM_OPS(imx283_pm_ops, imx283_power_off, 1614 imx283_power_on, NULL); 1615 1616 static const struct of_device_id imx283_dt_ids[] = { 1617 { .compatible = "sony,imx283" }, 1618 { /* sentinel */ } 1619 }; 1620 MODULE_DEVICE_TABLE(of, imx283_dt_ids); 1621 1622 static struct i2c_driver imx283_i2c_driver = { 1623 .driver = { 1624 .name = "imx283", 1625 .pm = pm_ptr(&imx283_pm_ops), 1626 .of_match_table = imx283_dt_ids, 1627 }, 1628 .probe = imx283_probe, 1629 .remove = imx283_remove, 1630 }; 1631 module_i2c_driver(imx283_i2c_driver); 1632 1633 MODULE_AUTHOR("Will Whang <will@willwhang.com>"); 1634 MODULE_AUTHOR("Kieran Bingham <kieran.bingham@ideasonboard.com>"); 1635 MODULE_AUTHOR("Umang Jain <umang.jain@ideasonboard.com>"); 1636 MODULE_DESCRIPTION("Sony IMX283 Sensor Driver"); 1637 MODULE_LICENSE("GPL"); 1638