1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * V4L2 Support for the IMX283 4 * 5 * Diagonal 15.86 mm (Type 1) CMOS Image Sensor with Square Pixel for Color 6 * Cameras. 7 * 8 * Copyright (C) 2024 Ideas on Board Oy. 9 * 10 * Based on Sony IMX283 driver prepared by Will Whang 11 * 12 * Based on Sony imx477 camera driver 13 * Copyright (C) 2019-2020 Raspberry Pi (Trading) Ltd 14 */ 15 16 #include <linux/array_size.h> 17 #include <linux/bitops.h> 18 #include <linux/container_of.h> 19 #include <linux/clk.h> 20 #include <linux/delay.h> 21 #include <linux/err.h> 22 #include <linux/gpio/consumer.h> 23 #include <linux/i2c.h> 24 #include <linux/minmax.h> 25 #include <linux/module.h> 26 #include <linux/mutex.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/property.h> 29 #include <linux/regulator/consumer.h> 30 #include <linux/types.h> 31 #include <linux/units.h> 32 #include <media/v4l2-cci.h> 33 #include <media/v4l2-ctrls.h> 34 #include <media/v4l2-device.h> 35 #include <media/v4l2-event.h> 36 #include <media/v4l2-fwnode.h> 37 #include <media/v4l2-mediabus.h> 38 39 /* Chip ID */ 40 #define IMX283_REG_CHIP_ID CCI_REG8(0x3000) 41 #define IMX283_CHIP_ID 0x0b // Default power on state 42 43 #define IMX283_REG_STANDBY CCI_REG8(0x3000) 44 #define IMX283_ACTIVE 0 45 #define IMX283_STANDBY BIT(0) 46 #define IMX283_STBLOGIC BIT(1) 47 #define IMX283_STBMIPI BIT(2) 48 #define IMX283_STBDV BIT(3) 49 #define IMX283_SLEEP BIT(4) 50 51 #define IMX283_REG_CLAMP CCI_REG8(0x3001) 52 #define IMX283_CLPSQRST BIT(4) 53 54 #define IMX283_REG_PLSTMG08 CCI_REG8(0x3003) 55 #define IMX283_PLSTMG08_VAL 0x77 56 57 #define IMX283_REG_MDSEL1 CCI_REG8(0x3004) 58 #define IMX283_REG_MDSEL2 CCI_REG8(0x3005) 59 #define IMX283_REG_MDSEL3 CCI_REG8(0x3006) 60 #define IMX283_MDSEL3_VCROP_EN BIT(5) 61 #define IMX283_REG_MDSEL4 CCI_REG8(0x3007) 62 #define IMX283_MDSEL4_VCROP_EN (BIT(4) | BIT(6)) 63 64 #define IMX283_REG_SVR CCI_REG16_LE(0x3009) 65 66 #define IMX283_REG_HTRIMMING CCI_REG8(0x300b) 67 #define IMX283_MDVREV BIT(0) /* VFLIP */ 68 #define IMX283_HTRIMMING_EN BIT(4) 69 70 #define IMX283_REG_VWINPOS CCI_REG16_LE(0x300f) 71 #define IMX283_REG_VWIDCUT CCI_REG16_LE(0x3011) 72 73 #define IMX283_REG_MDSEL7 CCI_REG16_LE(0x3013) 74 75 /* CSI Clock Configuration */ 76 #define IMX283_REG_TCLKPOST CCI_REG8(0x3018) 77 #define IMX283_REG_THSPREPARE CCI_REG8(0x301a) 78 #define IMX283_REG_THSZERO CCI_REG8(0x301c) 79 #define IMX283_REG_THSTRAIL CCI_REG8(0x301e) 80 #define IMX283_REG_TCLKTRAIL CCI_REG8(0x3020) 81 #define IMX283_REG_TCLKPREPARE CCI_REG8(0x3022) 82 #define IMX283_REG_TCLKZERO CCI_REG16_LE(0x3024) 83 #define IMX283_REG_TLPX CCI_REG8(0x3026) 84 #define IMX283_REG_THSEXIT CCI_REG8(0x3028) 85 #define IMX283_REG_TCLKPRE CCI_REG8(0x302a) 86 #define IMX283_REG_SYSMODE CCI_REG8(0x3104) 87 88 #define IMX283_REG_Y_OUT_SIZE CCI_REG16_LE(0x302f) 89 #define IMX283_REG_WRITE_VSIZE CCI_REG16_LE(0x3031) 90 #define IMX283_REG_OB_SIZE_V CCI_REG8(0x3033) 91 92 /* HMAX internal HBLANK */ 93 #define IMX283_REG_HMAX CCI_REG16_LE(0x3036) 94 #define IMX283_HMAX_MAX (BIT(16) - 1) 95 96 /* VMAX internal VBLANK */ 97 #define IMX283_REG_VMAX CCI_REG24_LE(0x3038) 98 #define IMX283_VMAX_MAX (BIT(16) - 1) 99 100 /* SHR internal */ 101 #define IMX283_REG_SHR CCI_REG16_LE(0x303b) 102 #define IMX283_SHR_MIN 11 103 104 /* 105 * Analog gain control 106 * Gain [dB] = -20log{(2048 - value [10:0]) /2048} 107 * Range: 0dB to approximately +27dB 108 */ 109 #define IMX283_REG_ANALOG_GAIN CCI_REG16_LE(0x3042) 110 #define IMX283_ANA_GAIN_MIN 0 111 #define IMX283_ANA_GAIN_MAX 1957 112 #define IMX283_ANA_GAIN_STEP 1 113 #define IMX283_ANA_GAIN_DEFAULT 0x0 114 115 /* 116 * Digital gain control 117 * Gain [dB] = value * 6 118 * Range: 0dB to +18db 119 */ 120 #define IMX283_REG_DIGITAL_GAIN CCI_REG8(0x3044) 121 #define IMX283_DGTL_GAIN_MIN 0 122 #define IMX283_DGTL_GAIN_MAX 3 123 #define IMX283_DGTL_GAIN_DEFAULT 0 124 #define IMX283_DGTL_GAIN_STEP 1 125 126 #define IMX283_REG_HTRIMMING_START CCI_REG16_LE(0x3058) 127 #define IMX283_REG_HTRIMMING_END CCI_REG16_LE(0x305a) 128 129 #define IMX283_REG_MDSEL18 CCI_REG16_LE(0x30f6) 130 131 /* Master Mode Operation Control */ 132 #define IMX283_REG_XMSTA CCI_REG8(0x3105) 133 #define IMX283_XMSTA BIT(0) 134 135 #define IMX283_REG_SYNCDRV CCI_REG8(0x3107) 136 #define IMX283_SYNCDRV_XHS_XVS (0xa0 | 0x02) 137 #define IMX283_SYNCDRV_HIZ (0xa0 | 0x03) 138 139 /* PLL Standby */ 140 #define IMX283_REG_STBPL CCI_REG8(0x320b) 141 #define IMX283_STBPL_NORMAL 0x00 142 #define IMX283_STBPL_STANDBY 0x03 143 144 /* Input Frequency Setting */ 145 #define IMX283_REG_PLRD1 CCI_REG8(0x36c1) 146 #define IMX283_REG_PLRD2 CCI_REG16_LE(0x36c2) 147 #define IMX283_REG_PLRD3 CCI_REG8(0x36f7) 148 #define IMX283_REG_PLRD4 CCI_REG8(0x36f8) 149 150 #define IMX283_REG_PLSTMG02 CCI_REG8(0x36aa) 151 #define IMX283_PLSTMG02_VAL 0x00 152 153 #define IMX283_REG_EBD_X_OUT_SIZE CCI_REG16_LE(0x3a54) 154 155 /* Test pattern generator */ 156 #define IMX283_REG_TPG_CTRL CCI_REG8(0x3156) 157 #define IMX283_TPG_CTRL_CLKEN BIT(0) 158 #define IMX283_TPG_CTRL_PATEN BIT(4) 159 160 #define IMX283_REG_TPG_PAT CCI_REG8(0x3157) 161 #define IMX283_TPG_PAT_ALL_000 0x00 162 #define IMX283_TPG_PAT_ALL_FFF 0x01 163 #define IMX283_TPG_PAT_ALL_555 0x02 164 #define IMX283_TPG_PAT_ALL_AAA 0x03 165 #define IMX283_TPG_PAT_H_COLOR_BARS 0x0a 166 #define IMX283_TPG_PAT_V_COLOR_BARS 0x0b 167 168 /* Exposure control */ 169 #define IMX283_EXPOSURE_MIN 52 170 #define IMX283_EXPOSURE_STEP 1 171 #define IMX283_EXPOSURE_DEFAULT 1000 172 #define IMX283_EXPOSURE_MAX 49865 173 174 #define IMAGE_PAD 0 175 176 #define IMX283_XCLR_MIN_DELAY_US (1 * USEC_PER_MSEC) 177 #define IMX283_XCLR_DELAY_RANGE_US (1 * USEC_PER_MSEC) 178 179 /* IMX283 native and active pixel array size. */ 180 static const struct v4l2_rect imx283_native_area = { 181 .top = 0, 182 .left = 0, 183 .width = 5592, 184 .height = 3710, 185 }; 186 187 static const struct v4l2_rect imx283_active_area = { 188 .top = 40, 189 .left = 108, 190 .width = 5472, 191 .height = 3648, 192 }; 193 194 struct imx283_reg_list { 195 unsigned int num_of_regs; 196 const struct cci_reg_sequence *regs; 197 }; 198 199 /* Mode : resolution and related config values */ 200 struct imx283_mode { 201 unsigned int mode; 202 203 /* Bits per pixel */ 204 unsigned int bpp; 205 206 /* Frame width */ 207 unsigned int width; 208 209 /* Frame height */ 210 unsigned int height; 211 212 /* 213 * Minimum horizontal timing in pixel-units 214 * 215 * Note that HMAX is written in 72MHz units, and the datasheet assumes a 216 * 720MHz link frequency. Convert datasheet values with the following: 217 * 218 * For 12 bpp modes (480Mbps) convert with: 219 * hmax = [hmax in 72MHz units] * 480 / 72 220 * 221 * For 10 bpp modes (576Mbps) convert with: 222 * hmax = [hmax in 72MHz units] * 576 / 72 223 */ 224 u32 min_hmax; 225 226 /* minimum V-timing in lines */ 227 u32 min_vmax; 228 229 /* default H-timing */ 230 u32 default_hmax; 231 232 /* default V-timing */ 233 u32 default_vmax; 234 235 /* minimum SHR */ 236 u32 min_shr; 237 238 /* 239 * Per-mode vertical crop constants used to calculate values 240 * of IMX283REG_WIDCUT and IMX283_REG_VWINPOS. 241 */ 242 u32 veff; 243 u32 vst; 244 u32 vct; 245 246 /* Horizontal and vertical binning ratio */ 247 u8 hbin_ratio; 248 u8 vbin_ratio; 249 250 /* Optical Blanking */ 251 u32 horizontal_ob; 252 u32 vertical_ob; 253 254 /* Analog crop rectangle. */ 255 struct v4l2_rect crop; 256 }; 257 258 struct imx283_input_frequency { 259 unsigned int mhz; 260 unsigned int reg_count; 261 struct cci_reg_sequence regs[4]; 262 }; 263 264 static const struct imx283_input_frequency imx283_frequencies[] = { 265 { 266 .mhz = 6 * HZ_PER_MHZ, 267 .reg_count = 4, 268 .regs = { 269 { IMX283_REG_PLRD1, 0x00 }, 270 { IMX283_REG_PLRD2, 0x00f0 }, 271 { IMX283_REG_PLRD3, 0x00 }, 272 { IMX283_REG_PLRD4, 0xc0 }, 273 }, 274 }, 275 { 276 .mhz = 12 * HZ_PER_MHZ, 277 .reg_count = 4, 278 .regs = { 279 { IMX283_REG_PLRD1, 0x01 }, 280 { IMX283_REG_PLRD2, 0x00f0 }, 281 { IMX283_REG_PLRD3, 0x01 }, 282 { IMX283_REG_PLRD4, 0xc0 }, 283 }, 284 }, 285 { 286 .mhz = 18 * HZ_PER_MHZ, 287 .reg_count = 4, 288 .regs = { 289 { IMX283_REG_PLRD1, 0x01 }, 290 { IMX283_REG_PLRD2, 0x00a0 }, 291 { IMX283_REG_PLRD3, 0x01 }, 292 { IMX283_REG_PLRD4, 0x80 }, 293 }, 294 }, 295 { 296 .mhz = 24 * HZ_PER_MHZ, 297 .reg_count = 4, 298 .regs = { 299 { IMX283_REG_PLRD1, 0x02 }, 300 { IMX283_REG_PLRD2, 0x00f0 }, 301 { IMX283_REG_PLRD3, 0x02 }, 302 { IMX283_REG_PLRD4, 0xc0 }, 303 }, 304 }, 305 }; 306 307 enum imx283_modes { 308 IMX283_MODE_0, 309 IMX283_MODE_1, 310 IMX283_MODE_1A, 311 IMX283_MODE_1S, 312 IMX283_MODE_2, 313 IMX283_MODE_2A, 314 IMX283_MODE_3, 315 IMX283_MODE_4, 316 IMX283_MODE_5, 317 IMX283_MODE_6, 318 }; 319 320 struct imx283_readout_mode { 321 u8 mdsel1; 322 u8 mdsel2; 323 u8 mdsel3; 324 u8 mdsel4; 325 }; 326 327 static const struct imx283_readout_mode imx283_readout_modes[] = { 328 /* All pixel scan modes */ 329 [IMX283_MODE_0] = { 0x04, 0x03, 0x10, 0x00 }, /* 12 bit */ 330 [IMX283_MODE_1] = { 0x04, 0x01, 0x00, 0x00 }, /* 10 bit */ 331 [IMX283_MODE_1A] = { 0x04, 0x01, 0x20, 0x50 }, /* 10 bit */ 332 [IMX283_MODE_1S] = { 0x04, 0x41, 0x20, 0x50 }, /* 10 bit */ 333 334 /* Horizontal / Vertical 2/2-line binning */ 335 [IMX283_MODE_2] = { 0x0d, 0x11, 0x50, 0x00 }, /* 12 bit */ 336 [IMX283_MODE_2A] = { 0x0d, 0x11, 0x70, 0x50 }, /* 12 bit */ 337 338 /* Horizontal / Vertical 3/3-line binning */ 339 [IMX283_MODE_3] = { 0x1e, 0x18, 0x10, 0x00 }, /* 12 bit */ 340 341 /* Vertical 2/9 subsampling, horizontal 3 binning cropping */ 342 [IMX283_MODE_4] = { 0x29, 0x18, 0x30, 0x50 }, /* 12 bit */ 343 344 /* Vertical 2/19 subsampling binning, horizontal 3 binning */ 345 [IMX283_MODE_5] = { 0x2d, 0x18, 0x10, 0x00 }, /* 12 bit */ 346 347 /* Vertical 2 binning horizontal 2/4, subsampling 16:9 cropping */ 348 [IMX283_MODE_6] = { 0x18, 0x21, 0x00, 0x09 }, /* 10 bit */ 349 350 /* 351 * New modes should make sure the offset period is complied. 352 * See imx283_exposure() for reference. 353 */ 354 }; 355 356 static const struct cci_reg_sequence mipi_data_rate_1440Mbps[] = { 357 /* The default register settings provide the 1440Mbps rate */ 358 { CCI_REG8(0x36c5), 0x00 }, /* Undocumented */ 359 { CCI_REG8(0x3ac4), 0x00 }, /* Undocumented */ 360 361 { IMX283_REG_STBPL, 0x00 }, 362 { IMX283_REG_TCLKPOST, 0xa7 }, 363 { IMX283_REG_THSPREPARE, 0x6f }, 364 { IMX283_REG_THSZERO, 0x9f }, 365 { IMX283_REG_THSTRAIL, 0x5f }, 366 { IMX283_REG_TCLKTRAIL, 0x5f }, 367 { IMX283_REG_TCLKPREPARE, 0x6f }, 368 { IMX283_REG_TCLKZERO, 0x017f }, 369 { IMX283_REG_TLPX, 0x4f }, 370 { IMX283_REG_THSEXIT, 0x47 }, 371 { IMX283_REG_TCLKPRE, 0x07 }, 372 { IMX283_REG_SYSMODE, 0x02 }, 373 }; 374 375 static const struct cci_reg_sequence mipi_data_rate_720Mbps[] = { 376 /* Undocumented Additions "For 720MBps" Setting */ 377 { CCI_REG8(0x36c5), 0x01 }, /* Undocumented */ 378 { CCI_REG8(0x3ac4), 0x01 }, /* Undocumented */ 379 380 { IMX283_REG_STBPL, 0x00 }, 381 { IMX283_REG_TCLKPOST, 0x77 }, 382 { IMX283_REG_THSPREPARE, 0x37 }, 383 { IMX283_REG_THSZERO, 0x67 }, 384 { IMX283_REG_THSTRAIL, 0x37 }, 385 { IMX283_REG_TCLKTRAIL, 0x37 }, 386 { IMX283_REG_TCLKPREPARE, 0x37 }, 387 { IMX283_REG_TCLKZERO, 0xdf }, 388 { IMX283_REG_TLPX, 0x2f }, 389 { IMX283_REG_THSEXIT, 0x47 }, 390 { IMX283_REG_TCLKPRE, 0x0f }, 391 { IMX283_REG_SYSMODE, 0x02 }, 392 }; 393 394 static const s64 link_frequencies[] = { 395 720 * HZ_PER_MHZ, /* 1440 Mbps lane data rate */ 396 360 * HZ_PER_MHZ, /* 720 Mbps data lane rate */ 397 }; 398 399 static const struct imx283_reg_list link_freq_reglist[] = { 400 { /* 720 MHz */ 401 .num_of_regs = ARRAY_SIZE(mipi_data_rate_1440Mbps), 402 .regs = mipi_data_rate_1440Mbps, 403 }, 404 { /* 360 MHz */ 405 .num_of_regs = ARRAY_SIZE(mipi_data_rate_720Mbps), 406 .regs = mipi_data_rate_720Mbps, 407 }, 408 }; 409 410 /* Mode configs */ 411 static const struct imx283_mode supported_modes_12bit[] = { 412 { 413 /* 20MPix 21.40 fps readout mode 0 */ 414 .mode = IMX283_MODE_0, 415 .bpp = 12, 416 .width = 5472, 417 .height = 3648, 418 .min_hmax = 5914, /* 887 @ 480MHz/72MHz */ 419 .min_vmax = 3793, /* Lines */ 420 421 .veff = 3694, 422 .vst = 0, 423 .vct = 0, 424 425 .hbin_ratio = 1, 426 .vbin_ratio = 1, 427 428 /* 20.00 FPS */ 429 .default_hmax = 6000, /* 900 @ 480MHz/72MHz */ 430 .default_vmax = 4000, 431 432 .min_shr = 11, 433 .horizontal_ob = 96, 434 .vertical_ob = 16, 435 .crop = { 436 .top = 40, 437 .left = 108, 438 .width = 5472, 439 .height = 3648, 440 }, 441 }, 442 { 443 /* 444 * Readout mode 2 : 2/2 binned mode (2736x1824) 445 */ 446 .mode = IMX283_MODE_2, 447 .bpp = 12, 448 .width = 2736, 449 .height = 1824, 450 .min_hmax = 2414, /* Pixels (362 * 480MHz/72MHz + padding) */ 451 .min_vmax = 3840, /* Lines */ 452 453 /* 50.00 FPS */ 454 .default_hmax = 2500, /* 375 @ 480MHz/72Mhz */ 455 .default_vmax = 3840, 456 457 .veff = 1824, 458 .vst = 0, 459 .vct = 0, 460 461 .hbin_ratio = 2, 462 .vbin_ratio = 2, 463 464 .min_shr = 12, 465 .horizontal_ob = 48, 466 .vertical_ob = 4, 467 468 .crop = { 469 .top = 40, 470 .left = 108, 471 .width = 5472, 472 .height = 3648, 473 }, 474 }, 475 }; 476 477 static const struct imx283_mode supported_modes_10bit[] = { 478 { 479 /* 20MPix 25.48 fps readout mode 1 */ 480 .mode = IMX283_MODE_1, 481 .bpp = 10, 482 .width = 5472, 483 .height = 3648, 484 .min_hmax = 5960, /* 745 @ 576MHz / 72MHz */ 485 .min_vmax = 3793, 486 487 /* 25.00 FPS */ 488 .default_hmax = 6000, /* 750 @ 576MHz / 72MHz */ 489 .default_vmax = 3840, 490 491 .min_shr = 10, 492 .horizontal_ob = 96, 493 .vertical_ob = 16, 494 .crop = { 495 .top = 40, 496 .left = 108, 497 .width = 5472, 498 .height = 3648, 499 }, 500 }, 501 }; 502 503 static const u32 imx283_mbus_codes[] = { 504 MEDIA_BUS_FMT_SRGGB12_1X12, 505 MEDIA_BUS_FMT_SRGGB10_1X10, 506 }; 507 508 /* regulator supplies */ 509 static const char *const imx283_supply_name[] = { 510 "vadd", /* Analog (2.9V) supply */ 511 "vdd1", /* Supply Voltage 2 (1.8V) supply */ 512 "vdd2", /* Supply Voltage 3 (1.2V) supply */ 513 }; 514 515 struct imx283 { 516 struct device *dev; 517 struct regmap *cci; 518 519 const struct imx283_input_frequency *freq; 520 521 struct v4l2_subdev sd; 522 struct media_pad pad; 523 524 struct clk *xclk; 525 526 struct gpio_desc *reset_gpio; 527 struct regulator_bulk_data supplies[ARRAY_SIZE(imx283_supply_name)]; 528 529 /* V4L2 Controls */ 530 struct v4l2_ctrl_handler ctrl_handler; 531 struct v4l2_ctrl *exposure; 532 struct v4l2_ctrl *vblank; 533 struct v4l2_ctrl *hblank; 534 struct v4l2_ctrl *vflip; 535 536 unsigned long link_freq_bitmap; 537 538 u16 hmax; 539 u32 vmax; 540 }; 541 542 static inline struct imx283 *to_imx283(struct v4l2_subdev *sd) 543 { 544 return container_of_const(sd, struct imx283, sd); 545 } 546 547 static inline void get_mode_table(unsigned int code, 548 const struct imx283_mode **mode_list, 549 unsigned int *num_modes) 550 { 551 switch (code) { 552 case MEDIA_BUS_FMT_SRGGB12_1X12: 553 case MEDIA_BUS_FMT_SGRBG12_1X12: 554 case MEDIA_BUS_FMT_SGBRG12_1X12: 555 case MEDIA_BUS_FMT_SBGGR12_1X12: 556 *mode_list = supported_modes_12bit; 557 *num_modes = ARRAY_SIZE(supported_modes_12bit); 558 break; 559 560 case MEDIA_BUS_FMT_SRGGB10_1X10: 561 case MEDIA_BUS_FMT_SGRBG10_1X10: 562 case MEDIA_BUS_FMT_SGBRG10_1X10: 563 case MEDIA_BUS_FMT_SBGGR10_1X10: 564 *mode_list = supported_modes_10bit; 565 *num_modes = ARRAY_SIZE(supported_modes_10bit); 566 break; 567 default: 568 *mode_list = NULL; 569 *num_modes = 0; 570 break; 571 } 572 } 573 574 /* Calculate the Pixel Rate based on the current mode */ 575 static u64 imx283_pixel_rate(struct imx283 *imx283, 576 const struct imx283_mode *mode) 577 { 578 u64 link_frequency = link_frequencies[__ffs(imx283->link_freq_bitmap)]; 579 unsigned int bpp = mode->bpp; 580 const unsigned int ddr = 2; /* Double Data Rate */ 581 const unsigned int lanes = 4; /* Only 4 lane support */ 582 u64 numerator = link_frequency * ddr * lanes; 583 584 do_div(numerator, bpp); 585 586 return numerator; 587 } 588 589 /* Convert from a variable pixel_rate to 72 MHz clock cycles */ 590 static u64 imx283_internal_clock(unsigned int pixel_rate, unsigned int pixels) 591 { 592 /* 593 * Determine the following operation without overflow: 594 * pixels = 72 Mhz / pixel_rate 595 * 596 * The internal clock at 72MHz and Pixel Rate (between 240 and 576MHz) 597 * can easily overflow this calculation, so pre-divide to simplify. 598 */ 599 const u32 iclk_pre = 72; 600 const u32 pclk_pre = pixel_rate / HZ_PER_MHZ; 601 u64 numerator = pixels * iclk_pre; 602 603 do_div(numerator, pclk_pre); 604 605 return numerator; 606 } 607 608 /* Internal clock (72MHz) to Pixel Rate clock (Variable) */ 609 static u64 imx283_iclk_to_pix(unsigned int pixel_rate, unsigned int cycles) 610 { 611 /* 612 * Determine the following operation without overflow: 613 * cycles * pixel_rate / 72 MHz 614 * 615 * The internal clock at 72MHz and Pixel Rate (between 240 and 576MHz) 616 * can easily overflow this calculation, so pre-divide to simplify. 617 */ 618 const u32 iclk_pre = 72; 619 const u32 pclk_pre = pixel_rate / HZ_PER_MHZ; 620 u64 numerator = cycles * pclk_pre; 621 622 do_div(numerator, iclk_pre); 623 624 return numerator; 625 } 626 627 /* Determine the exposure based on current hmax, vmax and a given SHR */ 628 static u32 imx283_exposure(struct imx283 *imx283, 629 const struct imx283_mode *mode, u64 shr) 630 { 631 u32 svr = 0; /* SVR feature is not currently supported */ 632 u32 offset; 633 u64 numerator; 634 635 /* Number of clocks per internal offset period */ 636 offset = mode->mode == IMX283_MODE_0 ? 209 : 157; 637 numerator = (imx283->vmax * (svr + 1) - shr) * imx283->hmax + offset; 638 639 do_div(numerator, imx283->hmax); 640 641 return clamp(numerator, 0, U32_MAX); 642 } 643 644 static void imx283_exposure_limits(struct imx283 *imx283, 645 const struct imx283_mode *mode, 646 s64 *min_exposure, s64 *max_exposure) 647 { 648 u32 svr = 0; /* SVR feature is not currently supported */ 649 u64 min_shr = mode->min_shr; 650 /* Global Shutter is not supported */ 651 u64 max_shr = (svr + 1) * imx283->vmax - 4; 652 653 max_shr = min(max_shr, BIT(16) - 1); 654 655 *min_exposure = imx283_exposure(imx283, mode, max_shr); 656 *max_exposure = imx283_exposure(imx283, mode, min_shr); 657 } 658 659 /* 660 * Integration Time [s] = [ {VMAX x (SVR + 1) – (SHR)} x HMAX + offset ] 661 * / [ 72 x 10^6 ] 662 */ 663 static u32 imx283_shr(struct imx283 *imx283, const struct imx283_mode *mode, 664 u32 exposure) 665 { 666 u32 svr = 0; /* SVR feature is not currently supported */ 667 u32 offset; 668 u64 temp; 669 670 /* Number of clocks per internal offset period */ 671 offset = mode->mode == IMX283_MODE_0 ? 209 : 157; 672 temp = ((u64)exposure * imx283->hmax - offset); 673 do_div(temp, imx283->hmax); 674 675 return (imx283->vmax * (svr + 1) - temp); 676 } 677 678 static const char * const imx283_tpg_menu[] = { 679 "Disabled", 680 "All 000h", 681 "All FFFh", 682 "All 555h", 683 "All AAAh", 684 "Horizontal color bars", 685 "Vertical color bars", 686 }; 687 688 static const int imx283_tpg_val[] = { 689 IMX283_TPG_PAT_ALL_000, 690 IMX283_TPG_PAT_ALL_000, 691 IMX283_TPG_PAT_ALL_FFF, 692 IMX283_TPG_PAT_ALL_555, 693 IMX283_TPG_PAT_ALL_AAA, 694 IMX283_TPG_PAT_H_COLOR_BARS, 695 IMX283_TPG_PAT_V_COLOR_BARS, 696 }; 697 698 static int imx283_update_test_pattern(struct imx283 *imx283, u32 pattern_index) 699 { 700 int ret; 701 702 if (pattern_index >= ARRAY_SIZE(imx283_tpg_val)) 703 return -EINVAL; 704 705 if (!pattern_index) 706 return cci_write(imx283->cci, IMX283_REG_TPG_CTRL, 0x00, NULL); 707 708 ret = cci_write(imx283->cci, IMX283_REG_TPG_PAT, 709 imx283_tpg_val[pattern_index], NULL); 710 if (ret) 711 return ret; 712 713 return cci_write(imx283->cci, IMX283_REG_TPG_CTRL, 714 IMX283_TPG_CTRL_CLKEN | IMX283_TPG_CTRL_PATEN, NULL); 715 } 716 717 static int imx283_set_ctrl(struct v4l2_ctrl *ctrl) 718 { 719 struct imx283 *imx283 = container_of(ctrl->handler, struct imx283, 720 ctrl_handler); 721 const struct imx283_mode *mode; 722 struct v4l2_mbus_framefmt *fmt; 723 const struct imx283_mode *mode_list; 724 struct v4l2_subdev_state *state; 725 unsigned int num_modes; 726 u64 shr, pixel_rate; 727 int ret = 0; 728 729 state = v4l2_subdev_get_locked_active_state(&imx283->sd); 730 fmt = v4l2_subdev_state_get_format(state, 0); 731 732 get_mode_table(fmt->code, &mode_list, &num_modes); 733 mode = v4l2_find_nearest_size(mode_list, num_modes, width, height, 734 fmt->width, fmt->height); 735 736 /* 737 * The VBLANK control may change the limits of usable exposure, so check 738 * and adjust if necessary. 739 */ 740 if (ctrl->id == V4L2_CID_VBLANK) { 741 /* Honour the VBLANK limits when setting exposure. */ 742 s64 current_exposure, max_exposure, min_exposure; 743 744 imx283->vmax = mode->height + ctrl->val; 745 746 imx283_exposure_limits(imx283, mode, 747 &min_exposure, &max_exposure); 748 749 current_exposure = imx283->exposure->val; 750 current_exposure = clamp(current_exposure, min_exposure, 751 max_exposure); 752 753 __v4l2_ctrl_modify_range(imx283->exposure, min_exposure, 754 max_exposure, 1, current_exposure); 755 } 756 757 /* 758 * Applying V4L2 control value only happens 759 * when power is up for streaming 760 */ 761 if (!pm_runtime_get_if_active(imx283->dev)) 762 return 0; 763 764 switch (ctrl->id) { 765 case V4L2_CID_EXPOSURE: 766 shr = imx283_shr(imx283, mode, ctrl->val); 767 dev_dbg(imx283->dev, "V4L2_CID_EXPOSURE : %d - SHR: %lld\n", 768 ctrl->val, shr); 769 ret = cci_write(imx283->cci, IMX283_REG_SHR, shr, NULL); 770 break; 771 772 case V4L2_CID_HBLANK: 773 pixel_rate = imx283_pixel_rate(imx283, mode); 774 imx283->hmax = imx283_internal_clock(pixel_rate, mode->width + ctrl->val); 775 dev_dbg(imx283->dev, "V4L2_CID_HBLANK : %d HMAX : %u\n", 776 ctrl->val, imx283->hmax); 777 ret = cci_write(imx283->cci, IMX283_REG_HMAX, imx283->hmax, NULL); 778 break; 779 780 case V4L2_CID_VBLANK: 781 imx283->vmax = mode->height + ctrl->val; 782 dev_dbg(imx283->dev, "V4L2_CID_VBLANK : %d VMAX : %u\n", 783 ctrl->val, imx283->vmax); 784 ret = cci_write(imx283->cci, IMX283_REG_VMAX, imx283->vmax, NULL); 785 break; 786 787 case V4L2_CID_ANALOGUE_GAIN: 788 ret = cci_write(imx283->cci, IMX283_REG_ANALOG_GAIN, ctrl->val, NULL); 789 break; 790 791 case V4L2_CID_DIGITAL_GAIN: 792 ret = cci_write(imx283->cci, IMX283_REG_DIGITAL_GAIN, ctrl->val, NULL); 793 break; 794 795 case V4L2_CID_VFLIP: 796 /* 797 * VFLIP is managed by BIT(0) of IMX283_REG_HTRIMMING address, hence 798 * both need to be set simultaneously. 799 */ 800 if (ctrl->val) { 801 cci_write(imx283->cci, IMX283_REG_HTRIMMING, 802 IMX283_HTRIMMING_EN | IMX283_MDVREV, &ret); 803 } else { 804 cci_write(imx283->cci, IMX283_REG_HTRIMMING, 805 IMX283_HTRIMMING_EN, &ret); 806 } 807 break; 808 809 case V4L2_CID_TEST_PATTERN: 810 ret = imx283_update_test_pattern(imx283, ctrl->val); 811 break; 812 813 default: 814 dev_err(imx283->dev, "ctrl(id:0x%x, val:0x%x) is not handled\n", 815 ctrl->id, ctrl->val); 816 break; 817 } 818 819 pm_runtime_put(imx283->dev); 820 821 return ret; 822 } 823 824 static const struct v4l2_ctrl_ops imx283_ctrl_ops = { 825 .s_ctrl = imx283_set_ctrl, 826 }; 827 828 static int imx283_enum_mbus_code(struct v4l2_subdev *sd, 829 struct v4l2_subdev_state *sd_state, 830 struct v4l2_subdev_mbus_code_enum *code) 831 { 832 if (code->index >= ARRAY_SIZE(imx283_mbus_codes)) 833 return -EINVAL; 834 835 code->code = imx283_mbus_codes[code->index]; 836 837 return 0; 838 } 839 840 static int imx283_enum_frame_size(struct v4l2_subdev *sd, 841 struct v4l2_subdev_state *sd_state, 842 struct v4l2_subdev_frame_size_enum *fse) 843 { 844 const struct imx283_mode *mode_list; 845 unsigned int num_modes; 846 847 get_mode_table(fse->code, &mode_list, &num_modes); 848 849 if (fse->index >= num_modes) 850 return -EINVAL; 851 852 fse->min_width = mode_list[fse->index].width; 853 fse->max_width = fse->min_width; 854 fse->min_height = mode_list[fse->index].height; 855 fse->max_height = fse->min_height; 856 857 return 0; 858 } 859 860 static void imx283_update_image_pad_format(struct imx283 *imx283, 861 const struct imx283_mode *mode, 862 struct v4l2_mbus_framefmt *format) 863 { 864 format->width = mode->width; 865 format->height = mode->height; 866 format->field = V4L2_FIELD_NONE; 867 format->colorspace = V4L2_COLORSPACE_RAW; 868 format->ycbcr_enc = V4L2_YCBCR_ENC_601; 869 format->quantization = V4L2_QUANTIZATION_FULL_RANGE; 870 format->xfer_func = V4L2_XFER_FUNC_NONE; 871 } 872 873 static int imx283_init_state(struct v4l2_subdev *sd, 874 struct v4l2_subdev_state *state) 875 { 876 struct imx283 *imx283 = to_imx283(sd); 877 struct v4l2_mbus_framefmt *format; 878 const struct imx283_mode *mode; 879 struct v4l2_rect *crop; 880 881 /* Initialize try_fmt */ 882 format = v4l2_subdev_state_get_format(state, IMAGE_PAD); 883 884 mode = &supported_modes_12bit[0]; 885 format->code = MEDIA_BUS_FMT_SRGGB12_1X12; 886 imx283_update_image_pad_format(imx283, mode, format); 887 888 /* Initialize crop rectangle to mode default */ 889 crop = v4l2_subdev_state_get_crop(state, IMAGE_PAD); 890 *crop = mode->crop; 891 892 return 0; 893 } 894 895 static void imx283_set_framing_limits(struct imx283 *imx283, 896 const struct imx283_mode *mode) 897 { 898 u64 pixel_rate = imx283_pixel_rate(imx283, mode); 899 u64 min_hblank, max_hblank, def_hblank; 900 901 /* Initialise hmax and vmax for exposure calculations */ 902 imx283->hmax = imx283_internal_clock(pixel_rate, mode->default_hmax); 903 imx283->vmax = mode->default_vmax; 904 905 /* 906 * Horizontal Blanking 907 * Convert the HMAX_MAX (72MHz) to Pixel rate values for HBLANK_MAX 908 */ 909 min_hblank = mode->min_hmax - mode->width; 910 max_hblank = imx283_iclk_to_pix(pixel_rate, IMX283_HMAX_MAX) - mode->width; 911 def_hblank = mode->default_hmax - mode->width; 912 __v4l2_ctrl_modify_range(imx283->hblank, min_hblank, max_hblank, 1, 913 def_hblank); 914 __v4l2_ctrl_s_ctrl(imx283->hblank, def_hblank); 915 916 /* Vertical Blanking */ 917 __v4l2_ctrl_modify_range(imx283->vblank, mode->min_vmax - mode->height, 918 IMX283_VMAX_MAX - mode->height, 1, 919 mode->default_vmax - mode->height); 920 __v4l2_ctrl_s_ctrl(imx283->vblank, mode->default_vmax - mode->height); 921 } 922 923 static int imx283_set_pad_format(struct v4l2_subdev *sd, 924 struct v4l2_subdev_state *sd_state, 925 struct v4l2_subdev_format *fmt) 926 { 927 struct v4l2_mbus_framefmt *format; 928 const struct imx283_mode *mode; 929 struct imx283 *imx283 = to_imx283(sd); 930 const struct imx283_mode *mode_list; 931 unsigned int num_modes; 932 933 get_mode_table(fmt->format.code, &mode_list, &num_modes); 934 935 mode = v4l2_find_nearest_size(mode_list, num_modes, width, height, 936 fmt->format.width, fmt->format.height); 937 938 fmt->format.width = mode->width; 939 fmt->format.height = mode->height; 940 fmt->format.field = V4L2_FIELD_NONE; 941 fmt->format.colorspace = V4L2_COLORSPACE_RAW; 942 fmt->format.ycbcr_enc = V4L2_YCBCR_ENC_601; 943 fmt->format.quantization = V4L2_QUANTIZATION_FULL_RANGE; 944 fmt->format.xfer_func = V4L2_XFER_FUNC_NONE; 945 946 format = v4l2_subdev_state_get_format(sd_state, 0); 947 948 if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) 949 imx283_set_framing_limits(imx283, mode); 950 951 *format = fmt->format; 952 953 return 0; 954 } 955 956 static int imx283_standby_cancel(struct imx283 *imx283) 957 { 958 unsigned int link_freq_idx; 959 int ret = 0; 960 961 cci_write(imx283->cci, IMX283_REG_STANDBY, 962 IMX283_STBLOGIC | IMX283_STBDV, &ret); 963 964 /* Configure PLL clocks based on the xclk */ 965 cci_multi_reg_write(imx283->cci, imx283->freq->regs, 966 imx283->freq->reg_count, &ret); 967 968 dev_dbg(imx283->dev, "Using clk freq %ld MHz", 969 imx283->freq->mhz / HZ_PER_MHZ); 970 971 /* Initialise communication */ 972 cci_write(imx283->cci, IMX283_REG_PLSTMG08, IMX283_PLSTMG08_VAL, &ret); 973 cci_write(imx283->cci, IMX283_REG_PLSTMG02, IMX283_PLSTMG02_VAL, &ret); 974 975 /* Enable PLL */ 976 cci_write(imx283->cci, IMX283_REG_STBPL, IMX283_STBPL_NORMAL, &ret); 977 978 /* Configure the MIPI link speed */ 979 link_freq_idx = __ffs(imx283->link_freq_bitmap); 980 cci_multi_reg_write(imx283->cci, link_freq_reglist[link_freq_idx].regs, 981 link_freq_reglist[link_freq_idx].num_of_regs, 982 &ret); 983 984 /* 1st Stabilisation period of 1 ms or more */ 985 usleep_range(1000, 2000); 986 987 /* Activate */ 988 cci_write(imx283->cci, IMX283_REG_STANDBY, IMX283_ACTIVE, &ret); 989 990 /* 2nd Stabilisation period of 19ms or more */ 991 usleep_range(19000, 20000); 992 993 cci_write(imx283->cci, IMX283_REG_CLAMP, IMX283_CLPSQRST, &ret); 994 cci_write(imx283->cci, IMX283_REG_XMSTA, 0, &ret); 995 cci_write(imx283->cci, IMX283_REG_SYNCDRV, IMX283_SYNCDRV_XHS_XVS, &ret); 996 997 return ret; 998 } 999 1000 /* Start streaming */ 1001 static int imx283_start_streaming(struct imx283 *imx283, 1002 struct v4l2_subdev_state *state) 1003 { 1004 const struct imx283_readout_mode *readout; 1005 const struct imx283_mode *mode; 1006 const struct v4l2_mbus_framefmt *fmt; 1007 const struct imx283_mode *mode_list; 1008 unsigned int num_modes; 1009 u32 v_widcut; 1010 s32 v_pos; 1011 u32 write_v_size; 1012 u32 y_out_size; 1013 int ret = 0; 1014 1015 fmt = v4l2_subdev_state_get_format(state, 0); 1016 get_mode_table(fmt->code, &mode_list, &num_modes); 1017 mode = v4l2_find_nearest_size(mode_list, num_modes, width, height, 1018 fmt->width, fmt->height); 1019 1020 ret = imx283_standby_cancel(imx283); 1021 if (ret) { 1022 dev_err(imx283->dev, "failed to cancel standby\n"); 1023 return ret; 1024 } 1025 1026 /* 1027 * Set the readout mode registers. 1028 * MDSEL3 and MDSEL4 are updated to enable Arbitrary Vertical Cropping. 1029 */ 1030 readout = &imx283_readout_modes[mode->mode]; 1031 cci_write(imx283->cci, IMX283_REG_MDSEL1, readout->mdsel1, &ret); 1032 cci_write(imx283->cci, IMX283_REG_MDSEL2, readout->mdsel2, &ret); 1033 cci_write(imx283->cci, IMX283_REG_MDSEL3, 1034 readout->mdsel3 | IMX283_MDSEL3_VCROP_EN, &ret); 1035 cci_write(imx283->cci, IMX283_REG_MDSEL4, 1036 readout->mdsel4 | IMX283_MDSEL4_VCROP_EN, &ret); 1037 1038 /* Mode 1S specific entries from the Readout Drive Mode Tables */ 1039 if (mode->mode == IMX283_MODE_1S) { 1040 cci_write(imx283->cci, IMX283_REG_MDSEL7, 0x01, &ret); 1041 cci_write(imx283->cci, IMX283_REG_MDSEL18, 0x1098, &ret); 1042 } 1043 1044 if (ret) { 1045 dev_err(imx283->dev, "failed to set readout\n"); 1046 return ret; 1047 } 1048 1049 /* Initialise SVR. Unsupported for now - Always 0 */ 1050 cci_write(imx283->cci, IMX283_REG_SVR, 0x00, &ret); 1051 1052 dev_dbg(imx283->dev, "Mode: Size %d x %d\n", mode->width, mode->height); 1053 dev_dbg(imx283->dev, "Analogue Crop (in the mode) %d,%d %dx%d\n", 1054 mode->crop.left, 1055 mode->crop.top, 1056 mode->crop.width, 1057 mode->crop.height); 1058 1059 y_out_size = mode->crop.height / mode->vbin_ratio; 1060 write_v_size = y_out_size + mode->vertical_ob; 1061 /* 1062 * cropping start position = (VWINPOS – Vst) × 2 1063 * cropping width = Veff – (VWIDCUT – Vct) × 2 1064 */ 1065 v_pos = imx283->vflip->val ? 1066 ((-mode->crop.top / mode->vbin_ratio) / 2) + mode->vst : 1067 ((mode->crop.top / mode->vbin_ratio) / 2) + mode->vst; 1068 v_widcut = ((mode->veff - y_out_size) / 2) + mode->vct; 1069 1070 cci_write(imx283->cci, IMX283_REG_Y_OUT_SIZE, y_out_size, &ret); 1071 cci_write(imx283->cci, IMX283_REG_WRITE_VSIZE, write_v_size, &ret); 1072 cci_write(imx283->cci, IMX283_REG_VWIDCUT, v_widcut, &ret); 1073 cci_write(imx283->cci, IMX283_REG_VWINPOS, v_pos, &ret); 1074 1075 cci_write(imx283->cci, IMX283_REG_OB_SIZE_V, mode->vertical_ob, &ret); 1076 1077 /* TODO: Validate mode->crop is fully contained within imx283_native_area */ 1078 cci_write(imx283->cci, IMX283_REG_HTRIMMING_START, mode->crop.left, &ret); 1079 cci_write(imx283->cci, IMX283_REG_HTRIMMING_END, 1080 mode->crop.left + mode->crop.width, &ret); 1081 1082 /* Disable embedded data */ 1083 cci_write(imx283->cci, IMX283_REG_EBD_X_OUT_SIZE, 0, &ret); 1084 1085 /* Apply customized values from controls (HMAX/VMAX/SHR) */ 1086 ret = __v4l2_ctrl_handler_setup(imx283->sd.ctrl_handler); 1087 1088 return ret; 1089 } 1090 1091 static int imx283_enable_streams(struct v4l2_subdev *sd, 1092 struct v4l2_subdev_state *state, u32 pad, 1093 u64 streams_mask) 1094 { 1095 struct imx283 *imx283 = to_imx283(sd); 1096 int ret; 1097 1098 if (pad != IMAGE_PAD) 1099 return -EINVAL; 1100 1101 ret = pm_runtime_get_sync(imx283->dev); 1102 if (ret < 0) { 1103 pm_runtime_put_noidle(imx283->dev); 1104 return ret; 1105 } 1106 1107 ret = imx283_start_streaming(imx283, state); 1108 if (ret) 1109 goto err_rpm_put; 1110 1111 return 0; 1112 1113 err_rpm_put: 1114 pm_runtime_mark_last_busy(imx283->dev); 1115 pm_runtime_put_autosuspend(imx283->dev); 1116 1117 return ret; 1118 } 1119 1120 static int imx283_disable_streams(struct v4l2_subdev *sd, 1121 struct v4l2_subdev_state *state, u32 pad, 1122 u64 streams_mask) 1123 { 1124 struct imx283 *imx283 = to_imx283(sd); 1125 int ret; 1126 1127 if (pad != IMAGE_PAD) 1128 return -EINVAL; 1129 1130 ret = cci_write(imx283->cci, IMX283_REG_STANDBY, IMX283_STBLOGIC, NULL); 1131 if (ret) 1132 dev_err(imx283->dev, "Failed to stop stream\n"); 1133 1134 pm_runtime_mark_last_busy(imx283->dev); 1135 pm_runtime_put_autosuspend(imx283->dev); 1136 1137 return ret; 1138 } 1139 1140 /* Power/clock management functions */ 1141 static int imx283_power_on(struct imx283 *imx283) 1142 { 1143 int ret; 1144 1145 ret = regulator_bulk_enable(ARRAY_SIZE(imx283_supply_name), 1146 imx283->supplies); 1147 if (ret) { 1148 dev_err(imx283->dev, "failed to enable regulators\n"); 1149 return ret; 1150 } 1151 1152 ret = clk_prepare_enable(imx283->xclk); 1153 if (ret) { 1154 dev_err(imx283->dev, "failed to enable clock\n"); 1155 goto reg_off; 1156 } 1157 1158 gpiod_set_value_cansleep(imx283->reset_gpio, 0); 1159 1160 usleep_range(IMX283_XCLR_MIN_DELAY_US, 1161 IMX283_XCLR_MIN_DELAY_US + IMX283_XCLR_DELAY_RANGE_US); 1162 1163 return 0; 1164 1165 reg_off: 1166 regulator_bulk_disable(ARRAY_SIZE(imx283_supply_name), imx283->supplies); 1167 return ret; 1168 } 1169 1170 static int imx283_power_off(struct imx283 *imx283) 1171 { 1172 gpiod_set_value_cansleep(imx283->reset_gpio, 1); 1173 regulator_bulk_disable(ARRAY_SIZE(imx283_supply_name), imx283->supplies); 1174 clk_disable_unprepare(imx283->xclk); 1175 1176 return 0; 1177 } 1178 1179 static int imx283_runtime_resume(struct device *dev) 1180 { 1181 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1182 struct imx283 *imx283 = to_imx283(sd); 1183 1184 return imx283_power_on(imx283); 1185 } 1186 1187 static int imx283_runtime_suspend(struct device *dev) 1188 { 1189 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1190 struct imx283 *imx283 = to_imx283(sd); 1191 1192 imx283_power_off(imx283); 1193 1194 return 0; 1195 } 1196 1197 static int imx283_get_regulators(struct imx283 *imx283) 1198 { 1199 unsigned int i; 1200 1201 for (i = 0; i < ARRAY_SIZE(imx283_supply_name); i++) 1202 imx283->supplies[i].supply = imx283_supply_name[i]; 1203 1204 return devm_regulator_bulk_get(imx283->dev, 1205 ARRAY_SIZE(imx283_supply_name), 1206 imx283->supplies); 1207 } 1208 1209 /* Verify chip ID */ 1210 static int imx283_identify_module(struct imx283 *imx283) 1211 { 1212 int ret; 1213 u64 val; 1214 1215 ret = cci_read(imx283->cci, IMX283_REG_CHIP_ID, &val, NULL); 1216 if (ret) { 1217 dev_err(imx283->dev, "failed to read chip id %x, with error %d\n", 1218 IMX283_CHIP_ID, ret); 1219 return ret; 1220 } 1221 1222 if (val != IMX283_CHIP_ID) { 1223 dev_err(imx283->dev, "chip id mismatch: %x!=%llx\n", 1224 IMX283_CHIP_ID, val); 1225 return -EIO; 1226 } 1227 1228 return 0; 1229 } 1230 1231 static int imx283_get_selection(struct v4l2_subdev *sd, 1232 struct v4l2_subdev_state *sd_state, 1233 struct v4l2_subdev_selection *sel) 1234 { 1235 switch (sel->target) { 1236 case V4L2_SEL_TGT_CROP: { 1237 sel->r = *v4l2_subdev_state_get_crop(sd_state, 0); 1238 return 0; 1239 } 1240 1241 case V4L2_SEL_TGT_NATIVE_SIZE: 1242 sel->r = imx283_native_area; 1243 return 0; 1244 1245 case V4L2_SEL_TGT_CROP_DEFAULT: 1246 case V4L2_SEL_TGT_CROP_BOUNDS: 1247 sel->r = imx283_active_area; 1248 return 0; 1249 default: 1250 return -EINVAL; 1251 } 1252 } 1253 1254 static const struct v4l2_subdev_core_ops imx283_core_ops = { 1255 .subscribe_event = v4l2_ctrl_subdev_subscribe_event, 1256 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 1257 }; 1258 1259 static const struct v4l2_subdev_video_ops imx283_video_ops = { 1260 .s_stream = v4l2_subdev_s_stream_helper, 1261 }; 1262 1263 static const struct v4l2_subdev_pad_ops imx283_pad_ops = { 1264 .enum_mbus_code = imx283_enum_mbus_code, 1265 .get_fmt = v4l2_subdev_get_fmt, 1266 .set_fmt = imx283_set_pad_format, 1267 .get_selection = imx283_get_selection, 1268 .enum_frame_size = imx283_enum_frame_size, 1269 .enable_streams = imx283_enable_streams, 1270 .disable_streams = imx283_disable_streams, 1271 }; 1272 1273 static const struct v4l2_subdev_internal_ops imx283_internal_ops = { 1274 .init_state = imx283_init_state, 1275 }; 1276 1277 static const struct v4l2_subdev_ops imx283_subdev_ops = { 1278 .core = &imx283_core_ops, 1279 .video = &imx283_video_ops, 1280 .pad = &imx283_pad_ops, 1281 }; 1282 1283 /* Initialize control handlers */ 1284 static int imx283_init_controls(struct imx283 *imx283) 1285 { 1286 struct v4l2_ctrl_handler *ctrl_hdlr; 1287 struct v4l2_fwnode_device_properties props; 1288 struct v4l2_ctrl *link_freq; 1289 const struct imx283_mode *mode = &supported_modes_12bit[0]; 1290 u64 min_hblank, max_hblank, def_hblank; 1291 u64 pixel_rate; 1292 int ret; 1293 1294 ctrl_hdlr = &imx283->ctrl_handler; 1295 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 16); 1296 if (ret) 1297 return ret; 1298 1299 /* 1300 * Create the controls here, but mode specific limits are setup 1301 * in the imx283_set_framing_limits() call below. 1302 */ 1303 1304 /* By default, PIXEL_RATE is read only */ 1305 pixel_rate = imx283_pixel_rate(imx283, mode); 1306 v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops, 1307 V4L2_CID_PIXEL_RATE, pixel_rate, 1308 pixel_rate, 1, pixel_rate); 1309 1310 link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &imx283_ctrl_ops, 1311 V4L2_CID_LINK_FREQ, 1312 __fls(imx283->link_freq_bitmap), 1313 __ffs(imx283->link_freq_bitmap), 1314 link_frequencies); 1315 if (link_freq) 1316 link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1317 1318 /* Initialise vblank/hblank/exposure based on the current mode. */ 1319 imx283->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops, 1320 V4L2_CID_VBLANK, 1321 mode->min_vmax - mode->height, 1322 IMX283_VMAX_MAX, 1, 1323 mode->default_vmax - mode->height); 1324 1325 min_hblank = mode->min_hmax - mode->width; 1326 max_hblank = imx283_iclk_to_pix(pixel_rate, IMX283_HMAX_MAX) - mode->width; 1327 def_hblank = mode->default_hmax - mode->width; 1328 imx283->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops, 1329 V4L2_CID_HBLANK, min_hblank, max_hblank, 1330 1, def_hblank); 1331 1332 imx283->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops, 1333 V4L2_CID_EXPOSURE, 1334 IMX283_EXPOSURE_MIN, 1335 IMX283_EXPOSURE_MAX, 1336 IMX283_EXPOSURE_STEP, 1337 IMX283_EXPOSURE_DEFAULT); 1338 1339 v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 1340 IMX283_ANA_GAIN_MIN, IMX283_ANA_GAIN_MAX, 1341 IMX283_ANA_GAIN_STEP, IMX283_ANA_GAIN_DEFAULT); 1342 1343 v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops, V4L2_CID_DIGITAL_GAIN, 1344 IMX283_DGTL_GAIN_MIN, IMX283_DGTL_GAIN_MAX, 1345 IMX283_DGTL_GAIN_STEP, IMX283_DGTL_GAIN_DEFAULT); 1346 1347 imx283->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops, V4L2_CID_VFLIP, 1348 0, 1, 1, 0); 1349 if (imx283->vflip) 1350 imx283->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; 1351 1352 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &imx283_ctrl_ops, 1353 V4L2_CID_TEST_PATTERN, 1354 ARRAY_SIZE(imx283_tpg_menu) - 1, 1355 0, 0, imx283_tpg_menu); 1356 1357 if (ctrl_hdlr->error) { 1358 ret = ctrl_hdlr->error; 1359 dev_err(imx283->dev, "control init failed (%d)\n", ret); 1360 goto error; 1361 } 1362 1363 ret = v4l2_fwnode_device_parse(imx283->dev, &props); 1364 if (ret) 1365 goto error; 1366 1367 ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &imx283_ctrl_ops, 1368 &props); 1369 if (ret) 1370 goto error; 1371 1372 imx283->sd.ctrl_handler = ctrl_hdlr; 1373 1374 mutex_lock(imx283->ctrl_handler.lock); 1375 1376 /* Setup exposure and frame/line length limits. */ 1377 imx283_set_framing_limits(imx283, mode); 1378 1379 mutex_unlock(imx283->ctrl_handler.lock); 1380 1381 return 0; 1382 1383 error: 1384 v4l2_ctrl_handler_free(ctrl_hdlr); 1385 1386 return ret; 1387 } 1388 1389 static int imx283_parse_endpoint(struct imx283 *imx283) 1390 { 1391 struct fwnode_handle *fwnode; 1392 struct v4l2_fwnode_endpoint bus_cfg = { 1393 .bus_type = V4L2_MBUS_CSI2_DPHY 1394 }; 1395 struct fwnode_handle *ep; 1396 int ret; 1397 1398 fwnode = dev_fwnode(imx283->dev); 1399 ep = fwnode_graph_get_next_endpoint(fwnode, NULL); 1400 if (!ep) { 1401 dev_err(imx283->dev, "Failed to get next endpoint\n"); 1402 return -ENXIO; 1403 } 1404 1405 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); 1406 fwnode_handle_put(ep); 1407 if (ret) 1408 return ret; 1409 1410 if (bus_cfg.bus.mipi_csi2.num_data_lanes != 4) { 1411 dev_err(imx283->dev, 1412 "number of CSI2 data lanes %d is not supported\n", 1413 bus_cfg.bus.mipi_csi2.num_data_lanes); 1414 ret = -EINVAL; 1415 goto done_endpoint_free; 1416 } 1417 1418 ret = v4l2_link_freq_to_bitmap(imx283->dev, bus_cfg.link_frequencies, 1419 bus_cfg.nr_of_link_frequencies, 1420 link_frequencies, ARRAY_SIZE(link_frequencies), 1421 &imx283->link_freq_bitmap); 1422 1423 done_endpoint_free: 1424 v4l2_fwnode_endpoint_free(&bus_cfg); 1425 1426 return ret; 1427 }; 1428 1429 static int imx283_probe(struct i2c_client *client) 1430 { 1431 struct imx283 *imx283; 1432 unsigned int i; 1433 unsigned int xclk_freq; 1434 int ret; 1435 1436 imx283 = devm_kzalloc(&client->dev, sizeof(*imx283), GFP_KERNEL); 1437 if (!imx283) 1438 return -ENOMEM; 1439 1440 imx283->dev = &client->dev; 1441 1442 v4l2_i2c_subdev_init(&imx283->sd, client, &imx283_subdev_ops); 1443 1444 imx283->cci = devm_cci_regmap_init_i2c(client, 16); 1445 if (IS_ERR(imx283->cci)) { 1446 ret = PTR_ERR(imx283->cci); 1447 dev_err(imx283->dev, "failed to initialize CCI: %d\n", ret); 1448 return ret; 1449 } 1450 1451 /* Get system clock (xclk) */ 1452 imx283->xclk = devm_clk_get(imx283->dev, NULL); 1453 if (IS_ERR(imx283->xclk)) { 1454 return dev_err_probe(imx283->dev, PTR_ERR(imx283->xclk), 1455 "failed to get xclk\n"); 1456 } 1457 1458 xclk_freq = clk_get_rate(imx283->xclk); 1459 for (i = 0; i < ARRAY_SIZE(imx283_frequencies); i++) { 1460 if (xclk_freq == imx283_frequencies[i].mhz) { 1461 imx283->freq = &imx283_frequencies[i]; 1462 break; 1463 } 1464 } 1465 if (!imx283->freq) { 1466 dev_err(imx283->dev, "xclk frequency unsupported: %d Hz\n", xclk_freq); 1467 return -EINVAL; 1468 } 1469 1470 ret = imx283_get_regulators(imx283); 1471 if (ret) { 1472 return dev_err_probe(imx283->dev, ret, 1473 "failed to get regulators\n"); 1474 } 1475 1476 ret = imx283_parse_endpoint(imx283); 1477 if (ret) { 1478 dev_err(imx283->dev, "failed to parse endpoint configuration\n"); 1479 return ret; 1480 } 1481 1482 /* Request optional enable pin */ 1483 imx283->reset_gpio = devm_gpiod_get_optional(imx283->dev, "reset", 1484 GPIOD_OUT_LOW); 1485 if (IS_ERR(imx283->reset_gpio)) 1486 return dev_err_probe(imx283->dev, PTR_ERR(imx283->reset_gpio), 1487 "failed to get reset GPIO\n"); 1488 1489 /* 1490 * The sensor must be powered for imx283_identify_module() 1491 * to be able to read the CHIP_ID register 1492 */ 1493 ret = imx283_power_on(imx283); 1494 if (ret) 1495 return ret; 1496 1497 ret = imx283_identify_module(imx283); 1498 if (ret) 1499 goto error_power_off; 1500 1501 /* 1502 * Enable runtime PM with autosuspend. As the device has been powered 1503 * manually, mark it as active, and increase the usage count without 1504 * resuming the device. 1505 */ 1506 pm_runtime_set_active(imx283->dev); 1507 pm_runtime_get_noresume(imx283->dev); 1508 pm_runtime_enable(imx283->dev); 1509 pm_runtime_set_autosuspend_delay(imx283->dev, 1000); 1510 pm_runtime_use_autosuspend(imx283->dev); 1511 1512 /* This needs the pm runtime to be registered. */ 1513 ret = imx283_init_controls(imx283); 1514 if (ret) 1515 goto error_pm; 1516 1517 /* Initialize subdev */ 1518 imx283->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | 1519 V4L2_SUBDEV_FL_HAS_EVENTS; 1520 imx283->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1521 imx283->sd.internal_ops = &imx283_internal_ops; 1522 1523 /* Initialize source pads */ 1524 imx283->pad.flags = MEDIA_PAD_FL_SOURCE; 1525 1526 ret = media_entity_pads_init(&imx283->sd.entity, 1, &imx283->pad); 1527 if (ret) { 1528 dev_err(imx283->dev, "failed to init entity pads: %d\n", ret); 1529 goto error_handler_free; 1530 } 1531 1532 imx283->sd.state_lock = imx283->ctrl_handler.lock; 1533 ret = v4l2_subdev_init_finalize(&imx283->sd); 1534 if (ret < 0) { 1535 dev_err(imx283->dev, "subdev init error: %d\n", ret); 1536 goto error_media_entity; 1537 } 1538 1539 ret = v4l2_async_register_subdev_sensor(&imx283->sd); 1540 if (ret < 0) { 1541 dev_err(imx283->dev, "failed to register sensor sub-device: %d\n", ret); 1542 goto error_subdev_cleanup; 1543 } 1544 1545 /* 1546 * Decrease the PM usage count. The device will get suspended after the 1547 * autosuspend delay, turning the power off. 1548 */ 1549 pm_runtime_mark_last_busy(imx283->dev); 1550 pm_runtime_put_autosuspend(imx283->dev); 1551 1552 return 0; 1553 1554 error_subdev_cleanup: 1555 v4l2_subdev_cleanup(&imx283->sd); 1556 1557 error_media_entity: 1558 media_entity_cleanup(&imx283->sd.entity); 1559 1560 error_handler_free: 1561 v4l2_ctrl_handler_free(imx283->sd.ctrl_handler); 1562 1563 error_pm: 1564 pm_runtime_disable(imx283->dev); 1565 pm_runtime_set_suspended(imx283->dev); 1566 error_power_off: 1567 imx283_power_off(imx283); 1568 1569 return ret; 1570 } 1571 1572 static void imx283_remove(struct i2c_client *client) 1573 { 1574 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1575 struct imx283 *imx283 = to_imx283(sd); 1576 1577 v4l2_async_unregister_subdev(sd); 1578 v4l2_subdev_cleanup(&imx283->sd); 1579 media_entity_cleanup(&sd->entity); 1580 v4l2_ctrl_handler_free(imx283->sd.ctrl_handler); 1581 1582 pm_runtime_disable(imx283->dev); 1583 if (!pm_runtime_status_suspended(imx283->dev)) 1584 imx283_power_off(imx283); 1585 pm_runtime_set_suspended(imx283->dev); 1586 } 1587 1588 static DEFINE_RUNTIME_DEV_PM_OPS(imx283_pm_ops, imx283_runtime_suspend, 1589 imx283_runtime_resume, NULL); 1590 1591 static const struct of_device_id imx283_dt_ids[] = { 1592 { .compatible = "sony,imx283" }, 1593 { /* sentinel */ } 1594 }; 1595 MODULE_DEVICE_TABLE(of, imx283_dt_ids); 1596 1597 static struct i2c_driver imx283_i2c_driver = { 1598 .driver = { 1599 .name = "imx283", 1600 .pm = pm_ptr(&imx283_pm_ops), 1601 .of_match_table = imx283_dt_ids, 1602 }, 1603 .probe = imx283_probe, 1604 .remove = imx283_remove, 1605 }; 1606 module_i2c_driver(imx283_i2c_driver); 1607 1608 MODULE_AUTHOR("Will Whang <will@willwhang.com>"); 1609 MODULE_AUTHOR("Kieran Bingham <kieran.bingham@ideasonboard.com>"); 1610 MODULE_AUTHOR("Umang Jain <umang.jain@ideasonboard.com>"); 1611 MODULE_DESCRIPTION("Sony IMX283 Sensor Driver"); 1612 MODULE_LICENSE("GPL"); 1613