1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * A V4L2 driver for Sony IMX219 cameras. 4 * Copyright (C) 2019, Raspberry Pi (Trading) Ltd 5 * 6 * Based on Sony imx258 camera driver 7 * Copyright (C) 2018 Intel Corporation 8 * 9 * DT / fwnode changes, and regulator / GPIO control taken from imx214 driver 10 * Copyright 2018 Qtechnology A/S 11 * 12 * Flip handling taken from the Sony IMX319 driver. 13 * Copyright (C) 2018 Intel Corporation 14 * 15 */ 16 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/gpio/consumer.h> 20 #include <linux/i2c.h> 21 #include <linux/minmax.h> 22 #include <linux/module.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/regulator/consumer.h> 25 26 #include <media/v4l2-cci.h> 27 #include <media/v4l2-ctrls.h> 28 #include <media/v4l2-device.h> 29 #include <media/v4l2-fwnode.h> 30 #include <media/v4l2-mediabus.h> 31 32 /* Chip ID */ 33 #define IMX219_REG_CHIP_ID CCI_REG16(0x0000) 34 #define IMX219_CHIP_ID 0x0219 35 36 #define IMX219_REG_MODE_SELECT CCI_REG8(0x0100) 37 #define IMX219_MODE_STANDBY 0x00 38 #define IMX219_MODE_STREAMING 0x01 39 40 #define IMX219_REG_CSI_LANE_MODE CCI_REG8(0x0114) 41 #define IMX219_CSI_2_LANE_MODE 0x01 42 #define IMX219_CSI_4_LANE_MODE 0x03 43 44 #define IMX219_REG_DPHY_CTRL CCI_REG8(0x0128) 45 #define IMX219_DPHY_CTRL_TIMING_AUTO 0 46 #define IMX219_DPHY_CTRL_TIMING_MANUAL 1 47 48 #define IMX219_REG_EXCK_FREQ CCI_REG16(0x012a) 49 #define IMX219_EXCK_FREQ(n) ((n) * 256) /* n expressed in MHz */ 50 51 /* Analog gain control */ 52 #define IMX219_REG_ANALOG_GAIN CCI_REG8(0x0157) 53 #define IMX219_ANA_GAIN_MIN 0 54 #define IMX219_ANA_GAIN_MAX 232 55 #define IMX219_ANA_GAIN_STEP 1 56 #define IMX219_ANA_GAIN_DEFAULT 0x0 57 58 /* Digital gain control */ 59 #define IMX219_REG_DIGITAL_GAIN CCI_REG16(0x0158) 60 #define IMX219_DGTL_GAIN_MIN 0x0100 61 #define IMX219_DGTL_GAIN_MAX 0x0fff 62 #define IMX219_DGTL_GAIN_DEFAULT 0x0100 63 #define IMX219_DGTL_GAIN_STEP 1 64 65 /* Exposure control */ 66 #define IMX219_REG_EXPOSURE CCI_REG16(0x015a) 67 #define IMX219_EXPOSURE_MIN 4 68 #define IMX219_EXPOSURE_STEP 1 69 #define IMX219_EXPOSURE_DEFAULT 0x640 70 #define IMX219_EXPOSURE_MAX 65535 71 #define IMX219_EXPOSURE_OFFSET 4 72 73 /* V_TIMING internal */ 74 #define IMX219_REG_FRM_LENGTH_A CCI_REG16(0x0160) 75 #define IMX219_FLL_MAX 0xfffe 76 #define IMX219_VBLANK_MIN 32 77 #define IMX219_REG_LINE_LENGTH_A CCI_REG16(0x0162) 78 #define IMX219_LLP_MIN 0x0d78 79 #define IMX219_BINNED_LLP_MIN 0x0de8 80 #define IMX219_LLP_MAX 0x7ff0 81 82 #define IMX219_REG_X_ADD_STA_A CCI_REG16(0x0164) 83 #define IMX219_REG_X_ADD_END_A CCI_REG16(0x0166) 84 #define IMX219_REG_Y_ADD_STA_A CCI_REG16(0x0168) 85 #define IMX219_REG_Y_ADD_END_A CCI_REG16(0x016a) 86 #define IMX219_REG_X_OUTPUT_SIZE CCI_REG16(0x016c) 87 #define IMX219_REG_Y_OUTPUT_SIZE CCI_REG16(0x016e) 88 #define IMX219_REG_X_ODD_INC_A CCI_REG8(0x0170) 89 #define IMX219_REG_Y_ODD_INC_A CCI_REG8(0x0171) 90 #define IMX219_REG_ORIENTATION CCI_REG8(0x0172) 91 92 /* Binning Mode */ 93 #define IMX219_REG_BINNING_MODE_H CCI_REG8(0x0174) 94 #define IMX219_REG_BINNING_MODE_V CCI_REG8(0x0175) 95 #define IMX219_BINNING_NONE 0x00 96 #define IMX219_BINNING_X2 0x01 97 #define IMX219_BINNING_X2_ANALOG 0x03 98 99 #define IMX219_REG_CSI_DATA_FORMAT_A CCI_REG16(0x018c) 100 101 /* PLL Settings */ 102 #define IMX219_REG_VTPXCK_DIV CCI_REG8(0x0301) 103 #define IMX219_REG_VTSYCK_DIV CCI_REG8(0x0303) 104 #define IMX219_REG_PREPLLCK_VT_DIV CCI_REG8(0x0304) 105 #define IMX219_REG_PREPLLCK_OP_DIV CCI_REG8(0x0305) 106 #define IMX219_REG_PLL_VT_MPY CCI_REG16(0x0306) 107 #define IMX219_REG_OPPXCK_DIV CCI_REG8(0x0309) 108 #define IMX219_REG_OPSYCK_DIV CCI_REG8(0x030b) 109 #define IMX219_REG_PLL_OP_MPY CCI_REG16(0x030c) 110 111 /* Test Pattern Control */ 112 #define IMX219_REG_TEST_PATTERN CCI_REG16(0x0600) 113 #define IMX219_TEST_PATTERN_DISABLE 0 114 #define IMX219_TEST_PATTERN_SOLID_COLOR 1 115 #define IMX219_TEST_PATTERN_COLOR_BARS 2 116 #define IMX219_TEST_PATTERN_GREY_COLOR 3 117 #define IMX219_TEST_PATTERN_PN9 4 118 #define IMX219_TEST_PATTERN_16SPLIT_COLOR_BARS 5 119 #define IMX219_TEST_PATTERN_16SPLIT_INV_COLOR_BARS 6 120 #define IMX219_TEST_PATTERN_COLUMN_COUNTER 7 121 #define IMX219_TEST_PATTERN_INV_COLUMN_COUNTER 8 122 #define IMX219_TEST_PATTERN_PN31 9 123 124 /* Test pattern colour components */ 125 #define IMX219_REG_TESTP_RED CCI_REG16(0x0602) 126 #define IMX219_REG_TESTP_GREENR CCI_REG16(0x0604) 127 #define IMX219_REG_TESTP_BLUE CCI_REG16(0x0606) 128 #define IMX219_REG_TESTP_GREENB CCI_REG16(0x0608) 129 #define IMX219_TESTP_COLOUR_MIN 0 130 #define IMX219_TESTP_COLOUR_MAX 0x03ff 131 #define IMX219_TESTP_COLOUR_STEP 1 132 133 #define IMX219_REG_TP_WINDOW_WIDTH CCI_REG16(0x0624) 134 #define IMX219_REG_TP_WINDOW_HEIGHT CCI_REG16(0x0626) 135 136 /* External clock frequency is 24.0M */ 137 #define IMX219_XCLK_FREQ 24000000 138 139 /* Pixel rate is fixed for all the modes */ 140 #define IMX219_PIXEL_RATE 182400000 141 #define IMX219_PIXEL_RATE_4LANE 281600000 142 143 #define IMX219_DEFAULT_LINK_FREQ 456000000 144 #define IMX219_DEFAULT_LINK_FREQ_4LANE_UNSUPPORTED 363000000 145 #define IMX219_DEFAULT_LINK_FREQ_4LANE 364000000 146 147 /* IMX219 native and active pixel array size. */ 148 #define IMX219_NATIVE_WIDTH 3296U 149 #define IMX219_NATIVE_HEIGHT 2480U 150 #define IMX219_ACTIVE_AREA_LEFT 8U 151 #define IMX219_ACTIVE_AREA_TOP 8U 152 #define IMX219_ACTIVE_AREA_WIDTH 3280U 153 #define IMX219_ACTIVE_AREA_HEIGHT 2464U 154 155 /* Mode : resolution and related config&values */ 156 struct imx219_mode { 157 /* Frame width */ 158 unsigned int width; 159 /* Frame height */ 160 unsigned int height; 161 162 /* V-timing */ 163 unsigned int fll_def; 164 }; 165 166 static const struct cci_reg_sequence imx219_common_regs[] = { 167 { IMX219_REG_MODE_SELECT, 0x00 }, /* Mode Select */ 168 169 /* To Access Addresses 3000-5fff, send the following commands */ 170 { CCI_REG8(0x30eb), 0x05 }, 171 { CCI_REG8(0x30eb), 0x0c }, 172 { CCI_REG8(0x300a), 0xff }, 173 { CCI_REG8(0x300b), 0xff }, 174 { CCI_REG8(0x30eb), 0x05 }, 175 { CCI_REG8(0x30eb), 0x09 }, 176 177 /* Undocumented registers */ 178 { CCI_REG8(0x455e), 0x00 }, 179 { CCI_REG8(0x471e), 0x4b }, 180 { CCI_REG8(0x4767), 0x0f }, 181 { CCI_REG8(0x4750), 0x14 }, 182 { CCI_REG8(0x4540), 0x00 }, 183 { CCI_REG8(0x47b4), 0x14 }, 184 { CCI_REG8(0x4713), 0x30 }, 185 { CCI_REG8(0x478b), 0x10 }, 186 { CCI_REG8(0x478f), 0x10 }, 187 { CCI_REG8(0x4793), 0x10 }, 188 { CCI_REG8(0x4797), 0x0e }, 189 { CCI_REG8(0x479b), 0x0e }, 190 191 /* Frame Bank Register Group "A" */ 192 { IMX219_REG_X_ODD_INC_A, 1 }, 193 { IMX219_REG_Y_ODD_INC_A, 1 }, 194 195 /* Output setup registers */ 196 { IMX219_REG_DPHY_CTRL, IMX219_DPHY_CTRL_TIMING_AUTO }, 197 { IMX219_REG_EXCK_FREQ, IMX219_EXCK_FREQ(IMX219_XCLK_FREQ / 1000000) }, 198 }; 199 200 static const struct cci_reg_sequence imx219_2lane_regs[] = { 201 /* PLL Clock Table */ 202 { IMX219_REG_VTPXCK_DIV, 5 }, 203 { IMX219_REG_VTSYCK_DIV, 1 }, 204 { IMX219_REG_PREPLLCK_VT_DIV, 3 }, /* 0x03 = AUTO set */ 205 { IMX219_REG_PREPLLCK_OP_DIV, 3 }, /* 0x03 = AUTO set */ 206 { IMX219_REG_PLL_VT_MPY, 57 }, 207 { IMX219_REG_OPSYCK_DIV, 1 }, 208 { IMX219_REG_PLL_OP_MPY, 114 }, 209 210 /* 2-Lane CSI Mode */ 211 { IMX219_REG_CSI_LANE_MODE, IMX219_CSI_2_LANE_MODE }, 212 }; 213 214 static const struct cci_reg_sequence imx219_4lane_regs[] = { 215 /* PLL Clock Table */ 216 { IMX219_REG_VTPXCK_DIV, 5 }, 217 { IMX219_REG_VTSYCK_DIV, 1 }, 218 { IMX219_REG_PREPLLCK_VT_DIV, 3 }, /* 0x03 = AUTO set */ 219 { IMX219_REG_PREPLLCK_OP_DIV, 3 }, /* 0x03 = AUTO set */ 220 { IMX219_REG_PLL_VT_MPY, 88 }, 221 { IMX219_REG_OPSYCK_DIV, 1 }, 222 { IMX219_REG_PLL_OP_MPY, 91 }, 223 224 /* 4-Lane CSI Mode */ 225 { IMX219_REG_CSI_LANE_MODE, IMX219_CSI_4_LANE_MODE }, 226 }; 227 228 static const s64 imx219_link_freq_menu[] = { 229 IMX219_DEFAULT_LINK_FREQ, 230 }; 231 232 static const s64 imx219_link_freq_4lane_menu[] = { 233 IMX219_DEFAULT_LINK_FREQ_4LANE, 234 /* 235 * This will never be advertised to userspace, but will be used for 236 * v4l2_link_freq_to_bitmap 237 */ 238 IMX219_DEFAULT_LINK_FREQ_4LANE_UNSUPPORTED, 239 }; 240 241 static const char * const imx219_test_pattern_menu[] = { 242 "Disabled", 243 "Color Bars", 244 "Solid Color", 245 "Grey Color Bars", 246 "PN9", 247 "16 Split Color Bars", 248 "16 Split Inverted Color Bars", 249 "Column Counter", 250 "Inverted Column Counter", 251 "PN31" 252 }; 253 254 static const int imx219_test_pattern_val[] = { 255 IMX219_TEST_PATTERN_DISABLE, 256 IMX219_TEST_PATTERN_COLOR_BARS, 257 IMX219_TEST_PATTERN_SOLID_COLOR, 258 IMX219_TEST_PATTERN_GREY_COLOR, 259 IMX219_TEST_PATTERN_PN9, 260 IMX219_TEST_PATTERN_16SPLIT_COLOR_BARS, 261 IMX219_TEST_PATTERN_16SPLIT_INV_COLOR_BARS, 262 IMX219_TEST_PATTERN_COLUMN_COUNTER, 263 IMX219_TEST_PATTERN_INV_COLUMN_COUNTER, 264 IMX219_TEST_PATTERN_PN31 265 }; 266 267 /* regulator supplies */ 268 static const char * const imx219_supply_name[] = { 269 /* Supplies can be enabled in any order */ 270 "VANA", /* Analog (2.8V) supply */ 271 "VDIG", /* Digital Core (1.8V) supply */ 272 "VDDL", /* IF (1.2V) supply */ 273 }; 274 275 #define IMX219_NUM_SUPPLIES ARRAY_SIZE(imx219_supply_name) 276 277 /* 278 * The supported formats. 279 * This table MUST contain 4 entries per format, to cover the various flip 280 * combinations in the order 281 * - no flip 282 * - h flip 283 * - v flip 284 * - h&v flips 285 */ 286 static const u32 imx219_mbus_formats[] = { 287 MEDIA_BUS_FMT_SRGGB10_1X10, 288 MEDIA_BUS_FMT_SGRBG10_1X10, 289 MEDIA_BUS_FMT_SGBRG10_1X10, 290 MEDIA_BUS_FMT_SBGGR10_1X10, 291 292 MEDIA_BUS_FMT_SRGGB8_1X8, 293 MEDIA_BUS_FMT_SGRBG8_1X8, 294 MEDIA_BUS_FMT_SGBRG8_1X8, 295 MEDIA_BUS_FMT_SBGGR8_1X8, 296 }; 297 298 /* 299 * Initialisation delay between XCLR low->high and the moment when the sensor 300 * can start capture (i.e. can leave software stanby) must be not less than: 301 * t4 + max(t5, t6 + <time to initialize the sensor register over I2C>) 302 * where 303 * t4 is fixed, and is max 200uS, 304 * t5 is fixed, and is 6000uS, 305 * t6 depends on the sensor external clock, and is max 32000 clock periods. 306 * As per sensor datasheet, the external clock must be from 6MHz to 27MHz. 307 * So for any acceptable external clock t6 is always within the range of 308 * 1185 to 5333 uS, and is always less than t5. 309 * For this reason this is always safe to wait (t4 + t5) = 6200 uS, then 310 * initialize the sensor over I2C, and then exit the software standby. 311 * 312 * This start-up time can be optimized a bit more, if we start the writes 313 * over I2C after (t4+t6), but before (t4+t5) expires. But then sensor 314 * initialization over I2C may complete before (t4+t5) expires, and we must 315 * ensure that capture is not started before (t4+t5). 316 * 317 * This delay doesn't account for the power supply startup time. If needed, 318 * this should be taken care of via the regulator framework. E.g. in the 319 * case of DT for regulator-fixed one should define the startup-delay-us 320 * property. 321 */ 322 #define IMX219_XCLR_MIN_DELAY_US 6200 323 #define IMX219_XCLR_DELAY_RANGE_US 1000 324 325 /* Mode configs */ 326 static const struct imx219_mode supported_modes[] = { 327 { 328 /* 8MPix 15fps mode */ 329 .width = 3280, 330 .height = 2464, 331 .fll_def = 3526, 332 }, 333 { 334 /* 1080P 30fps cropped */ 335 .width = 1920, 336 .height = 1080, 337 .fll_def = 1763, 338 }, 339 { 340 /* 2x2 binned 60fps mode */ 341 .width = 1640, 342 .height = 1232, 343 .fll_def = 1707, 344 }, 345 { 346 /* 640x480 60fps mode */ 347 .width = 640, 348 .height = 480, 349 .fll_def = 1707, 350 }, 351 }; 352 353 struct imx219 { 354 struct v4l2_subdev sd; 355 struct media_pad pad; 356 357 struct regmap *regmap; 358 struct clk *xclk; /* system clock to IMX219 */ 359 u32 xclk_freq; 360 361 struct gpio_desc *reset_gpio; 362 struct regulator_bulk_data supplies[IMX219_NUM_SUPPLIES]; 363 364 struct v4l2_ctrl_handler ctrl_handler; 365 /* V4L2 Controls */ 366 struct v4l2_ctrl *pixel_rate; 367 struct v4l2_ctrl *link_freq; 368 struct v4l2_ctrl *exposure; 369 struct v4l2_ctrl *vflip; 370 struct v4l2_ctrl *hflip; 371 struct v4l2_ctrl *vblank; 372 struct v4l2_ctrl *hblank; 373 374 /* Two or Four lanes */ 375 u8 lanes; 376 }; 377 378 static inline struct imx219 *to_imx219(struct v4l2_subdev *_sd) 379 { 380 return container_of(_sd, struct imx219, sd); 381 } 382 383 /* Get bayer order based on flip setting. */ 384 static u32 imx219_get_format_code(struct imx219 *imx219, u32 code) 385 { 386 unsigned int i; 387 388 for (i = 0; i < ARRAY_SIZE(imx219_mbus_formats); i++) 389 if (imx219_mbus_formats[i] == code) 390 break; 391 392 if (i >= ARRAY_SIZE(imx219_mbus_formats)) 393 i = 0; 394 395 i = (i & ~3) | (imx219->vflip->val ? 2 : 0) | 396 (imx219->hflip->val ? 1 : 0); 397 398 return imx219_mbus_formats[i]; 399 } 400 401 static u32 imx219_get_format_bpp(const struct v4l2_mbus_framefmt *format) 402 { 403 switch (format->code) { 404 case MEDIA_BUS_FMT_SRGGB8_1X8: 405 case MEDIA_BUS_FMT_SGRBG8_1X8: 406 case MEDIA_BUS_FMT_SGBRG8_1X8: 407 case MEDIA_BUS_FMT_SBGGR8_1X8: 408 return 8; 409 410 case MEDIA_BUS_FMT_SRGGB10_1X10: 411 case MEDIA_BUS_FMT_SGRBG10_1X10: 412 case MEDIA_BUS_FMT_SGBRG10_1X10: 413 case MEDIA_BUS_FMT_SBGGR10_1X10: 414 default: 415 return 10; 416 } 417 } 418 419 static void imx219_get_binning(struct v4l2_subdev_state *state, u8 *bin_h, 420 u8 *bin_v) 421 { 422 const struct v4l2_mbus_framefmt *format = 423 v4l2_subdev_state_get_format(state, 0); 424 const struct v4l2_rect *crop = v4l2_subdev_state_get_crop(state, 0); 425 u32 hbin = crop->width / format->width; 426 u32 vbin = crop->height / format->height; 427 428 if (hbin == 2 && vbin == 2) { 429 *bin_h = IMX219_BINNING_X2_ANALOG; 430 *bin_v = IMX219_BINNING_X2_ANALOG; 431 } else { 432 *bin_h = IMX219_BINNING_NONE; 433 *bin_v = IMX219_BINNING_NONE; 434 } 435 436 } 437 438 static inline u32 imx219_get_rate_factor(struct v4l2_subdev_state *state) 439 { 440 u8 bin_h, bin_v; 441 442 imx219_get_binning(state, &bin_h, &bin_v); 443 444 return (bin_h & bin_v) == IMX219_BINNING_X2_ANALOG ? 2 : 1; 445 } 446 447 /* ----------------------------------------------------------------------------- 448 * Controls 449 */ 450 451 static int imx219_set_ctrl(struct v4l2_ctrl *ctrl) 452 { 453 struct imx219 *imx219 = 454 container_of(ctrl->handler, struct imx219, ctrl_handler); 455 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd); 456 const struct v4l2_mbus_framefmt *format; 457 struct v4l2_subdev_state *state; 458 u32 rate_factor; 459 int ret = 0; 460 461 state = v4l2_subdev_get_locked_active_state(&imx219->sd); 462 format = v4l2_subdev_state_get_format(state, 0); 463 rate_factor = imx219_get_rate_factor(state); 464 465 if (ctrl->id == V4L2_CID_VBLANK) { 466 int exposure_max, exposure_def; 467 468 /* Update max exposure while meeting expected vblanking */ 469 exposure_max = format->height + ctrl->val - IMX219_EXPOSURE_OFFSET; 470 exposure_def = (exposure_max < IMX219_EXPOSURE_DEFAULT) ? 471 exposure_max : IMX219_EXPOSURE_DEFAULT; 472 ret = __v4l2_ctrl_modify_range(imx219->exposure, 473 imx219->exposure->minimum, 474 exposure_max, 475 imx219->exposure->step, 476 exposure_def); 477 if (ret) 478 return ret; 479 480 } 481 482 /* 483 * Applying V4L2 control value only happens 484 * when power is up for streaming 485 */ 486 if (pm_runtime_get_if_in_use(&client->dev) == 0) 487 return 0; 488 489 switch (ctrl->id) { 490 case V4L2_CID_ANALOGUE_GAIN: 491 cci_write(imx219->regmap, IMX219_REG_ANALOG_GAIN, 492 ctrl->val, &ret); 493 break; 494 case V4L2_CID_EXPOSURE: 495 cci_write(imx219->regmap, IMX219_REG_EXPOSURE, 496 ctrl->val / rate_factor, &ret); 497 break; 498 case V4L2_CID_DIGITAL_GAIN: 499 cci_write(imx219->regmap, IMX219_REG_DIGITAL_GAIN, 500 ctrl->val, &ret); 501 break; 502 case V4L2_CID_TEST_PATTERN: 503 cci_write(imx219->regmap, IMX219_REG_TEST_PATTERN, 504 imx219_test_pattern_val[ctrl->val], &ret); 505 break; 506 case V4L2_CID_HFLIP: 507 case V4L2_CID_VFLIP: 508 cci_write(imx219->regmap, IMX219_REG_ORIENTATION, 509 imx219->hflip->val | imx219->vflip->val << 1, &ret); 510 break; 511 case V4L2_CID_VBLANK: 512 cci_write(imx219->regmap, IMX219_REG_FRM_LENGTH_A, 513 (format->height + ctrl->val) / rate_factor, &ret); 514 break; 515 case V4L2_CID_HBLANK: 516 cci_write(imx219->regmap, IMX219_REG_LINE_LENGTH_A, 517 format->width + ctrl->val, &ret); 518 break; 519 case V4L2_CID_TEST_PATTERN_RED: 520 cci_write(imx219->regmap, IMX219_REG_TESTP_RED, 521 ctrl->val, &ret); 522 break; 523 case V4L2_CID_TEST_PATTERN_GREENR: 524 cci_write(imx219->regmap, IMX219_REG_TESTP_GREENR, 525 ctrl->val, &ret); 526 break; 527 case V4L2_CID_TEST_PATTERN_BLUE: 528 cci_write(imx219->regmap, IMX219_REG_TESTP_BLUE, 529 ctrl->val, &ret); 530 break; 531 case V4L2_CID_TEST_PATTERN_GREENB: 532 cci_write(imx219->regmap, IMX219_REG_TESTP_GREENB, 533 ctrl->val, &ret); 534 break; 535 default: 536 dev_info(&client->dev, 537 "ctrl(id:0x%x,val:0x%x) is not handled\n", 538 ctrl->id, ctrl->val); 539 ret = -EINVAL; 540 break; 541 } 542 543 pm_runtime_put(&client->dev); 544 545 return ret; 546 } 547 548 static const struct v4l2_ctrl_ops imx219_ctrl_ops = { 549 .s_ctrl = imx219_set_ctrl, 550 }; 551 552 static unsigned long imx219_get_pixel_rate(struct imx219 *imx219) 553 { 554 return (imx219->lanes == 2) ? IMX219_PIXEL_RATE : IMX219_PIXEL_RATE_4LANE; 555 } 556 557 /* Initialize control handlers */ 558 static int imx219_init_controls(struct imx219 *imx219) 559 { 560 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd); 561 const struct imx219_mode *mode = &supported_modes[0]; 562 struct v4l2_ctrl_handler *ctrl_hdlr; 563 struct v4l2_fwnode_device_properties props; 564 int exposure_max, exposure_def; 565 int i, ret; 566 567 ctrl_hdlr = &imx219->ctrl_handler; 568 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 12); 569 if (ret) 570 return ret; 571 572 /* By default, PIXEL_RATE is read only */ 573 imx219->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, 574 V4L2_CID_PIXEL_RATE, 575 imx219_get_pixel_rate(imx219), 576 imx219_get_pixel_rate(imx219), 1, 577 imx219_get_pixel_rate(imx219)); 578 579 imx219->link_freq = 580 v4l2_ctrl_new_int_menu(ctrl_hdlr, &imx219_ctrl_ops, 581 V4L2_CID_LINK_FREQ, 582 ARRAY_SIZE(imx219_link_freq_menu) - 1, 0, 583 (imx219->lanes == 2) ? imx219_link_freq_menu : 584 imx219_link_freq_4lane_menu); 585 if (imx219->link_freq) 586 imx219->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 587 588 /* Initial blanking and exposure. Limits are updated during set_fmt */ 589 imx219->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, 590 V4L2_CID_VBLANK, IMX219_VBLANK_MIN, 591 IMX219_FLL_MAX - mode->height, 1, 592 mode->fll_def - mode->height); 593 imx219->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, 594 V4L2_CID_HBLANK, 595 IMX219_LLP_MIN - mode->width, 596 IMX219_LLP_MAX - mode->width, 1, 597 IMX219_LLP_MIN - mode->width); 598 exposure_max = mode->fll_def - IMX219_EXPOSURE_OFFSET; 599 exposure_def = (exposure_max < IMX219_EXPOSURE_DEFAULT) ? 600 exposure_max : IMX219_EXPOSURE_DEFAULT; 601 imx219->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, 602 V4L2_CID_EXPOSURE, 603 IMX219_EXPOSURE_MIN, exposure_max, 604 IMX219_EXPOSURE_STEP, 605 exposure_def); 606 607 v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 608 IMX219_ANA_GAIN_MIN, IMX219_ANA_GAIN_MAX, 609 IMX219_ANA_GAIN_STEP, IMX219_ANA_GAIN_DEFAULT); 610 611 v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, V4L2_CID_DIGITAL_GAIN, 612 IMX219_DGTL_GAIN_MIN, IMX219_DGTL_GAIN_MAX, 613 IMX219_DGTL_GAIN_STEP, IMX219_DGTL_GAIN_DEFAULT); 614 615 imx219->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, 616 V4L2_CID_HFLIP, 0, 1, 1, 0); 617 if (imx219->hflip) 618 imx219->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; 619 620 imx219->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, 621 V4L2_CID_VFLIP, 0, 1, 1, 0); 622 if (imx219->vflip) 623 imx219->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; 624 625 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &imx219_ctrl_ops, 626 V4L2_CID_TEST_PATTERN, 627 ARRAY_SIZE(imx219_test_pattern_menu) - 1, 628 0, 0, imx219_test_pattern_menu); 629 for (i = 0; i < 4; i++) { 630 /* 631 * The assumption is that 632 * V4L2_CID_TEST_PATTERN_GREENR == V4L2_CID_TEST_PATTERN_RED + 1 633 * V4L2_CID_TEST_PATTERN_BLUE == V4L2_CID_TEST_PATTERN_RED + 2 634 * V4L2_CID_TEST_PATTERN_GREENB == V4L2_CID_TEST_PATTERN_RED + 3 635 */ 636 v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, 637 V4L2_CID_TEST_PATTERN_RED + i, 638 IMX219_TESTP_COLOUR_MIN, 639 IMX219_TESTP_COLOUR_MAX, 640 IMX219_TESTP_COLOUR_STEP, 641 IMX219_TESTP_COLOUR_MAX); 642 /* The "Solid color" pattern is white by default */ 643 } 644 645 if (ctrl_hdlr->error) { 646 ret = ctrl_hdlr->error; 647 dev_err_probe(&client->dev, ret, "Control init failed\n"); 648 goto error; 649 } 650 651 ret = v4l2_fwnode_device_parse(&client->dev, &props); 652 if (ret) 653 goto error; 654 655 ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &imx219_ctrl_ops, 656 &props); 657 if (ret) 658 goto error; 659 660 imx219->sd.ctrl_handler = ctrl_hdlr; 661 662 return 0; 663 664 error: 665 v4l2_ctrl_handler_free(ctrl_hdlr); 666 667 return ret; 668 } 669 670 static void imx219_free_controls(struct imx219 *imx219) 671 { 672 v4l2_ctrl_handler_free(imx219->sd.ctrl_handler); 673 } 674 675 /* ----------------------------------------------------------------------------- 676 * Subdev operations 677 */ 678 679 static int imx219_set_framefmt(struct imx219 *imx219, 680 struct v4l2_subdev_state *state) 681 { 682 const struct v4l2_mbus_framefmt *format; 683 const struct v4l2_rect *crop; 684 u8 bin_h, bin_v; 685 u32 bpp; 686 int ret = 0; 687 688 format = v4l2_subdev_state_get_format(state, 0); 689 crop = v4l2_subdev_state_get_crop(state, 0); 690 bpp = imx219_get_format_bpp(format); 691 692 cci_write(imx219->regmap, IMX219_REG_X_ADD_STA_A, 693 crop->left - IMX219_ACTIVE_AREA_LEFT, &ret); 694 cci_write(imx219->regmap, IMX219_REG_X_ADD_END_A, 695 crop->left - IMX219_ACTIVE_AREA_LEFT + crop->width - 1, &ret); 696 cci_write(imx219->regmap, IMX219_REG_Y_ADD_STA_A, 697 crop->top - IMX219_ACTIVE_AREA_TOP, &ret); 698 cci_write(imx219->regmap, IMX219_REG_Y_ADD_END_A, 699 crop->top - IMX219_ACTIVE_AREA_TOP + crop->height - 1, &ret); 700 701 imx219_get_binning(state, &bin_h, &bin_v); 702 cci_write(imx219->regmap, IMX219_REG_BINNING_MODE_H, bin_h, &ret); 703 cci_write(imx219->regmap, IMX219_REG_BINNING_MODE_V, bin_v, &ret); 704 705 cci_write(imx219->regmap, IMX219_REG_X_OUTPUT_SIZE, 706 format->width, &ret); 707 cci_write(imx219->regmap, IMX219_REG_Y_OUTPUT_SIZE, 708 format->height, &ret); 709 710 cci_write(imx219->regmap, IMX219_REG_TP_WINDOW_WIDTH, 711 format->width, &ret); 712 cci_write(imx219->regmap, IMX219_REG_TP_WINDOW_HEIGHT, 713 format->height, &ret); 714 715 cci_write(imx219->regmap, IMX219_REG_CSI_DATA_FORMAT_A, 716 (bpp << 8) | bpp, &ret); 717 cci_write(imx219->regmap, IMX219_REG_OPPXCK_DIV, bpp, &ret); 718 719 return ret; 720 } 721 722 static int imx219_configure_lanes(struct imx219 *imx219) 723 { 724 /* Write the appropriate PLL settings for the number of MIPI lanes */ 725 return cci_multi_reg_write(imx219->regmap, 726 imx219->lanes == 2 ? imx219_2lane_regs : imx219_4lane_regs, 727 imx219->lanes == 2 ? ARRAY_SIZE(imx219_2lane_regs) : 728 ARRAY_SIZE(imx219_4lane_regs), NULL); 729 }; 730 731 static int imx219_enable_streams(struct v4l2_subdev *sd, 732 struct v4l2_subdev_state *state, u32 pad, 733 u64 streams_mask) 734 { 735 struct imx219 *imx219 = to_imx219(sd); 736 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd); 737 int ret; 738 739 ret = pm_runtime_resume_and_get(&client->dev); 740 if (ret < 0) 741 return ret; 742 743 /* Send all registers that are common to all modes */ 744 ret = cci_multi_reg_write(imx219->regmap, imx219_common_regs, 745 ARRAY_SIZE(imx219_common_regs), NULL); 746 if (ret) { 747 dev_err(&client->dev, "%s failed to send mfg header\n", __func__); 748 goto err_rpm_put; 749 } 750 751 /* Configure two or four Lane mode */ 752 ret = imx219_configure_lanes(imx219); 753 if (ret) { 754 dev_err(&client->dev, "%s failed to configure lanes\n", __func__); 755 goto err_rpm_put; 756 } 757 758 /* Apply format and crop settings. */ 759 ret = imx219_set_framefmt(imx219, state); 760 if (ret) { 761 dev_err(&client->dev, "%s failed to set frame format: %d\n", 762 __func__, ret); 763 goto err_rpm_put; 764 } 765 766 /* Apply customized values from user */ 767 ret = __v4l2_ctrl_handler_setup(imx219->sd.ctrl_handler); 768 if (ret) 769 goto err_rpm_put; 770 771 /* set stream on register */ 772 ret = cci_write(imx219->regmap, IMX219_REG_MODE_SELECT, 773 IMX219_MODE_STREAMING, NULL); 774 if (ret) 775 goto err_rpm_put; 776 777 /* vflip and hflip cannot change during streaming */ 778 __v4l2_ctrl_grab(imx219->vflip, true); 779 __v4l2_ctrl_grab(imx219->hflip, true); 780 781 return 0; 782 783 err_rpm_put: 784 pm_runtime_put_autosuspend(&client->dev); 785 return ret; 786 } 787 788 static int imx219_disable_streams(struct v4l2_subdev *sd, 789 struct v4l2_subdev_state *state, u32 pad, 790 u64 streams_mask) 791 { 792 struct imx219 *imx219 = to_imx219(sd); 793 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd); 794 int ret; 795 796 /* set stream off register */ 797 ret = cci_write(imx219->regmap, IMX219_REG_MODE_SELECT, 798 IMX219_MODE_STANDBY, NULL); 799 if (ret) 800 dev_err(&client->dev, "%s failed to set stream\n", __func__); 801 802 __v4l2_ctrl_grab(imx219->vflip, false); 803 __v4l2_ctrl_grab(imx219->hflip, false); 804 805 pm_runtime_put_autosuspend(&client->dev); 806 807 return ret; 808 } 809 810 static int imx219_enum_mbus_code(struct v4l2_subdev *sd, 811 struct v4l2_subdev_state *state, 812 struct v4l2_subdev_mbus_code_enum *code) 813 { 814 struct imx219 *imx219 = to_imx219(sd); 815 816 if (code->index >= (ARRAY_SIZE(imx219_mbus_formats) / 4)) 817 return -EINVAL; 818 819 code->code = imx219_get_format_code(imx219, imx219_mbus_formats[code->index * 4]); 820 821 return 0; 822 } 823 824 static int imx219_enum_frame_size(struct v4l2_subdev *sd, 825 struct v4l2_subdev_state *state, 826 struct v4l2_subdev_frame_size_enum *fse) 827 { 828 struct imx219 *imx219 = to_imx219(sd); 829 u32 code; 830 831 if (fse->index >= ARRAY_SIZE(supported_modes)) 832 return -EINVAL; 833 834 code = imx219_get_format_code(imx219, fse->code); 835 if (fse->code != code) 836 return -EINVAL; 837 838 fse->min_width = supported_modes[fse->index].width; 839 fse->max_width = fse->min_width; 840 fse->min_height = supported_modes[fse->index].height; 841 fse->max_height = fse->min_height; 842 843 return 0; 844 } 845 846 static int imx219_set_pad_format(struct v4l2_subdev *sd, 847 struct v4l2_subdev_state *state, 848 struct v4l2_subdev_format *fmt) 849 { 850 struct imx219 *imx219 = to_imx219(sd); 851 const struct imx219_mode *mode; 852 struct v4l2_mbus_framefmt *format; 853 struct v4l2_rect *crop; 854 u8 bin_h, bin_v, binning; 855 int ret; 856 857 format = v4l2_subdev_state_get_format(state, 0); 858 859 /* 860 * Adjust the requested format to match the closest mode. The Bayer 861 * order varies with flips. 862 */ 863 mode = v4l2_find_nearest_size(supported_modes, 864 ARRAY_SIZE(supported_modes), 865 width, height, 866 fmt->format.width, fmt->format.height); 867 868 fmt->format.code = imx219_get_format_code(imx219, fmt->format.code); 869 fmt->format.width = mode->width; 870 fmt->format.height = mode->height; 871 fmt->format.field = V4L2_FIELD_NONE; 872 fmt->format.colorspace = V4L2_COLORSPACE_RAW; 873 fmt->format.ycbcr_enc = V4L2_YCBCR_ENC_601; 874 fmt->format.quantization = V4L2_QUANTIZATION_FULL_RANGE; 875 fmt->format.xfer_func = V4L2_XFER_FUNC_NONE; 876 877 *format = fmt->format; 878 879 /* 880 * Use binning to maximize the crop rectangle size, and centre it in the 881 * sensor. 882 */ 883 bin_h = min(IMX219_ACTIVE_AREA_WIDTH / format->width, 2U); 884 bin_v = min(IMX219_ACTIVE_AREA_HEIGHT / format->height, 2U); 885 886 /* Ensure bin_h and bin_v are same to avoid 1:2 or 2:1 stretching */ 887 binning = min(bin_h, bin_v); 888 889 crop = v4l2_subdev_state_get_crop(state, 0); 890 crop->width = format->width * binning; 891 crop->height = format->height * binning; 892 crop->left = (IMX219_NATIVE_WIDTH - crop->width) / 2; 893 crop->top = (IMX219_NATIVE_HEIGHT - crop->height) / 2; 894 895 if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 896 int exposure_max; 897 int exposure_def; 898 int llp_min; 899 int pixel_rate; 900 901 /* Update limits and set FPS to default */ 902 ret = __v4l2_ctrl_modify_range(imx219->vblank, IMX219_VBLANK_MIN, 903 IMX219_FLL_MAX - mode->height, 1, 904 mode->fll_def - mode->height); 905 if (ret) 906 return ret; 907 908 ret = __v4l2_ctrl_s_ctrl(imx219->vblank, 909 mode->fll_def - mode->height); 910 if (ret) 911 return ret; 912 913 /* Update max exposure while meeting expected vblanking */ 914 exposure_max = mode->fll_def - IMX219_EXPOSURE_OFFSET; 915 exposure_def = (exposure_max < IMX219_EXPOSURE_DEFAULT) ? 916 exposure_max : IMX219_EXPOSURE_DEFAULT; 917 ret = __v4l2_ctrl_modify_range(imx219->exposure, 918 imx219->exposure->minimum, 919 exposure_max, 920 imx219->exposure->step, 921 exposure_def); 922 if (ret) 923 return ret; 924 925 /* 926 * With analog binning the default minimum line length of 3448 927 * can cause artefacts with RAW10 formats, because the ADC 928 * operates on two lines together. So we switch to a higher 929 * minimum of 3560. 930 */ 931 imx219_get_binning(state, &bin_h, &bin_v); 932 llp_min = (bin_h & bin_v) == IMX219_BINNING_X2_ANALOG ? 933 IMX219_BINNED_LLP_MIN : IMX219_LLP_MIN; 934 ret = __v4l2_ctrl_modify_range(imx219->hblank, 935 llp_min - mode->width, 936 IMX219_LLP_MAX - mode->width, 1, 937 llp_min - mode->width); 938 if (ret) 939 return ret; 940 941 ret = __v4l2_ctrl_s_ctrl(imx219->hblank, llp_min - mode->width); 942 if (ret) 943 return ret; 944 945 /* Scale the pixel rate based on the mode specific factor */ 946 pixel_rate = imx219_get_pixel_rate(imx219) * 947 imx219_get_rate_factor(state); 948 ret = __v4l2_ctrl_modify_range(imx219->pixel_rate, pixel_rate, 949 pixel_rate, 1, pixel_rate); 950 if (ret) 951 return ret; 952 } 953 954 return 0; 955 } 956 957 static int imx219_get_selection(struct v4l2_subdev *sd, 958 struct v4l2_subdev_state *state, 959 struct v4l2_subdev_selection *sel) 960 { 961 switch (sel->target) { 962 case V4L2_SEL_TGT_CROP: 963 sel->r = *v4l2_subdev_state_get_crop(state, 0); 964 return 0; 965 966 case V4L2_SEL_TGT_NATIVE_SIZE: 967 sel->r.top = 0; 968 sel->r.left = 0; 969 sel->r.width = IMX219_NATIVE_WIDTH; 970 sel->r.height = IMX219_NATIVE_HEIGHT; 971 972 return 0; 973 974 case V4L2_SEL_TGT_CROP_DEFAULT: 975 case V4L2_SEL_TGT_CROP_BOUNDS: 976 sel->r.top = IMX219_ACTIVE_AREA_TOP; 977 sel->r.left = IMX219_ACTIVE_AREA_LEFT; 978 sel->r.width = IMX219_ACTIVE_AREA_WIDTH; 979 sel->r.height = IMX219_ACTIVE_AREA_HEIGHT; 980 981 return 0; 982 } 983 984 return -EINVAL; 985 } 986 987 static int imx219_init_state(struct v4l2_subdev *sd, 988 struct v4l2_subdev_state *state) 989 { 990 struct v4l2_subdev_format fmt = { 991 .which = V4L2_SUBDEV_FORMAT_TRY, 992 .pad = 0, 993 .format = { 994 .code = MEDIA_BUS_FMT_SRGGB10_1X10, 995 .width = supported_modes[0].width, 996 .height = supported_modes[0].height, 997 }, 998 }; 999 1000 return imx219_set_pad_format(sd, state, &fmt); 1001 } 1002 1003 static const struct v4l2_subdev_video_ops imx219_video_ops = { 1004 .s_stream = v4l2_subdev_s_stream_helper, 1005 }; 1006 1007 static const struct v4l2_subdev_pad_ops imx219_pad_ops = { 1008 .enum_mbus_code = imx219_enum_mbus_code, 1009 .get_fmt = v4l2_subdev_get_fmt, 1010 .set_fmt = imx219_set_pad_format, 1011 .get_selection = imx219_get_selection, 1012 .enum_frame_size = imx219_enum_frame_size, 1013 .enable_streams = imx219_enable_streams, 1014 .disable_streams = imx219_disable_streams, 1015 }; 1016 1017 static const struct v4l2_subdev_ops imx219_subdev_ops = { 1018 .video = &imx219_video_ops, 1019 .pad = &imx219_pad_ops, 1020 }; 1021 1022 static const struct v4l2_subdev_internal_ops imx219_internal_ops = { 1023 .init_state = imx219_init_state, 1024 }; 1025 1026 /* ----------------------------------------------------------------------------- 1027 * Power management 1028 */ 1029 1030 static int imx219_power_on(struct device *dev) 1031 { 1032 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1033 struct imx219 *imx219 = to_imx219(sd); 1034 int ret; 1035 1036 ret = regulator_bulk_enable(IMX219_NUM_SUPPLIES, 1037 imx219->supplies); 1038 if (ret) { 1039 dev_err(dev, "%s: failed to enable regulators\n", 1040 __func__); 1041 return ret; 1042 } 1043 1044 ret = clk_prepare_enable(imx219->xclk); 1045 if (ret) { 1046 dev_err(dev, "%s: failed to enable clock\n", 1047 __func__); 1048 goto reg_off; 1049 } 1050 1051 /* 1052 * Note: Misinterpretation of reset assertion - do not re-use this code. 1053 * XCLR pin is using incorrect (for reset signal) logical level. 1054 */ 1055 gpiod_set_value_cansleep(imx219->reset_gpio, 1); 1056 usleep_range(IMX219_XCLR_MIN_DELAY_US, 1057 IMX219_XCLR_MIN_DELAY_US + IMX219_XCLR_DELAY_RANGE_US); 1058 1059 return 0; 1060 1061 reg_off: 1062 regulator_bulk_disable(IMX219_NUM_SUPPLIES, imx219->supplies); 1063 1064 return ret; 1065 } 1066 1067 static int imx219_power_off(struct device *dev) 1068 { 1069 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1070 struct imx219 *imx219 = to_imx219(sd); 1071 1072 gpiod_set_value_cansleep(imx219->reset_gpio, 0); 1073 regulator_bulk_disable(IMX219_NUM_SUPPLIES, imx219->supplies); 1074 clk_disable_unprepare(imx219->xclk); 1075 1076 return 0; 1077 } 1078 1079 /* ----------------------------------------------------------------------------- 1080 * Probe & remove 1081 */ 1082 1083 static int imx219_get_regulators(struct imx219 *imx219) 1084 { 1085 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd); 1086 unsigned int i; 1087 1088 for (i = 0; i < IMX219_NUM_SUPPLIES; i++) 1089 imx219->supplies[i].supply = imx219_supply_name[i]; 1090 1091 return devm_regulator_bulk_get(&client->dev, 1092 IMX219_NUM_SUPPLIES, 1093 imx219->supplies); 1094 } 1095 1096 /* Verify chip ID */ 1097 static int imx219_identify_module(struct imx219 *imx219) 1098 { 1099 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd); 1100 int ret; 1101 u64 val; 1102 1103 ret = cci_read(imx219->regmap, IMX219_REG_CHIP_ID, &val, NULL); 1104 if (ret) 1105 return dev_err_probe(&client->dev, ret, 1106 "failed to read chip id %x\n", 1107 IMX219_CHIP_ID); 1108 1109 if (val != IMX219_CHIP_ID) 1110 return dev_err_probe(&client->dev, -EIO, 1111 "chip id mismatch: %x!=%llx\n", 1112 IMX219_CHIP_ID, val); 1113 1114 return 0; 1115 } 1116 1117 static int imx219_check_hwcfg(struct device *dev, struct imx219 *imx219) 1118 { 1119 struct fwnode_handle *endpoint; 1120 struct v4l2_fwnode_endpoint ep_cfg = { 1121 .bus_type = V4L2_MBUS_CSI2_DPHY 1122 }; 1123 unsigned long link_freq_bitmap; 1124 int ret = -EINVAL; 1125 1126 endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL); 1127 if (!endpoint) 1128 return dev_err_probe(dev, -EINVAL, "endpoint node not found\n"); 1129 1130 if (v4l2_fwnode_endpoint_alloc_parse(endpoint, &ep_cfg)) { 1131 dev_err_probe(dev, -EINVAL, "could not parse endpoint\n"); 1132 goto error_out; 1133 } 1134 1135 /* Check the number of MIPI CSI2 data lanes */ 1136 if (ep_cfg.bus.mipi_csi2.num_data_lanes != 2 && 1137 ep_cfg.bus.mipi_csi2.num_data_lanes != 4) { 1138 dev_err_probe(dev, -EINVAL, 1139 "only 2 or 4 data lanes are currently supported\n"); 1140 goto error_out; 1141 } 1142 imx219->lanes = ep_cfg.bus.mipi_csi2.num_data_lanes; 1143 1144 /* Check the link frequency set in device tree */ 1145 switch (imx219->lanes) { 1146 case 2: 1147 ret = v4l2_link_freq_to_bitmap(dev, 1148 ep_cfg.link_frequencies, 1149 ep_cfg.nr_of_link_frequencies, 1150 imx219_link_freq_menu, 1151 ARRAY_SIZE(imx219_link_freq_menu), 1152 &link_freq_bitmap); 1153 break; 1154 case 4: 1155 ret = v4l2_link_freq_to_bitmap(dev, 1156 ep_cfg.link_frequencies, 1157 ep_cfg.nr_of_link_frequencies, 1158 imx219_link_freq_4lane_menu, 1159 ARRAY_SIZE(imx219_link_freq_4lane_menu), 1160 &link_freq_bitmap); 1161 1162 if (!ret && (link_freq_bitmap & BIT(1))) { 1163 dev_warn(dev, "Link frequency of %d not supported, but has been incorrectly advertised previously\n", 1164 IMX219_DEFAULT_LINK_FREQ_4LANE_UNSUPPORTED); 1165 dev_warn(dev, "Using link frequency of %d\n", 1166 IMX219_DEFAULT_LINK_FREQ_4LANE); 1167 link_freq_bitmap |= BIT(0); 1168 } 1169 break; 1170 } 1171 1172 if (ret || !(link_freq_bitmap & BIT(0))) { 1173 ret = -EINVAL; 1174 dev_err_probe(dev, -EINVAL, 1175 "Link frequency not supported: %lld\n", 1176 ep_cfg.link_frequencies[0]); 1177 } 1178 1179 error_out: 1180 v4l2_fwnode_endpoint_free(&ep_cfg); 1181 fwnode_handle_put(endpoint); 1182 1183 return ret; 1184 } 1185 1186 static int imx219_probe(struct i2c_client *client) 1187 { 1188 struct device *dev = &client->dev; 1189 struct imx219 *imx219; 1190 int ret; 1191 1192 imx219 = devm_kzalloc(&client->dev, sizeof(*imx219), GFP_KERNEL); 1193 if (!imx219) 1194 return -ENOMEM; 1195 1196 v4l2_i2c_subdev_init(&imx219->sd, client, &imx219_subdev_ops); 1197 imx219->sd.internal_ops = &imx219_internal_ops; 1198 1199 /* Check the hardware configuration in device tree */ 1200 if (imx219_check_hwcfg(dev, imx219)) 1201 return -EINVAL; 1202 1203 imx219->regmap = devm_cci_regmap_init_i2c(client, 16); 1204 if (IS_ERR(imx219->regmap)) 1205 return dev_err_probe(dev, PTR_ERR(imx219->regmap), 1206 "failed to initialize CCI\n"); 1207 1208 /* Get system clock (xclk) */ 1209 imx219->xclk = devm_v4l2_sensor_clk_get(dev, NULL); 1210 if (IS_ERR(imx219->xclk)) 1211 return dev_err_probe(dev, PTR_ERR(imx219->xclk), 1212 "failed to get xclk\n"); 1213 1214 imx219->xclk_freq = clk_get_rate(imx219->xclk); 1215 if (imx219->xclk_freq != IMX219_XCLK_FREQ) 1216 return dev_err_probe(dev, -EINVAL, 1217 "xclk frequency not supported: %d Hz\n", 1218 imx219->xclk_freq); 1219 1220 ret = imx219_get_regulators(imx219); 1221 if (ret) 1222 return dev_err_probe(dev, ret, "failed to get regulators\n"); 1223 1224 /* Request optional enable pin */ 1225 imx219->reset_gpio = devm_gpiod_get_optional(dev, "reset", 1226 GPIOD_OUT_HIGH); 1227 if (IS_ERR(imx219->reset_gpio)) 1228 return dev_err_probe(dev, PTR_ERR(imx219->reset_gpio), 1229 "failed to get reset gpio\n"); 1230 1231 /* 1232 * The sensor must be powered for imx219_identify_module() 1233 * to be able to read the CHIP_ID register 1234 */ 1235 ret = imx219_power_on(dev); 1236 if (ret) 1237 return ret; 1238 1239 ret = imx219_identify_module(imx219); 1240 if (ret) 1241 goto error_power_off; 1242 1243 /* 1244 * Sensor doesn't enter LP-11 state upon power up until and unless 1245 * streaming is started, so upon power up switch the modes to: 1246 * streaming -> standby 1247 */ 1248 ret = cci_write(imx219->regmap, IMX219_REG_MODE_SELECT, 1249 IMX219_MODE_STREAMING, NULL); 1250 if (ret < 0) 1251 goto error_power_off; 1252 1253 usleep_range(100, 110); 1254 1255 /* put sensor back to standby mode */ 1256 ret = cci_write(imx219->regmap, IMX219_REG_MODE_SELECT, 1257 IMX219_MODE_STANDBY, NULL); 1258 if (ret < 0) 1259 goto error_power_off; 1260 1261 usleep_range(100, 110); 1262 1263 ret = imx219_init_controls(imx219); 1264 if (ret) 1265 goto error_power_off; 1266 1267 /* Initialize subdev */ 1268 imx219->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1269 imx219->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1270 1271 /* Initialize source pad */ 1272 imx219->pad.flags = MEDIA_PAD_FL_SOURCE; 1273 1274 ret = media_entity_pads_init(&imx219->sd.entity, 1, &imx219->pad); 1275 if (ret) { 1276 dev_err_probe(dev, ret, "failed to init entity pads\n"); 1277 goto error_handler_free; 1278 } 1279 1280 imx219->sd.state_lock = imx219->ctrl_handler.lock; 1281 ret = v4l2_subdev_init_finalize(&imx219->sd); 1282 if (ret < 0) { 1283 dev_err_probe(dev, ret, "subdev init error\n"); 1284 goto error_media_entity; 1285 } 1286 1287 pm_runtime_set_active(dev); 1288 pm_runtime_enable(dev); 1289 1290 ret = v4l2_async_register_subdev_sensor(&imx219->sd); 1291 if (ret < 0) { 1292 dev_err_probe(dev, ret, 1293 "failed to register sensor sub-device\n"); 1294 goto error_subdev_cleanup; 1295 } 1296 1297 pm_runtime_idle(dev); 1298 pm_runtime_set_autosuspend_delay(dev, 1000); 1299 pm_runtime_use_autosuspend(dev); 1300 1301 return 0; 1302 1303 error_subdev_cleanup: 1304 v4l2_subdev_cleanup(&imx219->sd); 1305 pm_runtime_disable(dev); 1306 pm_runtime_set_suspended(dev); 1307 1308 error_media_entity: 1309 media_entity_cleanup(&imx219->sd.entity); 1310 1311 error_handler_free: 1312 imx219_free_controls(imx219); 1313 1314 error_power_off: 1315 imx219_power_off(dev); 1316 1317 return ret; 1318 } 1319 1320 static void imx219_remove(struct i2c_client *client) 1321 { 1322 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1323 struct imx219 *imx219 = to_imx219(sd); 1324 1325 v4l2_async_unregister_subdev(sd); 1326 v4l2_subdev_cleanup(sd); 1327 media_entity_cleanup(&sd->entity); 1328 imx219_free_controls(imx219); 1329 1330 pm_runtime_disable(&client->dev); 1331 if (!pm_runtime_status_suspended(&client->dev)) { 1332 imx219_power_off(&client->dev); 1333 pm_runtime_set_suspended(&client->dev); 1334 } 1335 } 1336 1337 static const struct of_device_id imx219_dt_ids[] = { 1338 { .compatible = "sony,imx219" }, 1339 { /* sentinel */ } 1340 }; 1341 MODULE_DEVICE_TABLE(of, imx219_dt_ids); 1342 1343 static const struct dev_pm_ops imx219_pm_ops = { 1344 SET_RUNTIME_PM_OPS(imx219_power_off, imx219_power_on, NULL) 1345 }; 1346 1347 static struct i2c_driver imx219_i2c_driver = { 1348 .driver = { 1349 .name = "imx219", 1350 .of_match_table = imx219_dt_ids, 1351 .pm = &imx219_pm_ops, 1352 }, 1353 .probe = imx219_probe, 1354 .remove = imx219_remove, 1355 }; 1356 1357 module_i2c_driver(imx219_i2c_driver); 1358 1359 MODULE_AUTHOR("Dave Stevenson <dave.stevenson@raspberrypi.com"); 1360 MODULE_DESCRIPTION("Sony IMX219 sensor driver"); 1361 MODULE_LICENSE("GPL v2"); 1362