1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * A V4L2 driver for Sony IMX219 cameras. 4 * Copyright (C) 2019, Raspberry Pi (Trading) Ltd 5 * 6 * Based on Sony imx258 camera driver 7 * Copyright (C) 2018 Intel Corporation 8 * 9 * DT / fwnode changes, and regulator / GPIO control taken from imx214 driver 10 * Copyright 2018 Qtechnology A/S 11 * 12 * Flip handling taken from the Sony IMX319 driver. 13 * Copyright (C) 2018 Intel Corporation 14 * 15 */ 16 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/gpio/consumer.h> 20 #include <linux/i2c.h> 21 #include <linux/module.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/regulator/consumer.h> 24 #include <media/v4l2-ctrls.h> 25 #include <media/v4l2-device.h> 26 #include <media/v4l2-event.h> 27 #include <media/v4l2-fwnode.h> 28 #include <media/v4l2-mediabus.h> 29 #include <asm/unaligned.h> 30 31 #define IMX219_REG_VALUE_08BIT 1 32 #define IMX219_REG_VALUE_16BIT 2 33 34 #define IMX219_REG_MODE_SELECT 0x0100 35 #define IMX219_MODE_STANDBY 0x00 36 #define IMX219_MODE_STREAMING 0x01 37 38 /* Chip ID */ 39 #define IMX219_REG_CHIP_ID 0x0000 40 #define IMX219_CHIP_ID 0x0219 41 42 /* External clock frequency is 24.0M */ 43 #define IMX219_XCLK_FREQ 24000000 44 45 /* Pixel rate is fixed for all the modes */ 46 #define IMX219_PIXEL_RATE 182400000 47 #define IMX219_PIXEL_RATE_4LANE 280800000 48 49 #define IMX219_DEFAULT_LINK_FREQ 456000000 50 #define IMX219_DEFAULT_LINK_FREQ_4LANE 363000000 51 52 #define IMX219_REG_CSI_LANE_MODE 0x0114 53 #define IMX219_CSI_2_LANE_MODE 0x01 54 #define IMX219_CSI_4_LANE_MODE 0x03 55 56 /* V_TIMING internal */ 57 #define IMX219_REG_VTS 0x0160 58 #define IMX219_VTS_15FPS 0x0dc6 59 #define IMX219_VTS_30FPS_1080P 0x06e3 60 #define IMX219_VTS_30FPS_BINNED 0x06e3 61 #define IMX219_VTS_30FPS_640x480 0x06e3 62 #define IMX219_VTS_MAX 0xffff 63 64 #define IMX219_VBLANK_MIN 4 65 66 /*Frame Length Line*/ 67 #define IMX219_FLL_MIN 0x08a6 68 #define IMX219_FLL_MAX 0xffff 69 #define IMX219_FLL_STEP 1 70 #define IMX219_FLL_DEFAULT 0x0c98 71 72 /* HBLANK control - read only */ 73 #define IMX219_PPL_DEFAULT 3448 74 75 /* Exposure control */ 76 #define IMX219_REG_EXPOSURE 0x015a 77 #define IMX219_EXPOSURE_MIN 4 78 #define IMX219_EXPOSURE_STEP 1 79 #define IMX219_EXPOSURE_DEFAULT 0x640 80 #define IMX219_EXPOSURE_MAX 65535 81 82 /* Analog gain control */ 83 #define IMX219_REG_ANALOG_GAIN 0x0157 84 #define IMX219_ANA_GAIN_MIN 0 85 #define IMX219_ANA_GAIN_MAX 232 86 #define IMX219_ANA_GAIN_STEP 1 87 #define IMX219_ANA_GAIN_DEFAULT 0x0 88 89 /* Digital gain control */ 90 #define IMX219_REG_DIGITAL_GAIN 0x0158 91 #define IMX219_DGTL_GAIN_MIN 0x0100 92 #define IMX219_DGTL_GAIN_MAX 0x0fff 93 #define IMX219_DGTL_GAIN_DEFAULT 0x0100 94 #define IMX219_DGTL_GAIN_STEP 1 95 96 #define IMX219_REG_ORIENTATION 0x0172 97 98 /* Binning Mode */ 99 #define IMX219_REG_BINNING_MODE 0x0174 100 #define IMX219_BINNING_NONE 0x0000 101 #define IMX219_BINNING_2X2 0x0101 102 #define IMX219_BINNING_2X2_ANALOG 0x0303 103 104 /* Test Pattern Control */ 105 #define IMX219_REG_TEST_PATTERN 0x0600 106 #define IMX219_TEST_PATTERN_DISABLE 0 107 #define IMX219_TEST_PATTERN_SOLID_COLOR 1 108 #define IMX219_TEST_PATTERN_COLOR_BARS 2 109 #define IMX219_TEST_PATTERN_GREY_COLOR 3 110 #define IMX219_TEST_PATTERN_PN9 4 111 112 /* Test pattern colour components */ 113 #define IMX219_REG_TESTP_RED 0x0602 114 #define IMX219_REG_TESTP_GREENR 0x0604 115 #define IMX219_REG_TESTP_BLUE 0x0606 116 #define IMX219_REG_TESTP_GREENB 0x0608 117 #define IMX219_TESTP_COLOUR_MIN 0 118 #define IMX219_TESTP_COLOUR_MAX 0x03ff 119 #define IMX219_TESTP_COLOUR_STEP 1 120 #define IMX219_TESTP_RED_DEFAULT IMX219_TESTP_COLOUR_MAX 121 #define IMX219_TESTP_GREENR_DEFAULT 0 122 #define IMX219_TESTP_BLUE_DEFAULT 0 123 #define IMX219_TESTP_GREENB_DEFAULT 0 124 125 /* IMX219 native and active pixel array size. */ 126 #define IMX219_NATIVE_WIDTH 3296U 127 #define IMX219_NATIVE_HEIGHT 2480U 128 #define IMX219_PIXEL_ARRAY_LEFT 8U 129 #define IMX219_PIXEL_ARRAY_TOP 8U 130 #define IMX219_PIXEL_ARRAY_WIDTH 3280U 131 #define IMX219_PIXEL_ARRAY_HEIGHT 2464U 132 133 struct imx219_reg { 134 u16 address; 135 u8 val; 136 }; 137 138 struct imx219_reg_list { 139 unsigned int num_of_regs; 140 const struct imx219_reg *regs; 141 }; 142 143 /* Mode : resolution and related config&values */ 144 struct imx219_mode { 145 /* Frame width */ 146 unsigned int width; 147 /* Frame height */ 148 unsigned int height; 149 150 /* Analog crop rectangle. */ 151 struct v4l2_rect crop; 152 153 /* V-timing */ 154 unsigned int vts_def; 155 156 /* Default register values */ 157 struct imx219_reg_list reg_list; 158 159 /* 2x2 binning is used */ 160 bool binning; 161 }; 162 163 static const struct imx219_reg imx219_common_regs[] = { 164 {0x0100, 0x00}, /* Mode Select */ 165 166 /* To Access Addresses 3000-5fff, send the following commands */ 167 {0x30eb, 0x0c}, 168 {0x30eb, 0x05}, 169 {0x300a, 0xff}, 170 {0x300b, 0xff}, 171 {0x30eb, 0x05}, 172 {0x30eb, 0x09}, 173 174 /* PLL Clock Table */ 175 {0x0301, 0x05}, /* VTPXCK_DIV */ 176 {0x0303, 0x01}, /* VTSYSCK_DIV */ 177 {0x0304, 0x03}, /* PREPLLCK_VT_DIV 0x03 = AUTO set */ 178 {0x0305, 0x03}, /* PREPLLCK_OP_DIV 0x03 = AUTO set */ 179 {0x0306, 0x00}, /* PLL_VT_MPY */ 180 {0x0307, 0x39}, 181 {0x030b, 0x01}, /* OP_SYS_CLK_DIV */ 182 {0x030c, 0x00}, /* PLL_OP_MPY */ 183 {0x030d, 0x72}, 184 185 /* Undocumented registers */ 186 {0x455e, 0x00}, 187 {0x471e, 0x4b}, 188 {0x4767, 0x0f}, 189 {0x4750, 0x14}, 190 {0x4540, 0x00}, 191 {0x47b4, 0x14}, 192 {0x4713, 0x30}, 193 {0x478b, 0x10}, 194 {0x478f, 0x10}, 195 {0x4793, 0x10}, 196 {0x4797, 0x0e}, 197 {0x479b, 0x0e}, 198 199 /* Frame Bank Register Group "A" */ 200 {0x0162, 0x0d}, /* Line_Length_A */ 201 {0x0163, 0x78}, 202 {0x0170, 0x01}, /* X_ODD_INC_A */ 203 {0x0171, 0x01}, /* Y_ODD_INC_A */ 204 205 /* Output setup registers */ 206 {0x0114, 0x01}, /* CSI 2-Lane Mode */ 207 {0x0128, 0x00}, /* DPHY Auto Mode */ 208 {0x012a, 0x18}, /* EXCK_Freq */ 209 {0x012b, 0x00}, 210 }; 211 212 /* 213 * Register sets lifted off the i2C interface from the Raspberry Pi firmware 214 * driver. 215 * 3280x2464 = mode 2, 1920x1080 = mode 1, 1640x1232 = mode 4, 640x480 = mode 7. 216 */ 217 static const struct imx219_reg mode_3280x2464_regs[] = { 218 {0x0164, 0x00}, 219 {0x0165, 0x00}, 220 {0x0166, 0x0c}, 221 {0x0167, 0xcf}, 222 {0x0168, 0x00}, 223 {0x0169, 0x00}, 224 {0x016a, 0x09}, 225 {0x016b, 0x9f}, 226 {0x016c, 0x0c}, 227 {0x016d, 0xd0}, 228 {0x016e, 0x09}, 229 {0x016f, 0xa0}, 230 {0x0624, 0x0c}, 231 {0x0625, 0xd0}, 232 {0x0626, 0x09}, 233 {0x0627, 0xa0}, 234 }; 235 236 static const struct imx219_reg mode_1920_1080_regs[] = { 237 {0x0164, 0x02}, 238 {0x0165, 0xa8}, 239 {0x0166, 0x0a}, 240 {0x0167, 0x27}, 241 {0x0168, 0x02}, 242 {0x0169, 0xb4}, 243 {0x016a, 0x06}, 244 {0x016b, 0xeb}, 245 {0x016c, 0x07}, 246 {0x016d, 0x80}, 247 {0x016e, 0x04}, 248 {0x016f, 0x38}, 249 {0x0624, 0x07}, 250 {0x0625, 0x80}, 251 {0x0626, 0x04}, 252 {0x0627, 0x38}, 253 }; 254 255 static const struct imx219_reg mode_1640_1232_regs[] = { 256 {0x0164, 0x00}, 257 {0x0165, 0x00}, 258 {0x0166, 0x0c}, 259 {0x0167, 0xcf}, 260 {0x0168, 0x00}, 261 {0x0169, 0x00}, 262 {0x016a, 0x09}, 263 {0x016b, 0x9f}, 264 {0x016c, 0x06}, 265 {0x016d, 0x68}, 266 {0x016e, 0x04}, 267 {0x016f, 0xd0}, 268 {0x0624, 0x06}, 269 {0x0625, 0x68}, 270 {0x0626, 0x04}, 271 {0x0627, 0xd0}, 272 }; 273 274 static const struct imx219_reg mode_640_480_regs[] = { 275 {0x0164, 0x03}, 276 {0x0165, 0xe8}, 277 {0x0166, 0x08}, 278 {0x0167, 0xe7}, 279 {0x0168, 0x02}, 280 {0x0169, 0xf0}, 281 {0x016a, 0x06}, 282 {0x016b, 0xaf}, 283 {0x016c, 0x02}, 284 {0x016d, 0x80}, 285 {0x016e, 0x01}, 286 {0x016f, 0xe0}, 287 {0x0624, 0x06}, 288 {0x0625, 0x68}, 289 {0x0626, 0x04}, 290 {0x0627, 0xd0}, 291 }; 292 293 static const struct imx219_reg raw8_framefmt_regs[] = { 294 {0x018c, 0x08}, 295 {0x018d, 0x08}, 296 {0x0309, 0x08}, 297 }; 298 299 static const struct imx219_reg raw10_framefmt_regs[] = { 300 {0x018c, 0x0a}, 301 {0x018d, 0x0a}, 302 {0x0309, 0x0a}, 303 }; 304 305 static const s64 imx219_link_freq_menu[] = { 306 IMX219_DEFAULT_LINK_FREQ, 307 }; 308 309 static const s64 imx219_link_freq_4lane_menu[] = { 310 IMX219_DEFAULT_LINK_FREQ_4LANE, 311 }; 312 313 static const char * const imx219_test_pattern_menu[] = { 314 "Disabled", 315 "Color Bars", 316 "Solid Color", 317 "Grey Color Bars", 318 "PN9" 319 }; 320 321 static const int imx219_test_pattern_val[] = { 322 IMX219_TEST_PATTERN_DISABLE, 323 IMX219_TEST_PATTERN_COLOR_BARS, 324 IMX219_TEST_PATTERN_SOLID_COLOR, 325 IMX219_TEST_PATTERN_GREY_COLOR, 326 IMX219_TEST_PATTERN_PN9, 327 }; 328 329 /* regulator supplies */ 330 static const char * const imx219_supply_name[] = { 331 /* Supplies can be enabled in any order */ 332 "VANA", /* Analog (2.8V) supply */ 333 "VDIG", /* Digital Core (1.8V) supply */ 334 "VDDL", /* IF (1.2V) supply */ 335 }; 336 337 #define IMX219_NUM_SUPPLIES ARRAY_SIZE(imx219_supply_name) 338 339 /* 340 * The supported formats. 341 * This table MUST contain 4 entries per format, to cover the various flip 342 * combinations in the order 343 * - no flip 344 * - h flip 345 * - v flip 346 * - h&v flips 347 */ 348 static const u32 imx219_mbus_formats[] = { 349 MEDIA_BUS_FMT_SRGGB10_1X10, 350 MEDIA_BUS_FMT_SGRBG10_1X10, 351 MEDIA_BUS_FMT_SGBRG10_1X10, 352 MEDIA_BUS_FMT_SBGGR10_1X10, 353 354 MEDIA_BUS_FMT_SRGGB8_1X8, 355 MEDIA_BUS_FMT_SGRBG8_1X8, 356 MEDIA_BUS_FMT_SGBRG8_1X8, 357 MEDIA_BUS_FMT_SBGGR8_1X8, 358 }; 359 360 /* 361 * Initialisation delay between XCLR low->high and the moment when the sensor 362 * can start capture (i.e. can leave software stanby) must be not less than: 363 * t4 + max(t5, t6 + <time to initialize the sensor register over I2C>) 364 * where 365 * t4 is fixed, and is max 200uS, 366 * t5 is fixed, and is 6000uS, 367 * t6 depends on the sensor external clock, and is max 32000 clock periods. 368 * As per sensor datasheet, the external clock must be from 6MHz to 27MHz. 369 * So for any acceptable external clock t6 is always within the range of 370 * 1185 to 5333 uS, and is always less than t5. 371 * For this reason this is always safe to wait (t4 + t5) = 6200 uS, then 372 * initialize the sensor over I2C, and then exit the software standby. 373 * 374 * This start-up time can be optimized a bit more, if we start the writes 375 * over I2C after (t4+t6), but before (t4+t5) expires. But then sensor 376 * initialization over I2C may complete before (t4+t5) expires, and we must 377 * ensure that capture is not started before (t4+t5). 378 * 379 * This delay doesn't account for the power supply startup time. If needed, 380 * this should be taken care of via the regulator framework. E.g. in the 381 * case of DT for regulator-fixed one should define the startup-delay-us 382 * property. 383 */ 384 #define IMX219_XCLR_MIN_DELAY_US 6200 385 #define IMX219_XCLR_DELAY_RANGE_US 1000 386 387 /* Mode configs */ 388 static const struct imx219_mode supported_modes[] = { 389 { 390 /* 8MPix 15fps mode */ 391 .width = 3280, 392 .height = 2464, 393 .crop = { 394 .left = IMX219_PIXEL_ARRAY_LEFT, 395 .top = IMX219_PIXEL_ARRAY_TOP, 396 .width = 3280, 397 .height = 2464 398 }, 399 .vts_def = IMX219_VTS_15FPS, 400 .reg_list = { 401 .num_of_regs = ARRAY_SIZE(mode_3280x2464_regs), 402 .regs = mode_3280x2464_regs, 403 }, 404 .binning = false, 405 }, 406 { 407 /* 1080P 30fps cropped */ 408 .width = 1920, 409 .height = 1080, 410 .crop = { 411 .left = 688, 412 .top = 700, 413 .width = 1920, 414 .height = 1080 415 }, 416 .vts_def = IMX219_VTS_30FPS_1080P, 417 .reg_list = { 418 .num_of_regs = ARRAY_SIZE(mode_1920_1080_regs), 419 .regs = mode_1920_1080_regs, 420 }, 421 .binning = false, 422 }, 423 { 424 /* 2x2 binned 30fps mode */ 425 .width = 1640, 426 .height = 1232, 427 .crop = { 428 .left = IMX219_PIXEL_ARRAY_LEFT, 429 .top = IMX219_PIXEL_ARRAY_TOP, 430 .width = 3280, 431 .height = 2464 432 }, 433 .vts_def = IMX219_VTS_30FPS_BINNED, 434 .reg_list = { 435 .num_of_regs = ARRAY_SIZE(mode_1640_1232_regs), 436 .regs = mode_1640_1232_regs, 437 }, 438 .binning = true, 439 }, 440 { 441 /* 640x480 30fps mode */ 442 .width = 640, 443 .height = 480, 444 .crop = { 445 .left = 1008, 446 .top = 760, 447 .width = 1280, 448 .height = 960 449 }, 450 .vts_def = IMX219_VTS_30FPS_640x480, 451 .reg_list = { 452 .num_of_regs = ARRAY_SIZE(mode_640_480_regs), 453 .regs = mode_640_480_regs, 454 }, 455 .binning = true, 456 }, 457 }; 458 459 struct imx219 { 460 struct v4l2_subdev sd; 461 struct media_pad pad; 462 463 struct clk *xclk; /* system clock to IMX219 */ 464 u32 xclk_freq; 465 466 struct gpio_desc *reset_gpio; 467 struct regulator_bulk_data supplies[IMX219_NUM_SUPPLIES]; 468 469 struct v4l2_ctrl_handler ctrl_handler; 470 /* V4L2 Controls */ 471 struct v4l2_ctrl *pixel_rate; 472 struct v4l2_ctrl *link_freq; 473 struct v4l2_ctrl *exposure; 474 struct v4l2_ctrl *vflip; 475 struct v4l2_ctrl *hflip; 476 struct v4l2_ctrl *vblank; 477 struct v4l2_ctrl *hblank; 478 479 /* Current mode */ 480 const struct imx219_mode *mode; 481 482 /* Streaming on/off */ 483 bool streaming; 484 485 /* Two or Four lanes */ 486 u8 lanes; 487 }; 488 489 static inline struct imx219 *to_imx219(struct v4l2_subdev *_sd) 490 { 491 return container_of(_sd, struct imx219, sd); 492 } 493 494 /* Read registers up to 2 at a time */ 495 static int imx219_read_reg(struct imx219 *imx219, u16 reg, u32 len, u32 *val) 496 { 497 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd); 498 struct i2c_msg msgs[2]; 499 u8 addr_buf[2] = { reg >> 8, reg & 0xff }; 500 u8 data_buf[4] = { 0, }; 501 int ret; 502 503 if (len > 4) 504 return -EINVAL; 505 506 /* Write register address */ 507 msgs[0].addr = client->addr; 508 msgs[0].flags = 0; 509 msgs[0].len = ARRAY_SIZE(addr_buf); 510 msgs[0].buf = addr_buf; 511 512 /* Read data from register */ 513 msgs[1].addr = client->addr; 514 msgs[1].flags = I2C_M_RD; 515 msgs[1].len = len; 516 msgs[1].buf = &data_buf[4 - len]; 517 518 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); 519 if (ret != ARRAY_SIZE(msgs)) 520 return -EIO; 521 522 *val = get_unaligned_be32(data_buf); 523 524 return 0; 525 } 526 527 /* Write registers up to 2 at a time */ 528 static int imx219_write_reg(struct imx219 *imx219, u16 reg, u32 len, u32 val) 529 { 530 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd); 531 u8 buf[6]; 532 533 if (len > 4) 534 return -EINVAL; 535 536 put_unaligned_be16(reg, buf); 537 put_unaligned_be32(val << (8 * (4 - len)), buf + 2); 538 if (i2c_master_send(client, buf, len + 2) != len + 2) 539 return -EIO; 540 541 return 0; 542 } 543 544 /* Write a list of registers */ 545 static int imx219_write_regs(struct imx219 *imx219, 546 const struct imx219_reg *regs, u32 len) 547 { 548 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd); 549 unsigned int i; 550 int ret; 551 552 for (i = 0; i < len; i++) { 553 ret = imx219_write_reg(imx219, regs[i].address, 1, regs[i].val); 554 if (ret) { 555 dev_err_ratelimited(&client->dev, 556 "Failed to write reg 0x%4.4x. error = %d\n", 557 regs[i].address, ret); 558 559 return ret; 560 } 561 } 562 563 return 0; 564 } 565 566 /* Get bayer order based on flip setting. */ 567 static u32 imx219_get_format_code(struct imx219 *imx219, u32 code) 568 { 569 unsigned int i; 570 571 for (i = 0; i < ARRAY_SIZE(imx219_mbus_formats); i++) 572 if (imx219_mbus_formats[i] == code) 573 break; 574 575 if (i >= ARRAY_SIZE(imx219_mbus_formats)) 576 i = 0; 577 578 i = (i & ~3) | (imx219->vflip->val ? 2 : 0) | 579 (imx219->hflip->val ? 1 : 0); 580 581 return imx219_mbus_formats[i]; 582 } 583 584 static int imx219_set_ctrl(struct v4l2_ctrl *ctrl) 585 { 586 struct imx219 *imx219 = 587 container_of(ctrl->handler, struct imx219, ctrl_handler); 588 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd); 589 int ret; 590 591 if (ctrl->id == V4L2_CID_VBLANK) { 592 int exposure_max, exposure_def; 593 594 /* Update max exposure while meeting expected vblanking */ 595 exposure_max = imx219->mode->height + ctrl->val - 4; 596 exposure_def = (exposure_max < IMX219_EXPOSURE_DEFAULT) ? 597 exposure_max : IMX219_EXPOSURE_DEFAULT; 598 __v4l2_ctrl_modify_range(imx219->exposure, 599 imx219->exposure->minimum, 600 exposure_max, imx219->exposure->step, 601 exposure_def); 602 } 603 604 /* 605 * Applying V4L2 control value only happens 606 * when power is up for streaming 607 */ 608 if (pm_runtime_get_if_in_use(&client->dev) == 0) 609 return 0; 610 611 switch (ctrl->id) { 612 case V4L2_CID_ANALOGUE_GAIN: 613 ret = imx219_write_reg(imx219, IMX219_REG_ANALOG_GAIN, 614 IMX219_REG_VALUE_08BIT, ctrl->val); 615 break; 616 case V4L2_CID_EXPOSURE: 617 ret = imx219_write_reg(imx219, IMX219_REG_EXPOSURE, 618 IMX219_REG_VALUE_16BIT, ctrl->val); 619 break; 620 case V4L2_CID_DIGITAL_GAIN: 621 ret = imx219_write_reg(imx219, IMX219_REG_DIGITAL_GAIN, 622 IMX219_REG_VALUE_16BIT, ctrl->val); 623 break; 624 case V4L2_CID_TEST_PATTERN: 625 ret = imx219_write_reg(imx219, IMX219_REG_TEST_PATTERN, 626 IMX219_REG_VALUE_16BIT, 627 imx219_test_pattern_val[ctrl->val]); 628 break; 629 case V4L2_CID_HFLIP: 630 case V4L2_CID_VFLIP: 631 ret = imx219_write_reg(imx219, IMX219_REG_ORIENTATION, 1, 632 imx219->hflip->val | 633 imx219->vflip->val << 1); 634 break; 635 case V4L2_CID_VBLANK: 636 ret = imx219_write_reg(imx219, IMX219_REG_VTS, 637 IMX219_REG_VALUE_16BIT, 638 imx219->mode->height + ctrl->val); 639 break; 640 case V4L2_CID_TEST_PATTERN_RED: 641 ret = imx219_write_reg(imx219, IMX219_REG_TESTP_RED, 642 IMX219_REG_VALUE_16BIT, ctrl->val); 643 break; 644 case V4L2_CID_TEST_PATTERN_GREENR: 645 ret = imx219_write_reg(imx219, IMX219_REG_TESTP_GREENR, 646 IMX219_REG_VALUE_16BIT, ctrl->val); 647 break; 648 case V4L2_CID_TEST_PATTERN_BLUE: 649 ret = imx219_write_reg(imx219, IMX219_REG_TESTP_BLUE, 650 IMX219_REG_VALUE_16BIT, ctrl->val); 651 break; 652 case V4L2_CID_TEST_PATTERN_GREENB: 653 ret = imx219_write_reg(imx219, IMX219_REG_TESTP_GREENB, 654 IMX219_REG_VALUE_16BIT, ctrl->val); 655 break; 656 default: 657 dev_info(&client->dev, 658 "ctrl(id:0x%x,val:0x%x) is not handled\n", 659 ctrl->id, ctrl->val); 660 ret = -EINVAL; 661 break; 662 } 663 664 pm_runtime_put(&client->dev); 665 666 return ret; 667 } 668 669 static const struct v4l2_ctrl_ops imx219_ctrl_ops = { 670 .s_ctrl = imx219_set_ctrl, 671 }; 672 673 static void imx219_update_pad_format(struct imx219 *imx219, 674 const struct imx219_mode *mode, 675 struct v4l2_mbus_framefmt *fmt, u32 code) 676 { 677 /* Bayer order varies with flips */ 678 fmt->code = imx219_get_format_code(imx219, code); 679 fmt->width = mode->width; 680 fmt->height = mode->height; 681 fmt->field = V4L2_FIELD_NONE; 682 fmt->colorspace = V4L2_COLORSPACE_RAW; 683 fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE; 684 fmt->xfer_func = V4L2_XFER_FUNC_NONE; 685 } 686 687 static int imx219_init_cfg(struct v4l2_subdev *sd, 688 struct v4l2_subdev_state *state) 689 { 690 struct imx219 *imx219 = to_imx219(sd); 691 struct v4l2_mbus_framefmt *format; 692 struct v4l2_rect *crop; 693 694 /* Initialize try_fmt */ 695 format = v4l2_subdev_get_pad_format(sd, state, 0); 696 imx219_update_pad_format(imx219, &supported_modes[0], format, 697 MEDIA_BUS_FMT_SRGGB10_1X10); 698 699 /* Initialize crop rectangle. */ 700 crop = v4l2_subdev_get_pad_crop(sd, state, 0); 701 crop->top = IMX219_PIXEL_ARRAY_TOP; 702 crop->left = IMX219_PIXEL_ARRAY_LEFT; 703 crop->width = IMX219_PIXEL_ARRAY_WIDTH; 704 crop->height = IMX219_PIXEL_ARRAY_HEIGHT; 705 706 return 0; 707 } 708 709 static int imx219_enum_mbus_code(struct v4l2_subdev *sd, 710 struct v4l2_subdev_state *sd_state, 711 struct v4l2_subdev_mbus_code_enum *code) 712 { 713 struct imx219 *imx219 = to_imx219(sd); 714 715 if (code->index >= (ARRAY_SIZE(imx219_mbus_formats) / 4)) 716 return -EINVAL; 717 718 code->code = imx219_get_format_code(imx219, imx219_mbus_formats[code->index * 4]); 719 720 return 0; 721 } 722 723 static int imx219_enum_frame_size(struct v4l2_subdev *sd, 724 struct v4l2_subdev_state *sd_state, 725 struct v4l2_subdev_frame_size_enum *fse) 726 { 727 struct imx219 *imx219 = to_imx219(sd); 728 u32 code; 729 730 if (fse->index >= ARRAY_SIZE(supported_modes)) 731 return -EINVAL; 732 733 code = imx219_get_format_code(imx219, fse->code); 734 if (fse->code != code) 735 return -EINVAL; 736 737 fse->min_width = supported_modes[fse->index].width; 738 fse->max_width = fse->min_width; 739 fse->min_height = supported_modes[fse->index].height; 740 fse->max_height = fse->min_height; 741 742 return 0; 743 } 744 745 static int imx219_set_pad_format(struct v4l2_subdev *sd, 746 struct v4l2_subdev_state *sd_state, 747 struct v4l2_subdev_format *fmt) 748 { 749 struct imx219 *imx219 = to_imx219(sd); 750 const struct imx219_mode *mode; 751 int exposure_max, exposure_def, hblank; 752 struct v4l2_mbus_framefmt *format; 753 754 mode = v4l2_find_nearest_size(supported_modes, 755 ARRAY_SIZE(supported_modes), 756 width, height, 757 fmt->format.width, fmt->format.height); 758 759 imx219_update_pad_format(imx219, mode, &fmt->format, fmt->format.code); 760 format = v4l2_subdev_get_pad_format(sd, sd_state, 0); 761 762 if (imx219->mode == mode && format->code == fmt->format.code) 763 return 0; 764 765 if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 766 imx219->mode = mode; 767 /* Update limits and set FPS to default */ 768 __v4l2_ctrl_modify_range(imx219->vblank, IMX219_VBLANK_MIN, 769 IMX219_VTS_MAX - mode->height, 1, 770 mode->vts_def - mode->height); 771 __v4l2_ctrl_s_ctrl(imx219->vblank, 772 mode->vts_def - mode->height); 773 /* Update max exposure while meeting expected vblanking */ 774 exposure_max = mode->vts_def - 4; 775 exposure_def = (exposure_max < IMX219_EXPOSURE_DEFAULT) ? 776 exposure_max : IMX219_EXPOSURE_DEFAULT; 777 __v4l2_ctrl_modify_range(imx219->exposure, 778 imx219->exposure->minimum, 779 exposure_max, imx219->exposure->step, 780 exposure_def); 781 /* 782 * Currently PPL is fixed to IMX219_PPL_DEFAULT, so hblank 783 * depends on mode->width only, and is not changeble in any 784 * way other than changing the mode. 785 */ 786 hblank = IMX219_PPL_DEFAULT - mode->width; 787 __v4l2_ctrl_modify_range(imx219->hblank, hblank, hblank, 1, 788 hblank); 789 } 790 791 *format = fmt->format; 792 793 return 0; 794 } 795 796 static int imx219_set_framefmt(struct imx219 *imx219, 797 const struct v4l2_mbus_framefmt *format) 798 { 799 switch (format->code) { 800 case MEDIA_BUS_FMT_SRGGB8_1X8: 801 case MEDIA_BUS_FMT_SGRBG8_1X8: 802 case MEDIA_BUS_FMT_SGBRG8_1X8: 803 case MEDIA_BUS_FMT_SBGGR8_1X8: 804 return imx219_write_regs(imx219, raw8_framefmt_regs, 805 ARRAY_SIZE(raw8_framefmt_regs)); 806 807 case MEDIA_BUS_FMT_SRGGB10_1X10: 808 case MEDIA_BUS_FMT_SGRBG10_1X10: 809 case MEDIA_BUS_FMT_SGBRG10_1X10: 810 case MEDIA_BUS_FMT_SBGGR10_1X10: 811 return imx219_write_regs(imx219, raw10_framefmt_regs, 812 ARRAY_SIZE(raw10_framefmt_regs)); 813 } 814 815 return -EINVAL; 816 } 817 818 static int imx219_set_binning(struct imx219 *imx219, 819 const struct v4l2_mbus_framefmt *format) 820 { 821 if (!imx219->mode->binning) { 822 return imx219_write_reg(imx219, IMX219_REG_BINNING_MODE, 823 IMX219_REG_VALUE_16BIT, 824 IMX219_BINNING_NONE); 825 } 826 827 switch (format->code) { 828 case MEDIA_BUS_FMT_SRGGB8_1X8: 829 case MEDIA_BUS_FMT_SGRBG8_1X8: 830 case MEDIA_BUS_FMT_SGBRG8_1X8: 831 case MEDIA_BUS_FMT_SBGGR8_1X8: 832 return imx219_write_reg(imx219, IMX219_REG_BINNING_MODE, 833 IMX219_REG_VALUE_16BIT, 834 IMX219_BINNING_2X2_ANALOG); 835 836 case MEDIA_BUS_FMT_SRGGB10_1X10: 837 case MEDIA_BUS_FMT_SGRBG10_1X10: 838 case MEDIA_BUS_FMT_SGBRG10_1X10: 839 case MEDIA_BUS_FMT_SBGGR10_1X10: 840 return imx219_write_reg(imx219, IMX219_REG_BINNING_MODE, 841 IMX219_REG_VALUE_16BIT, 842 IMX219_BINNING_2X2); 843 } 844 845 return -EINVAL; 846 } 847 848 static int imx219_get_selection(struct v4l2_subdev *sd, 849 struct v4l2_subdev_state *sd_state, 850 struct v4l2_subdev_selection *sel) 851 { 852 switch (sel->target) { 853 case V4L2_SEL_TGT_CROP: { 854 sel->r = *v4l2_subdev_get_pad_crop(sd, sd_state, 0); 855 return 0; 856 } 857 858 case V4L2_SEL_TGT_NATIVE_SIZE: 859 sel->r.top = 0; 860 sel->r.left = 0; 861 sel->r.width = IMX219_NATIVE_WIDTH; 862 sel->r.height = IMX219_NATIVE_HEIGHT; 863 864 return 0; 865 866 case V4L2_SEL_TGT_CROP_DEFAULT: 867 case V4L2_SEL_TGT_CROP_BOUNDS: 868 sel->r.top = IMX219_PIXEL_ARRAY_TOP; 869 sel->r.left = IMX219_PIXEL_ARRAY_LEFT; 870 sel->r.width = IMX219_PIXEL_ARRAY_WIDTH; 871 sel->r.height = IMX219_PIXEL_ARRAY_HEIGHT; 872 873 return 0; 874 } 875 876 return -EINVAL; 877 } 878 879 static int imx219_configure_lanes(struct imx219 *imx219) 880 { 881 return imx219_write_reg(imx219, IMX219_REG_CSI_LANE_MODE, 882 IMX219_REG_VALUE_08BIT, (imx219->lanes == 2) ? 883 IMX219_CSI_2_LANE_MODE : IMX219_CSI_4_LANE_MODE); 884 }; 885 886 static int imx219_start_streaming(struct imx219 *imx219, 887 struct v4l2_subdev_state *state) 888 { 889 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd); 890 const struct v4l2_mbus_framefmt *format; 891 const struct imx219_reg_list *reg_list; 892 int ret; 893 894 ret = pm_runtime_resume_and_get(&client->dev); 895 if (ret < 0) 896 return ret; 897 898 /* Send all registers that are common to all modes */ 899 ret = imx219_write_regs(imx219, imx219_common_regs, ARRAY_SIZE(imx219_common_regs)); 900 if (ret) { 901 dev_err(&client->dev, "%s failed to send mfg header\n", __func__); 902 goto err_rpm_put; 903 } 904 905 /* Configure two or four Lane mode */ 906 ret = imx219_configure_lanes(imx219); 907 if (ret) { 908 dev_err(&client->dev, "%s failed to configure lanes\n", __func__); 909 goto err_rpm_put; 910 } 911 912 /* Apply default values of current mode */ 913 reg_list = &imx219->mode->reg_list; 914 ret = imx219_write_regs(imx219, reg_list->regs, reg_list->num_of_regs); 915 if (ret) { 916 dev_err(&client->dev, "%s failed to set mode\n", __func__); 917 goto err_rpm_put; 918 } 919 920 format = v4l2_subdev_get_pad_format(&imx219->sd, state, 0); 921 ret = imx219_set_framefmt(imx219, format); 922 if (ret) { 923 dev_err(&client->dev, "%s failed to set frame format: %d\n", 924 __func__, ret); 925 goto err_rpm_put; 926 } 927 928 ret = imx219_set_binning(imx219, format); 929 if (ret) { 930 dev_err(&client->dev, "%s failed to set binning: %d\n", 931 __func__, ret); 932 goto err_rpm_put; 933 } 934 935 /* Apply customized values from user */ 936 ret = __v4l2_ctrl_handler_setup(imx219->sd.ctrl_handler); 937 if (ret) 938 goto err_rpm_put; 939 940 /* set stream on register */ 941 ret = imx219_write_reg(imx219, IMX219_REG_MODE_SELECT, 942 IMX219_REG_VALUE_08BIT, IMX219_MODE_STREAMING); 943 if (ret) 944 goto err_rpm_put; 945 946 /* vflip and hflip cannot change during streaming */ 947 __v4l2_ctrl_grab(imx219->vflip, true); 948 __v4l2_ctrl_grab(imx219->hflip, true); 949 950 return 0; 951 952 err_rpm_put: 953 pm_runtime_put(&client->dev); 954 return ret; 955 } 956 957 static void imx219_stop_streaming(struct imx219 *imx219) 958 { 959 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd); 960 int ret; 961 962 /* set stream off register */ 963 ret = imx219_write_reg(imx219, IMX219_REG_MODE_SELECT, 964 IMX219_REG_VALUE_08BIT, IMX219_MODE_STANDBY); 965 if (ret) 966 dev_err(&client->dev, "%s failed to set stream\n", __func__); 967 968 __v4l2_ctrl_grab(imx219->vflip, false); 969 __v4l2_ctrl_grab(imx219->hflip, false); 970 971 pm_runtime_put(&client->dev); 972 } 973 974 static int imx219_set_stream(struct v4l2_subdev *sd, int enable) 975 { 976 struct imx219 *imx219 = to_imx219(sd); 977 struct v4l2_subdev_state *state; 978 int ret = 0; 979 980 state = v4l2_subdev_lock_and_get_active_state(sd); 981 982 if (imx219->streaming == enable) 983 goto unlock; 984 985 if (enable) { 986 /* 987 * Apply default & customized values 988 * and then start streaming. 989 */ 990 ret = imx219_start_streaming(imx219, state); 991 if (ret) 992 goto unlock; 993 } else { 994 imx219_stop_streaming(imx219); 995 } 996 997 imx219->streaming = enable; 998 999 unlock: 1000 v4l2_subdev_unlock_state(state); 1001 return ret; 1002 } 1003 1004 /* Power/clock management functions */ 1005 static int imx219_power_on(struct device *dev) 1006 { 1007 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1008 struct imx219 *imx219 = to_imx219(sd); 1009 int ret; 1010 1011 ret = regulator_bulk_enable(IMX219_NUM_SUPPLIES, 1012 imx219->supplies); 1013 if (ret) { 1014 dev_err(dev, "%s: failed to enable regulators\n", 1015 __func__); 1016 return ret; 1017 } 1018 1019 ret = clk_prepare_enable(imx219->xclk); 1020 if (ret) { 1021 dev_err(dev, "%s: failed to enable clock\n", 1022 __func__); 1023 goto reg_off; 1024 } 1025 1026 gpiod_set_value_cansleep(imx219->reset_gpio, 1); 1027 usleep_range(IMX219_XCLR_MIN_DELAY_US, 1028 IMX219_XCLR_MIN_DELAY_US + IMX219_XCLR_DELAY_RANGE_US); 1029 1030 return 0; 1031 1032 reg_off: 1033 regulator_bulk_disable(IMX219_NUM_SUPPLIES, imx219->supplies); 1034 1035 return ret; 1036 } 1037 1038 static int imx219_power_off(struct device *dev) 1039 { 1040 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1041 struct imx219 *imx219 = to_imx219(sd); 1042 1043 gpiod_set_value_cansleep(imx219->reset_gpio, 0); 1044 regulator_bulk_disable(IMX219_NUM_SUPPLIES, imx219->supplies); 1045 clk_disable_unprepare(imx219->xclk); 1046 1047 return 0; 1048 } 1049 1050 static int __maybe_unused imx219_suspend(struct device *dev) 1051 { 1052 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1053 struct imx219 *imx219 = to_imx219(sd); 1054 1055 if (imx219->streaming) 1056 imx219_stop_streaming(imx219); 1057 1058 return 0; 1059 } 1060 1061 static int __maybe_unused imx219_resume(struct device *dev) 1062 { 1063 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1064 struct imx219 *imx219 = to_imx219(sd); 1065 struct v4l2_subdev_state *state; 1066 int ret; 1067 1068 if (imx219->streaming) { 1069 state = v4l2_subdev_lock_and_get_active_state(sd); 1070 ret = imx219_start_streaming(imx219, state); 1071 v4l2_subdev_unlock_state(state); 1072 if (ret) 1073 goto error; 1074 } 1075 1076 return 0; 1077 1078 error: 1079 imx219_stop_streaming(imx219); 1080 imx219->streaming = false; 1081 1082 return ret; 1083 } 1084 1085 static int imx219_get_regulators(struct imx219 *imx219) 1086 { 1087 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd); 1088 unsigned int i; 1089 1090 for (i = 0; i < IMX219_NUM_SUPPLIES; i++) 1091 imx219->supplies[i].supply = imx219_supply_name[i]; 1092 1093 return devm_regulator_bulk_get(&client->dev, 1094 IMX219_NUM_SUPPLIES, 1095 imx219->supplies); 1096 } 1097 1098 /* Verify chip ID */ 1099 static int imx219_identify_module(struct imx219 *imx219) 1100 { 1101 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd); 1102 int ret; 1103 u32 val; 1104 1105 ret = imx219_read_reg(imx219, IMX219_REG_CHIP_ID, 1106 IMX219_REG_VALUE_16BIT, &val); 1107 if (ret) { 1108 dev_err(&client->dev, "failed to read chip id %x\n", 1109 IMX219_CHIP_ID); 1110 return ret; 1111 } 1112 1113 if (val != IMX219_CHIP_ID) { 1114 dev_err(&client->dev, "chip id mismatch: %x!=%x\n", 1115 IMX219_CHIP_ID, val); 1116 return -EIO; 1117 } 1118 1119 return 0; 1120 } 1121 1122 static const struct v4l2_subdev_core_ops imx219_core_ops = { 1123 .subscribe_event = v4l2_ctrl_subdev_subscribe_event, 1124 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 1125 }; 1126 1127 static const struct v4l2_subdev_video_ops imx219_video_ops = { 1128 .s_stream = imx219_set_stream, 1129 }; 1130 1131 static const struct v4l2_subdev_pad_ops imx219_pad_ops = { 1132 .init_cfg = imx219_init_cfg, 1133 .enum_mbus_code = imx219_enum_mbus_code, 1134 .get_fmt = v4l2_subdev_get_fmt, 1135 .set_fmt = imx219_set_pad_format, 1136 .get_selection = imx219_get_selection, 1137 .enum_frame_size = imx219_enum_frame_size, 1138 }; 1139 1140 static const struct v4l2_subdev_ops imx219_subdev_ops = { 1141 .core = &imx219_core_ops, 1142 .video = &imx219_video_ops, 1143 .pad = &imx219_pad_ops, 1144 }; 1145 1146 1147 static unsigned long imx219_get_pixel_rate(struct imx219 *imx219) 1148 { 1149 return (imx219->lanes == 2) ? IMX219_PIXEL_RATE : IMX219_PIXEL_RATE_4LANE; 1150 } 1151 1152 /* Initialize control handlers */ 1153 static int imx219_init_controls(struct imx219 *imx219) 1154 { 1155 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd); 1156 struct v4l2_ctrl_handler *ctrl_hdlr; 1157 unsigned int height = imx219->mode->height; 1158 struct v4l2_fwnode_device_properties props; 1159 int exposure_max, exposure_def, hblank; 1160 int i, ret; 1161 1162 ctrl_hdlr = &imx219->ctrl_handler; 1163 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 12); 1164 if (ret) 1165 return ret; 1166 1167 /* By default, PIXEL_RATE is read only */ 1168 imx219->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, 1169 V4L2_CID_PIXEL_RATE, 1170 imx219_get_pixel_rate(imx219), 1171 imx219_get_pixel_rate(imx219), 1, 1172 imx219_get_pixel_rate(imx219)); 1173 1174 imx219->link_freq = 1175 v4l2_ctrl_new_int_menu(ctrl_hdlr, &imx219_ctrl_ops, 1176 V4L2_CID_LINK_FREQ, 1177 ARRAY_SIZE(imx219_link_freq_menu) - 1, 0, 1178 (imx219->lanes == 2) ? imx219_link_freq_menu : 1179 imx219_link_freq_4lane_menu); 1180 if (imx219->link_freq) 1181 imx219->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1182 1183 /* Initial vblank/hblank/exposure parameters based on current mode */ 1184 imx219->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, 1185 V4L2_CID_VBLANK, IMX219_VBLANK_MIN, 1186 IMX219_VTS_MAX - height, 1, 1187 imx219->mode->vts_def - height); 1188 hblank = IMX219_PPL_DEFAULT - imx219->mode->width; 1189 imx219->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, 1190 V4L2_CID_HBLANK, hblank, hblank, 1191 1, hblank); 1192 if (imx219->hblank) 1193 imx219->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1194 exposure_max = imx219->mode->vts_def - 4; 1195 exposure_def = (exposure_max < IMX219_EXPOSURE_DEFAULT) ? 1196 exposure_max : IMX219_EXPOSURE_DEFAULT; 1197 imx219->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, 1198 V4L2_CID_EXPOSURE, 1199 IMX219_EXPOSURE_MIN, exposure_max, 1200 IMX219_EXPOSURE_STEP, 1201 exposure_def); 1202 1203 v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 1204 IMX219_ANA_GAIN_MIN, IMX219_ANA_GAIN_MAX, 1205 IMX219_ANA_GAIN_STEP, IMX219_ANA_GAIN_DEFAULT); 1206 1207 v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, V4L2_CID_DIGITAL_GAIN, 1208 IMX219_DGTL_GAIN_MIN, IMX219_DGTL_GAIN_MAX, 1209 IMX219_DGTL_GAIN_STEP, IMX219_DGTL_GAIN_DEFAULT); 1210 1211 imx219->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, 1212 V4L2_CID_HFLIP, 0, 1, 1, 0); 1213 if (imx219->hflip) 1214 imx219->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; 1215 1216 imx219->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, 1217 V4L2_CID_VFLIP, 0, 1, 1, 0); 1218 if (imx219->vflip) 1219 imx219->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; 1220 1221 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &imx219_ctrl_ops, 1222 V4L2_CID_TEST_PATTERN, 1223 ARRAY_SIZE(imx219_test_pattern_menu) - 1, 1224 0, 0, imx219_test_pattern_menu); 1225 for (i = 0; i < 4; i++) { 1226 /* 1227 * The assumption is that 1228 * V4L2_CID_TEST_PATTERN_GREENR == V4L2_CID_TEST_PATTERN_RED + 1 1229 * V4L2_CID_TEST_PATTERN_BLUE == V4L2_CID_TEST_PATTERN_RED + 2 1230 * V4L2_CID_TEST_PATTERN_GREENB == V4L2_CID_TEST_PATTERN_RED + 3 1231 */ 1232 v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, 1233 V4L2_CID_TEST_PATTERN_RED + i, 1234 IMX219_TESTP_COLOUR_MIN, 1235 IMX219_TESTP_COLOUR_MAX, 1236 IMX219_TESTP_COLOUR_STEP, 1237 IMX219_TESTP_COLOUR_MAX); 1238 /* The "Solid color" pattern is white by default */ 1239 } 1240 1241 if (ctrl_hdlr->error) { 1242 ret = ctrl_hdlr->error; 1243 dev_err(&client->dev, "%s control init failed (%d)\n", 1244 __func__, ret); 1245 goto error; 1246 } 1247 1248 ret = v4l2_fwnode_device_parse(&client->dev, &props); 1249 if (ret) 1250 goto error; 1251 1252 ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &imx219_ctrl_ops, 1253 &props); 1254 if (ret) 1255 goto error; 1256 1257 imx219->sd.ctrl_handler = ctrl_hdlr; 1258 1259 return 0; 1260 1261 error: 1262 v4l2_ctrl_handler_free(ctrl_hdlr); 1263 1264 return ret; 1265 } 1266 1267 static void imx219_free_controls(struct imx219 *imx219) 1268 { 1269 v4l2_ctrl_handler_free(imx219->sd.ctrl_handler); 1270 } 1271 1272 static int imx219_check_hwcfg(struct device *dev, struct imx219 *imx219) 1273 { 1274 struct fwnode_handle *endpoint; 1275 struct v4l2_fwnode_endpoint ep_cfg = { 1276 .bus_type = V4L2_MBUS_CSI2_DPHY 1277 }; 1278 int ret = -EINVAL; 1279 1280 endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL); 1281 if (!endpoint) { 1282 dev_err(dev, "endpoint node not found\n"); 1283 return -EINVAL; 1284 } 1285 1286 if (v4l2_fwnode_endpoint_alloc_parse(endpoint, &ep_cfg)) { 1287 dev_err(dev, "could not parse endpoint\n"); 1288 goto error_out; 1289 } 1290 1291 /* Check the number of MIPI CSI2 data lanes */ 1292 if (ep_cfg.bus.mipi_csi2.num_data_lanes != 2 && 1293 ep_cfg.bus.mipi_csi2.num_data_lanes != 4) { 1294 dev_err(dev, "only 2 or 4 data lanes are currently supported\n"); 1295 goto error_out; 1296 } 1297 imx219->lanes = ep_cfg.bus.mipi_csi2.num_data_lanes; 1298 1299 /* Check the link frequency set in device tree */ 1300 if (!ep_cfg.nr_of_link_frequencies) { 1301 dev_err(dev, "link-frequency property not found in DT\n"); 1302 goto error_out; 1303 } 1304 1305 if (ep_cfg.nr_of_link_frequencies != 1 || 1306 (ep_cfg.link_frequencies[0] != ((imx219->lanes == 2) ? 1307 IMX219_DEFAULT_LINK_FREQ : IMX219_DEFAULT_LINK_FREQ_4LANE))) { 1308 dev_err(dev, "Link frequency not supported: %lld\n", 1309 ep_cfg.link_frequencies[0]); 1310 goto error_out; 1311 } 1312 1313 ret = 0; 1314 1315 error_out: 1316 v4l2_fwnode_endpoint_free(&ep_cfg); 1317 fwnode_handle_put(endpoint); 1318 1319 return ret; 1320 } 1321 1322 static int imx219_probe(struct i2c_client *client) 1323 { 1324 struct device *dev = &client->dev; 1325 struct imx219 *imx219; 1326 int ret; 1327 1328 imx219 = devm_kzalloc(&client->dev, sizeof(*imx219), GFP_KERNEL); 1329 if (!imx219) 1330 return -ENOMEM; 1331 1332 v4l2_i2c_subdev_init(&imx219->sd, client, &imx219_subdev_ops); 1333 1334 /* Check the hardware configuration in device tree */ 1335 if (imx219_check_hwcfg(dev, imx219)) 1336 return -EINVAL; 1337 1338 /* Get system clock (xclk) */ 1339 imx219->xclk = devm_clk_get(dev, NULL); 1340 if (IS_ERR(imx219->xclk)) { 1341 dev_err(dev, "failed to get xclk\n"); 1342 return PTR_ERR(imx219->xclk); 1343 } 1344 1345 imx219->xclk_freq = clk_get_rate(imx219->xclk); 1346 if (imx219->xclk_freq != IMX219_XCLK_FREQ) { 1347 dev_err(dev, "xclk frequency not supported: %d Hz\n", 1348 imx219->xclk_freq); 1349 return -EINVAL; 1350 } 1351 1352 ret = imx219_get_regulators(imx219); 1353 if (ret) { 1354 dev_err(dev, "failed to get regulators\n"); 1355 return ret; 1356 } 1357 1358 /* Request optional enable pin */ 1359 imx219->reset_gpio = devm_gpiod_get_optional(dev, "reset", 1360 GPIOD_OUT_HIGH); 1361 1362 /* 1363 * The sensor must be powered for imx219_identify_module() 1364 * to be able to read the CHIP_ID register 1365 */ 1366 ret = imx219_power_on(dev); 1367 if (ret) 1368 return ret; 1369 1370 ret = imx219_identify_module(imx219); 1371 if (ret) 1372 goto error_power_off; 1373 1374 /* Set default mode to max resolution */ 1375 imx219->mode = &supported_modes[0]; 1376 1377 /* sensor doesn't enter LP-11 state upon power up until and unless 1378 * streaming is started, so upon power up switch the modes to: 1379 * streaming -> standby 1380 */ 1381 ret = imx219_write_reg(imx219, IMX219_REG_MODE_SELECT, 1382 IMX219_REG_VALUE_08BIT, IMX219_MODE_STREAMING); 1383 if (ret < 0) 1384 goto error_power_off; 1385 usleep_range(100, 110); 1386 1387 /* put sensor back to standby mode */ 1388 ret = imx219_write_reg(imx219, IMX219_REG_MODE_SELECT, 1389 IMX219_REG_VALUE_08BIT, IMX219_MODE_STANDBY); 1390 if (ret < 0) 1391 goto error_power_off; 1392 usleep_range(100, 110); 1393 1394 ret = imx219_init_controls(imx219); 1395 if (ret) 1396 goto error_power_off; 1397 1398 /* Initialize subdev */ 1399 imx219->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | 1400 V4L2_SUBDEV_FL_HAS_EVENTS; 1401 imx219->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1402 1403 /* Initialize source pad */ 1404 imx219->pad.flags = MEDIA_PAD_FL_SOURCE; 1405 1406 ret = media_entity_pads_init(&imx219->sd.entity, 1, &imx219->pad); 1407 if (ret) { 1408 dev_err(dev, "failed to init entity pads: %d\n", ret); 1409 goto error_handler_free; 1410 } 1411 1412 imx219->sd.state_lock = imx219->ctrl_handler.lock; 1413 ret = v4l2_subdev_init_finalize(&imx219->sd); 1414 if (ret < 0) { 1415 dev_err(dev, "subdev init error: %d\n", ret); 1416 goto error_media_entity; 1417 } 1418 1419 ret = v4l2_async_register_subdev_sensor(&imx219->sd); 1420 if (ret < 0) { 1421 dev_err(dev, "failed to register sensor sub-device: %d\n", ret); 1422 goto error_subdev_cleanup; 1423 } 1424 1425 /* Enable runtime PM and turn off the device */ 1426 pm_runtime_set_active(dev); 1427 pm_runtime_enable(dev); 1428 pm_runtime_idle(dev); 1429 1430 return 0; 1431 1432 error_subdev_cleanup: 1433 v4l2_subdev_cleanup(&imx219->sd); 1434 1435 error_media_entity: 1436 media_entity_cleanup(&imx219->sd.entity); 1437 1438 error_handler_free: 1439 imx219_free_controls(imx219); 1440 1441 error_power_off: 1442 imx219_power_off(dev); 1443 1444 return ret; 1445 } 1446 1447 static void imx219_remove(struct i2c_client *client) 1448 { 1449 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1450 struct imx219 *imx219 = to_imx219(sd); 1451 1452 v4l2_async_unregister_subdev(sd); 1453 v4l2_subdev_cleanup(sd); 1454 media_entity_cleanup(&sd->entity); 1455 imx219_free_controls(imx219); 1456 1457 pm_runtime_disable(&client->dev); 1458 if (!pm_runtime_status_suspended(&client->dev)) 1459 imx219_power_off(&client->dev); 1460 pm_runtime_set_suspended(&client->dev); 1461 } 1462 1463 static const struct of_device_id imx219_dt_ids[] = { 1464 { .compatible = "sony,imx219" }, 1465 { /* sentinel */ } 1466 }; 1467 MODULE_DEVICE_TABLE(of, imx219_dt_ids); 1468 1469 static const struct dev_pm_ops imx219_pm_ops = { 1470 SET_SYSTEM_SLEEP_PM_OPS(imx219_suspend, imx219_resume) 1471 SET_RUNTIME_PM_OPS(imx219_power_off, imx219_power_on, NULL) 1472 }; 1473 1474 static struct i2c_driver imx219_i2c_driver = { 1475 .driver = { 1476 .name = "imx219", 1477 .of_match_table = imx219_dt_ids, 1478 .pm = &imx219_pm_ops, 1479 }, 1480 .probe = imx219_probe, 1481 .remove = imx219_remove, 1482 }; 1483 1484 module_i2c_driver(imx219_i2c_driver); 1485 1486 MODULE_AUTHOR("Dave Stevenson <dave.stevenson@raspberrypi.com"); 1487 MODULE_DESCRIPTION("Sony IMX219 sensor driver"); 1488 MODULE_LICENSE("GPL v2"); 1489