1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * imx214.c - imx214 sensor driver 4 * 5 * Copyright 2018 Qtechnology A/S 6 * 7 * Ricardo Ribalda <ribalda@kernel.org> 8 */ 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/i2c.h> 13 #include <linux/module.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regmap.h> 16 #include <linux/regulator/consumer.h> 17 #include <media/media-entity.h> 18 #include <media/v4l2-cci.h> 19 #include <media/v4l2-ctrls.h> 20 #include <media/v4l2-fwnode.h> 21 #include <media/v4l2-subdev.h> 22 23 #include "ccs-pll.h" 24 25 /* Chip ID */ 26 #define IMX214_REG_CHIP_ID CCI_REG16(0x0016) 27 #define IMX214_CHIP_ID 0x0214 28 29 #define IMX214_REG_MODE_SELECT CCI_REG8(0x0100) 30 #define IMX214_MODE_STANDBY 0x00 31 #define IMX214_MODE_STREAMING 0x01 32 33 #define IMX214_REG_FAST_STANDBY_CTRL CCI_REG8(0x0106) 34 35 #define IMX214_DEFAULT_LINK_FREQ 600000000 36 /* Keep wrong link frequency for backward compatibility */ 37 #define IMX214_DEFAULT_LINK_FREQ_LEGACY 480000000 38 #define IMX214_FPS 30 39 40 /* V-TIMING internal */ 41 #define IMX214_REG_FRM_LENGTH_LINES CCI_REG16(0x0340) 42 #define IMX214_VTS_MAX 0xffff 43 44 #define IMX214_VBLANK_MIN 890 45 46 /* HBLANK control - read only */ 47 #define IMX214_PPL_DEFAULT 5008 48 49 /* Exposure control */ 50 #define IMX214_REG_EXPOSURE CCI_REG16(0x0202) 51 #define IMX214_EXPOSURE_OFFSET 10 52 #define IMX214_EXPOSURE_MIN 1 53 #define IMX214_EXPOSURE_STEP 1 54 #define IMX214_EXPOSURE_DEFAULT 3184 55 #define IMX214_REG_EXPOSURE_RATIO CCI_REG8(0x0222) 56 #define IMX214_REG_SHORT_EXPOSURE CCI_REG16(0x0224) 57 58 /* Analog gain control */ 59 #define IMX214_REG_ANALOG_GAIN CCI_REG16(0x0204) 60 #define IMX214_REG_SHORT_ANALOG_GAIN CCI_REG16(0x0216) 61 #define IMX214_ANA_GAIN_MIN 0 62 #define IMX214_ANA_GAIN_MAX 448 63 #define IMX214_ANA_GAIN_STEP 1 64 #define IMX214_ANA_GAIN_DEFAULT 0x0 65 66 /* Digital gain control */ 67 #define IMX214_REG_DIG_GAIN_GREENR CCI_REG16(0x020e) 68 #define IMX214_REG_DIG_GAIN_RED CCI_REG16(0x0210) 69 #define IMX214_REG_DIG_GAIN_BLUE CCI_REG16(0x0212) 70 #define IMX214_REG_DIG_GAIN_GREENB CCI_REG16(0x0214) 71 #define IMX214_DGTL_GAIN_MIN 0x0100 72 #define IMX214_DGTL_GAIN_MAX 0x0fff 73 #define IMX214_DGTL_GAIN_DEFAULT 0x0100 74 #define IMX214_DGTL_GAIN_STEP 1 75 76 #define IMX214_REG_ORIENTATION CCI_REG8(0x0101) 77 78 #define IMX214_REG_MASK_CORR_FRAMES CCI_REG8(0x0105) 79 #define IMX214_CORR_FRAMES_TRANSMIT 0 80 #define IMX214_CORR_FRAMES_MASK 1 81 82 #define IMX214_REG_CSI_DATA_FORMAT CCI_REG16(0x0112) 83 #define IMX214_CSI_DATA_FORMAT_RAW8 0x0808 84 #define IMX214_CSI_DATA_FORMAT_RAW10 0x0A0A 85 #define IMX214_CSI_DATA_FORMAT_COMP6 0x0A06 86 #define IMX214_CSI_DATA_FORMAT_COMP8 0x0A08 87 #define IMX214_BITS_PER_PIXEL_MASK 0xFF 88 89 #define IMX214_REG_CSI_LANE_MODE CCI_REG8(0x0114) 90 #define IMX214_CSI_2_LANE_MODE 1 91 #define IMX214_CSI_4_LANE_MODE 3 92 93 #define IMX214_REG_EXCK_FREQ CCI_REG16(0x0136) 94 #define IMX214_EXCK_FREQ(n) ((n) * 256) /* n expressed in MHz */ 95 96 #define IMX214_REG_TEMP_SENSOR_CONTROL CCI_REG8(0x0138) 97 98 #define IMX214_REG_HDR_MODE CCI_REG8(0x0220) 99 #define IMX214_HDR_MODE_OFF 0 100 #define IMX214_HDR_MODE_ON 1 101 102 #define IMX214_REG_HDR_RES_REDUCTION CCI_REG8(0x0221) 103 #define IMX214_HDR_RES_REDU_THROUGH 0x11 104 #define IMX214_HDR_RES_REDU_2_BINNING 0x22 105 106 /* PLL settings */ 107 #define IMX214_REG_VTPXCK_DIV CCI_REG8(0x0301) 108 #define IMX214_REG_VTSYCK_DIV CCI_REG8(0x0303) 109 #define IMX214_REG_PREPLLCK_VT_DIV CCI_REG8(0x0305) 110 #define IMX214_REG_PLL_VT_MPY CCI_REG16(0x0306) 111 #define IMX214_REG_OPPXCK_DIV CCI_REG8(0x0309) 112 #define IMX214_REG_OPSYCK_DIV CCI_REG8(0x030b) 113 #define IMX214_REG_PLL_MULT_DRIV CCI_REG8(0x0310) 114 #define IMX214_PLL_SINGLE 0 115 #define IMX214_PLL_DUAL 1 116 117 #define IMX214_REG_LINE_LENGTH_PCK CCI_REG16(0x0342) 118 #define IMX214_REG_X_ADD_STA CCI_REG16(0x0344) 119 #define IMX214_REG_Y_ADD_STA CCI_REG16(0x0346) 120 #define IMX214_REG_X_ADD_END CCI_REG16(0x0348) 121 #define IMX214_REG_Y_ADD_END CCI_REG16(0x034a) 122 #define IMX214_REG_X_OUTPUT_SIZE CCI_REG16(0x034c) 123 #define IMX214_REG_Y_OUTPUT_SIZE CCI_REG16(0x034e) 124 #define IMX214_REG_X_EVEN_INC CCI_REG8(0x0381) 125 #define IMX214_REG_X_ODD_INC CCI_REG8(0x0383) 126 #define IMX214_REG_Y_EVEN_INC CCI_REG8(0x0385) 127 #define IMX214_REG_Y_ODD_INC CCI_REG8(0x0387) 128 129 #define IMX214_REG_SCALE_MODE CCI_REG8(0x0401) 130 #define IMX214_SCALE_NONE 0 131 #define IMX214_SCALE_HORIZONTAL 1 132 #define IMX214_SCALE_FULL 2 133 #define IMX214_REG_SCALE_M CCI_REG16(0x0404) 134 135 #define IMX214_REG_DIG_CROP_X_OFFSET CCI_REG16(0x0408) 136 #define IMX214_REG_DIG_CROP_Y_OFFSET CCI_REG16(0x040a) 137 #define IMX214_REG_DIG_CROP_WIDTH CCI_REG16(0x040c) 138 #define IMX214_REG_DIG_CROP_HEIGHT CCI_REG16(0x040e) 139 140 #define IMX214_REG_REQ_LINK_BIT_RATE CCI_REG32(0x0820) 141 #define IMX214_LINK_BIT_RATE_MBPS(n) ((n) << 16) 142 143 /* Binning mode */ 144 #define IMX214_REG_BINNING_MODE CCI_REG8(0x0900) 145 #define IMX214_BINNING_NONE 0 146 #define IMX214_BINNING_ENABLE 1 147 #define IMX214_REG_BINNING_TYPE CCI_REG8(0x0901) 148 #define IMX214_REG_BINNING_WEIGHTING CCI_REG8(0x0902) 149 #define IMX214_BINNING_AVERAGE 0x00 150 #define IMX214_BINNING_SUMMED 0x01 151 #define IMX214_BINNING_BAYER 0x02 152 153 #define IMX214_REG_SING_DEF_CORR_EN CCI_REG8(0x0b06) 154 #define IMX214_SING_DEF_CORR_OFF 0 155 #define IMX214_SING_DEF_CORR_ON 1 156 157 /* AWB control */ 158 #define IMX214_REG_ABS_GAIN_GREENR CCI_REG16(0x0b8e) 159 #define IMX214_REG_ABS_GAIN_RED CCI_REG16(0x0b90) 160 #define IMX214_REG_ABS_GAIN_BLUE CCI_REG16(0x0b92) 161 #define IMX214_REG_ABS_GAIN_GREENB CCI_REG16(0x0b94) 162 163 #define IMX214_REG_RMSC_NR_MODE CCI_REG8(0x3001) 164 #define IMX214_REG_STATS_OUT_EN CCI_REG8(0x3013) 165 #define IMX214_STATS_OUT_OFF 0 166 #define IMX214_STATS_OUT_ON 1 167 168 /* Chroma noise reduction */ 169 #define IMX214_REG_NML_NR_EN CCI_REG8(0x30a2) 170 #define IMX214_NML_NR_OFF 0 171 #define IMX214_NML_NR_ON 1 172 173 #define IMX214_REG_EBD_SIZE_V CCI_REG8(0x5041) 174 #define IMX214_EBD_NO 0 175 #define IMX214_EBD_4_LINE 4 176 177 #define IMX214_REG_RG_STATS_LMT CCI_REG16(0x6d12) 178 #define IMX214_RG_STATS_LMT_10_BIT 0x03FF 179 #define IMX214_RG_STATS_LMT_14_BIT 0x3FFF 180 181 #define IMX214_REG_ATR_FAST_MOVE CCI_REG8(0x9300) 182 183 /* Test Pattern Control */ 184 #define IMX214_REG_TEST_PATTERN CCI_REG16(0x0600) 185 #define IMX214_TEST_PATTERN_DISABLE 0 186 #define IMX214_TEST_PATTERN_SOLID_COLOR 1 187 #define IMX214_TEST_PATTERN_COLOR_BARS 2 188 #define IMX214_TEST_PATTERN_GREY_COLOR 3 189 #define IMX214_TEST_PATTERN_PN9 4 190 191 /* Test pattern colour components */ 192 #define IMX214_REG_TESTP_RED CCI_REG16(0x0602) 193 #define IMX214_REG_TESTP_GREENR CCI_REG16(0x0604) 194 #define IMX214_REG_TESTP_BLUE CCI_REG16(0x0606) 195 #define IMX214_REG_TESTP_GREENB CCI_REG16(0x0608) 196 #define IMX214_TESTP_COLOUR_MIN 0 197 #define IMX214_TESTP_COLOUR_MAX 0x03ff 198 #define IMX214_TESTP_COLOUR_STEP 1 199 200 /* IMX214 native and active pixel array size */ 201 #define IMX214_NATIVE_WIDTH 4224U 202 #define IMX214_NATIVE_HEIGHT 3136U 203 #define IMX214_PIXEL_ARRAY_LEFT 8U 204 #define IMX214_PIXEL_ARRAY_TOP 8U 205 #define IMX214_PIXEL_ARRAY_WIDTH 4208U 206 #define IMX214_PIXEL_ARRAY_HEIGHT 3120U 207 208 static const char * const imx214_supply_name[] = { 209 "vdda", 210 "vddd", 211 "vdddo", 212 }; 213 214 #define IMX214_NUM_SUPPLIES ARRAY_SIZE(imx214_supply_name) 215 216 /* 217 * The supported formats. 218 * This table MUST contain 4 entries per format, to cover the various flip 219 * combinations in the order 220 * - no flip 221 * - h flip 222 * - v flip 223 * - h&v flips 224 */ 225 static const u32 imx214_mbus_formats[] = { 226 MEDIA_BUS_FMT_SRGGB10_1X10, 227 MEDIA_BUS_FMT_SGRBG10_1X10, 228 MEDIA_BUS_FMT_SGBRG10_1X10, 229 MEDIA_BUS_FMT_SBGGR10_1X10, 230 }; 231 232 static const char * const imx214_test_pattern_menu[] = { 233 "Disabled", 234 "Color Bars", 235 "Solid Color", 236 "Grey Color Bars", 237 "PN9" 238 }; 239 240 static const int imx214_test_pattern_val[] = { 241 IMX214_TEST_PATTERN_DISABLE, 242 IMX214_TEST_PATTERN_COLOR_BARS, 243 IMX214_TEST_PATTERN_SOLID_COLOR, 244 IMX214_TEST_PATTERN_GREY_COLOR, 245 IMX214_TEST_PATTERN_PN9, 246 }; 247 248 struct imx214 { 249 struct device *dev; 250 struct clk *xclk; 251 struct regmap *regmap; 252 253 struct ccs_pll pll; 254 255 struct v4l2_fwnode_endpoint bus_cfg; 256 257 struct v4l2_subdev sd; 258 struct media_pad pad; 259 260 struct v4l2_ctrl_handler ctrls; 261 struct v4l2_ctrl *pixel_rate; 262 struct v4l2_ctrl *link_freq; 263 struct v4l2_ctrl *vblank; 264 struct v4l2_ctrl *hblank; 265 struct v4l2_ctrl *exposure; 266 struct v4l2_ctrl *unit_size; 267 struct { 268 struct v4l2_ctrl *hflip; 269 struct v4l2_ctrl *vflip; 270 }; 271 272 struct regulator_bulk_data supplies[IMX214_NUM_SUPPLIES]; 273 274 struct gpio_desc *enable_gpio; 275 }; 276 277 /*From imx214_mode_tbls.h*/ 278 static const struct cci_reg_sequence mode_4096x2304[] = { 279 { IMX214_REG_HDR_MODE, IMX214_HDR_MODE_OFF }, 280 { IMX214_REG_HDR_RES_REDUCTION, IMX214_HDR_RES_REDU_THROUGH }, 281 { IMX214_REG_EXPOSURE_RATIO, 1 }, 282 { IMX214_REG_X_ADD_STA, 56 }, 283 { IMX214_REG_Y_ADD_STA, 408 }, 284 { IMX214_REG_X_ADD_END, 4151 }, 285 { IMX214_REG_Y_ADD_END, 2711 }, 286 { IMX214_REG_X_EVEN_INC, 1 }, 287 { IMX214_REG_X_ODD_INC, 1 }, 288 { IMX214_REG_Y_EVEN_INC, 1 }, 289 { IMX214_REG_Y_ODD_INC, 1 }, 290 { IMX214_REG_BINNING_MODE, IMX214_BINNING_NONE }, 291 { IMX214_REG_BINNING_TYPE, 0 }, 292 { IMX214_REG_BINNING_WEIGHTING, IMX214_BINNING_AVERAGE }, 293 { CCI_REG8(0x3000), 0x35 }, 294 { CCI_REG8(0x3054), 0x01 }, 295 { CCI_REG8(0x305C), 0x11 }, 296 297 { IMX214_REG_CSI_DATA_FORMAT, IMX214_CSI_DATA_FORMAT_RAW10 }, 298 { IMX214_REG_X_OUTPUT_SIZE, 4096 }, 299 { IMX214_REG_Y_OUTPUT_SIZE, 2304 }, 300 { IMX214_REG_SCALE_MODE, IMX214_SCALE_NONE }, 301 { IMX214_REG_SCALE_M, 2 }, 302 { IMX214_REG_DIG_CROP_X_OFFSET, 0 }, 303 { IMX214_REG_DIG_CROP_Y_OFFSET, 0 }, 304 { IMX214_REG_DIG_CROP_WIDTH, 4096 }, 305 { IMX214_REG_DIG_CROP_HEIGHT, 2304 }, 306 307 { CCI_REG8(0x3A03), 0x09 }, 308 { CCI_REG8(0x3A04), 0x50 }, 309 { CCI_REG8(0x3A05), 0x01 }, 310 311 { IMX214_REG_SING_DEF_CORR_EN, IMX214_SING_DEF_CORR_ON }, 312 { IMX214_REG_NML_NR_EN, IMX214_NML_NR_OFF }, 313 314 { CCI_REG8(0x30B4), 0x00 }, 315 316 { CCI_REG8(0x3A02), 0xFF }, 317 318 { CCI_REG8(0x3011), 0x00 }, 319 { IMX214_REG_STATS_OUT_EN, IMX214_STATS_OUT_ON }, 320 321 { IMX214_REG_SHORT_EXPOSURE, 500 }, 322 323 { CCI_REG8(0x4170), 0x00 }, 324 { CCI_REG8(0x4171), 0x10 }, 325 { CCI_REG8(0x4176), 0x00 }, 326 { CCI_REG8(0x4177), 0x3C }, 327 { CCI_REG8(0xAE20), 0x04 }, 328 { CCI_REG8(0xAE21), 0x5C }, 329 }; 330 331 static const struct cci_reg_sequence mode_1920x1080[] = { 332 { IMX214_REG_HDR_MODE, IMX214_HDR_MODE_OFF }, 333 { IMX214_REG_HDR_RES_REDUCTION, IMX214_HDR_RES_REDU_THROUGH }, 334 { IMX214_REG_EXPOSURE_RATIO, 1 }, 335 { IMX214_REG_X_ADD_STA, 1144 }, 336 { IMX214_REG_Y_ADD_STA, 1020 }, 337 { IMX214_REG_X_ADD_END, 3063 }, 338 { IMX214_REG_Y_ADD_END, 2099 }, 339 { IMX214_REG_X_EVEN_INC, 1 }, 340 { IMX214_REG_X_ODD_INC, 1 }, 341 { IMX214_REG_Y_EVEN_INC, 1 }, 342 { IMX214_REG_Y_ODD_INC, 1 }, 343 { IMX214_REG_BINNING_MODE, IMX214_BINNING_NONE }, 344 { IMX214_REG_BINNING_TYPE, 0 }, 345 { IMX214_REG_BINNING_WEIGHTING, IMX214_BINNING_AVERAGE }, 346 { CCI_REG8(0x3000), 0x35 }, 347 { CCI_REG8(0x3054), 0x01 }, 348 { CCI_REG8(0x305C), 0x11 }, 349 350 { IMX214_REG_CSI_DATA_FORMAT, IMX214_CSI_DATA_FORMAT_RAW10 }, 351 { IMX214_REG_X_OUTPUT_SIZE, 1920 }, 352 { IMX214_REG_Y_OUTPUT_SIZE, 1080 }, 353 { IMX214_REG_SCALE_MODE, IMX214_SCALE_NONE }, 354 { IMX214_REG_SCALE_M, 2 }, 355 { IMX214_REG_DIG_CROP_X_OFFSET, 0 }, 356 { IMX214_REG_DIG_CROP_Y_OFFSET, 0 }, 357 { IMX214_REG_DIG_CROP_WIDTH, 1920 }, 358 { IMX214_REG_DIG_CROP_HEIGHT, 1080 }, 359 360 { CCI_REG8(0x3A03), 0x04 }, 361 { CCI_REG8(0x3A04), 0xF8 }, 362 { CCI_REG8(0x3A05), 0x02 }, 363 364 { IMX214_REG_SING_DEF_CORR_EN, IMX214_SING_DEF_CORR_ON }, 365 { IMX214_REG_NML_NR_EN, IMX214_NML_NR_OFF }, 366 367 { CCI_REG8(0x30B4), 0x00 }, 368 369 { CCI_REG8(0x3A02), 0xFF }, 370 371 { CCI_REG8(0x3011), 0x00 }, 372 { IMX214_REG_STATS_OUT_EN, IMX214_STATS_OUT_ON }, 373 374 { IMX214_REG_SHORT_EXPOSURE, 500 }, 375 376 { CCI_REG8(0x4170), 0x00 }, 377 { CCI_REG8(0x4171), 0x10 }, 378 { CCI_REG8(0x4176), 0x00 }, 379 { CCI_REG8(0x4177), 0x3C }, 380 { CCI_REG8(0xAE20), 0x04 }, 381 { CCI_REG8(0xAE21), 0x5C }, 382 }; 383 384 static const struct cci_reg_sequence mode_table_common[] = { 385 /* software reset */ 386 387 /* software standby settings */ 388 { IMX214_REG_MODE_SELECT, IMX214_MODE_STANDBY }, 389 390 /* ATR setting */ 391 { IMX214_REG_ATR_FAST_MOVE, 2 }, 392 393 /* global setting */ 394 /* basic config */ 395 { IMX214_REG_MASK_CORR_FRAMES, IMX214_CORR_FRAMES_MASK }, 396 { IMX214_REG_FAST_STANDBY_CTRL, 1 }, 397 { IMX214_REG_LINE_LENGTH_PCK, IMX214_PPL_DEFAULT }, 398 { CCI_REG8(0x4550), 0x02 }, 399 { CCI_REG8(0x4601), 0x00 }, 400 { CCI_REG8(0x4642), 0x05 }, 401 { CCI_REG8(0x6227), 0x11 }, 402 { CCI_REG8(0x6276), 0x00 }, 403 { CCI_REG8(0x900E), 0x06 }, 404 { CCI_REG8(0xA802), 0x90 }, 405 { CCI_REG8(0xA803), 0x11 }, 406 { CCI_REG8(0xA804), 0x62 }, 407 { CCI_REG8(0xA805), 0x77 }, 408 { CCI_REG8(0xA806), 0xAE }, 409 { CCI_REG8(0xA807), 0x34 }, 410 { CCI_REG8(0xA808), 0xAE }, 411 { CCI_REG8(0xA809), 0x35 }, 412 { CCI_REG8(0xA80A), 0x62 }, 413 { CCI_REG8(0xA80B), 0x83 }, 414 { CCI_REG8(0xAE33), 0x00 }, 415 416 /* analog setting */ 417 { CCI_REG8(0x4174), 0x00 }, 418 { CCI_REG8(0x4175), 0x11 }, 419 { CCI_REG8(0x4612), 0x29 }, 420 { CCI_REG8(0x461B), 0x12 }, 421 { CCI_REG8(0x461F), 0x06 }, 422 { CCI_REG8(0x4635), 0x07 }, 423 { CCI_REG8(0x4637), 0x30 }, 424 { CCI_REG8(0x463F), 0x18 }, 425 { CCI_REG8(0x4641), 0x0D }, 426 { CCI_REG8(0x465B), 0x12 }, 427 { CCI_REG8(0x465F), 0x11 }, 428 { CCI_REG8(0x4663), 0x11 }, 429 { CCI_REG8(0x4667), 0x0F }, 430 { CCI_REG8(0x466F), 0x0F }, 431 { CCI_REG8(0x470E), 0x09 }, 432 { CCI_REG8(0x4909), 0xAB }, 433 { CCI_REG8(0x490B), 0x95 }, 434 { CCI_REG8(0x4915), 0x5D }, 435 { CCI_REG8(0x4A5F), 0xFF }, 436 { CCI_REG8(0x4A61), 0xFF }, 437 { CCI_REG8(0x4A73), 0x62 }, 438 { CCI_REG8(0x4A85), 0x00 }, 439 { CCI_REG8(0x4A87), 0xFF }, 440 441 /* embedded data */ 442 { IMX214_REG_EBD_SIZE_V, IMX214_EBD_4_LINE }, 443 { CCI_REG8(0x583C), 0x04 }, 444 { CCI_REG8(0x620E), 0x04 }, 445 { CCI_REG8(0x6EB2), 0x01 }, 446 { CCI_REG8(0x6EB3), 0x00 }, 447 { IMX214_REG_ATR_FAST_MOVE, 2 }, 448 449 /* imagequality */ 450 /* HDR setting */ 451 { IMX214_REG_RMSC_NR_MODE, 0x07 }, 452 { IMX214_REG_RG_STATS_LMT, IMX214_RG_STATS_LMT_14_BIT }, 453 { CCI_REG8(0x9344), 0x03 }, 454 { CCI_REG8(0x9706), 0x10 }, 455 { CCI_REG8(0x9707), 0x03 }, 456 { CCI_REG8(0x9708), 0x03 }, 457 { CCI_REG8(0x9E04), 0x01 }, 458 { CCI_REG8(0x9E05), 0x00 }, 459 { CCI_REG8(0x9E0C), 0x01 }, 460 { CCI_REG8(0x9E0D), 0x02 }, 461 { CCI_REG8(0x9E24), 0x00 }, 462 { CCI_REG8(0x9E25), 0x8C }, 463 { CCI_REG8(0x9E26), 0x00 }, 464 { CCI_REG8(0x9E27), 0x94 }, 465 { CCI_REG8(0x9E28), 0x00 }, 466 { CCI_REG8(0x9E29), 0x96 }, 467 468 /* CNR parameter setting */ 469 { CCI_REG8(0x69DB), 0x01 }, 470 471 /* Moire reduction */ 472 { CCI_REG8(0x6957), 0x01 }, 473 474 /* image enhancement */ 475 { CCI_REG8(0x6987), 0x17 }, 476 { CCI_REG8(0x698A), 0x03 }, 477 { CCI_REG8(0x698B), 0x03 }, 478 479 /* white balanace */ 480 { IMX214_REG_ABS_GAIN_GREENR, 0x0100 }, 481 { IMX214_REG_ABS_GAIN_RED, 0x0100 }, 482 { IMX214_REG_ABS_GAIN_BLUE, 0x0100 }, 483 { IMX214_REG_ABS_GAIN_GREENB, 0x0100 }, 484 485 /* ATR setting */ 486 { CCI_REG8(0x6E50), 0x00 }, 487 { CCI_REG8(0x6E51), 0x32 }, 488 { CCI_REG8(0x9340), 0x00 }, 489 { CCI_REG8(0x9341), 0x3C }, 490 { CCI_REG8(0x9342), 0x03 }, 491 { CCI_REG8(0x9343), 0xFF }, 492 }; 493 494 /* 495 * Declare modes in order, from biggest 496 * to smallest height. 497 */ 498 static const struct imx214_mode { 499 u32 width; 500 u32 height; 501 502 /* V-timing */ 503 unsigned int vts_def; 504 505 unsigned int num_of_regs; 506 const struct cci_reg_sequence *reg_table; 507 } imx214_modes[] = { 508 { 509 .width = 4096, 510 .height = 2304, 511 .vts_def = 3194, 512 .num_of_regs = ARRAY_SIZE(mode_4096x2304), 513 .reg_table = mode_4096x2304, 514 }, 515 { 516 .width = 1920, 517 .height = 1080, 518 .vts_def = 3194, 519 .num_of_regs = ARRAY_SIZE(mode_1920x1080), 520 .reg_table = mode_1920x1080, 521 }, 522 }; 523 524 static inline struct imx214 *to_imx214(struct v4l2_subdev *sd) 525 { 526 return container_of(sd, struct imx214, sd); 527 } 528 529 static int __maybe_unused imx214_power_on(struct device *dev) 530 { 531 struct i2c_client *client = to_i2c_client(dev); 532 struct v4l2_subdev *sd = i2c_get_clientdata(client); 533 struct imx214 *imx214 = to_imx214(sd); 534 int ret; 535 536 ret = regulator_bulk_enable(IMX214_NUM_SUPPLIES, imx214->supplies); 537 if (ret < 0) { 538 dev_err(imx214->dev, "failed to enable regulators: %d\n", ret); 539 return ret; 540 } 541 542 usleep_range(2000, 3000); 543 544 ret = clk_prepare_enable(imx214->xclk); 545 if (ret < 0) { 546 regulator_bulk_disable(IMX214_NUM_SUPPLIES, imx214->supplies); 547 dev_err(imx214->dev, "clk prepare enable failed\n"); 548 return ret; 549 } 550 551 gpiod_set_value_cansleep(imx214->enable_gpio, 1); 552 usleep_range(12000, 15000); 553 554 return 0; 555 } 556 557 static int __maybe_unused imx214_power_off(struct device *dev) 558 { 559 struct i2c_client *client = to_i2c_client(dev); 560 struct v4l2_subdev *sd = i2c_get_clientdata(client); 561 struct imx214 *imx214 = to_imx214(sd); 562 563 gpiod_set_value_cansleep(imx214->enable_gpio, 0); 564 565 clk_disable_unprepare(imx214->xclk); 566 567 regulator_bulk_disable(IMX214_NUM_SUPPLIES, imx214->supplies); 568 usleep_range(10, 20); 569 570 return 0; 571 } 572 573 /* Get bayer order based on flip setting. */ 574 static u32 imx214_get_format_code(struct imx214 *imx214) 575 { 576 unsigned int i; 577 578 i = (imx214->vflip->val ? 2 : 0) | (imx214->hflip->val ? 1 : 0); 579 580 return imx214_mbus_formats[i]; 581 } 582 583 static void imx214_update_pad_format(struct imx214 *imx214, 584 const struct imx214_mode *mode, 585 struct v4l2_mbus_framefmt *fmt, u32 code) 586 { 587 fmt->code = imx214_get_format_code(imx214); 588 fmt->width = mode->width; 589 fmt->height = mode->height; 590 fmt->field = V4L2_FIELD_NONE; 591 fmt->colorspace = V4L2_COLORSPACE_SRGB; 592 fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt->colorspace); 593 fmt->quantization = V4L2_MAP_QUANTIZATION_DEFAULT(true, 594 fmt->colorspace, 595 fmt->ycbcr_enc); 596 fmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt->colorspace); 597 } 598 599 static int imx214_enum_mbus_code(struct v4l2_subdev *sd, 600 struct v4l2_subdev_state *sd_state, 601 struct v4l2_subdev_mbus_code_enum *code) 602 { 603 struct imx214 *imx214 = to_imx214(sd); 604 605 if (code->index >= (ARRAY_SIZE(imx214_mbus_formats) / 4)) 606 return -EINVAL; 607 608 code->code = imx214_get_format_code(imx214); 609 610 return 0; 611 } 612 613 static int imx214_enum_frame_size(struct v4l2_subdev *subdev, 614 struct v4l2_subdev_state *sd_state, 615 struct v4l2_subdev_frame_size_enum *fse) 616 { 617 struct imx214 *imx214 = to_imx214(subdev); 618 u32 code; 619 620 code = imx214_get_format_code(imx214); 621 if (fse->code != code) 622 return -EINVAL; 623 624 if (fse->index >= ARRAY_SIZE(imx214_modes)) 625 return -EINVAL; 626 627 fse->min_width = fse->max_width = imx214_modes[fse->index].width; 628 fse->min_height = fse->max_height = imx214_modes[fse->index].height; 629 630 return 0; 631 } 632 633 #ifdef CONFIG_VIDEO_ADV_DEBUG 634 static int imx214_s_register(struct v4l2_subdev *subdev, 635 const struct v4l2_dbg_register *reg) 636 { 637 struct imx214 *imx214 = container_of(subdev, struct imx214, sd); 638 639 return regmap_write(imx214->regmap, reg->reg, reg->val); 640 } 641 642 static int imx214_g_register(struct v4l2_subdev *subdev, 643 struct v4l2_dbg_register *reg) 644 { 645 struct imx214 *imx214 = container_of(subdev, struct imx214, sd); 646 unsigned int aux; 647 int ret; 648 649 reg->size = 1; 650 ret = regmap_read(imx214->regmap, reg->reg, &aux); 651 reg->val = aux; 652 653 return ret; 654 } 655 #endif 656 657 static const struct v4l2_subdev_core_ops imx214_core_ops = { 658 #ifdef CONFIG_VIDEO_ADV_DEBUG 659 .g_register = imx214_g_register, 660 .s_register = imx214_s_register, 661 #endif 662 }; 663 664 static int imx214_set_format(struct v4l2_subdev *sd, 665 struct v4l2_subdev_state *sd_state, 666 struct v4l2_subdev_format *format) 667 { 668 struct imx214 *imx214 = to_imx214(sd); 669 struct v4l2_mbus_framefmt *__format; 670 struct v4l2_rect *__crop; 671 const struct imx214_mode *mode; 672 673 mode = v4l2_find_nearest_size(imx214_modes, 674 ARRAY_SIZE(imx214_modes), width, height, 675 format->format.width, 676 format->format.height); 677 678 imx214_update_pad_format(imx214, mode, &format->format, 679 format->format.code); 680 __format = v4l2_subdev_state_get_format(sd_state, 0); 681 682 *__format = format->format; 683 684 __crop = v4l2_subdev_state_get_crop(sd_state, 0); 685 __crop->width = mode->width; 686 __crop->height = mode->height; 687 688 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 689 int exposure_max; 690 int exposure_def; 691 int hblank; 692 693 /* Update blank limits */ 694 __v4l2_ctrl_modify_range(imx214->vblank, IMX214_VBLANK_MIN, 695 IMX214_VTS_MAX - mode->height, 2, 696 mode->vts_def - mode->height); 697 698 /* Update max exposure while meeting expected vblanking */ 699 exposure_max = mode->vts_def - IMX214_EXPOSURE_OFFSET; 700 exposure_def = min(exposure_max, IMX214_EXPOSURE_DEFAULT); 701 __v4l2_ctrl_modify_range(imx214->exposure, 702 imx214->exposure->minimum, 703 exposure_max, imx214->exposure->step, 704 exposure_def); 705 706 /* 707 * Currently PPL is fixed to IMX214_PPL_DEFAULT, so hblank 708 * depends on mode->width only, and is not changeable in any 709 * way other than changing the mode. 710 */ 711 hblank = IMX214_PPL_DEFAULT - mode->width; 712 __v4l2_ctrl_modify_range(imx214->hblank, hblank, hblank, 1, 713 hblank); 714 } 715 716 return 0; 717 } 718 719 static int imx214_get_selection(struct v4l2_subdev *sd, 720 struct v4l2_subdev_state *sd_state, 721 struct v4l2_subdev_selection *sel) 722 { 723 switch (sel->target) { 724 case V4L2_SEL_TGT_CROP: 725 sel->r = *v4l2_subdev_state_get_crop(sd_state, 0); 726 return 0; 727 728 case V4L2_SEL_TGT_NATIVE_SIZE: 729 sel->r.top = 0; 730 sel->r.left = 0; 731 sel->r.width = IMX214_NATIVE_WIDTH; 732 sel->r.height = IMX214_NATIVE_HEIGHT; 733 return 0; 734 735 case V4L2_SEL_TGT_CROP_DEFAULT: 736 case V4L2_SEL_TGT_CROP_BOUNDS: 737 sel->r.top = IMX214_PIXEL_ARRAY_TOP; 738 sel->r.left = IMX214_PIXEL_ARRAY_LEFT; 739 sel->r.width = IMX214_PIXEL_ARRAY_WIDTH; 740 sel->r.height = IMX214_PIXEL_ARRAY_HEIGHT; 741 return 0; 742 } 743 744 return -EINVAL; 745 } 746 747 static int imx214_entity_init_state(struct v4l2_subdev *subdev, 748 struct v4l2_subdev_state *sd_state) 749 { 750 struct v4l2_subdev_format fmt = { }; 751 752 fmt.which = sd_state ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE; 753 fmt.format.code = MEDIA_BUS_FMT_SRGGB10_1X10; 754 fmt.format.width = imx214_modes[0].width; 755 fmt.format.height = imx214_modes[0].height; 756 757 imx214_set_format(subdev, sd_state, &fmt); 758 759 return 0; 760 } 761 762 static int imx214_configure_pll(struct imx214 *imx214) 763 { 764 int ret = 0; 765 766 cci_write(imx214->regmap, IMX214_REG_VTPXCK_DIV, 767 imx214->pll.vt_bk.pix_clk_div, &ret); 768 cci_write(imx214->regmap, IMX214_REG_VTSYCK_DIV, 769 imx214->pll.vt_bk.sys_clk_div, &ret); 770 cci_write(imx214->regmap, IMX214_REG_PREPLLCK_VT_DIV, 771 imx214->pll.vt_fr.pre_pll_clk_div, &ret); 772 cci_write(imx214->regmap, IMX214_REG_PLL_VT_MPY, 773 imx214->pll.vt_fr.pll_multiplier, &ret); 774 cci_write(imx214->regmap, IMX214_REG_OPPXCK_DIV, 775 imx214->pll.op_bk.pix_clk_div, &ret); 776 cci_write(imx214->regmap, IMX214_REG_OPSYCK_DIV, 777 imx214->pll.op_bk.sys_clk_div, &ret); 778 cci_write(imx214->regmap, IMX214_REG_PLL_MULT_DRIV, 779 IMX214_PLL_SINGLE, &ret); 780 cci_write(imx214->regmap, IMX214_REG_EXCK_FREQ, 781 IMX214_EXCK_FREQ(imx214->pll.ext_clk_freq_hz / 1000000), &ret); 782 783 return ret; 784 } 785 786 static int imx214_update_digital_gain(struct imx214 *imx214, u32 val) 787 { 788 int ret = 0; 789 790 cci_write(imx214->regmap, IMX214_REG_DIG_GAIN_GREENR, val, &ret); 791 cci_write(imx214->regmap, IMX214_REG_DIG_GAIN_RED, val, &ret); 792 cci_write(imx214->regmap, IMX214_REG_DIG_GAIN_BLUE, val, &ret); 793 cci_write(imx214->regmap, IMX214_REG_DIG_GAIN_GREENB, val, &ret); 794 795 return ret; 796 } 797 798 static int imx214_set_ctrl(struct v4l2_ctrl *ctrl) 799 { 800 struct imx214 *imx214 = container_of(ctrl->handler, 801 struct imx214, ctrls); 802 const struct v4l2_mbus_framefmt *format = NULL; 803 struct v4l2_subdev_state *state; 804 int ret = 0; 805 806 if (ctrl->id == V4L2_CID_VBLANK) { 807 int exposure_max, exposure_def; 808 809 state = v4l2_subdev_get_locked_active_state(&imx214->sd); 810 format = v4l2_subdev_state_get_format(state, 0); 811 812 /* Update max exposure while meeting expected vblanking */ 813 exposure_max = 814 format->height + ctrl->val - IMX214_EXPOSURE_OFFSET; 815 exposure_def = min(exposure_max, IMX214_EXPOSURE_DEFAULT); 816 __v4l2_ctrl_modify_range(imx214->exposure, 817 imx214->exposure->minimum, 818 exposure_max, imx214->exposure->step, 819 exposure_def); 820 } 821 822 /* 823 * Applying V4L2 control value only happens 824 * when power is up for streaming 825 */ 826 if (!pm_runtime_get_if_in_use(imx214->dev)) 827 return 0; 828 829 switch (ctrl->id) { 830 case V4L2_CID_ANALOGUE_GAIN: 831 cci_write(imx214->regmap, IMX214_REG_ANALOG_GAIN, 832 ctrl->val, &ret); 833 cci_write(imx214->regmap, IMX214_REG_SHORT_ANALOG_GAIN, 834 ctrl->val, &ret); 835 break; 836 case V4L2_CID_DIGITAL_GAIN: 837 ret = imx214_update_digital_gain(imx214, ctrl->val); 838 break; 839 case V4L2_CID_EXPOSURE: 840 cci_write(imx214->regmap, IMX214_REG_EXPOSURE, ctrl->val, &ret); 841 break; 842 case V4L2_CID_HFLIP: 843 case V4L2_CID_VFLIP: 844 cci_write(imx214->regmap, IMX214_REG_ORIENTATION, 845 imx214->hflip->val | imx214->vflip->val << 1, &ret); 846 break; 847 case V4L2_CID_VBLANK: 848 cci_write(imx214->regmap, IMX214_REG_FRM_LENGTH_LINES, 849 format->height + ctrl->val, &ret); 850 break; 851 case V4L2_CID_TEST_PATTERN: 852 cci_write(imx214->regmap, IMX214_REG_TEST_PATTERN, 853 imx214_test_pattern_val[ctrl->val], &ret); 854 break; 855 case V4L2_CID_TEST_PATTERN_RED: 856 cci_write(imx214->regmap, IMX214_REG_TESTP_RED, 857 ctrl->val, &ret); 858 break; 859 case V4L2_CID_TEST_PATTERN_GREENR: 860 cci_write(imx214->regmap, IMX214_REG_TESTP_GREENR, 861 ctrl->val, &ret); 862 break; 863 case V4L2_CID_TEST_PATTERN_BLUE: 864 cci_write(imx214->regmap, IMX214_REG_TESTP_BLUE, 865 ctrl->val, &ret); 866 break; 867 case V4L2_CID_TEST_PATTERN_GREENB: 868 cci_write(imx214->regmap, IMX214_REG_TESTP_GREENB, 869 ctrl->val, &ret); 870 break; 871 default: 872 ret = -EINVAL; 873 } 874 875 pm_runtime_put(imx214->dev); 876 877 return ret; 878 } 879 880 static const struct v4l2_ctrl_ops imx214_ctrl_ops = { 881 .s_ctrl = imx214_set_ctrl, 882 }; 883 884 static int imx214_ctrls_init(struct imx214 *imx214) 885 { 886 static const struct v4l2_area unit_size = { 887 .width = 1120, 888 .height = 1120, 889 }; 890 const struct imx214_mode *mode = &imx214_modes[0]; 891 struct v4l2_fwnode_device_properties props; 892 struct v4l2_ctrl_handler *ctrl_hdlr; 893 int exposure_max, exposure_def; 894 int hblank; 895 int i, ret; 896 897 ret = v4l2_fwnode_device_parse(imx214->dev, &props); 898 if (ret < 0) 899 return ret; 900 901 ctrl_hdlr = &imx214->ctrls; 902 ret = v4l2_ctrl_handler_init(&imx214->ctrls, 13); 903 if (ret) 904 return ret; 905 906 imx214->pixel_rate = 907 v4l2_ctrl_new_std(ctrl_hdlr, NULL, V4L2_CID_PIXEL_RATE, 1, 908 INT_MAX, 1, 1); 909 910 imx214->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, NULL, 911 V4L2_CID_LINK_FREQ, 912 imx214->bus_cfg.nr_of_link_frequencies - 1, 913 0, imx214->bus_cfg.link_frequencies); 914 if (imx214->link_freq) 915 imx214->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 916 917 /* 918 * WARNING! 919 * Values obtained reverse engineering blobs and/or devices. 920 * Ranges and functionality might be wrong. 921 * 922 * Sony, please release some register set documentation for the 923 * device. 924 * 925 * Yours sincerely, Ricardo. 926 */ 927 928 /* Initial vblank/hblank/exposure parameters based on current mode */ 929 imx214->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx214_ctrl_ops, 930 V4L2_CID_VBLANK, IMX214_VBLANK_MIN, 931 IMX214_VTS_MAX - mode->height, 2, 932 mode->vts_def - mode->height); 933 934 hblank = IMX214_PPL_DEFAULT - mode->width; 935 imx214->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx214_ctrl_ops, 936 V4L2_CID_HBLANK, hblank, hblank, 937 1, hblank); 938 if (imx214->hblank) 939 imx214->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 940 941 exposure_max = mode->vts_def - IMX214_EXPOSURE_OFFSET; 942 exposure_def = min(exposure_max, IMX214_EXPOSURE_DEFAULT); 943 imx214->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &imx214_ctrl_ops, 944 V4L2_CID_EXPOSURE, 945 IMX214_EXPOSURE_MIN, 946 exposure_max, 947 IMX214_EXPOSURE_STEP, 948 exposure_def); 949 950 v4l2_ctrl_new_std(ctrl_hdlr, &imx214_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 951 IMX214_ANA_GAIN_MIN, IMX214_ANA_GAIN_MAX, 952 IMX214_ANA_GAIN_STEP, IMX214_ANA_GAIN_DEFAULT); 953 954 v4l2_ctrl_new_std(ctrl_hdlr, &imx214_ctrl_ops, V4L2_CID_DIGITAL_GAIN, 955 IMX214_DGTL_GAIN_MIN, IMX214_DGTL_GAIN_MAX, 956 IMX214_DGTL_GAIN_STEP, IMX214_DGTL_GAIN_DEFAULT); 957 958 imx214->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx214_ctrl_ops, 959 V4L2_CID_HFLIP, 0, 1, 1, 0); 960 if (imx214->hflip) 961 imx214->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; 962 963 imx214->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx214_ctrl_ops, 964 V4L2_CID_VFLIP, 0, 1, 1, 0); 965 if (imx214->vflip) 966 imx214->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; 967 968 v4l2_ctrl_cluster(2, &imx214->hflip); 969 970 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &imx214_ctrl_ops, 971 V4L2_CID_TEST_PATTERN, 972 ARRAY_SIZE(imx214_test_pattern_menu) - 1, 973 0, 0, imx214_test_pattern_menu); 974 for (i = 0; i < 4; i++) { 975 /* 976 * The assumption is that 977 * V4L2_CID_TEST_PATTERN_GREENR == V4L2_CID_TEST_PATTERN_RED + 1 978 * V4L2_CID_TEST_PATTERN_BLUE == V4L2_CID_TEST_PATTERN_RED + 2 979 * V4L2_CID_TEST_PATTERN_GREENB == V4L2_CID_TEST_PATTERN_RED + 3 980 */ 981 v4l2_ctrl_new_std(ctrl_hdlr, &imx214_ctrl_ops, 982 V4L2_CID_TEST_PATTERN_RED + i, 983 IMX214_TESTP_COLOUR_MIN, 984 IMX214_TESTP_COLOUR_MAX, 985 IMX214_TESTP_COLOUR_STEP, 986 IMX214_TESTP_COLOUR_MAX); 987 /* The "Solid color" pattern is white by default */ 988 } 989 990 imx214->unit_size = v4l2_ctrl_new_std_compound(ctrl_hdlr, 991 NULL, 992 V4L2_CID_UNIT_CELL_SIZE, 993 v4l2_ctrl_ptr_create((void *)&unit_size), 994 v4l2_ctrl_ptr_create(NULL), 995 v4l2_ctrl_ptr_create(NULL)); 996 997 v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &imx214_ctrl_ops, &props); 998 999 ret = ctrl_hdlr->error; 1000 if (ret) { 1001 v4l2_ctrl_handler_free(ctrl_hdlr); 1002 dev_err(imx214->dev, "failed to add controls: %d\n", ret); 1003 return ret; 1004 } 1005 1006 imx214->sd.ctrl_handler = ctrl_hdlr; 1007 1008 return 0; 1009 }; 1010 1011 static int imx214_start_streaming(struct imx214 *imx214) 1012 { 1013 const struct v4l2_mbus_framefmt *fmt; 1014 struct v4l2_subdev_state *state; 1015 const struct imx214_mode *mode; 1016 int bit_rate_mbps; 1017 int ret; 1018 1019 ret = cci_multi_reg_write(imx214->regmap, mode_table_common, 1020 ARRAY_SIZE(mode_table_common), NULL); 1021 if (ret < 0) { 1022 dev_err(imx214->dev, "could not sent common table %d\n", ret); 1023 return ret; 1024 } 1025 1026 ret = imx214_configure_pll(imx214); 1027 if (ret) { 1028 dev_err(imx214->dev, "failed to configure PLL: %d\n", ret); 1029 return ret; 1030 } 1031 1032 bit_rate_mbps = (imx214->pll.pixel_rate_csi / 1000000) 1033 * imx214->pll.bits_per_pixel; 1034 ret = cci_write(imx214->regmap, IMX214_REG_REQ_LINK_BIT_RATE, 1035 IMX214_LINK_BIT_RATE_MBPS(bit_rate_mbps), NULL); 1036 if (ret) { 1037 dev_err(imx214->dev, "failed to configure link bit rate\n"); 1038 return ret; 1039 } 1040 1041 ret = cci_write(imx214->regmap, IMX214_REG_CSI_LANE_MODE, 1042 IMX214_CSI_4_LANE_MODE, NULL); 1043 if (ret) { 1044 dev_err(imx214->dev, "failed to configure lanes\n"); 1045 return ret; 1046 } 1047 1048 state = v4l2_subdev_get_locked_active_state(&imx214->sd); 1049 fmt = v4l2_subdev_state_get_format(state, 0); 1050 mode = v4l2_find_nearest_size(imx214_modes, ARRAY_SIZE(imx214_modes), 1051 width, height, fmt->width, fmt->height); 1052 ret = cci_multi_reg_write(imx214->regmap, mode->reg_table, 1053 mode->num_of_regs, NULL); 1054 if (ret < 0) { 1055 dev_err(imx214->dev, "could not sent mode table %d\n", ret); 1056 return ret; 1057 } 1058 1059 usleep_range(10000, 10500); 1060 1061 cci_write(imx214->regmap, IMX214_REG_TEMP_SENSOR_CONTROL, 0x01, NULL); 1062 1063 ret = __v4l2_ctrl_handler_setup(&imx214->ctrls); 1064 if (ret < 0) { 1065 dev_err(imx214->dev, "could not sync v4l2 controls\n"); 1066 return ret; 1067 } 1068 ret = cci_write(imx214->regmap, IMX214_REG_MODE_SELECT, 1069 IMX214_MODE_STREAMING, NULL); 1070 if (ret < 0) 1071 dev_err(imx214->dev, "could not sent start table %d\n", ret); 1072 1073 return ret; 1074 } 1075 1076 static int imx214_stop_streaming(struct imx214 *imx214) 1077 { 1078 int ret; 1079 1080 ret = cci_write(imx214->regmap, IMX214_REG_MODE_SELECT, 1081 IMX214_MODE_STANDBY, NULL); 1082 if (ret < 0) 1083 dev_err(imx214->dev, "could not sent stop table %d\n", ret); 1084 1085 return ret; 1086 } 1087 1088 static int imx214_s_stream(struct v4l2_subdev *subdev, int enable) 1089 { 1090 struct imx214 *imx214 = to_imx214(subdev); 1091 struct v4l2_subdev_state *state; 1092 int ret; 1093 1094 if (enable) { 1095 ret = pm_runtime_resume_and_get(imx214->dev); 1096 if (ret < 0) 1097 return ret; 1098 1099 state = v4l2_subdev_lock_and_get_active_state(subdev); 1100 ret = imx214_start_streaming(imx214); 1101 v4l2_subdev_unlock_state(state); 1102 if (ret < 0) 1103 goto err_rpm_put; 1104 } else { 1105 ret = imx214_stop_streaming(imx214); 1106 if (ret < 0) 1107 goto err_rpm_put; 1108 pm_runtime_put(imx214->dev); 1109 } 1110 1111 return 0; 1112 1113 err_rpm_put: 1114 pm_runtime_put(imx214->dev); 1115 return ret; 1116 } 1117 1118 static int imx214_pll_calculate(struct imx214 *imx214, struct ccs_pll *pll, 1119 unsigned int link_freq) 1120 { 1121 struct ccs_pll_limits limits = { 1122 .min_ext_clk_freq_hz = 6000000, 1123 .max_ext_clk_freq_hz = 27000000, 1124 1125 .vt_fr = { 1126 .min_pre_pll_clk_div = 1, 1127 .max_pre_pll_clk_div = 15, 1128 /* Value is educated guess as we don't have a spec */ 1129 .min_pll_ip_clk_freq_hz = 6000000, 1130 /* Value is educated guess as we don't have a spec */ 1131 .max_pll_ip_clk_freq_hz = 12000000, 1132 .min_pll_multiplier = 12, 1133 .max_pll_multiplier = 1200, 1134 .min_pll_op_clk_freq_hz = 338000000, 1135 .max_pll_op_clk_freq_hz = 1200000000, 1136 }, 1137 .vt_bk = { 1138 .min_sys_clk_div = 2, 1139 .max_sys_clk_div = 4, 1140 .min_pix_clk_div = 5, 1141 .max_pix_clk_div = 10, 1142 .min_pix_clk_freq_hz = 30000000, 1143 .max_pix_clk_freq_hz = 120000000, 1144 }, 1145 .op_bk = { 1146 .min_sys_clk_div = 1, 1147 .max_sys_clk_div = 2, 1148 .min_pix_clk_div = 6, 1149 .max_pix_clk_div = 10, 1150 .min_pix_clk_freq_hz = 30000000, 1151 .max_pix_clk_freq_hz = 120000000, 1152 }, 1153 1154 .min_line_length_pck_bin = IMX214_PPL_DEFAULT, 1155 .min_line_length_pck = IMX214_PPL_DEFAULT, 1156 }; 1157 unsigned int num_lanes = imx214->bus_cfg.bus.mipi_csi2.num_data_lanes; 1158 1159 /* 1160 * There are no documented constraints on the sys clock frequency, for 1161 * either branch. Recover them based on the PLL output clock frequency 1162 * and sys_clk_div limits on one hand, and the pix clock frequency and 1163 * the pix_clk_div limits on the other hand. 1164 */ 1165 limits.vt_bk.min_sys_clk_freq_hz = 1166 max(limits.vt_fr.min_pll_op_clk_freq_hz / limits.vt_bk.max_sys_clk_div, 1167 limits.vt_bk.min_pix_clk_freq_hz * limits.vt_bk.min_pix_clk_div); 1168 limits.vt_bk.max_sys_clk_freq_hz = 1169 min(limits.vt_fr.max_pll_op_clk_freq_hz / limits.vt_bk.min_sys_clk_div, 1170 limits.vt_bk.max_pix_clk_freq_hz * limits.vt_bk.max_pix_clk_div); 1171 1172 limits.op_bk.min_sys_clk_freq_hz = 1173 max(limits.vt_fr.min_pll_op_clk_freq_hz / limits.op_bk.max_sys_clk_div, 1174 limits.op_bk.min_pix_clk_freq_hz * limits.op_bk.min_pix_clk_div); 1175 limits.op_bk.max_sys_clk_freq_hz = 1176 min(limits.vt_fr.max_pll_op_clk_freq_hz / limits.op_bk.min_sys_clk_div, 1177 limits.op_bk.max_pix_clk_freq_hz * limits.op_bk.max_pix_clk_div); 1178 1179 memset(pll, 0, sizeof(*pll)); 1180 1181 pll->bus_type = CCS_PLL_BUS_TYPE_CSI2_DPHY; 1182 pll->op_lanes = num_lanes; 1183 pll->vt_lanes = num_lanes; 1184 pll->csi2.lanes = num_lanes; 1185 1186 pll->binning_horizontal = 1; 1187 pll->binning_vertical = 1; 1188 pll->scale_m = 1; 1189 pll->scale_n = 1; 1190 pll->bits_per_pixel = 1191 IMX214_CSI_DATA_FORMAT_RAW10 & IMX214_BITS_PER_PIXEL_MASK; 1192 pll->flags = CCS_PLL_FLAG_LANE_SPEED_MODEL; 1193 pll->link_freq = link_freq; 1194 pll->ext_clk_freq_hz = clk_get_rate(imx214->xclk); 1195 1196 return ccs_pll_calculate(imx214->dev, &limits, pll); 1197 } 1198 1199 static int imx214_pll_update(struct imx214 *imx214) 1200 { 1201 u64 link_freq; 1202 int ret; 1203 1204 link_freq = imx214->bus_cfg.link_frequencies[imx214->link_freq->val]; 1205 ret = imx214_pll_calculate(imx214, &imx214->pll, link_freq); 1206 if (ret) { 1207 dev_err(imx214->dev, "PLL calculations failed: %d\n", ret); 1208 return ret; 1209 } 1210 1211 ret = v4l2_ctrl_s_ctrl_int64(imx214->pixel_rate, 1212 imx214->pll.pixel_rate_pixel_array); 1213 if (ret) { 1214 dev_err(imx214->dev, "failed to set pixel rate\n"); 1215 return ret; 1216 } 1217 1218 return 0; 1219 } 1220 1221 static int imx214_get_frame_interval(struct v4l2_subdev *subdev, 1222 struct v4l2_subdev_state *sd_state, 1223 struct v4l2_subdev_frame_interval *fival) 1224 { 1225 /* 1226 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2 1227 * subdev active state API. 1228 */ 1229 if (fival->which != V4L2_SUBDEV_FORMAT_ACTIVE) 1230 return -EINVAL; 1231 1232 fival->interval.numerator = 1; 1233 fival->interval.denominator = IMX214_FPS; 1234 1235 return 0; 1236 } 1237 1238 /* 1239 * Raw sensors should be using the VBLANK and HBLANK controls to determine 1240 * the frame rate. However this driver was initially added using the 1241 * [S|G|ENUM]_FRAME_INTERVAL ioctls with a fixed rate of 30fps. 1242 * Retain the frame_interval ops for backwards compatibility, but they do 1243 * nothing. 1244 */ 1245 static int imx214_enum_frame_interval(struct v4l2_subdev *subdev, 1246 struct v4l2_subdev_state *sd_state, 1247 struct v4l2_subdev_frame_interval_enum *fie) 1248 { 1249 struct imx214 *imx214 = to_imx214(subdev); 1250 const struct imx214_mode *mode; 1251 1252 dev_warn_once(imx214->dev, "frame_interval functions return an unreliable value for compatibility reasons. Use the VBLANK and HBLANK controls to determine the correct frame rate.\n"); 1253 1254 if (fie->index != 0) 1255 return -EINVAL; 1256 1257 mode = v4l2_find_nearest_size(imx214_modes, 1258 ARRAY_SIZE(imx214_modes), width, height, 1259 fie->width, fie->height); 1260 1261 fie->code = imx214_get_format_code(imx214); 1262 fie->width = mode->width; 1263 fie->height = mode->height; 1264 fie->interval.numerator = 1; 1265 fie->interval.denominator = IMX214_FPS; 1266 1267 return 0; 1268 } 1269 1270 static const struct v4l2_subdev_video_ops imx214_video_ops = { 1271 .s_stream = imx214_s_stream, 1272 }; 1273 1274 static const struct v4l2_subdev_pad_ops imx214_subdev_pad_ops = { 1275 .enum_mbus_code = imx214_enum_mbus_code, 1276 .enum_frame_size = imx214_enum_frame_size, 1277 .enum_frame_interval = imx214_enum_frame_interval, 1278 .get_fmt = v4l2_subdev_get_fmt, 1279 .set_fmt = imx214_set_format, 1280 .get_selection = imx214_get_selection, 1281 .get_frame_interval = imx214_get_frame_interval, 1282 .set_frame_interval = imx214_get_frame_interval, 1283 }; 1284 1285 static const struct v4l2_subdev_ops imx214_subdev_ops = { 1286 .core = &imx214_core_ops, 1287 .video = &imx214_video_ops, 1288 .pad = &imx214_subdev_pad_ops, 1289 }; 1290 1291 static const struct v4l2_subdev_internal_ops imx214_internal_ops = { 1292 .init_state = imx214_entity_init_state, 1293 }; 1294 1295 static int imx214_get_regulators(struct device *dev, struct imx214 *imx214) 1296 { 1297 unsigned int i; 1298 1299 for (i = 0; i < IMX214_NUM_SUPPLIES; i++) 1300 imx214->supplies[i].supply = imx214_supply_name[i]; 1301 1302 return devm_regulator_bulk_get(dev, IMX214_NUM_SUPPLIES, 1303 imx214->supplies); 1304 } 1305 1306 /* Verify chip ID */ 1307 static int imx214_identify_module(struct imx214 *imx214) 1308 { 1309 struct i2c_client *client = v4l2_get_subdevdata(&imx214->sd); 1310 int ret; 1311 u64 val; 1312 1313 ret = cci_read(imx214->regmap, IMX214_REG_CHIP_ID, &val, NULL); 1314 if (ret) 1315 return dev_err_probe(&client->dev, ret, 1316 "failed to read chip id %x\n", 1317 IMX214_CHIP_ID); 1318 1319 if (val != IMX214_CHIP_ID) 1320 return dev_err_probe(&client->dev, -EIO, 1321 "chip id mismatch: %x!=%llx\n", 1322 IMX214_CHIP_ID, val); 1323 1324 return 0; 1325 } 1326 1327 static int imx214_parse_fwnode(struct device *dev, struct imx214 *imx214) 1328 { 1329 struct v4l2_fwnode_endpoint *bus_cfg = &imx214->bus_cfg; 1330 struct fwnode_handle *endpoint; 1331 unsigned int i; 1332 int ret; 1333 1334 endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL); 1335 if (!endpoint) 1336 return dev_err_probe(dev, -EINVAL, "endpoint node not found\n"); 1337 1338 bus_cfg->bus_type = V4L2_MBUS_CSI2_DPHY; 1339 ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, bus_cfg); 1340 fwnode_handle_put(endpoint); 1341 if (ret) { 1342 dev_err_probe(dev, ret, "parsing endpoint node failed\n"); 1343 goto error; 1344 } 1345 1346 /* Check the number of MIPI CSI2 data lanes */ 1347 if (bus_cfg->bus.mipi_csi2.num_data_lanes != 4) { 1348 ret = dev_err_probe(dev, -EINVAL, 1349 "only 4 data lanes are currently supported\n"); 1350 goto error; 1351 } 1352 1353 if (bus_cfg->nr_of_link_frequencies != 1) 1354 dev_warn(dev, "Only one link-frequency supported, please review your DT. Continuing anyway\n"); 1355 1356 for (i = 0; i < bus_cfg->nr_of_link_frequencies; i++) { 1357 u64 freq = bus_cfg->link_frequencies[i]; 1358 struct ccs_pll pll; 1359 1360 if (!imx214_pll_calculate(imx214, &pll, freq)) 1361 break; 1362 if (freq == IMX214_DEFAULT_LINK_FREQ_LEGACY) { 1363 dev_warn(dev, 1364 "link-frequencies %d not supported, please review your DT. Continuing anyway\n", 1365 IMX214_DEFAULT_LINK_FREQ); 1366 freq = IMX214_DEFAULT_LINK_FREQ; 1367 if (imx214_pll_calculate(imx214, &pll, freq)) 1368 continue; 1369 bus_cfg->link_frequencies[i] = freq; 1370 break; 1371 } 1372 } 1373 1374 if (i == bus_cfg->nr_of_link_frequencies) 1375 ret = dev_err_probe(dev, -EINVAL, 1376 "link-frequencies %lld not supported, please review your DT\n", 1377 bus_cfg->nr_of_link_frequencies ? 1378 bus_cfg->link_frequencies[0] : 0); 1379 1380 return 0; 1381 1382 error: 1383 v4l2_fwnode_endpoint_free(&imx214->bus_cfg); 1384 return ret; 1385 } 1386 1387 static int imx214_probe(struct i2c_client *client) 1388 { 1389 struct device *dev = &client->dev; 1390 struct imx214 *imx214; 1391 int ret; 1392 1393 imx214 = devm_kzalloc(dev, sizeof(*imx214), GFP_KERNEL); 1394 if (!imx214) 1395 return -ENOMEM; 1396 1397 imx214->dev = dev; 1398 1399 imx214->xclk = devm_clk_get(dev, NULL); 1400 if (IS_ERR(imx214->xclk)) 1401 return dev_err_probe(dev, PTR_ERR(imx214->xclk), 1402 "failed to get xclk\n"); 1403 1404 ret = imx214_get_regulators(dev, imx214); 1405 if (ret < 0) 1406 return dev_err_probe(dev, ret, "failed to get regulators\n"); 1407 1408 imx214->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW); 1409 if (IS_ERR(imx214->enable_gpio)) 1410 return dev_err_probe(dev, PTR_ERR(imx214->enable_gpio), 1411 "failed to get enable gpio\n"); 1412 1413 imx214->regmap = devm_cci_regmap_init_i2c(client, 16); 1414 if (IS_ERR(imx214->regmap)) 1415 return dev_err_probe(dev, PTR_ERR(imx214->regmap), 1416 "failed to initialize CCI\n"); 1417 1418 ret = imx214_parse_fwnode(dev, imx214); 1419 if (ret) 1420 return ret; 1421 1422 v4l2_i2c_subdev_init(&imx214->sd, client, &imx214_subdev_ops); 1423 imx214->sd.internal_ops = &imx214_internal_ops; 1424 1425 /* 1426 * Enable power initially, to avoid warnings 1427 * from clk_disable on power_off 1428 */ 1429 ret = imx214_power_on(imx214->dev); 1430 if (ret < 0) 1431 goto error_fwnode; 1432 1433 ret = imx214_identify_module(imx214); 1434 if (ret) 1435 goto error_power_off; 1436 1437 ret = imx214_ctrls_init(imx214); 1438 if (ret < 0) 1439 goto error_power_off; 1440 1441 imx214->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1442 imx214->pad.flags = MEDIA_PAD_FL_SOURCE; 1443 imx214->sd.dev = &client->dev; 1444 imx214->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1445 1446 ret = media_entity_pads_init(&imx214->sd.entity, 1, &imx214->pad); 1447 if (ret < 0) { 1448 dev_err_probe(dev, ret, "failed to init entity pads\n"); 1449 goto free_ctrl; 1450 } 1451 1452 imx214->sd.state_lock = imx214->ctrls.lock; 1453 ret = v4l2_subdev_init_finalize(&imx214->sd); 1454 if (ret < 0) { 1455 dev_err_probe(dev, ret, "subdev init error\n"); 1456 goto free_entity; 1457 } 1458 1459 pm_runtime_set_active(imx214->dev); 1460 pm_runtime_enable(imx214->dev); 1461 1462 ret = imx214_pll_update(imx214); 1463 if (ret < 0) { 1464 dev_err_probe(dev, ret, "failed to update PLL\n"); 1465 goto error_subdev_cleanup; 1466 } 1467 1468 ret = v4l2_async_register_subdev_sensor(&imx214->sd); 1469 if (ret < 0) { 1470 dev_err_probe(dev, ret, 1471 "failed to register sensor sub-device\n"); 1472 goto error_subdev_cleanup; 1473 } 1474 1475 pm_runtime_idle(imx214->dev); 1476 1477 return 0; 1478 1479 error_subdev_cleanup: 1480 pm_runtime_disable(imx214->dev); 1481 pm_runtime_set_suspended(&client->dev); 1482 v4l2_subdev_cleanup(&imx214->sd); 1483 1484 free_entity: 1485 media_entity_cleanup(&imx214->sd.entity); 1486 1487 free_ctrl: 1488 v4l2_ctrl_handler_free(&imx214->ctrls); 1489 1490 error_power_off: 1491 imx214_power_off(imx214->dev); 1492 1493 error_fwnode: 1494 v4l2_fwnode_endpoint_free(&imx214->bus_cfg); 1495 1496 return ret; 1497 } 1498 1499 static void imx214_remove(struct i2c_client *client) 1500 { 1501 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1502 struct imx214 *imx214 = to_imx214(sd); 1503 1504 v4l2_async_unregister_subdev(&imx214->sd); 1505 v4l2_subdev_cleanup(sd); 1506 media_entity_cleanup(&imx214->sd.entity); 1507 v4l2_ctrl_handler_free(&imx214->ctrls); 1508 v4l2_fwnode_endpoint_free(&imx214->bus_cfg); 1509 1510 pm_runtime_disable(&client->dev); 1511 if (!pm_runtime_status_suspended(&client->dev)) { 1512 imx214_power_off(imx214->dev); 1513 pm_runtime_set_suspended(&client->dev); 1514 } 1515 } 1516 1517 static const struct of_device_id imx214_of_match[] = { 1518 { .compatible = "sony,imx214" }, 1519 { } 1520 }; 1521 MODULE_DEVICE_TABLE(of, imx214_of_match); 1522 1523 static const struct dev_pm_ops imx214_pm_ops = { 1524 SET_RUNTIME_PM_OPS(imx214_power_off, imx214_power_on, NULL) 1525 }; 1526 1527 static struct i2c_driver imx214_i2c_driver = { 1528 .driver = { 1529 .of_match_table = imx214_of_match, 1530 .pm = &imx214_pm_ops, 1531 .name = "imx214", 1532 }, 1533 .probe = imx214_probe, 1534 .remove = imx214_remove, 1535 }; 1536 1537 module_i2c_driver(imx214_i2c_driver); 1538 1539 MODULE_DESCRIPTION("Sony IMX214 Camera driver"); 1540 MODULE_AUTHOR("Ricardo Ribalda <ribalda@kernel.org>"); 1541 MODULE_LICENSE("GPL v2"); 1542