1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2021 Purism SPC
3
4 #include <linux/unaligned.h>
5 #include <linux/clk.h>
6 #include <linux/delay.h>
7 #include <linux/gpio/consumer.h>
8 #include <linux/i2c.h>
9 #include <linux/module.h>
10 #include <linux/pm_runtime.h>
11 #include <linux/pm.h>
12 #include <linux/property.h>
13 #include <linux/regulator/consumer.h>
14 #include <media/v4l2-ctrls.h>
15 #include <media/v4l2-device.h>
16 #include <media/v4l2-fwnode.h>
17
18 #define HI846_MEDIA_BUS_FORMAT MEDIA_BUS_FMT_SGBRG10_1X10
19 #define HI846_RGB_DEPTH 10
20
21 /* Frame length lines / vertical timings */
22 #define HI846_REG_FLL 0x0006
23 #define HI846_FLL_MAX 0xffff
24
25 /* Horizontal timing */
26 #define HI846_REG_LLP 0x0008
27 #define HI846_LINE_LENGTH 3800
28
29 #define HI846_REG_BINNING_MODE 0x000c
30
31 #define HI846_REG_IMAGE_ORIENTATION 0x000e
32
33 #define HI846_REG_UNKNOWN_0022 0x0022
34
35 #define HI846_REG_Y_ADDR_START_VACT_H 0x0026
36 #define HI846_REG_Y_ADDR_START_VACT_L 0x0027
37 #define HI846_REG_UNKNOWN_0028 0x0028
38
39 #define HI846_REG_Y_ADDR_END_VACT_H 0x002c
40 #define HI846_REG_Y_ADDR_END_VACT_L 0x002d
41
42 #define HI846_REG_Y_ODD_INC_FOBP 0x002e
43 #define HI846_REG_Y_EVEN_INC_FOBP 0x002f
44
45 #define HI846_REG_Y_ODD_INC_VACT 0x0032
46 #define HI846_REG_Y_EVEN_INC_VACT 0x0033
47
48 #define HI846_REG_GROUPED_PARA_HOLD 0x0046
49
50 #define HI846_REG_TG_ENABLE 0x004c
51
52 #define HI846_REG_UNKNOWN_005C 0x005c
53
54 #define HI846_REG_UNKNOWN_006A 0x006a
55
56 /*
57 * Long exposure time. Actually, exposure is a 20 bit value that
58 * includes the lower 4 bits of 0x0073 too. Only 16 bits are used
59 * right now
60 */
61 #define HI846_REG_EXPOSURE 0x0074
62 #define HI846_EXPOSURE_MIN 6
63 #define HI846_EXPOSURE_MAX_MARGIN 2
64 #define HI846_EXPOSURE_STEP 1
65
66 /* Analog gain controls from sensor */
67 #define HI846_REG_ANALOG_GAIN 0x0077
68 #define HI846_ANAL_GAIN_MIN 0
69 #define HI846_ANAL_GAIN_MAX 240
70 #define HI846_ANAL_GAIN_STEP 8
71
72 /* Digital gain controls from sensor */
73 #define HI846_REG_MWB_GR_GAIN_H 0x0078
74 #define HI846_REG_MWB_GR_GAIN_L 0x0079
75 #define HI846_REG_MWB_GB_GAIN_H 0x007a
76 #define HI846_REG_MWB_GB_GAIN_L 0x007b
77 #define HI846_REG_MWB_R_GAIN_H 0x007c
78 #define HI846_REG_MWB_R_GAIN_L 0x007d
79 #define HI846_REG_MWB_B_GAIN_H 0x007e
80 #define HI846_REG_MWB_B_GAIN_L 0x007f
81 #define HI846_DGTL_GAIN_MIN 512
82 #define HI846_DGTL_GAIN_MAX 8191
83 #define HI846_DGTL_GAIN_STEP 1
84 #define HI846_DGTL_GAIN_DEFAULT 512
85
86 #define HI846_REG_X_ADDR_START_HACT_H 0x0120
87 #define HI846_REG_X_ADDR_END_HACT_H 0x0122
88
89 #define HI846_REG_UNKNOWN_012A 0x012a
90
91 #define HI846_REG_UNKNOWN_0200 0x0200
92
93 #define HI846_REG_UNKNOWN_021C 0x021c
94 #define HI846_REG_UNKNOWN_021E 0x021e
95
96 #define HI846_REG_UNKNOWN_0402 0x0402
97 #define HI846_REG_UNKNOWN_0404 0x0404
98 #define HI846_REG_UNKNOWN_0408 0x0408
99 #define HI846_REG_UNKNOWN_0410 0x0410
100 #define HI846_REG_UNKNOWN_0412 0x0412
101 #define HI846_REG_UNKNOWN_0414 0x0414
102
103 #define HI846_REG_UNKNOWN_0418 0x0418
104
105 #define HI846_REG_UNKNOWN_051E 0x051e
106
107 /* Formatter */
108 #define HI846_REG_X_START_H 0x0804
109 #define HI846_REG_X_START_L 0x0805
110
111 /* MIPI */
112 #define HI846_REG_UNKNOWN_0900 0x0900
113 #define HI846_REG_MIPI_TX_OP_EN 0x0901
114 #define HI846_REG_MIPI_TX_OP_MODE 0x0902
115 #define HI846_RAW8 BIT(5)
116
117 #define HI846_REG_UNKNOWN_090C 0x090c
118 #define HI846_REG_UNKNOWN_090E 0x090e
119
120 #define HI846_REG_UNKNOWN_0914 0x0914
121 #define HI846_REG_TLPX 0x0915
122 #define HI846_REG_TCLK_PREPARE 0x0916
123 #define HI846_REG_TCLK_ZERO 0x0917
124 #define HI846_REG_UNKNOWN_0918 0x0918
125 #define HI846_REG_THS_PREPARE 0x0919
126 #define HI846_REG_THS_ZERO 0x091a
127 #define HI846_REG_THS_TRAIL 0x091b
128 #define HI846_REG_TCLK_POST 0x091c
129 #define HI846_REG_TCLK_TRAIL_MIN 0x091d
130 #define HI846_REG_UNKNOWN_091E 0x091e
131
132 #define HI846_REG_UNKNOWN_0954 0x0954
133 #define HI846_REG_UNKNOWN_0956 0x0956
134 #define HI846_REG_UNKNOWN_0958 0x0958
135 #define HI846_REG_UNKNOWN_095A 0x095a
136
137 /* ISP Common */
138 #define HI846_REG_MODE_SELECT 0x0a00
139 #define HI846_MODE_STANDBY 0x00
140 #define HI846_MODE_STREAMING 0x01
141 #define HI846_REG_FAST_STANDBY_MODE 0x0a02
142 #define HI846_REG_ISP_EN_H 0x0a04
143
144 /* Test Pattern Control */
145 #define HI846_REG_ISP 0x0a05
146 #define HI846_REG_ISP_TPG_EN 0x01
147 #define HI846_REG_TEST_PATTERN 0x020a /* 1-9 */
148
149 #define HI846_REG_UNKNOWN_0A0C 0x0a0c
150
151 /* Windowing */
152 #define HI846_REG_X_OUTPUT_SIZE_H 0x0a12
153 #define HI846_REG_X_OUTPUT_SIZE_L 0x0a13
154 #define HI846_REG_Y_OUTPUT_SIZE_H 0x0a14
155 #define HI846_REG_Y_OUTPUT_SIZE_L 0x0a15
156
157 /* ISP Common */
158 #define HI846_REG_PEDESTAL_EN 0x0a1a
159
160 #define HI846_REG_UNKNOWN_0A1E 0x0a1e
161
162 /* Horizontal Binning Mode */
163 #define HI846_REG_HBIN_MODE 0x0a22
164
165 #define HI846_REG_UNKNOWN_0A24 0x0a24
166 #define HI846_REG_UNKNOWN_0B02 0x0b02
167 #define HI846_REG_UNKNOWN_0B10 0x0b10
168 #define HI846_REG_UNKNOWN_0B12 0x0b12
169 #define HI846_REG_UNKNOWN_0B14 0x0b14
170
171 /* BLC (Black Level Calibration) */
172 #define HI846_REG_BLC_CTL0 0x0c00
173
174 #define HI846_REG_UNKNOWN_0C06 0x0c06
175 #define HI846_REG_UNKNOWN_0C10 0x0c10
176 #define HI846_REG_UNKNOWN_0C12 0x0c12
177 #define HI846_REG_UNKNOWN_0C14 0x0c14
178 #define HI846_REG_UNKNOWN_0C16 0x0c16
179
180 #define HI846_REG_UNKNOWN_0E04 0x0e04
181
182 #define HI846_REG_CHIP_ID_L 0x0f16
183 #define HI846_REG_CHIP_ID_H 0x0f17
184 #define HI846_CHIP_ID_L 0x46
185 #define HI846_CHIP_ID_H 0x08
186
187 #define HI846_REG_UNKNOWN_0F04 0x0f04
188 #define HI846_REG_UNKNOWN_0F08 0x0f08
189
190 /* PLL */
191 #define HI846_REG_PLL_CFG_MIPI2_H 0x0f2a
192 #define HI846_REG_PLL_CFG_MIPI2_L 0x0f2b
193
194 #define HI846_REG_UNKNOWN_0F30 0x0f30
195 #define HI846_REG_PLL_CFG_RAMP1_H 0x0f32
196 #define HI846_REG_UNKNOWN_0F36 0x0f36
197 #define HI846_REG_PLL_CFG_MIPI1_H 0x0f38
198
199 #define HI846_REG_UNKNOWN_2008 0x2008
200 #define HI846_REG_UNKNOWN_326E 0x326e
201
202 struct hi846_reg {
203 u16 address;
204 u16 val;
205 };
206
207 struct hi846_reg_list {
208 u32 num_of_regs;
209 const struct hi846_reg *regs;
210 };
211
212 struct hi846_mode {
213 /* Frame width in pixels */
214 u32 width;
215
216 /* Frame height in pixels */
217 u32 height;
218
219 /* Horizontal timing size */
220 u32 llp;
221
222 /* Link frequency needed for this resolution */
223 u8 link_freq_index;
224
225 u16 fps;
226
227 /* Vertical timining size */
228 u16 frame_len;
229
230 const struct hi846_reg_list reg_list_config;
231 const struct hi846_reg_list reg_list_2lane;
232 const struct hi846_reg_list reg_list_4lane;
233
234 /* Position inside of the 3264x2448 pixel array */
235 struct v4l2_rect crop;
236 };
237
238 static const struct hi846_reg hi846_init_2lane[] = {
239 {HI846_REG_MODE_SELECT, 0x0000},
240 /* regs below are unknown */
241 {0x2000, 0x100a},
242 {0x2002, 0x00ff},
243 {0x2004, 0x0007},
244 {0x2006, 0x3fff},
245 {0x2008, 0x3fff},
246 {0x200a, 0xc216},
247 {0x200c, 0x1292},
248 {0x200e, 0xc01a},
249 {0x2010, 0x403d},
250 {0x2012, 0x000e},
251 {0x2014, 0x403e},
252 {0x2016, 0x0b80},
253 {0x2018, 0x403f},
254 {0x201a, 0x82ae},
255 {0x201c, 0x1292},
256 {0x201e, 0xc00c},
257 {0x2020, 0x4130},
258 {0x2022, 0x43e2},
259 {0x2024, 0x0180},
260 {0x2026, 0x4130},
261 {0x2028, 0x7400},
262 {0x202a, 0x5000},
263 {0x202c, 0x0253},
264 {0x202e, 0x0ad1},
265 {0x2030, 0x2360},
266 {0x2032, 0x0009},
267 {0x2034, 0x5020},
268 {0x2036, 0x000b},
269 {0x2038, 0x0002},
270 {0x203a, 0x0044},
271 {0x203c, 0x0016},
272 {0x203e, 0x1792},
273 {0x2040, 0x7002},
274 {0x2042, 0x154f},
275 {0x2044, 0x00d5},
276 {0x2046, 0x000b},
277 {0x2048, 0x0019},
278 {0x204a, 0x1698},
279 {0x204c, 0x000e},
280 {0x204e, 0x099a},
281 {0x2050, 0x0058},
282 {0x2052, 0x7000},
283 {0x2054, 0x1799},
284 {0x2056, 0x0310},
285 {0x2058, 0x03c3},
286 {0x205a, 0x004c},
287 {0x205c, 0x064a},
288 {0x205e, 0x0001},
289 {0x2060, 0x0007},
290 {0x2062, 0x0bc7},
291 {0x2064, 0x0055},
292 {0x2066, 0x7000},
293 {0x2068, 0x1550},
294 {0x206a, 0x158a},
295 {0x206c, 0x0004},
296 {0x206e, 0x1488},
297 {0x2070, 0x7010},
298 {0x2072, 0x1508},
299 {0x2074, 0x0004},
300 {0x2076, 0x0016},
301 {0x2078, 0x03d5},
302 {0x207a, 0x0055},
303 {0x207c, 0x08ca},
304 {0x207e, 0x2019},
305 {0x2080, 0x0007},
306 {0x2082, 0x7057},
307 {0x2084, 0x0fc7},
308 {0x2086, 0x5041},
309 {0x2088, 0x12c8},
310 {0x208a, 0x5060},
311 {0x208c, 0x5080},
312 {0x208e, 0x2084},
313 {0x2090, 0x12c8},
314 {0x2092, 0x7800},
315 {0x2094, 0x0802},
316 {0x2096, 0x040f},
317 {0x2098, 0x1007},
318 {0x209a, 0x0803},
319 {0x209c, 0x080b},
320 {0x209e, 0x3803},
321 {0x20a0, 0x0807},
322 {0x20a2, 0x0404},
323 {0x20a4, 0x0400},
324 {0x20a6, 0xffff},
325 {0x20a8, 0xf0b2},
326 {0x20aa, 0xffef},
327 {0x20ac, 0x0a84},
328 {0x20ae, 0x1292},
329 {0x20b0, 0xc02e},
330 {0x20b2, 0x4130},
331 {0x23fe, 0xc056},
332 {0x3232, 0xfc0c},
333 {0x3236, 0xfc22},
334 {0x3248, 0xfca8},
335 {0x326a, 0x8302},
336 {0x326c, 0x830a},
337 {0x326e, 0x0000},
338 {0x32ca, 0xfc28},
339 {0x32cc, 0xc3bc},
340 {0x32ce, 0xc34c},
341 {0x32d0, 0xc35a},
342 {0x32d2, 0xc368},
343 {0x32d4, 0xc376},
344 {0x32d6, 0xc3c2},
345 {0x32d8, 0xc3e6},
346 {0x32da, 0x0003},
347 {0x32dc, 0x0003},
348 {0x32de, 0x00c7},
349 {0x32e0, 0x0031},
350 {0x32e2, 0x0031},
351 {0x32e4, 0x0031},
352 {0x32e6, 0xfc28},
353 {0x32e8, 0xc3bc},
354 {0x32ea, 0xc384},
355 {0x32ec, 0xc392},
356 {0x32ee, 0xc3a0},
357 {0x32f0, 0xc3ae},
358 {0x32f2, 0xc3c4},
359 {0x32f4, 0xc3e6},
360 {0x32f6, 0x0003},
361 {0x32f8, 0x0003},
362 {0x32fa, 0x00c7},
363 {0x32fc, 0x0031},
364 {0x32fe, 0x0031},
365 {0x3300, 0x0031},
366 {0x3302, 0x82ca},
367 {0x3304, 0xc164},
368 {0x3306, 0x82e6},
369 {0x3308, 0xc19c},
370 {0x330a, 0x001f},
371 {0x330c, 0x001a},
372 {0x330e, 0x0034},
373 {0x3310, 0x0000},
374 {0x3312, 0x0000},
375 {0x3314, 0xfc94},
376 {0x3316, 0xc3d8},
377 /* regs above are unknown */
378 {HI846_REG_MODE_SELECT, 0x0000},
379 {HI846_REG_UNKNOWN_0E04, 0x0012},
380 {HI846_REG_Y_ODD_INC_FOBP, 0x1111},
381 {HI846_REG_Y_ODD_INC_VACT, 0x1111},
382 {HI846_REG_UNKNOWN_0022, 0x0008},
383 {HI846_REG_Y_ADDR_START_VACT_H, 0x0040},
384 {HI846_REG_UNKNOWN_0028, 0x0017},
385 {HI846_REG_Y_ADDR_END_VACT_H, 0x09cf},
386 {HI846_REG_UNKNOWN_005C, 0x2101},
387 {HI846_REG_FLL, 0x09de},
388 {HI846_REG_LLP, 0x0ed8},
389 {HI846_REG_IMAGE_ORIENTATION, 0x0100},
390 {HI846_REG_BINNING_MODE, 0x0022},
391 {HI846_REG_HBIN_MODE, 0x0000},
392 {HI846_REG_UNKNOWN_0A24, 0x0000},
393 {HI846_REG_X_START_H, 0x0000},
394 {HI846_REG_X_OUTPUT_SIZE_H, 0x0cc0},
395 {HI846_REG_Y_OUTPUT_SIZE_H, 0x0990},
396 {HI846_REG_EXPOSURE, 0x09d8},
397 {HI846_REG_ANALOG_GAIN, 0x0000},
398 {HI846_REG_GROUPED_PARA_HOLD, 0x0000},
399 {HI846_REG_UNKNOWN_051E, 0x0000},
400 {HI846_REG_UNKNOWN_0200, 0x0400},
401 {HI846_REG_PEDESTAL_EN, 0x0c00},
402 {HI846_REG_UNKNOWN_0A0C, 0x0010},
403 {HI846_REG_UNKNOWN_0A1E, 0x0ccf},
404 {HI846_REG_UNKNOWN_0402, 0x0110},
405 {HI846_REG_UNKNOWN_0404, 0x00f4},
406 {HI846_REG_UNKNOWN_0408, 0x0000},
407 {HI846_REG_UNKNOWN_0410, 0x008d},
408 {HI846_REG_UNKNOWN_0412, 0x011a},
409 {HI846_REG_UNKNOWN_0414, 0x864c},
410 {HI846_REG_UNKNOWN_021C, 0x0003},
411 {HI846_REG_UNKNOWN_021E, 0x0235},
412 {HI846_REG_BLC_CTL0, 0x9150},
413 {HI846_REG_UNKNOWN_0C06, 0x0021},
414 {HI846_REG_UNKNOWN_0C10, 0x0040},
415 {HI846_REG_UNKNOWN_0C12, 0x0040},
416 {HI846_REG_UNKNOWN_0C14, 0x0040},
417 {HI846_REG_UNKNOWN_0C16, 0x0040},
418 {HI846_REG_FAST_STANDBY_MODE, 0x0100},
419 {HI846_REG_ISP_EN_H, 0x014a},
420 {HI846_REG_UNKNOWN_0418, 0x0000},
421 {HI846_REG_UNKNOWN_012A, 0x03b4},
422 {HI846_REG_X_ADDR_START_HACT_H, 0x0046},
423 {HI846_REG_X_ADDR_END_HACT_H, 0x0376},
424 {HI846_REG_UNKNOWN_0B02, 0xe04d},
425 {HI846_REG_UNKNOWN_0B10, 0x6821},
426 {HI846_REG_UNKNOWN_0B12, 0x0120},
427 {HI846_REG_UNKNOWN_0B14, 0x0001},
428 {HI846_REG_UNKNOWN_2008, 0x38fd},
429 {HI846_REG_UNKNOWN_326E, 0x0000},
430 {HI846_REG_UNKNOWN_0900, 0x0320},
431 {HI846_REG_MIPI_TX_OP_MODE, 0xc31a},
432 {HI846_REG_UNKNOWN_0914, 0xc109},
433 {HI846_REG_TCLK_PREPARE, 0x061a},
434 {HI846_REG_UNKNOWN_0918, 0x0306},
435 {HI846_REG_THS_ZERO, 0x0b09},
436 {HI846_REG_TCLK_POST, 0x0c07},
437 {HI846_REG_UNKNOWN_091E, 0x0a00},
438 {HI846_REG_UNKNOWN_090C, 0x042a},
439 {HI846_REG_UNKNOWN_090E, 0x006b},
440 {HI846_REG_UNKNOWN_0954, 0x0089},
441 {HI846_REG_UNKNOWN_0956, 0x0000},
442 {HI846_REG_UNKNOWN_0958, 0xca00},
443 {HI846_REG_UNKNOWN_095A, 0x9240},
444 {HI846_REG_UNKNOWN_0F08, 0x2f04},
445 {HI846_REG_UNKNOWN_0F30, 0x001f},
446 {HI846_REG_UNKNOWN_0F36, 0x001f},
447 {HI846_REG_UNKNOWN_0F04, 0x3a00},
448 {HI846_REG_PLL_CFG_RAMP1_H, 0x025a},
449 {HI846_REG_PLL_CFG_MIPI1_H, 0x025a},
450 {HI846_REG_PLL_CFG_MIPI2_H, 0x0024},
451 {HI846_REG_UNKNOWN_006A, 0x0100},
452 {HI846_REG_TG_ENABLE, 0x0100},
453 };
454
455 static const struct hi846_reg hi846_init_4lane[] = {
456 {0x2000, 0x987a},
457 {0x2002, 0x00ff},
458 {0x2004, 0x0047},
459 {0x2006, 0x3fff},
460 {0x2008, 0x3fff},
461 {0x200a, 0xc216},
462 {0x200c, 0x1292},
463 {0x200e, 0xc01a},
464 {0x2010, 0x403d},
465 {0x2012, 0x000e},
466 {0x2014, 0x403e},
467 {0x2016, 0x0b80},
468 {0x2018, 0x403f},
469 {0x201a, 0x82ae},
470 {0x201c, 0x1292},
471 {0x201e, 0xc00c},
472 {0x2020, 0x4130},
473 {0x2022, 0x43e2},
474 {0x2024, 0x0180},
475 {0x2026, 0x4130},
476 {0x2028, 0x7400},
477 {0x202a, 0x5000},
478 {0x202c, 0x0253},
479 {0x202e, 0x0ad1},
480 {0x2030, 0x2360},
481 {0x2032, 0x0009},
482 {0x2034, 0x5020},
483 {0x2036, 0x000b},
484 {0x2038, 0x0002},
485 {0x203a, 0x0044},
486 {0x203c, 0x0016},
487 {0x203e, 0x1792},
488 {0x2040, 0x7002},
489 {0x2042, 0x154f},
490 {0x2044, 0x00d5},
491 {0x2046, 0x000b},
492 {0x2048, 0x0019},
493 {0x204a, 0x1698},
494 {0x204c, 0x000e},
495 {0x204e, 0x099a},
496 {0x2050, 0x0058},
497 {0x2052, 0x7000},
498 {0x2054, 0x1799},
499 {0x2056, 0x0310},
500 {0x2058, 0x03c3},
501 {0x205a, 0x004c},
502 {0x205c, 0x064a},
503 {0x205e, 0x0001},
504 {0x2060, 0x0007},
505 {0x2062, 0x0bc7},
506 {0x2064, 0x0055},
507 {0x2066, 0x7000},
508 {0x2068, 0x1550},
509 {0x206a, 0x158a},
510 {0x206c, 0x0004},
511 {0x206e, 0x1488},
512 {0x2070, 0x7010},
513 {0x2072, 0x1508},
514 {0x2074, 0x0004},
515 {0x2076, 0x0016},
516 {0x2078, 0x03d5},
517 {0x207a, 0x0055},
518 {0x207c, 0x08ca},
519 {0x207e, 0x2019},
520 {0x2080, 0x0007},
521 {0x2082, 0x7057},
522 {0x2084, 0x0fc7},
523 {0x2086, 0x5041},
524 {0x2088, 0x12c8},
525 {0x208a, 0x5060},
526 {0x208c, 0x5080},
527 {0x208e, 0x2084},
528 {0x2090, 0x12c8},
529 {0x2092, 0x7800},
530 {0x2094, 0x0802},
531 {0x2096, 0x040f},
532 {0x2098, 0x1007},
533 {0x209a, 0x0803},
534 {0x209c, 0x080b},
535 {0x209e, 0x3803},
536 {0x20a0, 0x0807},
537 {0x20a2, 0x0404},
538 {0x20a4, 0x0400},
539 {0x20a6, 0xffff},
540 {0x20a8, 0xf0b2},
541 {0x20aa, 0xffef},
542 {0x20ac, 0x0a84},
543 {0x20ae, 0x1292},
544 {0x20b0, 0xc02e},
545 {0x20b2, 0x4130},
546 {0x20b4, 0xf0b2},
547 {0x20b6, 0xffbf},
548 {0x20b8, 0x2004},
549 {0x20ba, 0x403f},
550 {0x20bc, 0x00c3},
551 {0x20be, 0x4fe2},
552 {0x20c0, 0x8318},
553 {0x20c2, 0x43cf},
554 {0x20c4, 0x0000},
555 {0x20c6, 0x9382},
556 {0x20c8, 0xc314},
557 {0x20ca, 0x2003},
558 {0x20cc, 0x12b0},
559 {0x20ce, 0xcab0},
560 {0x20d0, 0x4130},
561 {0x20d2, 0x12b0},
562 {0x20d4, 0xc90a},
563 {0x20d6, 0x4130},
564 {0x20d8, 0x42d2},
565 {0x20da, 0x8318},
566 {0x20dc, 0x00c3},
567 {0x20de, 0x9382},
568 {0x20e0, 0xc314},
569 {0x20e2, 0x2009},
570 {0x20e4, 0x120b},
571 {0x20e6, 0x120a},
572 {0x20e8, 0x1209},
573 {0x20ea, 0x1208},
574 {0x20ec, 0x1207},
575 {0x20ee, 0x1206},
576 {0x20f0, 0x4030},
577 {0x20f2, 0xc15e},
578 {0x20f4, 0x4130},
579 {0x20f6, 0x1292},
580 {0x20f8, 0xc008},
581 {0x20fa, 0x4130},
582 {0x20fc, 0x42d2},
583 {0x20fe, 0x82a1},
584 {0x2100, 0x00c2},
585 {0x2102, 0x1292},
586 {0x2104, 0xc040},
587 {0x2106, 0x4130},
588 {0x2108, 0x1292},
589 {0x210a, 0xc006},
590 {0x210c, 0x42a2},
591 {0x210e, 0x7324},
592 {0x2110, 0x9382},
593 {0x2112, 0xc314},
594 {0x2114, 0x2011},
595 {0x2116, 0x425f},
596 {0x2118, 0x82a1},
597 {0x211a, 0xf25f},
598 {0x211c, 0x00c1},
599 {0x211e, 0xf35f},
600 {0x2120, 0x2406},
601 {0x2122, 0x425f},
602 {0x2124, 0x00c0},
603 {0x2126, 0xf37f},
604 {0x2128, 0x522f},
605 {0x212a, 0x4f82},
606 {0x212c, 0x7324},
607 {0x212e, 0x425f},
608 {0x2130, 0x82d4},
609 {0x2132, 0xf35f},
610 {0x2134, 0x4fc2},
611 {0x2136, 0x01b3},
612 {0x2138, 0x93c2},
613 {0x213a, 0x829f},
614 {0x213c, 0x2421},
615 {0x213e, 0x403e},
616 {0x2140, 0xfffe},
617 {0x2142, 0x40b2},
618 {0x2144, 0xec78},
619 {0x2146, 0x831c},
620 {0x2148, 0x40b2},
621 {0x214a, 0xec78},
622 {0x214c, 0x831e},
623 {0x214e, 0x40b2},
624 {0x2150, 0xec78},
625 {0x2152, 0x8320},
626 {0x2154, 0xb3d2},
627 {0x2156, 0x008c},
628 {0x2158, 0x2405},
629 {0x215a, 0x4e0f},
630 {0x215c, 0x503f},
631 {0x215e, 0xffd8},
632 {0x2160, 0x4f82},
633 {0x2162, 0x831c},
634 {0x2164, 0x90f2},
635 {0x2166, 0x0003},
636 {0x2168, 0x008c},
637 {0x216a, 0x2401},
638 {0x216c, 0x4130},
639 {0x216e, 0x421f},
640 {0x2170, 0x831c},
641 {0x2172, 0x5e0f},
642 {0x2174, 0x4f82},
643 {0x2176, 0x831e},
644 {0x2178, 0x5e0f},
645 {0x217a, 0x4f82},
646 {0x217c, 0x8320},
647 {0x217e, 0x3ff6},
648 {0x2180, 0x432e},
649 {0x2182, 0x3fdf},
650 {0x2184, 0x421f},
651 {0x2186, 0x7100},
652 {0x2188, 0x4f0e},
653 {0x218a, 0x503e},
654 {0x218c, 0xffd8},
655 {0x218e, 0x4e82},
656 {0x2190, 0x7a04},
657 {0x2192, 0x421e},
658 {0x2194, 0x831c},
659 {0x2196, 0x5f0e},
660 {0x2198, 0x4e82},
661 {0x219a, 0x7a06},
662 {0x219c, 0x0b00},
663 {0x219e, 0x7304},
664 {0x21a0, 0x0050},
665 {0x21a2, 0x40b2},
666 {0x21a4, 0xd081},
667 {0x21a6, 0x0b88},
668 {0x21a8, 0x421e},
669 {0x21aa, 0x831e},
670 {0x21ac, 0x5f0e},
671 {0x21ae, 0x4e82},
672 {0x21b0, 0x7a0e},
673 {0x21b2, 0x521f},
674 {0x21b4, 0x8320},
675 {0x21b6, 0x4f82},
676 {0x21b8, 0x7a10},
677 {0x21ba, 0x0b00},
678 {0x21bc, 0x7304},
679 {0x21be, 0x007a},
680 {0x21c0, 0x40b2},
681 {0x21c2, 0x0081},
682 {0x21c4, 0x0b88},
683 {0x21c6, 0x4392},
684 {0x21c8, 0x7a0a},
685 {0x21ca, 0x0800},
686 {0x21cc, 0x7a0c},
687 {0x21ce, 0x0b00},
688 {0x21d0, 0x7304},
689 {0x21d2, 0x022b},
690 {0x21d4, 0x40b2},
691 {0x21d6, 0xd081},
692 {0x21d8, 0x0b88},
693 {0x21da, 0x0b00},
694 {0x21dc, 0x7304},
695 {0x21de, 0x0255},
696 {0x21e0, 0x40b2},
697 {0x21e2, 0x0081},
698 {0x21e4, 0x0b88},
699 {0x21e6, 0x4130},
700 {0x23fe, 0xc056},
701 {0x3232, 0xfc0c},
702 {0x3236, 0xfc22},
703 {0x3238, 0xfcfc},
704 {0x323a, 0xfd84},
705 {0x323c, 0xfd08},
706 {0x3246, 0xfcd8},
707 {0x3248, 0xfca8},
708 {0x324e, 0xfcb4},
709 {0x326a, 0x8302},
710 {0x326c, 0x830a},
711 {0x326e, 0x0000},
712 {0x32ca, 0xfc28},
713 {0x32cc, 0xc3bc},
714 {0x32ce, 0xc34c},
715 {0x32d0, 0xc35a},
716 {0x32d2, 0xc368},
717 {0x32d4, 0xc376},
718 {0x32d6, 0xc3c2},
719 {0x32d8, 0xc3e6},
720 {0x32da, 0x0003},
721 {0x32dc, 0x0003},
722 {0x32de, 0x00c7},
723 {0x32e0, 0x0031},
724 {0x32e2, 0x0031},
725 {0x32e4, 0x0031},
726 {0x32e6, 0xfc28},
727 {0x32e8, 0xc3bc},
728 {0x32ea, 0xc384},
729 {0x32ec, 0xc392},
730 {0x32ee, 0xc3a0},
731 {0x32f0, 0xc3ae},
732 {0x32f2, 0xc3c4},
733 {0x32f4, 0xc3e6},
734 {0x32f6, 0x0003},
735 {0x32f8, 0x0003},
736 {0x32fa, 0x00c7},
737 {0x32fc, 0x0031},
738 {0x32fe, 0x0031},
739 {0x3300, 0x0031},
740 {0x3302, 0x82ca},
741 {0x3304, 0xc164},
742 {0x3306, 0x82e6},
743 {0x3308, 0xc19c},
744 {0x330a, 0x001f},
745 {0x330c, 0x001a},
746 {0x330e, 0x0034},
747 {0x3310, 0x0000},
748 {0x3312, 0x0000},
749 {0x3314, 0xfc94},
750 {0x3316, 0xc3d8},
751
752 {0x0a00, 0x0000},
753 {0x0e04, 0x0012},
754 {0x002e, 0x1111},
755 {0x0032, 0x1111},
756 {0x0022, 0x0008},
757 {0x0026, 0x0040},
758 {0x0028, 0x0017},
759 {0x002c, 0x09cf},
760 {0x005c, 0x2101},
761 {0x0006, 0x09de},
762 {0x0008, 0x0ed8},
763 {0x000e, 0x0100},
764 {0x000c, 0x0022},
765 {0x0a22, 0x0000},
766 {0x0a24, 0x0000},
767 {0x0804, 0x0000},
768 {0x0a12, 0x0cc0},
769 {0x0a14, 0x0990},
770 {0x0074, 0x09d8},
771 {0x0076, 0x0000},
772 {0x051e, 0x0000},
773 {0x0200, 0x0400},
774 {0x0a1a, 0x0c00},
775 {0x0a0c, 0x0010},
776 {0x0a1e, 0x0ccf},
777 {0x0402, 0x0110},
778 {0x0404, 0x00f4},
779 {0x0408, 0x0000},
780 {0x0410, 0x008d},
781 {0x0412, 0x011a},
782 {0x0414, 0x864c},
783 /* for OTP */
784 {0x021c, 0x0003},
785 {0x021e, 0x0235},
786 /* for OTP */
787 {0x0c00, 0x9950},
788 {0x0c06, 0x0021},
789 {0x0c10, 0x0040},
790 {0x0c12, 0x0040},
791 {0x0c14, 0x0040},
792 {0x0c16, 0x0040},
793 {0x0a02, 0x0100},
794 {0x0a04, 0x015a},
795 {0x0418, 0x0000},
796 {0x0128, 0x0028},
797 {0x012a, 0xffff},
798 {0x0120, 0x0046},
799 {0x0122, 0x0376},
800 {0x012c, 0x0020},
801 {0x012e, 0xffff},
802 {0x0124, 0x0040},
803 {0x0126, 0x0378},
804 {0x0746, 0x0050},
805 {0x0748, 0x01d5},
806 {0x074a, 0x022b},
807 {0x074c, 0x03b0},
808 {0x0756, 0x043f},
809 {0x0758, 0x3f1d},
810 {0x0b02, 0xe04d},
811 {0x0b10, 0x6821},
812 {0x0b12, 0x0120},
813 {0x0b14, 0x0001},
814 {0x2008, 0x38fd},
815 {0x326e, 0x0000},
816 {0x0900, 0x0300},
817 {0x0902, 0xc319},
818 {0x0914, 0xc109},
819 {0x0916, 0x061a},
820 {0x0918, 0x0407},
821 {0x091a, 0x0a0b},
822 {0x091c, 0x0e08},
823 {0x091e, 0x0a00},
824 {0x090c, 0x0427},
825 {0x090e, 0x0059},
826 {0x0954, 0x0089},
827 {0x0956, 0x0000},
828 {0x0958, 0xca80},
829 {0x095a, 0x9240},
830 {0x0f08, 0x2f04},
831 {0x0f30, 0x001f},
832 {0x0f36, 0x001f},
833 {0x0f04, 0x3a00},
834 {0x0f32, 0x025a},
835 {0x0f38, 0x025a},
836 {0x0f2a, 0x4124},
837 {0x006a, 0x0100},
838 {0x004c, 0x0100},
839 {0x0044, 0x0001},
840 };
841
842 static const struct hi846_reg mode_640x480_config[] = {
843 {HI846_REG_MODE_SELECT, 0x0000},
844 {HI846_REG_Y_ODD_INC_FOBP, 0x7711},
845 {HI846_REG_Y_ODD_INC_VACT, 0x7711},
846 {HI846_REG_Y_ADDR_START_VACT_H, 0x0148},
847 {HI846_REG_Y_ADDR_END_VACT_H, 0x08c7},
848 {HI846_REG_UNKNOWN_005C, 0x4404},
849 {HI846_REG_FLL, 0x0277},
850 {HI846_REG_LLP, 0x0ed8},
851 {HI846_REG_BINNING_MODE, 0x0322},
852 {HI846_REG_HBIN_MODE, 0x0200},
853 {HI846_REG_UNKNOWN_0A24, 0x0000},
854 {HI846_REG_X_START_H, 0x0058},
855 {HI846_REG_X_OUTPUT_SIZE_H, 0x0280},
856 {HI846_REG_Y_OUTPUT_SIZE_H, 0x01e0},
857
858 /* For OTP */
859 {HI846_REG_UNKNOWN_021C, 0x0003},
860 {HI846_REG_UNKNOWN_021E, 0x0235},
861
862 {HI846_REG_ISP_EN_H, 0x016a},
863 {HI846_REG_UNKNOWN_0418, 0x0210},
864 {HI846_REG_UNKNOWN_0B02, 0xe04d},
865 {HI846_REG_UNKNOWN_0B10, 0x7021},
866 {HI846_REG_UNKNOWN_0B12, 0x0120},
867 {HI846_REG_UNKNOWN_0B14, 0x0001},
868 {HI846_REG_UNKNOWN_2008, 0x38fd},
869 {HI846_REG_UNKNOWN_326E, 0x0000},
870 };
871
872 static const struct hi846_reg mode_640x480_mipi_2lane[] = {
873 {HI846_REG_UNKNOWN_0900, 0x0300},
874 {HI846_REG_MIPI_TX_OP_MODE, 0x4319},
875 {HI846_REG_UNKNOWN_0914, 0xc105},
876 {HI846_REG_TCLK_PREPARE, 0x030c},
877 {HI846_REG_UNKNOWN_0918, 0x0304},
878 {HI846_REG_THS_ZERO, 0x0708},
879 {HI846_REG_TCLK_POST, 0x0b04},
880 {HI846_REG_UNKNOWN_091E, 0x0500},
881 {HI846_REG_UNKNOWN_090C, 0x0208},
882 {HI846_REG_UNKNOWN_090E, 0x009a},
883 {HI846_REG_UNKNOWN_0954, 0x0089},
884 {HI846_REG_UNKNOWN_0956, 0x0000},
885 {HI846_REG_UNKNOWN_0958, 0xca80},
886 {HI846_REG_UNKNOWN_095A, 0x9240},
887 {HI846_REG_PLL_CFG_MIPI2_H, 0x4924},
888 {HI846_REG_TG_ENABLE, 0x0100},
889 };
890
891 static const struct hi846_reg mode_1280x720_config[] = {
892 {HI846_REG_MODE_SELECT, 0x0000},
893 {HI846_REG_Y_ODD_INC_FOBP, 0x3311},
894 {HI846_REG_Y_ODD_INC_VACT, 0x3311},
895 {HI846_REG_Y_ADDR_START_VACT_H, 0x0238},
896 {HI846_REG_Y_ADDR_END_VACT_H, 0x07d7},
897 {HI846_REG_UNKNOWN_005C, 0x4202},
898 {HI846_REG_FLL, 0x034a},
899 {HI846_REG_LLP, 0x0ed8},
900 {HI846_REG_BINNING_MODE, 0x0122},
901 {HI846_REG_HBIN_MODE, 0x0100},
902 {HI846_REG_UNKNOWN_0A24, 0x0000},
903 {HI846_REG_X_START_H, 0x00b0},
904 {HI846_REG_X_OUTPUT_SIZE_H, 0x0500},
905 {HI846_REG_Y_OUTPUT_SIZE_H, 0x02d0},
906 {HI846_REG_EXPOSURE, 0x0344},
907
908 /* For OTP */
909 {HI846_REG_UNKNOWN_021C, 0x0003},
910 {HI846_REG_UNKNOWN_021E, 0x0235},
911
912 {HI846_REG_ISP_EN_H, 0x016a},
913 {HI846_REG_UNKNOWN_0418, 0x0410},
914 {HI846_REG_UNKNOWN_0B02, 0xe04d},
915 {HI846_REG_UNKNOWN_0B10, 0x6c21},
916 {HI846_REG_UNKNOWN_0B12, 0x0120},
917 {HI846_REG_UNKNOWN_0B14, 0x0005},
918 {HI846_REG_UNKNOWN_2008, 0x38fd},
919 {HI846_REG_UNKNOWN_326E, 0x0000},
920 };
921
922 static const struct hi846_reg mode_1280x720_mipi_2lane[] = {
923 {HI846_REG_UNKNOWN_0900, 0x0300},
924 {HI846_REG_MIPI_TX_OP_MODE, 0x4319},
925 {HI846_REG_UNKNOWN_0914, 0xc109},
926 {HI846_REG_TCLK_PREPARE, 0x061a},
927 {HI846_REG_UNKNOWN_0918, 0x0407},
928 {HI846_REG_THS_ZERO, 0x0a0b},
929 {HI846_REG_TCLK_POST, 0x0e08},
930 {HI846_REG_UNKNOWN_091E, 0x0a00},
931 {HI846_REG_UNKNOWN_090C, 0x0427},
932 {HI846_REG_UNKNOWN_090E, 0x0145},
933 {HI846_REG_UNKNOWN_0954, 0x0089},
934 {HI846_REG_UNKNOWN_0956, 0x0000},
935 {HI846_REG_UNKNOWN_0958, 0xca80},
936 {HI846_REG_UNKNOWN_095A, 0x9240},
937 {HI846_REG_PLL_CFG_MIPI2_H, 0x4124},
938 {HI846_REG_TG_ENABLE, 0x0100},
939 };
940
941 static const struct hi846_reg mode_1280x720_mipi_4lane[] = {
942 /* 360Mbps */
943 {HI846_REG_UNKNOWN_0900, 0x0300},
944 {HI846_REG_MIPI_TX_OP_MODE, 0xc319},
945 {HI846_REG_UNKNOWN_0914, 0xc105},
946 {HI846_REG_TCLK_PREPARE, 0x030c},
947 {HI846_REG_UNKNOWN_0918, 0x0304},
948 {HI846_REG_THS_ZERO, 0x0708},
949 {HI846_REG_TCLK_POST, 0x0b04},
950 {HI846_REG_UNKNOWN_091E, 0x0500},
951 {HI846_REG_UNKNOWN_090C, 0x0208},
952 {HI846_REG_UNKNOWN_090E, 0x008a},
953 {HI846_REG_UNKNOWN_0954, 0x0089},
954 {HI846_REG_UNKNOWN_0956, 0x0000},
955 {HI846_REG_UNKNOWN_0958, 0xca80},
956 {HI846_REG_UNKNOWN_095A, 0x9240},
957 {HI846_REG_PLL_CFG_MIPI2_H, 0x4924},
958 {HI846_REG_TG_ENABLE, 0x0100},
959 };
960
961 static const struct hi846_reg mode_1632x1224_config[] = {
962 {HI846_REG_MODE_SELECT, 0x0000},
963 {HI846_REG_Y_ODD_INC_FOBP, 0x3311},
964 {HI846_REG_Y_ODD_INC_VACT, 0x3311},
965 {HI846_REG_Y_ADDR_START_VACT_H, 0x0040},
966 {HI846_REG_Y_ADDR_END_VACT_H, 0x09cf},
967 {HI846_REG_UNKNOWN_005C, 0x4202},
968 {HI846_REG_FLL, 0x09de},
969 {HI846_REG_LLP, 0x0ed8},
970 {HI846_REG_BINNING_MODE, 0x0122},
971 {HI846_REG_HBIN_MODE, 0x0100},
972 {HI846_REG_UNKNOWN_0A24, 0x0000},
973 {HI846_REG_X_START_H, 0x0000},
974 {HI846_REG_X_OUTPUT_SIZE_H, 0x0660},
975 {HI846_REG_Y_OUTPUT_SIZE_H, 0x04c8},
976 {HI846_REG_EXPOSURE, 0x09d8},
977
978 /* For OTP */
979 {HI846_REG_UNKNOWN_021C, 0x0003},
980 {HI846_REG_UNKNOWN_021E, 0x0235},
981
982 {HI846_REG_ISP_EN_H, 0x016a},
983 {HI846_REG_UNKNOWN_0418, 0x0000},
984 {HI846_REG_UNKNOWN_0B02, 0xe04d},
985 {HI846_REG_UNKNOWN_0B10, 0x6c21},
986 {HI846_REG_UNKNOWN_0B12, 0x0120},
987 {HI846_REG_UNKNOWN_0B14, 0x0005},
988 {HI846_REG_UNKNOWN_2008, 0x38fd},
989 {HI846_REG_UNKNOWN_326E, 0x0000},
990 };
991
992 static const struct hi846_reg mode_1632x1224_mipi_2lane[] = {
993 {HI846_REG_UNKNOWN_0900, 0x0300},
994 {HI846_REG_MIPI_TX_OP_MODE, 0x4319},
995 {HI846_REG_UNKNOWN_0914, 0xc109},
996 {HI846_REG_TCLK_PREPARE, 0x061a},
997 {HI846_REG_UNKNOWN_0918, 0x0407},
998 {HI846_REG_THS_ZERO, 0x0a0b},
999 {HI846_REG_TCLK_POST, 0x0e08},
1000 {HI846_REG_UNKNOWN_091E, 0x0a00},
1001 {HI846_REG_UNKNOWN_090C, 0x0427},
1002 {HI846_REG_UNKNOWN_090E, 0x0069},
1003 {HI846_REG_UNKNOWN_0954, 0x0089},
1004 {HI846_REG_UNKNOWN_0956, 0x0000},
1005 {HI846_REG_UNKNOWN_0958, 0xca80},
1006 {HI846_REG_UNKNOWN_095A, 0x9240},
1007 {HI846_REG_PLL_CFG_MIPI2_H, 0x4124},
1008 {HI846_REG_TG_ENABLE, 0x0100},
1009 };
1010
1011 static const struct hi846_reg mode_1632x1224_mipi_4lane[] = {
1012 {HI846_REG_UNKNOWN_0900, 0x0300},
1013 {HI846_REG_MIPI_TX_OP_MODE, 0xc319},
1014 {HI846_REG_UNKNOWN_0914, 0xc105},
1015 {HI846_REG_TCLK_PREPARE, 0x030c},
1016 {HI846_REG_UNKNOWN_0918, 0x0304},
1017 {HI846_REG_THS_ZERO, 0x0708},
1018 {HI846_REG_TCLK_POST, 0x0b04},
1019 {HI846_REG_UNKNOWN_091E, 0x0500},
1020 {HI846_REG_UNKNOWN_090C, 0x0208},
1021 {HI846_REG_UNKNOWN_090E, 0x001c},
1022 {HI846_REG_UNKNOWN_0954, 0x0089},
1023 {HI846_REG_UNKNOWN_0956, 0x0000},
1024 {HI846_REG_UNKNOWN_0958, 0xca80},
1025 {HI846_REG_UNKNOWN_095A, 0x9240},
1026 {HI846_REG_PLL_CFG_MIPI2_H, 0x4924},
1027 {HI846_REG_TG_ENABLE, 0x0100},
1028 };
1029
1030 static const char * const hi846_test_pattern_menu[] = {
1031 "Disabled",
1032 "Solid Colour",
1033 "100% Colour Bars",
1034 "Fade To Grey Colour Bars",
1035 "PN9",
1036 "Gradient Horizontal",
1037 "Gradient Vertical",
1038 "Check Board",
1039 "Slant Pattern",
1040 "Resolution Pattern",
1041 };
1042
1043 #define FREQ_INDEX_640 0
1044 #define FREQ_INDEX_1280 1
1045 static const s64 hi846_link_freqs[] = {
1046 [FREQ_INDEX_640] = 80000000,
1047 [FREQ_INDEX_1280] = 200000000,
1048 };
1049
1050 static const struct hi846_reg_list hi846_init_regs_list_2lane = {
1051 .num_of_regs = ARRAY_SIZE(hi846_init_2lane),
1052 .regs = hi846_init_2lane,
1053 };
1054
1055 static const struct hi846_reg_list hi846_init_regs_list_4lane = {
1056 .num_of_regs = ARRAY_SIZE(hi846_init_4lane),
1057 .regs = hi846_init_4lane,
1058 };
1059
1060 static const struct hi846_mode supported_modes[] = {
1061 {
1062 .width = 640,
1063 .height = 480,
1064 .link_freq_index = FREQ_INDEX_640,
1065 .fps = 120,
1066 .frame_len = 631,
1067 .llp = HI846_LINE_LENGTH,
1068 .reg_list_config = {
1069 .num_of_regs = ARRAY_SIZE(mode_640x480_config),
1070 .regs = mode_640x480_config,
1071 },
1072 .reg_list_2lane = {
1073 .num_of_regs = ARRAY_SIZE(mode_640x480_mipi_2lane),
1074 .regs = mode_640x480_mipi_2lane,
1075 },
1076 .reg_list_4lane = {
1077 .num_of_regs = 0,
1078 },
1079 .crop = {
1080 .left = 0x58,
1081 .top = 0x148,
1082 .width = 640 * 4,
1083 .height = 480 * 4,
1084 },
1085 },
1086 {
1087 .width = 1280,
1088 .height = 720,
1089 .link_freq_index = FREQ_INDEX_1280,
1090 .fps = 90,
1091 .frame_len = 842,
1092 .llp = HI846_LINE_LENGTH,
1093 .reg_list_config = {
1094 .num_of_regs = ARRAY_SIZE(mode_1280x720_config),
1095 .regs = mode_1280x720_config,
1096 },
1097 .reg_list_2lane = {
1098 .num_of_regs = ARRAY_SIZE(mode_1280x720_mipi_2lane),
1099 .regs = mode_1280x720_mipi_2lane,
1100 },
1101 .reg_list_4lane = {
1102 .num_of_regs = ARRAY_SIZE(mode_1280x720_mipi_4lane),
1103 .regs = mode_1280x720_mipi_4lane,
1104 },
1105 .crop = {
1106 .left = 0xb0,
1107 .top = 0x238,
1108 .width = 1280 * 2,
1109 .height = 720 * 2,
1110 },
1111 },
1112 {
1113 .width = 1632,
1114 .height = 1224,
1115 .link_freq_index = FREQ_INDEX_1280,
1116 .fps = 30,
1117 .frame_len = 2526,
1118 .llp = HI846_LINE_LENGTH,
1119 .reg_list_config = {
1120 .num_of_regs = ARRAY_SIZE(mode_1632x1224_config),
1121 .regs = mode_1632x1224_config,
1122 },
1123 .reg_list_2lane = {
1124 .num_of_regs = ARRAY_SIZE(mode_1632x1224_mipi_2lane),
1125 .regs = mode_1632x1224_mipi_2lane,
1126 },
1127 .reg_list_4lane = {
1128 .num_of_regs = ARRAY_SIZE(mode_1632x1224_mipi_4lane),
1129 .regs = mode_1632x1224_mipi_4lane,
1130 },
1131 .crop = {
1132 .left = 0x0,
1133 .top = 0x0,
1134 .width = 1632 * 2,
1135 .height = 1224 * 2,
1136 },
1137 }
1138 };
1139
1140 struct hi846_datafmt {
1141 u32 code;
1142 enum v4l2_colorspace colorspace;
1143 };
1144
1145 static const char * const hi846_supply_names[] = {
1146 "vddio", /* Digital I/O (1.8V or 2.8V) */
1147 "vdda", /* Analog (2.8V) */
1148 "vddd", /* Digital Core (1.2V) */
1149 };
1150
1151 #define HI846_NUM_SUPPLIES ARRAY_SIZE(hi846_supply_names)
1152
1153 struct hi846 {
1154 struct gpio_desc *rst_gpio;
1155 struct gpio_desc *shutdown_gpio;
1156 struct regulator_bulk_data supplies[HI846_NUM_SUPPLIES];
1157 struct clk *clock;
1158 const struct hi846_datafmt *fmt;
1159 struct v4l2_subdev sd;
1160 struct media_pad pad;
1161 struct v4l2_ctrl_handler ctrl_handler;
1162 u8 nr_lanes;
1163
1164 struct v4l2_ctrl *link_freq;
1165 struct v4l2_ctrl *pixel_rate;
1166 struct v4l2_ctrl *vblank;
1167 struct v4l2_ctrl *hblank;
1168 struct v4l2_ctrl *exposure;
1169
1170 struct mutex mutex; /* protect cur_mode, streaming and chip access */
1171 const struct hi846_mode *cur_mode;
1172 bool streaming;
1173 };
1174
to_hi846(struct v4l2_subdev * sd)1175 static inline struct hi846 *to_hi846(struct v4l2_subdev *sd)
1176 {
1177 return container_of(sd, struct hi846, sd);
1178 }
1179
1180 static const struct hi846_datafmt hi846_colour_fmts[] = {
1181 { HI846_MEDIA_BUS_FORMAT, V4L2_COLORSPACE_RAW },
1182 };
1183
hi846_find_datafmt(u32 code)1184 static const struct hi846_datafmt *hi846_find_datafmt(u32 code)
1185 {
1186 unsigned int i;
1187
1188 for (i = 0; i < ARRAY_SIZE(hi846_colour_fmts); i++)
1189 if (hi846_colour_fmts[i].code == code)
1190 return &hi846_colour_fmts[i];
1191
1192 return NULL;
1193 }
1194
hi846_get_link_freq_index(struct hi846 * hi846)1195 static inline u8 hi846_get_link_freq_index(struct hi846 *hi846)
1196 {
1197 return hi846->cur_mode->link_freq_index;
1198 }
1199
hi846_get_link_freq(struct hi846 * hi846)1200 static u64 hi846_get_link_freq(struct hi846 *hi846)
1201 {
1202 u8 index = hi846_get_link_freq_index(hi846);
1203
1204 return hi846_link_freqs[index];
1205 }
1206
hi846_calc_pixel_rate(struct hi846 * hi846)1207 static u64 hi846_calc_pixel_rate(struct hi846 *hi846)
1208 {
1209 u64 link_freq = hi846_get_link_freq(hi846);
1210 u64 pixel_rate = link_freq * 2 * hi846->nr_lanes;
1211
1212 do_div(pixel_rate, HI846_RGB_DEPTH);
1213
1214 return pixel_rate;
1215 }
1216
hi846_read_reg(struct hi846 * hi846,u16 reg,u8 * val)1217 static int hi846_read_reg(struct hi846 *hi846, u16 reg, u8 *val)
1218 {
1219 struct i2c_client *client = v4l2_get_subdevdata(&hi846->sd);
1220 struct i2c_msg msgs[2];
1221 u8 addr_buf[2];
1222 u8 data_buf[1] = {0};
1223 int ret;
1224
1225 put_unaligned_be16(reg, addr_buf);
1226 msgs[0].addr = client->addr;
1227 msgs[0].flags = 0;
1228 msgs[0].len = sizeof(addr_buf);
1229 msgs[0].buf = addr_buf;
1230 msgs[1].addr = client->addr;
1231 msgs[1].flags = I2C_M_RD;
1232 msgs[1].len = 1;
1233 msgs[1].buf = data_buf;
1234
1235 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
1236 if (ret != ARRAY_SIZE(msgs)) {
1237 dev_err(&client->dev, "i2c read error: %d\n", ret);
1238 return -EIO;
1239 }
1240
1241 *val = data_buf[0];
1242
1243 return 0;
1244 }
1245
hi846_write_reg(struct hi846 * hi846,u16 reg,u8 val)1246 static int hi846_write_reg(struct hi846 *hi846, u16 reg, u8 val)
1247 {
1248 struct i2c_client *client = v4l2_get_subdevdata(&hi846->sd);
1249 u8 buf[3] = { reg >> 8, reg & 0xff, val };
1250 struct i2c_msg msg[] = {
1251 { .addr = client->addr, .flags = 0,
1252 .len = ARRAY_SIZE(buf), .buf = buf },
1253 };
1254 int ret;
1255
1256 ret = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg));
1257 if (ret != ARRAY_SIZE(msg)) {
1258 dev_err(&client->dev, "i2c write error\n");
1259 return -EIO;
1260 }
1261
1262 return 0;
1263 }
1264
hi846_write_reg_16(struct hi846 * hi846,u16 reg,u16 val,int * err)1265 static void hi846_write_reg_16(struct hi846 *hi846, u16 reg, u16 val, int *err)
1266 {
1267 struct i2c_client *client = v4l2_get_subdevdata(&hi846->sd);
1268 u8 buf[4];
1269 int ret;
1270
1271 if (*err < 0)
1272 return;
1273
1274 put_unaligned_be16(reg, buf);
1275 put_unaligned_be16(val, buf + 2);
1276 ret = i2c_master_send(client, buf, sizeof(buf));
1277 if (ret != sizeof(buf)) {
1278 dev_err(&client->dev, "i2c_master_send != %zu: %d\n",
1279 sizeof(buf), ret);
1280 *err = -EIO;
1281 }
1282 }
1283
hi846_write_reg_list(struct hi846 * hi846,const struct hi846_reg_list * r_list)1284 static int hi846_write_reg_list(struct hi846 *hi846,
1285 const struct hi846_reg_list *r_list)
1286 {
1287 struct i2c_client *client = v4l2_get_subdevdata(&hi846->sd);
1288 unsigned int i;
1289 int ret = 0;
1290
1291 for (i = 0; i < r_list->num_of_regs; i++) {
1292 hi846_write_reg_16(hi846, r_list->regs[i].address,
1293 r_list->regs[i].val, &ret);
1294 if (ret) {
1295 dev_err_ratelimited(&client->dev,
1296 "failed to write reg 0x%4.4x: %d",
1297 r_list->regs[i].address, ret);
1298 return ret;
1299 }
1300 }
1301
1302 return 0;
1303 }
1304
hi846_update_digital_gain(struct hi846 * hi846,u16 d_gain)1305 static int hi846_update_digital_gain(struct hi846 *hi846, u16 d_gain)
1306 {
1307 int ret = 0;
1308
1309 hi846_write_reg_16(hi846, HI846_REG_MWB_GR_GAIN_H, d_gain, &ret);
1310 hi846_write_reg_16(hi846, HI846_REG_MWB_GB_GAIN_H, d_gain, &ret);
1311 hi846_write_reg_16(hi846, HI846_REG_MWB_R_GAIN_H, d_gain, &ret);
1312 hi846_write_reg_16(hi846, HI846_REG_MWB_B_GAIN_H, d_gain, &ret);
1313
1314 return ret;
1315 }
1316
hi846_test_pattern(struct hi846 * hi846,u32 pattern)1317 static int hi846_test_pattern(struct hi846 *hi846, u32 pattern)
1318 {
1319 int ret;
1320 u8 val;
1321
1322 if (pattern) {
1323 ret = hi846_read_reg(hi846, HI846_REG_ISP, &val);
1324 if (ret)
1325 return ret;
1326
1327 ret = hi846_write_reg(hi846, HI846_REG_ISP,
1328 val | HI846_REG_ISP_TPG_EN);
1329 if (ret)
1330 return ret;
1331 }
1332
1333 return hi846_write_reg(hi846, HI846_REG_TEST_PATTERN, pattern);
1334 }
1335
hi846_set_ctrl(struct v4l2_ctrl * ctrl)1336 static int hi846_set_ctrl(struct v4l2_ctrl *ctrl)
1337 {
1338 struct hi846 *hi846 = container_of(ctrl->handler,
1339 struct hi846, ctrl_handler);
1340 struct i2c_client *client = v4l2_get_subdevdata(&hi846->sd);
1341 s64 exposure_max;
1342 int ret = 0;
1343 u32 shutter, frame_len;
1344
1345 /* Propagate change of current control to all related controls */
1346 if (ctrl->id == V4L2_CID_VBLANK) {
1347 /* Update max exposure while meeting expected vblanking */
1348 exposure_max = hi846->cur_mode->height + ctrl->val -
1349 HI846_EXPOSURE_MAX_MARGIN;
1350 __v4l2_ctrl_modify_range(hi846->exposure,
1351 hi846->exposure->minimum,
1352 exposure_max, hi846->exposure->step,
1353 exposure_max);
1354 }
1355
1356 ret = pm_runtime_get_if_in_use(&client->dev);
1357 if (!ret || ret == -EAGAIN)
1358 return 0;
1359
1360 switch (ctrl->id) {
1361 case V4L2_CID_ANALOGUE_GAIN:
1362 ret = hi846_write_reg(hi846, HI846_REG_ANALOG_GAIN, ctrl->val);
1363 break;
1364
1365 case V4L2_CID_DIGITAL_GAIN:
1366 ret = hi846_update_digital_gain(hi846, ctrl->val);
1367 break;
1368
1369 case V4L2_CID_EXPOSURE:
1370 shutter = ctrl->val;
1371 frame_len = hi846->cur_mode->frame_len;
1372
1373 if (shutter > frame_len - 6) { /* margin */
1374 frame_len = shutter + 6;
1375 if (frame_len > 0xffff) { /* max frame len */
1376 frame_len = 0xffff;
1377 }
1378 }
1379
1380 if (shutter < 6)
1381 shutter = 6;
1382 if (shutter > (0xffff - 6))
1383 shutter = 0xffff - 6;
1384
1385 hi846_write_reg_16(hi846, HI846_REG_FLL, frame_len, &ret);
1386 hi846_write_reg_16(hi846, HI846_REG_EXPOSURE, shutter, &ret);
1387 break;
1388
1389 case V4L2_CID_VBLANK:
1390 /* Update FLL that meets expected vertical blanking */
1391 hi846_write_reg_16(hi846, HI846_REG_FLL,
1392 hi846->cur_mode->height + ctrl->val, &ret);
1393 break;
1394 case V4L2_CID_TEST_PATTERN:
1395 ret = hi846_test_pattern(hi846, ctrl->val);
1396 break;
1397
1398 default:
1399 ret = -EINVAL;
1400 break;
1401 }
1402
1403 pm_runtime_put(&client->dev);
1404
1405 return ret;
1406 }
1407
1408 static const struct v4l2_ctrl_ops hi846_ctrl_ops = {
1409 .s_ctrl = hi846_set_ctrl,
1410 };
1411
hi846_init_controls(struct hi846 * hi846)1412 static int hi846_init_controls(struct hi846 *hi846)
1413 {
1414 struct v4l2_ctrl_handler *ctrl_hdlr;
1415 s64 exposure_max, h_blank;
1416 int ret;
1417 struct i2c_client *client = v4l2_get_subdevdata(&hi846->sd);
1418 struct v4l2_fwnode_device_properties props;
1419
1420 ctrl_hdlr = &hi846->ctrl_handler;
1421 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 10);
1422 if (ret)
1423 return ret;
1424
1425 ctrl_hdlr->lock = &hi846->mutex;
1426
1427 hi846->link_freq =
1428 v4l2_ctrl_new_int_menu(ctrl_hdlr, &hi846_ctrl_ops,
1429 V4L2_CID_LINK_FREQ,
1430 ARRAY_SIZE(hi846_link_freqs) - 1,
1431 0, hi846_link_freqs);
1432 if (hi846->link_freq)
1433 hi846->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1434
1435 hi846->pixel_rate =
1436 v4l2_ctrl_new_std(ctrl_hdlr, &hi846_ctrl_ops,
1437 V4L2_CID_PIXEL_RATE, 0,
1438 hi846_calc_pixel_rate(hi846), 1,
1439 hi846_calc_pixel_rate(hi846));
1440 hi846->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &hi846_ctrl_ops,
1441 V4L2_CID_VBLANK,
1442 hi846->cur_mode->frame_len -
1443 hi846->cur_mode->height,
1444 HI846_FLL_MAX -
1445 hi846->cur_mode->height, 1,
1446 hi846->cur_mode->frame_len -
1447 hi846->cur_mode->height);
1448
1449 h_blank = hi846->cur_mode->llp - hi846->cur_mode->width;
1450
1451 hi846->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &hi846_ctrl_ops,
1452 V4L2_CID_HBLANK, h_blank, h_blank, 1,
1453 h_blank);
1454 if (hi846->hblank)
1455 hi846->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1456
1457 v4l2_ctrl_new_std(ctrl_hdlr, &hi846_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
1458 HI846_ANAL_GAIN_MIN, HI846_ANAL_GAIN_MAX,
1459 HI846_ANAL_GAIN_STEP, HI846_ANAL_GAIN_MIN);
1460 v4l2_ctrl_new_std(ctrl_hdlr, &hi846_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
1461 HI846_DGTL_GAIN_MIN, HI846_DGTL_GAIN_MAX,
1462 HI846_DGTL_GAIN_STEP, HI846_DGTL_GAIN_DEFAULT);
1463 exposure_max = hi846->cur_mode->frame_len - HI846_EXPOSURE_MAX_MARGIN;
1464 hi846->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &hi846_ctrl_ops,
1465 V4L2_CID_EXPOSURE,
1466 HI846_EXPOSURE_MIN, exposure_max,
1467 HI846_EXPOSURE_STEP,
1468 exposure_max);
1469 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &hi846_ctrl_ops,
1470 V4L2_CID_TEST_PATTERN,
1471 ARRAY_SIZE(hi846_test_pattern_menu) - 1,
1472 0, 0, hi846_test_pattern_menu);
1473 if (ctrl_hdlr->error) {
1474 dev_err(&client->dev, "v4l ctrl handler error: %d\n",
1475 ctrl_hdlr->error);
1476 ret = ctrl_hdlr->error;
1477 goto error;
1478 }
1479
1480 ret = v4l2_fwnode_device_parse(&client->dev, &props);
1481 if (ret)
1482 goto error;
1483
1484 ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &hi846_ctrl_ops,
1485 &props);
1486 if (ret)
1487 goto error;
1488
1489 hi846->sd.ctrl_handler = ctrl_hdlr;
1490
1491 return 0;
1492
1493 error:
1494 v4l2_ctrl_handler_free(ctrl_hdlr);
1495 return ret;
1496 }
1497
hi846_set_video_mode(struct hi846 * hi846,int fps)1498 static int hi846_set_video_mode(struct hi846 *hi846, int fps)
1499 {
1500 struct i2c_client *client = v4l2_get_subdevdata(&hi846->sd);
1501 u64 frame_length;
1502 int ret = 0;
1503 int dummy_lines;
1504 u64 link_freq = hi846_get_link_freq(hi846);
1505
1506 dev_dbg(&client->dev, "%s: link freq: %llu\n", __func__,
1507 hi846_get_link_freq(hi846));
1508
1509 do_div(link_freq, fps);
1510 frame_length = link_freq;
1511 do_div(frame_length, HI846_LINE_LENGTH);
1512
1513 dummy_lines = (frame_length > hi846->cur_mode->frame_len) ?
1514 (frame_length - hi846->cur_mode->frame_len) : 0;
1515
1516 frame_length = hi846->cur_mode->frame_len + dummy_lines;
1517
1518 dev_dbg(&client->dev, "%s: frame length calculated: %llu\n", __func__,
1519 frame_length);
1520
1521 hi846_write_reg_16(hi846, HI846_REG_FLL, frame_length & 0xFFFF, &ret);
1522 hi846_write_reg_16(hi846, HI846_REG_LLP,
1523 HI846_LINE_LENGTH & 0xFFFF, &ret);
1524
1525 return ret;
1526 }
1527
hi846_start_streaming(struct hi846 * hi846)1528 static int hi846_start_streaming(struct hi846 *hi846)
1529 {
1530 struct i2c_client *client = v4l2_get_subdevdata(&hi846->sd);
1531 int ret = 0;
1532 u8 val;
1533
1534 if (hi846->nr_lanes == 2)
1535 ret = hi846_write_reg_list(hi846, &hi846_init_regs_list_2lane);
1536 else
1537 ret = hi846_write_reg_list(hi846, &hi846_init_regs_list_4lane);
1538 if (ret) {
1539 dev_err(&client->dev, "failed to set plls: %d\n", ret);
1540 return ret;
1541 }
1542
1543 ret = hi846_write_reg_list(hi846, &hi846->cur_mode->reg_list_config);
1544 if (ret) {
1545 dev_err(&client->dev, "failed to set mode: %d\n", ret);
1546 return ret;
1547 }
1548
1549 if (hi846->nr_lanes == 2)
1550 ret = hi846_write_reg_list(hi846,
1551 &hi846->cur_mode->reg_list_2lane);
1552 else
1553 ret = hi846_write_reg_list(hi846,
1554 &hi846->cur_mode->reg_list_4lane);
1555 if (ret) {
1556 dev_err(&client->dev, "failed to set mipi mode: %d\n", ret);
1557 return ret;
1558 }
1559
1560 hi846_set_video_mode(hi846, hi846->cur_mode->fps);
1561
1562 ret = __v4l2_ctrl_handler_setup(hi846->sd.ctrl_handler);
1563 if (ret)
1564 return ret;
1565
1566 /*
1567 * Reading 0x0034 is purely done for debugging reasons: It is not
1568 * documented in the DS but only mentioned once:
1569 * "If 0x0034[2] bit is disabled , Visible pixel width and height is 0."
1570 * So even though that sounds like we won't see anything, we don't
1571 * know more about this, so in that case only inform the user but do
1572 * nothing more.
1573 */
1574 ret = hi846_read_reg(hi846, 0x0034, &val);
1575 if (ret)
1576 return ret;
1577 if (!(val & BIT(2)))
1578 dev_info(&client->dev, "visible pixel width and height is 0\n");
1579
1580 ret = hi846_write_reg(hi846, HI846_REG_MODE_SELECT,
1581 HI846_MODE_STREAMING);
1582 if (ret) {
1583 dev_err(&client->dev, "failed to start stream");
1584 return ret;
1585 }
1586
1587 hi846->streaming = 1;
1588
1589 dev_dbg(&client->dev, "%s: started streaming successfully\n", __func__);
1590
1591 return ret;
1592 }
1593
hi846_stop_streaming(struct hi846 * hi846)1594 static void hi846_stop_streaming(struct hi846 *hi846)
1595 {
1596 struct i2c_client *client = v4l2_get_subdevdata(&hi846->sd);
1597
1598 if (hi846_write_reg(hi846, HI846_REG_MODE_SELECT, HI846_MODE_STANDBY))
1599 dev_err(&client->dev, "failed to stop stream");
1600
1601 hi846->streaming = 0;
1602 }
1603
hi846_set_stream(struct v4l2_subdev * sd,int enable)1604 static int hi846_set_stream(struct v4l2_subdev *sd, int enable)
1605 {
1606 struct hi846 *hi846 = to_hi846(sd);
1607 struct i2c_client *client = v4l2_get_subdevdata(sd);
1608 int ret = 0;
1609
1610 mutex_lock(&hi846->mutex);
1611
1612 if (enable) {
1613 ret = pm_runtime_resume_and_get(&client->dev);
1614 if (ret)
1615 goto out;
1616
1617 ret = hi846_start_streaming(hi846);
1618 }
1619
1620 if (!enable || ret) {
1621 hi846_stop_streaming(hi846);
1622 pm_runtime_put(&client->dev);
1623 }
1624
1625 out:
1626 mutex_unlock(&hi846->mutex);
1627
1628 return ret;
1629 }
1630
hi846_power_on(struct hi846 * hi846)1631 static int hi846_power_on(struct hi846 *hi846)
1632 {
1633 int ret;
1634
1635 ret = regulator_bulk_enable(HI846_NUM_SUPPLIES, hi846->supplies);
1636 if (ret < 0)
1637 return ret;
1638
1639 ret = clk_prepare_enable(hi846->clock);
1640 if (ret < 0)
1641 goto err_reg;
1642
1643 if (hi846->shutdown_gpio)
1644 gpiod_set_value_cansleep(hi846->shutdown_gpio, 0);
1645
1646 /* 30us = 2400 cycles at 80Mhz */
1647 usleep_range(30, 60);
1648 if (hi846->rst_gpio)
1649 gpiod_set_value_cansleep(hi846->rst_gpio, 0);
1650 usleep_range(30, 60);
1651
1652 return 0;
1653
1654 err_reg:
1655 regulator_bulk_disable(HI846_NUM_SUPPLIES, hi846->supplies);
1656
1657 return ret;
1658 }
1659
hi846_power_off(struct hi846 * hi846)1660 static int hi846_power_off(struct hi846 *hi846)
1661 {
1662 if (hi846->rst_gpio)
1663 gpiod_set_value_cansleep(hi846->rst_gpio, 1);
1664
1665 if (hi846->shutdown_gpio)
1666 gpiod_set_value_cansleep(hi846->shutdown_gpio, 1);
1667
1668 clk_disable_unprepare(hi846->clock);
1669 return regulator_bulk_disable(HI846_NUM_SUPPLIES, hi846->supplies);
1670 }
1671
hi846_suspend(struct device * dev)1672 static int __maybe_unused hi846_suspend(struct device *dev)
1673 {
1674 struct i2c_client *client = to_i2c_client(dev);
1675 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1676 struct hi846 *hi846 = to_hi846(sd);
1677
1678 return hi846_power_off(hi846);
1679 }
1680
hi846_resume(struct device * dev)1681 static int __maybe_unused hi846_resume(struct device *dev)
1682 {
1683 struct i2c_client *client = to_i2c_client(dev);
1684 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1685 struct hi846 *hi846 = to_hi846(sd);
1686
1687 return hi846_power_on(hi846);
1688 }
1689
hi846_set_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)1690 static int hi846_set_format(struct v4l2_subdev *sd,
1691 struct v4l2_subdev_state *sd_state,
1692 struct v4l2_subdev_format *format)
1693 {
1694 struct hi846 *hi846 = to_hi846(sd);
1695 struct v4l2_mbus_framefmt *mf = &format->format;
1696 struct i2c_client *client = v4l2_get_subdevdata(sd);
1697 const struct hi846_datafmt *fmt = hi846_find_datafmt(mf->code);
1698 u32 tgt_fps;
1699 s32 vblank_def, h_blank;
1700
1701 if (!fmt) {
1702 mf->code = hi846_colour_fmts[0].code;
1703 mf->colorspace = hi846_colour_fmts[0].colorspace;
1704 fmt = &hi846_colour_fmts[0];
1705 }
1706
1707 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1708 *v4l2_subdev_state_get_format(sd_state, format->pad) = *mf;
1709 return 0;
1710 }
1711
1712 if (hi846->nr_lanes == 2) {
1713 if (!hi846->cur_mode->reg_list_2lane.num_of_regs) {
1714 dev_err(&client->dev,
1715 "this mode is not supported for 2 lanes\n");
1716 return -EINVAL;
1717 }
1718 } else {
1719 if (!hi846->cur_mode->reg_list_4lane.num_of_regs) {
1720 dev_err(&client->dev,
1721 "this mode is not supported for 4 lanes\n");
1722 return -EINVAL;
1723 }
1724 }
1725
1726 mutex_lock(&hi846->mutex);
1727
1728 if (hi846->streaming) {
1729 mutex_unlock(&hi846->mutex);
1730 return -EBUSY;
1731 }
1732
1733 hi846->fmt = fmt;
1734
1735 hi846->cur_mode =
1736 v4l2_find_nearest_size(supported_modes,
1737 ARRAY_SIZE(supported_modes),
1738 width, height, mf->width, mf->height);
1739 dev_dbg(&client->dev, "%s: found mode: %dx%d\n", __func__,
1740 hi846->cur_mode->width, hi846->cur_mode->height);
1741
1742 tgt_fps = hi846->cur_mode->fps;
1743 dev_dbg(&client->dev, "%s: target fps: %d\n", __func__, tgt_fps);
1744
1745 mf->width = hi846->cur_mode->width;
1746 mf->height = hi846->cur_mode->height;
1747 mf->code = HI846_MEDIA_BUS_FORMAT;
1748 mf->field = V4L2_FIELD_NONE;
1749
1750 __v4l2_ctrl_s_ctrl(hi846->link_freq, hi846_get_link_freq_index(hi846));
1751 __v4l2_ctrl_s_ctrl_int64(hi846->pixel_rate,
1752 hi846_calc_pixel_rate(hi846));
1753
1754 /* Update limits and set FPS to default */
1755 vblank_def = hi846->cur_mode->frame_len - hi846->cur_mode->height;
1756 __v4l2_ctrl_modify_range(hi846->vblank,
1757 hi846->cur_mode->frame_len -
1758 hi846->cur_mode->height,
1759 HI846_FLL_MAX - hi846->cur_mode->height, 1,
1760 vblank_def);
1761 __v4l2_ctrl_s_ctrl(hi846->vblank, vblank_def);
1762
1763 h_blank = hi846->cur_mode->llp - hi846->cur_mode->width;
1764
1765 __v4l2_ctrl_modify_range(hi846->hblank, h_blank, h_blank, 1,
1766 h_blank);
1767
1768 dev_dbg(&client->dev, "Set fmt w=%d h=%d code=0x%x colorspace=0x%x\n",
1769 mf->width, mf->height,
1770 fmt->code, fmt->colorspace);
1771
1772 mutex_unlock(&hi846->mutex);
1773
1774 return 0;
1775 }
1776
hi846_get_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)1777 static int hi846_get_format(struct v4l2_subdev *sd,
1778 struct v4l2_subdev_state *sd_state,
1779 struct v4l2_subdev_format *format)
1780 {
1781 struct hi846 *hi846 = to_hi846(sd);
1782 struct v4l2_mbus_framefmt *mf = &format->format;
1783 struct i2c_client *client = v4l2_get_subdevdata(sd);
1784
1785 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1786 format->format = *v4l2_subdev_state_get_format(sd_state,
1787 format->pad);
1788 return 0;
1789 }
1790
1791 mutex_lock(&hi846->mutex);
1792 mf->code = HI846_MEDIA_BUS_FORMAT;
1793 mf->colorspace = V4L2_COLORSPACE_RAW;
1794 mf->field = V4L2_FIELD_NONE;
1795 mf->width = hi846->cur_mode->width;
1796 mf->height = hi846->cur_mode->height;
1797 mutex_unlock(&hi846->mutex);
1798 dev_dbg(&client->dev,
1799 "Get format w=%d h=%d code=0x%x colorspace=0x%x\n",
1800 mf->width, mf->height, mf->code, mf->colorspace);
1801
1802 return 0;
1803 }
1804
hi846_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)1805 static int hi846_enum_mbus_code(struct v4l2_subdev *sd,
1806 struct v4l2_subdev_state *sd_state,
1807 struct v4l2_subdev_mbus_code_enum *code)
1808 {
1809 if (code->pad || code->index > 0)
1810 return -EINVAL;
1811
1812 code->code = HI846_MEDIA_BUS_FORMAT;
1813
1814 return 0;
1815 }
1816
hi846_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_size_enum * fse)1817 static int hi846_enum_frame_size(struct v4l2_subdev *sd,
1818 struct v4l2_subdev_state *sd_state,
1819 struct v4l2_subdev_frame_size_enum *fse)
1820 {
1821 struct i2c_client *client = v4l2_get_subdevdata(sd);
1822
1823 if (fse->pad || fse->index >= ARRAY_SIZE(supported_modes))
1824 return -EINVAL;
1825
1826 if (fse->code != HI846_MEDIA_BUS_FORMAT) {
1827 dev_err(&client->dev, "frame size enum not matching\n");
1828 return -EINVAL;
1829 }
1830
1831 fse->min_width = supported_modes[fse->index].width;
1832 fse->max_width = supported_modes[fse->index].width;
1833 fse->min_height = supported_modes[fse->index].height;
1834 fse->max_height = supported_modes[fse->index].height;
1835
1836 dev_dbg(&client->dev, "%s: max width: %d max height: %d\n", __func__,
1837 fse->max_width, fse->max_height);
1838
1839 return 0;
1840 }
1841
hi846_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_selection * sel)1842 static int hi846_get_selection(struct v4l2_subdev *sd,
1843 struct v4l2_subdev_state *sd_state,
1844 struct v4l2_subdev_selection *sel)
1845 {
1846 struct hi846 *hi846 = to_hi846(sd);
1847
1848 switch (sel->target) {
1849 case V4L2_SEL_TGT_CROP:
1850 case V4L2_SEL_TGT_CROP_DEFAULT:
1851 mutex_lock(&hi846->mutex);
1852 switch (sel->which) {
1853 case V4L2_SUBDEV_FORMAT_TRY:
1854 sel->r = *v4l2_subdev_state_get_crop(sd_state, sel->pad);
1855 break;
1856 case V4L2_SUBDEV_FORMAT_ACTIVE:
1857 sel->r = hi846->cur_mode->crop;
1858 break;
1859 }
1860 mutex_unlock(&hi846->mutex);
1861 return 0;
1862 case V4L2_SEL_TGT_CROP_BOUNDS:
1863 case V4L2_SEL_TGT_NATIVE_SIZE:
1864 sel->r.top = 0;
1865 sel->r.left = 0;
1866 sel->r.width = 3264;
1867 sel->r.height = 2448;
1868 return 0;
1869 default:
1870 return -EINVAL;
1871 }
1872 }
1873
hi846_init_state(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state)1874 static int hi846_init_state(struct v4l2_subdev *sd,
1875 struct v4l2_subdev_state *sd_state)
1876 {
1877 struct hi846 *hi846 = to_hi846(sd);
1878 struct v4l2_mbus_framefmt *mf;
1879
1880 mf = v4l2_subdev_state_get_format(sd_state, 0);
1881
1882 mutex_lock(&hi846->mutex);
1883 mf->code = HI846_MEDIA_BUS_FORMAT;
1884 mf->colorspace = V4L2_COLORSPACE_RAW;
1885 mf->field = V4L2_FIELD_NONE;
1886 mf->width = hi846->cur_mode->width;
1887 mf->height = hi846->cur_mode->height;
1888 mutex_unlock(&hi846->mutex);
1889
1890 return 0;
1891 }
1892
1893 static const struct v4l2_subdev_video_ops hi846_video_ops = {
1894 .s_stream = hi846_set_stream,
1895 };
1896
1897 static const struct v4l2_subdev_pad_ops hi846_pad_ops = {
1898 .enum_frame_size = hi846_enum_frame_size,
1899 .enum_mbus_code = hi846_enum_mbus_code,
1900 .set_fmt = hi846_set_format,
1901 .get_fmt = hi846_get_format,
1902 .get_selection = hi846_get_selection,
1903 };
1904
1905 static const struct v4l2_subdev_ops hi846_subdev_ops = {
1906 .video = &hi846_video_ops,
1907 .pad = &hi846_pad_ops,
1908 };
1909
1910 static const struct v4l2_subdev_internal_ops hi846_internal_ops = {
1911 .init_state = hi846_init_state,
1912 };
1913
1914 static const struct media_entity_operations hi846_subdev_entity_ops = {
1915 .link_validate = v4l2_subdev_link_validate,
1916 };
1917
hi846_identify_module(struct hi846 * hi846)1918 static int hi846_identify_module(struct hi846 *hi846)
1919 {
1920 struct i2c_client *client = v4l2_get_subdevdata(&hi846->sd);
1921 int ret;
1922 u8 hi, lo;
1923
1924 ret = hi846_read_reg(hi846, HI846_REG_CHIP_ID_L, &lo);
1925 if (ret)
1926 return ret;
1927
1928 if (lo != HI846_CHIP_ID_L) {
1929 dev_err(&client->dev, "wrong chip id low byte: %x", lo);
1930 return -ENXIO;
1931 }
1932
1933 ret = hi846_read_reg(hi846, HI846_REG_CHIP_ID_H, &hi);
1934 if (ret)
1935 return ret;
1936
1937 if (hi != HI846_CHIP_ID_H) {
1938 dev_err(&client->dev, "wrong chip id high byte: %x", hi);
1939 return -ENXIO;
1940 }
1941
1942 dev_info(&client->dev, "chip id %02X %02X using %d mipi lanes\n",
1943 hi, lo, hi846->nr_lanes);
1944
1945 return 0;
1946 }
1947
hi846_check_link_freqs(struct hi846 * hi846,struct v4l2_fwnode_endpoint * ep)1948 static s64 hi846_check_link_freqs(struct hi846 *hi846,
1949 struct v4l2_fwnode_endpoint *ep)
1950 {
1951 const s64 *freqs = hi846_link_freqs;
1952 int freqs_count = ARRAY_SIZE(hi846_link_freqs);
1953 int i, j;
1954
1955 for (i = 0; i < freqs_count; i++) {
1956 for (j = 0; j < ep->nr_of_link_frequencies; j++)
1957 if (freqs[i] == ep->link_frequencies[j])
1958 break;
1959 if (j == ep->nr_of_link_frequencies)
1960 return freqs[i];
1961 }
1962
1963 return 0;
1964 }
1965
hi846_parse_dt(struct hi846 * hi846,struct device * dev)1966 static int hi846_parse_dt(struct hi846 *hi846, struct device *dev)
1967 {
1968 struct fwnode_handle *ep;
1969 struct fwnode_handle *fwnode = dev_fwnode(dev);
1970 struct v4l2_fwnode_endpoint bus_cfg = {
1971 .bus_type = V4L2_MBUS_CSI2_DPHY
1972 };
1973 int ret;
1974 s64 fq;
1975
1976 ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
1977 if (!ep) {
1978 dev_err(dev, "unable to find endpoint node\n");
1979 return -ENXIO;
1980 }
1981
1982 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
1983 fwnode_handle_put(ep);
1984 if (ret) {
1985 dev_err(dev, "failed to parse endpoint node: %d\n", ret);
1986 return ret;
1987 }
1988
1989 if (bus_cfg.bus.mipi_csi2.num_data_lanes != 2 &&
1990 bus_cfg.bus.mipi_csi2.num_data_lanes != 4) {
1991 dev_err(dev, "number of CSI2 data lanes %d is not supported",
1992 bus_cfg.bus.mipi_csi2.num_data_lanes);
1993 ret = -EINVAL;
1994 goto check_hwcfg_error;
1995 }
1996
1997 hi846->nr_lanes = bus_cfg.bus.mipi_csi2.num_data_lanes;
1998
1999 if (!bus_cfg.nr_of_link_frequencies) {
2000 dev_err(dev, "link-frequency property not found in DT\n");
2001 ret = -EINVAL;
2002 goto check_hwcfg_error;
2003 }
2004
2005 /* Check that link frequences for all the modes are in device tree */
2006 fq = hi846_check_link_freqs(hi846, &bus_cfg);
2007 if (fq) {
2008 dev_err(dev, "Link frequency of %lld is not supported\n", fq);
2009 ret = -EINVAL;
2010 goto check_hwcfg_error;
2011 }
2012
2013 v4l2_fwnode_endpoint_free(&bus_cfg);
2014
2015 hi846->rst_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
2016 if (IS_ERR(hi846->rst_gpio)) {
2017 dev_err(dev, "failed to get reset gpio: %pe\n",
2018 hi846->rst_gpio);
2019 return PTR_ERR(hi846->rst_gpio);
2020 }
2021
2022 hi846->shutdown_gpio = devm_gpiod_get_optional(dev, "shutdown",
2023 GPIOD_OUT_LOW);
2024 if (IS_ERR(hi846->shutdown_gpio)) {
2025 dev_err(dev, "failed to get shutdown gpio: %pe\n",
2026 hi846->shutdown_gpio);
2027 return PTR_ERR(hi846->shutdown_gpio);
2028 }
2029
2030 return 0;
2031
2032 check_hwcfg_error:
2033 v4l2_fwnode_endpoint_free(&bus_cfg);
2034 return ret;
2035 }
2036
hi846_probe(struct i2c_client * client)2037 static int hi846_probe(struct i2c_client *client)
2038 {
2039 struct hi846 *hi846;
2040 int ret;
2041 int i;
2042 u32 mclk_freq;
2043
2044 hi846 = devm_kzalloc(&client->dev, sizeof(*hi846), GFP_KERNEL);
2045 if (!hi846)
2046 return -ENOMEM;
2047
2048 ret = hi846_parse_dt(hi846, &client->dev);
2049 if (ret) {
2050 dev_err(&client->dev, "failed to check HW configuration: %d",
2051 ret);
2052 return ret;
2053 }
2054
2055 hi846->clock = devm_clk_get(&client->dev, NULL);
2056 if (IS_ERR(hi846->clock)) {
2057 dev_err(&client->dev, "failed to get clock: %pe\n",
2058 hi846->clock);
2059 return PTR_ERR(hi846->clock);
2060 }
2061
2062 mclk_freq = clk_get_rate(hi846->clock);
2063 if (mclk_freq != 25000000)
2064 dev_warn(&client->dev,
2065 "External clock freq should be 25000000, not %u.\n",
2066 mclk_freq);
2067
2068 for (i = 0; i < HI846_NUM_SUPPLIES; i++)
2069 hi846->supplies[i].supply = hi846_supply_names[i];
2070
2071 ret = devm_regulator_bulk_get(&client->dev, HI846_NUM_SUPPLIES,
2072 hi846->supplies);
2073 if (ret < 0)
2074 return ret;
2075
2076 v4l2_i2c_subdev_init(&hi846->sd, client, &hi846_subdev_ops);
2077 hi846->sd.internal_ops = &hi846_internal_ops;
2078
2079 mutex_init(&hi846->mutex);
2080
2081 ret = hi846_power_on(hi846);
2082 if (ret)
2083 goto err_mutex;
2084
2085 ret = hi846_identify_module(hi846);
2086 if (ret)
2087 goto err_power_off;
2088
2089 hi846->cur_mode = &supported_modes[0];
2090
2091 ret = hi846_init_controls(hi846);
2092 if (ret) {
2093 dev_err(&client->dev, "failed to init controls: %d", ret);
2094 goto err_power_off;
2095 }
2096
2097 hi846->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
2098 hi846->sd.entity.ops = &hi846_subdev_entity_ops;
2099 hi846->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
2100 hi846->pad.flags = MEDIA_PAD_FL_SOURCE;
2101 ret = media_entity_pads_init(&hi846->sd.entity, 1, &hi846->pad);
2102 if (ret) {
2103 dev_err(&client->dev, "failed to init entity pads: %d", ret);
2104 goto err_v4l2_ctrl_handler_free;
2105 }
2106
2107 ret = v4l2_async_register_subdev_sensor(&hi846->sd);
2108 if (ret < 0) {
2109 dev_err(&client->dev, "failed to register V4L2 subdev: %d",
2110 ret);
2111 goto err_media_entity_cleanup;
2112 }
2113
2114 pm_runtime_set_active(&client->dev);
2115 pm_runtime_enable(&client->dev);
2116 pm_runtime_idle(&client->dev);
2117
2118 return 0;
2119
2120 err_media_entity_cleanup:
2121 media_entity_cleanup(&hi846->sd.entity);
2122
2123 err_v4l2_ctrl_handler_free:
2124 v4l2_ctrl_handler_free(hi846->sd.ctrl_handler);
2125
2126 err_power_off:
2127 hi846_power_off(hi846);
2128
2129 err_mutex:
2130 mutex_destroy(&hi846->mutex);
2131
2132 return ret;
2133 }
2134
hi846_remove(struct i2c_client * client)2135 static void hi846_remove(struct i2c_client *client)
2136 {
2137 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2138 struct hi846 *hi846 = to_hi846(sd);
2139
2140 v4l2_async_unregister_subdev(sd);
2141 media_entity_cleanup(&sd->entity);
2142 v4l2_ctrl_handler_free(sd->ctrl_handler);
2143
2144 pm_runtime_disable(&client->dev);
2145 if (!pm_runtime_status_suspended(&client->dev))
2146 hi846_suspend(&client->dev);
2147 pm_runtime_set_suspended(&client->dev);
2148
2149 mutex_destroy(&hi846->mutex);
2150 }
2151
2152 static const struct dev_pm_ops hi846_pm_ops = {
2153 SET_RUNTIME_PM_OPS(hi846_suspend, hi846_resume, NULL)
2154 };
2155
2156 static const struct of_device_id hi846_of_match[] = {
2157 { .compatible = "hynix,hi846", },
2158 {},
2159 };
2160 MODULE_DEVICE_TABLE(of, hi846_of_match);
2161
2162 static struct i2c_driver hi846_i2c_driver = {
2163 .driver = {
2164 .name = "hi846",
2165 .pm = &hi846_pm_ops,
2166 .of_match_table = hi846_of_match,
2167 },
2168 .probe = hi846_probe,
2169 .remove = hi846_remove,
2170 };
2171
2172 module_i2c_driver(hi846_i2c_driver);
2173
2174 MODULE_AUTHOR("Angus Ainslie <angus@akkea.ca>");
2175 MODULE_AUTHOR("Martin Kepplinger <martin.kepplinger@puri.sm>");
2176 MODULE_DESCRIPTION("Hynix HI846 sensor driver");
2177 MODULE_LICENSE("GPL v2");
2178