1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * A V4L2 driver for Galaxycore GC2145 camera. 4 * Copyright (C) 2023, STMicroelectronics SA 5 * 6 * Inspired by the imx219.c driver 7 * 8 * Datasheet v1.0 available at http://files.pine64.org/doc/datasheet/PinebookPro/GC2145%20CSP%20DataSheet%20release%20V1.0_20131201.pdf 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/i2c.h> 15 #include <linux/module.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regulator/consumer.h> 18 #include <linux/units.h> 19 20 #include <media/mipi-csi2.h> 21 #include <media/v4l2-cci.h> 22 #include <media/v4l2-ctrls.h> 23 #include <media/v4l2-device.h> 24 #include <media/v4l2-fwnode.h> 25 #include <media/v4l2-mediabus.h> 26 27 /* Chip ID */ 28 #define GC2145_CHIP_ID 0x2145 29 30 /* Page 0 */ 31 #define GC2145_REG_EXPOSURE CCI_REG16(0x03) 32 #define GC2145_REG_HBLANK CCI_REG16(0x05) 33 #define GC2145_REG_VBLANK CCI_REG16(0x07) 34 #define GC2145_REG_ROW_START CCI_REG16(0x09) 35 #define GC2145_REG_COL_START CCI_REG16(0x0b) 36 #define GC2145_REG_WIN_HEIGHT CCI_REG16(0x0d) 37 #define GC2145_REG_WIN_WIDTH CCI_REG16(0x0f) 38 #define GC2145_REG_ANALOG_MODE1 CCI_REG8(0x17) 39 #define GC2145_REG_OUTPUT_FMT CCI_REG8(0x84) 40 #define GC2145_REG_SYNC_MODE CCI_REG8(0x86) 41 #define GC2145_SYNC_MODE_COL_SWITCH BIT(4) 42 #define GC2145_SYNC_MODE_ROW_SWITCH BIT(5) 43 #define GC2145_REG_BYPASS_MODE CCI_REG8(0x89) 44 #define GC2145_BYPASS_MODE_SWITCH BIT(5) 45 #define GC2145_REG_DEBUG_MODE2 CCI_REG8(0x8c) 46 #define GC2145_REG_DEBUG_MODE3 CCI_REG8(0x8d) 47 #define GC2145_REG_CROP_ENABLE CCI_REG8(0x90) 48 #define GC2145_REG_CROP_Y CCI_REG16(0x91) 49 #define GC2145_REG_CROP_X CCI_REG16(0x93) 50 #define GC2145_REG_CROP_HEIGHT CCI_REG16(0x95) 51 #define GC2145_REG_CROP_WIDTH CCI_REG16(0x97) 52 #define GC2145_REG_GLOBAL_GAIN CCI_REG8(0xb0) 53 #define GC2145_REG_CHIP_ID CCI_REG16(0xf0) 54 #define GC2145_REG_PAD_IO CCI_REG8(0xf2) 55 #define GC2145_REG_PAGE_SELECT CCI_REG8(0xfe) 56 /* Page 3 */ 57 #define GC2145_REG_DPHY_ANALOG_MODE1 CCI_REG8(0x01) 58 #define GC2145_DPHY_MODE_PHY_CLK_EN BIT(0) 59 #define GC2145_DPHY_MODE_PHY_LANE0_EN BIT(1) 60 #define GC2145_DPHY_MODE_PHY_LANE1_EN BIT(2) 61 #define GC2145_DPHY_MODE_PHY_CLK_LANE_P2S_SEL BIT(7) 62 #define GC2145_REG_DPHY_ANALOG_MODE2 CCI_REG8(0x02) 63 #define GC2145_DPHY_CLK_DIFF(a) ((a) & 0x07) 64 #define GC2145_DPHY_LANE0_DIFF(a) (((a) & 0x07) << 4) 65 #define GC2145_REG_DPHY_ANALOG_MODE3 CCI_REG8(0x03) 66 #define GC2145_DPHY_LANE1_DIFF(a) ((a) & 0x07) 67 #define GC2145_DPHY_CLK_DELAY BIT(4) 68 #define GC2145_DPHY_LANE0_DELAY BIT(5) 69 #define GC2145_DPHY_LANE1_DELAY BIT(6) 70 #define GC2145_REG_FIFO_FULL_LVL CCI_REG16_LE(0x04) 71 #define GC2145_REG_FIFO_MODE CCI_REG8(0x06) 72 #define GC2145_FIFO_MODE_READ_GATE BIT(3) 73 #define GC2145_FIFO_MODE_MIPI_CLK_MODULE BIT(7) 74 #define GC2145_REG_BUF_CSI2_MODE CCI_REG8(0x10) 75 #define GC2145_CSI2_MODE_DOUBLE BIT(0) 76 #define GC2145_CSI2_MODE_RAW8 BIT(2) 77 #define GC2145_CSI2_MODE_MIPI_EN BIT(4) 78 #define GC2145_CSI2_MODE_EN BIT(7) 79 #define GC2145_REG_MIPI_DT CCI_REG8(0x11) 80 #define GC2145_REG_LWC CCI_REG16_LE(0x12) 81 #define GC2145_REG_DPHY_MODE CCI_REG8(0x15) 82 #define GC2145_DPHY_MODE_TRIGGER_PROG BIT(4) 83 #define GC2145_REG_FIFO_GATE_MODE CCI_REG8(0x17) 84 #define GC2145_REG_T_LPX CCI_REG8(0x21) 85 #define GC2145_REG_T_CLK_HS_PREPARE CCI_REG8(0x22) 86 #define GC2145_REG_T_CLK_ZERO CCI_REG8(0x23) 87 #define GC2145_REG_T_CLK_PRE CCI_REG8(0x24) 88 #define GC2145_REG_T_CLK_POST CCI_REG8(0x25) 89 #define GC2145_REG_T_CLK_TRAIL CCI_REG8(0x26) 90 #define GC2145_REG_T_HS_EXIT CCI_REG8(0x27) 91 #define GC2145_REG_T_WAKEUP CCI_REG8(0x28) 92 #define GC2145_REG_T_HS_PREPARE CCI_REG8(0x29) 93 #define GC2145_REG_T_HS_ZERO CCI_REG8(0x2a) 94 #define GC2145_REG_T_HS_TRAIL CCI_REG8(0x2b) 95 96 /* External clock frequency is 24.0MHz */ 97 #define GC2145_XCLK_FREQ (24 * HZ_PER_MHZ) 98 99 #define GC2145_NATIVE_WIDTH 1616U 100 #define GC2145_NATIVE_HEIGHT 1232U 101 102 /** 103 * struct gc2145_mode - GC2145 mode description 104 * @width: frame width (in pixels) 105 * @height: frame height (in pixels) 106 * @reg_seq: registers config sequence to enter into the mode 107 * @reg_seq_size: size of the sequence 108 * @pixel_rate: pixel rate associated with the mode 109 * @crop: window area captured 110 * @hblank: default horizontal blanking 111 * @vblank: default vertical blanking 112 * @link_freq_index: index within the link frequency menu 113 */ 114 struct gc2145_mode { 115 unsigned int width; 116 unsigned int height; 117 const struct cci_reg_sequence *reg_seq; 118 size_t reg_seq_size; 119 unsigned long pixel_rate; 120 struct v4l2_rect crop; 121 unsigned int hblank; 122 unsigned int vblank; 123 unsigned int link_freq_index; 124 }; 125 126 #define GC2145_DEFAULT_EXPOSURE 0x04e2 127 #define GC2145_DEFAULT_GLOBAL_GAIN 0x55 128 static const struct cci_reg_sequence gc2145_common_regs[] = { 129 {GC2145_REG_PAGE_SELECT, 0x00}, 130 /* SH Delay */ 131 {CCI_REG8(0x12), 0x2e}, 132 /* Flip */ 133 {GC2145_REG_ANALOG_MODE1, 0x14}, 134 /* Analog Conf */ 135 {CCI_REG8(0x18), 0x22}, {CCI_REG8(0x19), 0x0e}, {CCI_REG8(0x1a), 0x01}, 136 {CCI_REG8(0x1b), 0x4b}, {CCI_REG8(0x1c), 0x07}, {CCI_REG8(0x1d), 0x10}, 137 {CCI_REG8(0x1e), 0x88}, {CCI_REG8(0x1f), 0x78}, {CCI_REG8(0x20), 0x03}, 138 {CCI_REG8(0x21), 0x40}, {CCI_REG8(0x22), 0xa0}, {CCI_REG8(0x24), 0x16}, 139 {CCI_REG8(0x25), 0x01}, {CCI_REG8(0x26), 0x10}, {CCI_REG8(0x2d), 0x60}, 140 {CCI_REG8(0x30), 0x01}, {CCI_REG8(0x31), 0x90}, {CCI_REG8(0x33), 0x06}, 141 {CCI_REG8(0x34), 0x01}, 142 /* ISP related */ 143 {CCI_REG8(0x80), 0x7f}, {CCI_REG8(0x81), 0x26}, {CCI_REG8(0x82), 0xfa}, 144 {CCI_REG8(0x83), 0x00}, {CCI_REG8(0x84), 0x02}, {CCI_REG8(0x86), 0x02}, 145 {CCI_REG8(0x88), 0x03}, 146 {GC2145_REG_BYPASS_MODE, 0x03}, 147 {CCI_REG8(0x85), 0x08}, {CCI_REG8(0x8a), 0x00}, {CCI_REG8(0x8b), 0x00}, 148 {GC2145_REG_GLOBAL_GAIN, GC2145_DEFAULT_GLOBAL_GAIN}, 149 {CCI_REG8(0xc3), 0x00}, {CCI_REG8(0xc4), 0x80}, {CCI_REG8(0xc5), 0x90}, 150 {CCI_REG8(0xc6), 0x3b}, {CCI_REG8(0xc7), 0x46}, 151 /* BLK */ 152 {GC2145_REG_PAGE_SELECT, 0x00}, 153 {CCI_REG8(0x40), 0x42}, {CCI_REG8(0x41), 0x00}, {CCI_REG8(0x43), 0x5b}, 154 {CCI_REG8(0x5e), 0x00}, {CCI_REG8(0x5f), 0x00}, {CCI_REG8(0x60), 0x00}, 155 {CCI_REG8(0x61), 0x00}, {CCI_REG8(0x62), 0x00}, {CCI_REG8(0x63), 0x00}, 156 {CCI_REG8(0x64), 0x00}, {CCI_REG8(0x65), 0x00}, {CCI_REG8(0x66), 0x20}, 157 {CCI_REG8(0x67), 0x20}, {CCI_REG8(0x68), 0x20}, {CCI_REG8(0x69), 0x20}, 158 {CCI_REG8(0x76), 0x00}, {CCI_REG8(0x6a), 0x08}, {CCI_REG8(0x6b), 0x08}, 159 {CCI_REG8(0x6c), 0x08}, {CCI_REG8(0x6d), 0x08}, {CCI_REG8(0x6e), 0x08}, 160 {CCI_REG8(0x6f), 0x08}, {CCI_REG8(0x70), 0x08}, {CCI_REG8(0x71), 0x08}, 161 {CCI_REG8(0x76), 0x00}, {CCI_REG8(0x72), 0xf0}, {CCI_REG8(0x7e), 0x3c}, 162 {CCI_REG8(0x7f), 0x00}, 163 {GC2145_REG_PAGE_SELECT, 0x02}, 164 {CCI_REG8(0x48), 0x15}, {CCI_REG8(0x49), 0x00}, {CCI_REG8(0x4b), 0x0b}, 165 /* AEC */ 166 {GC2145_REG_PAGE_SELECT, 0x00}, 167 {GC2145_REG_EXPOSURE, GC2145_DEFAULT_EXPOSURE}, 168 {GC2145_REG_PAGE_SELECT, 0x01}, 169 {CCI_REG8(0x01), 0x04}, {CCI_REG8(0x02), 0xc0}, {CCI_REG8(0x03), 0x04}, 170 {CCI_REG8(0x04), 0x90}, {CCI_REG8(0x05), 0x30}, {CCI_REG8(0x06), 0x90}, 171 {CCI_REG8(0x07), 0x30}, {CCI_REG8(0x08), 0x80}, {CCI_REG8(0x09), 0x00}, 172 {CCI_REG8(0x0a), 0x82}, {CCI_REG8(0x0b), 0x11}, {CCI_REG8(0x0c), 0x10}, 173 {CCI_REG8(0x11), 0x10}, {CCI_REG8(0x13), 0x7b}, {CCI_REG8(0x17), 0x00}, 174 {CCI_REG8(0x1c), 0x11}, {CCI_REG8(0x1e), 0x61}, {CCI_REG8(0x1f), 0x35}, 175 {CCI_REG8(0x20), 0x40}, {CCI_REG8(0x22), 0x40}, {CCI_REG8(0x23), 0x20}, 176 {GC2145_REG_PAGE_SELECT, 0x02}, 177 {CCI_REG8(0x0f), 0x04}, 178 {GC2145_REG_PAGE_SELECT, 0x01}, 179 {CCI_REG8(0x12), 0x35}, {CCI_REG8(0x15), 0xb0}, {CCI_REG8(0x10), 0x31}, 180 {CCI_REG8(0x3e), 0x28}, {CCI_REG8(0x3f), 0xb0}, {CCI_REG8(0x40), 0x90}, 181 {CCI_REG8(0x41), 0x0f}, 182 /* INTPEE */ 183 {GC2145_REG_PAGE_SELECT, 0x02}, 184 {CCI_REG8(0x90), 0x6c}, {CCI_REG8(0x91), 0x03}, {CCI_REG8(0x92), 0xcb}, 185 {CCI_REG8(0x94), 0x33}, {CCI_REG8(0x95), 0x84}, {CCI_REG8(0x97), 0x65}, 186 {CCI_REG8(0xa2), 0x11}, 187 /* DNDD */ 188 {GC2145_REG_PAGE_SELECT, 0x02}, 189 {CCI_REG8(0x80), 0xc1}, {CCI_REG8(0x81), 0x08}, {CCI_REG8(0x82), 0x05}, 190 {CCI_REG8(0x83), 0x08}, {CCI_REG8(0x84), 0x0a}, {CCI_REG8(0x86), 0xf0}, 191 {CCI_REG8(0x87), 0x50}, {CCI_REG8(0x88), 0x15}, {CCI_REG8(0x89), 0xb0}, 192 {CCI_REG8(0x8a), 0x30}, {CCI_REG8(0x8b), 0x10}, 193 /* ASDE */ 194 {GC2145_REG_PAGE_SELECT, 0x01}, 195 {CCI_REG8(0x21), 0x04}, 196 {GC2145_REG_PAGE_SELECT, 0x02}, 197 {CCI_REG8(0xa3), 0x50}, {CCI_REG8(0xa4), 0x20}, {CCI_REG8(0xa5), 0x40}, 198 {CCI_REG8(0xa6), 0x80}, {CCI_REG8(0xab), 0x40}, {CCI_REG8(0xae), 0x0c}, 199 {CCI_REG8(0xb3), 0x46}, {CCI_REG8(0xb4), 0x64}, {CCI_REG8(0xb6), 0x38}, 200 {CCI_REG8(0xb7), 0x01}, {CCI_REG8(0xb9), 0x2b}, {CCI_REG8(0x3c), 0x04}, 201 {CCI_REG8(0x3d), 0x15}, {CCI_REG8(0x4b), 0x06}, {CCI_REG8(0x4c), 0x20}, 202 /* Gamma */ 203 {GC2145_REG_PAGE_SELECT, 0x02}, 204 {CCI_REG8(0x10), 0x09}, {CCI_REG8(0x11), 0x0d}, {CCI_REG8(0x12), 0x13}, 205 {CCI_REG8(0x13), 0x19}, {CCI_REG8(0x14), 0x27}, {CCI_REG8(0x15), 0x37}, 206 {CCI_REG8(0x16), 0x45}, {CCI_REG8(0x17), 0x53}, {CCI_REG8(0x18), 0x69}, 207 {CCI_REG8(0x19), 0x7d}, {CCI_REG8(0x1a), 0x8f}, {CCI_REG8(0x1b), 0x9d}, 208 {CCI_REG8(0x1c), 0xa9}, {CCI_REG8(0x1d), 0xbd}, {CCI_REG8(0x1e), 0xcd}, 209 {CCI_REG8(0x1f), 0xd9}, {CCI_REG8(0x20), 0xe3}, {CCI_REG8(0x21), 0xea}, 210 {CCI_REG8(0x22), 0xef}, {CCI_REG8(0x23), 0xf5}, {CCI_REG8(0x24), 0xf9}, 211 {CCI_REG8(0x25), 0xff}, 212 {GC2145_REG_PAGE_SELECT, 0x00}, 213 {CCI_REG8(0xc6), 0x20}, {CCI_REG8(0xc7), 0x2b}, 214 /* Gamma 2 */ 215 {GC2145_REG_PAGE_SELECT, 0x02}, 216 {CCI_REG8(0x26), 0x0f}, {CCI_REG8(0x27), 0x14}, {CCI_REG8(0x28), 0x19}, 217 {CCI_REG8(0x29), 0x1e}, {CCI_REG8(0x2a), 0x27}, {CCI_REG8(0x2b), 0x33}, 218 {CCI_REG8(0x2c), 0x3b}, {CCI_REG8(0x2d), 0x45}, {CCI_REG8(0x2e), 0x59}, 219 {CCI_REG8(0x2f), 0x69}, {CCI_REG8(0x30), 0x7c}, {CCI_REG8(0x31), 0x89}, 220 {CCI_REG8(0x32), 0x98}, {CCI_REG8(0x33), 0xae}, {CCI_REG8(0x34), 0xc0}, 221 {CCI_REG8(0x35), 0xcf}, {CCI_REG8(0x36), 0xda}, {CCI_REG8(0x37), 0xe2}, 222 {CCI_REG8(0x38), 0xe9}, {CCI_REG8(0x39), 0xf3}, {CCI_REG8(0x3a), 0xf9}, 223 {CCI_REG8(0x3b), 0xff}, 224 /* YCP */ 225 {GC2145_REG_PAGE_SELECT, 0x02}, 226 {CCI_REG8(0xd1), 0x32}, {CCI_REG8(0xd2), 0x32}, {CCI_REG8(0xd3), 0x40}, 227 {CCI_REG8(0xd6), 0xf0}, {CCI_REG8(0xd7), 0x10}, {CCI_REG8(0xd8), 0xda}, 228 {CCI_REG8(0xdd), 0x14}, {CCI_REG8(0xde), 0x86}, {CCI_REG8(0xed), 0x80}, 229 {CCI_REG8(0xee), 0x00}, {CCI_REG8(0xef), 0x3f}, {CCI_REG8(0xd8), 0xd8}, 230 /* ABS */ 231 {GC2145_REG_PAGE_SELECT, 0x01}, 232 {CCI_REG8(0x9f), 0x40}, 233 /* LSC */ 234 {GC2145_REG_PAGE_SELECT, 0x01}, 235 {CCI_REG8(0xc2), 0x14}, {CCI_REG8(0xc3), 0x0d}, {CCI_REG8(0xc4), 0x0c}, 236 {CCI_REG8(0xc8), 0x15}, {CCI_REG8(0xc9), 0x0d}, {CCI_REG8(0xca), 0x0a}, 237 {CCI_REG8(0xbc), 0x24}, {CCI_REG8(0xbd), 0x10}, {CCI_REG8(0xbe), 0x0b}, 238 {CCI_REG8(0xb6), 0x25}, {CCI_REG8(0xb7), 0x16}, {CCI_REG8(0xb8), 0x15}, 239 {CCI_REG8(0xc5), 0x00}, {CCI_REG8(0xc6), 0x00}, {CCI_REG8(0xc7), 0x00}, 240 {CCI_REG8(0xcb), 0x00}, {CCI_REG8(0xcc), 0x00}, {CCI_REG8(0xcd), 0x00}, 241 {CCI_REG8(0xbf), 0x07}, {CCI_REG8(0xc0), 0x00}, {CCI_REG8(0xc1), 0x00}, 242 {CCI_REG8(0xb9), 0x00}, {CCI_REG8(0xba), 0x00}, {CCI_REG8(0xbb), 0x00}, 243 {CCI_REG8(0xaa), 0x01}, {CCI_REG8(0xab), 0x01}, {CCI_REG8(0xac), 0x00}, 244 {CCI_REG8(0xad), 0x05}, {CCI_REG8(0xae), 0x06}, {CCI_REG8(0xaf), 0x0e}, 245 {CCI_REG8(0xb0), 0x0b}, {CCI_REG8(0xb1), 0x07}, {CCI_REG8(0xb2), 0x06}, 246 {CCI_REG8(0xb3), 0x17}, {CCI_REG8(0xb4), 0x0e}, {CCI_REG8(0xb5), 0x0e}, 247 {CCI_REG8(0xd0), 0x09}, {CCI_REG8(0xd1), 0x00}, {CCI_REG8(0xd2), 0x00}, 248 {CCI_REG8(0xd6), 0x08}, {CCI_REG8(0xd7), 0x00}, {CCI_REG8(0xd8), 0x00}, 249 {CCI_REG8(0xd9), 0x00}, {CCI_REG8(0xda), 0x00}, {CCI_REG8(0xdb), 0x00}, 250 {CCI_REG8(0xd3), 0x0a}, {CCI_REG8(0xd4), 0x00}, {CCI_REG8(0xd5), 0x00}, 251 {CCI_REG8(0xa4), 0x00}, {CCI_REG8(0xa5), 0x00}, {CCI_REG8(0xa6), 0x77}, 252 {CCI_REG8(0xa7), 0x77}, {CCI_REG8(0xa8), 0x77}, {CCI_REG8(0xa9), 0x77}, 253 {CCI_REG8(0xa1), 0x80}, {CCI_REG8(0xa2), 0x80}, 254 {GC2145_REG_PAGE_SELECT, 0x01}, 255 {CCI_REG8(0xdf), 0x0d}, {CCI_REG8(0xdc), 0x25}, {CCI_REG8(0xdd), 0x30}, 256 {CCI_REG8(0xe0), 0x77}, {CCI_REG8(0xe1), 0x80}, {CCI_REG8(0xe2), 0x77}, 257 {CCI_REG8(0xe3), 0x90}, {CCI_REG8(0xe6), 0x90}, {CCI_REG8(0xe7), 0xa0}, 258 {CCI_REG8(0xe8), 0x90}, {CCI_REG8(0xe9), 0xa0}, 259 /* AWB */ 260 /* measure window */ 261 {GC2145_REG_PAGE_SELECT, 0x00}, 262 {CCI_REG8(0xec), 0x06}, {CCI_REG8(0xed), 0x04}, {CCI_REG8(0xee), 0x60}, 263 {CCI_REG8(0xef), 0x90}, {CCI_REG8(0xb6), 0x01}, 264 {GC2145_REG_PAGE_SELECT, 0x01}, 265 {CCI_REG8(0x4f), 0x00}, {CCI_REG8(0x4f), 0x00}, {CCI_REG8(0x4b), 0x01}, 266 {CCI_REG8(0x4f), 0x00}, 267 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x71}, {CCI_REG8(0x4e), 0x01}, 268 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x91}, {CCI_REG8(0x4e), 0x01}, 269 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x70}, {CCI_REG8(0x4e), 0x01}, 270 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x90}, {CCI_REG8(0x4e), 0x02}, 271 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xb0}, {CCI_REG8(0x4e), 0x02}, 272 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x8f}, {CCI_REG8(0x4e), 0x02}, 273 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x6f}, {CCI_REG8(0x4e), 0x02}, 274 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xaf}, {CCI_REG8(0x4e), 0x02}, 275 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xd0}, {CCI_REG8(0x4e), 0x02}, 276 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xf0}, {CCI_REG8(0x4e), 0x02}, 277 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xcf}, {CCI_REG8(0x4e), 0x02}, 278 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xef}, {CCI_REG8(0x4e), 0x02}, 279 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x6e}, {CCI_REG8(0x4e), 0x03}, 280 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x8e}, {CCI_REG8(0x4e), 0x03}, 281 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xae}, {CCI_REG8(0x4e), 0x03}, 282 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xce}, {CCI_REG8(0x4e), 0x03}, 283 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x4d}, {CCI_REG8(0x4e), 0x03}, 284 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x6d}, {CCI_REG8(0x4e), 0x03}, 285 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x8d}, {CCI_REG8(0x4e), 0x03}, 286 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xad}, {CCI_REG8(0x4e), 0x03}, 287 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xcd}, {CCI_REG8(0x4e), 0x03}, 288 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x4c}, {CCI_REG8(0x4e), 0x03}, 289 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x6c}, {CCI_REG8(0x4e), 0x03}, 290 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x8c}, {CCI_REG8(0x4e), 0x03}, 291 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xac}, {CCI_REG8(0x4e), 0x03}, 292 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xcc}, {CCI_REG8(0x4e), 0x03}, 293 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xcb}, {CCI_REG8(0x4e), 0x03}, 294 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x4b}, {CCI_REG8(0x4e), 0x03}, 295 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x6b}, {CCI_REG8(0x4e), 0x03}, 296 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x8b}, {CCI_REG8(0x4e), 0x03}, 297 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xab}, {CCI_REG8(0x4e), 0x03}, 298 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x8a}, {CCI_REG8(0x4e), 0x04}, 299 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xaa}, {CCI_REG8(0x4e), 0x04}, 300 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xca}, {CCI_REG8(0x4e), 0x04}, 301 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xca}, {CCI_REG8(0x4e), 0x04}, 302 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xc9}, {CCI_REG8(0x4e), 0x04}, 303 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x8a}, {CCI_REG8(0x4e), 0x04}, 304 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x89}, {CCI_REG8(0x4e), 0x04}, 305 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xa9}, {CCI_REG8(0x4e), 0x04}, 306 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x0b}, {CCI_REG8(0x4e), 0x05}, 307 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x0a}, {CCI_REG8(0x4e), 0x05}, 308 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xeb}, {CCI_REG8(0x4e), 0x05}, 309 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xea}, {CCI_REG8(0x4e), 0x05}, 310 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x09}, {CCI_REG8(0x4e), 0x05}, 311 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x29}, {CCI_REG8(0x4e), 0x05}, 312 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x2a}, {CCI_REG8(0x4e), 0x05}, 313 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x4a}, {CCI_REG8(0x4e), 0x05}, 314 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x8a}, {CCI_REG8(0x4e), 0x06}, 315 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x49}, {CCI_REG8(0x4e), 0x06}, 316 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x69}, {CCI_REG8(0x4e), 0x06}, 317 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x89}, {CCI_REG8(0x4e), 0x06}, 318 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0xa9}, {CCI_REG8(0x4e), 0x06}, 319 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x48}, {CCI_REG8(0x4e), 0x06}, 320 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x68}, {CCI_REG8(0x4e), 0x06}, 321 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x69}, {CCI_REG8(0x4e), 0x06}, 322 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0xca}, {CCI_REG8(0x4e), 0x07}, 323 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0xc9}, {CCI_REG8(0x4e), 0x07}, 324 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0xe9}, {CCI_REG8(0x4e), 0x07}, 325 {CCI_REG8(0x4c), 0x03}, {CCI_REG8(0x4d), 0x09}, {CCI_REG8(0x4e), 0x07}, 326 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0xc8}, {CCI_REG8(0x4e), 0x07}, 327 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0xe8}, {CCI_REG8(0x4e), 0x07}, 328 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0xa7}, {CCI_REG8(0x4e), 0x07}, 329 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0xc7}, {CCI_REG8(0x4e), 0x07}, 330 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0xe7}, {CCI_REG8(0x4e), 0x07}, 331 {CCI_REG8(0x4c), 0x03}, {CCI_REG8(0x4d), 0x07}, {CCI_REG8(0x4e), 0x07}, 332 {CCI_REG8(0x4f), 0x01}, 333 {CCI_REG8(0x50), 0x80}, {CCI_REG8(0x51), 0xa8}, {CCI_REG8(0x52), 0x47}, 334 {CCI_REG8(0x53), 0x38}, {CCI_REG8(0x54), 0xc7}, {CCI_REG8(0x56), 0x0e}, 335 {CCI_REG8(0x58), 0x08}, {CCI_REG8(0x5b), 0x00}, {CCI_REG8(0x5c), 0x74}, 336 {CCI_REG8(0x5d), 0x8b}, {CCI_REG8(0x61), 0xdb}, {CCI_REG8(0x62), 0xb8}, 337 {CCI_REG8(0x63), 0x86}, {CCI_REG8(0x64), 0xc0}, {CCI_REG8(0x65), 0x04}, 338 {CCI_REG8(0x67), 0xa8}, {CCI_REG8(0x68), 0xb0}, {CCI_REG8(0x69), 0x00}, 339 {CCI_REG8(0x6a), 0xa8}, {CCI_REG8(0x6b), 0xb0}, {CCI_REG8(0x6c), 0xaf}, 340 {CCI_REG8(0x6d), 0x8b}, {CCI_REG8(0x6e), 0x50}, {CCI_REG8(0x6f), 0x18}, 341 {CCI_REG8(0x73), 0xf0}, {CCI_REG8(0x70), 0x0d}, {CCI_REG8(0x71), 0x60}, 342 {CCI_REG8(0x72), 0x80}, {CCI_REG8(0x74), 0x01}, {CCI_REG8(0x75), 0x01}, 343 {CCI_REG8(0x7f), 0x0c}, {CCI_REG8(0x76), 0x70}, {CCI_REG8(0x77), 0x58}, 344 {CCI_REG8(0x78), 0xa0}, {CCI_REG8(0x79), 0x5e}, {CCI_REG8(0x7a), 0x54}, 345 {CCI_REG8(0x7b), 0x58}, 346 /* CC */ 347 {GC2145_REG_PAGE_SELECT, 0x02}, 348 {CCI_REG8(0xc0), 0x01}, {CCI_REG8(0xc1), 0x44}, {CCI_REG8(0xc2), 0xfd}, 349 {CCI_REG8(0xc3), 0x04}, {CCI_REG8(0xc4), 0xf0}, {CCI_REG8(0xc5), 0x48}, 350 {CCI_REG8(0xc6), 0xfd}, {CCI_REG8(0xc7), 0x46}, {CCI_REG8(0xc8), 0xfd}, 351 {CCI_REG8(0xc9), 0x02}, {CCI_REG8(0xca), 0xe0}, {CCI_REG8(0xcb), 0x45}, 352 {CCI_REG8(0xcc), 0xec}, {CCI_REG8(0xcd), 0x48}, {CCI_REG8(0xce), 0xf0}, 353 {CCI_REG8(0xcf), 0xf0}, {CCI_REG8(0xe3), 0x0c}, {CCI_REG8(0xe4), 0x4b}, 354 {CCI_REG8(0xe5), 0xe0}, 355 /* ABS */ 356 {GC2145_REG_PAGE_SELECT, 0x01}, 357 {CCI_REG8(0x9f), 0x40}, 358 /* Dark sun */ 359 {GC2145_REG_PAGE_SELECT, 0x02}, 360 {CCI_REG8(0x40), 0xbf}, {CCI_REG8(0x46), 0xcf}, 361 }; 362 363 #define GC2145_640_480_PIXELRATE 30000000 364 #define GC2145_640_480_LINKFREQ 120000000 365 #define GC2145_640_480_HBLANK 0x0130 366 #define GC2145_640_480_VBLANK 0x000c 367 static const struct cci_reg_sequence gc2145_mode_640_480_regs[] = { 368 {GC2145_REG_PAGE_SELECT, 0xf0}, {GC2145_REG_PAGE_SELECT, 0xf0}, 369 {GC2145_REG_PAGE_SELECT, 0xf0}, {CCI_REG8(0xfc), 0x06}, 370 {CCI_REG8(0xf6), 0x00}, {CCI_REG8(0xf7), 0x1d}, {CCI_REG8(0xf8), 0x86}, 371 {CCI_REG8(0xfa), 0x00}, {CCI_REG8(0xf9), 0x8e}, 372 /* Disable PAD IO */ 373 {GC2145_REG_PAD_IO, 0x00}, 374 {GC2145_REG_PAGE_SELECT, 0x00}, 375 /* Row/Col start - 0/0 */ 376 {GC2145_REG_ROW_START, 0x0000}, 377 {GC2145_REG_COL_START, 0x0000}, 378 /* Window size 1216/1618 */ 379 {GC2145_REG_WIN_HEIGHT, 0x04c0}, 380 {GC2145_REG_WIN_WIDTH, 0x0652}, 381 /* Scalar more */ 382 {CCI_REG8(0xfd), 0x01}, {CCI_REG8(0xfa), 0x00}, 383 /* Crop 640-480@0-0 */ 384 {GC2145_REG_CROP_ENABLE, 0x01}, 385 {GC2145_REG_CROP_Y, 0x0000}, 386 {GC2145_REG_CROP_X, 0x0000}, 387 {GC2145_REG_CROP_HEIGHT, 0x01e0}, 388 {GC2145_REG_CROP_WIDTH, 0x0280}, 389 /* Subsampling configuration */ 390 {CCI_REG8(0x99), 0x55}, {CCI_REG8(0x9a), 0x06}, {CCI_REG8(0x9b), 0x01}, 391 {CCI_REG8(0x9c), 0x23}, {CCI_REG8(0x9d), 0x00}, {CCI_REG8(0x9e), 0x00}, 392 {CCI_REG8(0x9f), 0x01}, {CCI_REG8(0xa0), 0x23}, {CCI_REG8(0xa1), 0x00}, 393 {CCI_REG8(0xa2), 0x00}, 394 {GC2145_REG_PAGE_SELECT, 0x01}, 395 /* AEC anti-flicker */ 396 {CCI_REG16(0x25), 0x0175}, 397 /* AEC exposure level 1-5 */ 398 {CCI_REG16(0x27), 0x045f}, {CCI_REG16(0x29), 0x045f}, 399 {CCI_REG16(0x2b), 0x045f}, {CCI_REG16(0x2d), 0x045f}, 400 }; 401 402 #define GC2145_1280_720_PIXELRATE 48000000 403 #define GC2145_1280_720_LINKFREQ 192000000 404 #define GC2145_1280_720_HBLANK 0x0156 405 #define GC2145_1280_720_VBLANK 0x0011 406 static const struct cci_reg_sequence gc2145_mode_1280_720_regs[] = { 407 {GC2145_REG_PAGE_SELECT, 0xf0}, {GC2145_REG_PAGE_SELECT, 0xf0}, 408 {GC2145_REG_PAGE_SELECT, 0xf0}, {CCI_REG8(0xfc), 0x06}, 409 {CCI_REG8(0xf6), 0x00}, {CCI_REG8(0xf7), 0x1d}, {CCI_REG8(0xf8), 0x83}, 410 {CCI_REG8(0xfa), 0x00}, {CCI_REG8(0xf9), 0x8e}, 411 /* Disable PAD IO */ 412 {GC2145_REG_PAD_IO, 0x00}, 413 {GC2145_REG_PAGE_SELECT, 0x00}, 414 /* Row/Col start - 240/160 */ 415 {GC2145_REG_ROW_START, 0x00f0}, 416 {GC2145_REG_COL_START, 0x00a0}, 417 /* Window size 736/1296 */ 418 {GC2145_REG_WIN_HEIGHT, 0x02e0}, 419 {GC2145_REG_WIN_WIDTH, 0x0510}, 420 /* Crop 1280-720@0-0 */ 421 {GC2145_REG_CROP_ENABLE, 0x01}, 422 {GC2145_REG_CROP_Y, 0x0000}, 423 {GC2145_REG_CROP_X, 0x0000}, 424 {GC2145_REG_CROP_HEIGHT, 0x02d0}, 425 {GC2145_REG_CROP_WIDTH, 0x0500}, 426 {GC2145_REG_PAGE_SELECT, 0x01}, 427 /* AEC anti-flicker */ 428 {CCI_REG16(0x25), 0x00e6}, 429 /* AEC exposure level 1-5 */ 430 {CCI_REG16(0x27), 0x02b2}, {CCI_REG16(0x29), 0x02b2}, 431 {CCI_REG16(0x2b), 0x02b2}, {CCI_REG16(0x2d), 0x02b2}, 432 }; 433 434 #define GC2145_1600_1200_PIXELRATE 60000000 435 #define GC2145_1600_1200_LINKFREQ 240000000 436 #define GC2145_1600_1200_HBLANK 0x0156 437 #define GC2145_1600_1200_VBLANK 0x0010 438 static const struct cci_reg_sequence gc2145_mode_1600_1200_regs[] = { 439 {GC2145_REG_PAGE_SELECT, 0xf0}, {GC2145_REG_PAGE_SELECT, 0xf0}, 440 {GC2145_REG_PAGE_SELECT, 0xf0}, {CCI_REG8(0xfc), 0x06}, 441 {CCI_REG8(0xf6), 0x00}, {CCI_REG8(0xf7), 0x1d}, {CCI_REG8(0xf8), 0x84}, 442 {CCI_REG8(0xfa), 0x00}, {CCI_REG8(0xf9), 0x8e}, 443 /* Disable PAD IO */ 444 {GC2145_REG_PAD_IO, 0x00}, 445 {GC2145_REG_PAGE_SELECT, 0x00}, 446 /* Row/Col start - 0/0 */ 447 {GC2145_REG_ROW_START, 0x0000}, 448 {GC2145_REG_COL_START, 0x0000}, 449 /* Window size: 1216/1618 */ 450 {GC2145_REG_WIN_HEIGHT, 0x04c0}, 451 {GC2145_REG_WIN_WIDTH, 0x0652}, 452 /* Crop 1600-1200@0-0 */ 453 {GC2145_REG_CROP_ENABLE, 0x01}, 454 {GC2145_REG_CROP_Y, 0x0000}, 455 {GC2145_REG_CROP_X, 0x0000}, 456 {GC2145_REG_CROP_HEIGHT, 0x04b0}, 457 {GC2145_REG_CROP_WIDTH, 0x0640}, 458 {GC2145_REG_PAGE_SELECT, 0x01}, 459 /* AEC anti-flicker */ 460 {CCI_REG16(0x25), 0x00fa}, 461 /* AEC exposure level 1-5 */ 462 {CCI_REG16(0x27), 0x04e2}, {CCI_REG16(0x29), 0x04e2}, 463 {CCI_REG16(0x2b), 0x04e2}, {CCI_REG16(0x2d), 0x04e2}, 464 }; 465 466 static const s64 gc2145_link_freq_menu[] = { 467 GC2145_640_480_LINKFREQ, 468 GC2145_1280_720_LINKFREQ, 469 GC2145_1600_1200_LINKFREQ, 470 }; 471 472 /* Regulators supplies */ 473 static const char * const gc2145_supply_name[] = { 474 "iovdd", /* Digital I/O (1.7-3V) suppply */ 475 "avdd", /* Analog (2.7-3V) supply */ 476 "dvdd", /* Digital Core (1.7-1.9V) supply */ 477 }; 478 479 #define GC2145_NUM_SUPPLIES ARRAY_SIZE(gc2145_supply_name) 480 481 /* Mode configs */ 482 #define GC2145_MODE_640X480 0 483 #define GC2145_MODE_1280X720 1 484 #define GC2145_MODE_1600X1200 2 485 static const struct gc2145_mode supported_modes[] = { 486 { 487 /* 640x480 30fps mode */ 488 .width = 640, 489 .height = 480, 490 .reg_seq = gc2145_mode_640_480_regs, 491 .reg_seq_size = ARRAY_SIZE(gc2145_mode_640_480_regs), 492 .pixel_rate = GC2145_640_480_PIXELRATE, 493 .crop = { 494 .top = 0, 495 .left = 0, 496 .width = 640, 497 .height = 480, 498 }, 499 .hblank = GC2145_640_480_HBLANK, 500 .vblank = GC2145_640_480_VBLANK, 501 .link_freq_index = GC2145_MODE_640X480, 502 }, 503 { 504 /* 1280x720 30fps mode */ 505 .width = 1280, 506 .height = 720, 507 .reg_seq = gc2145_mode_1280_720_regs, 508 .reg_seq_size = ARRAY_SIZE(gc2145_mode_1280_720_regs), 509 .pixel_rate = GC2145_1280_720_PIXELRATE, 510 .crop = { 511 .top = 160, 512 .left = 240, 513 .width = 1280, 514 .height = 720, 515 }, 516 .hblank = GC2145_1280_720_HBLANK, 517 .vblank = GC2145_1280_720_VBLANK, 518 .link_freq_index = GC2145_MODE_1280X720, 519 }, 520 { 521 /* 1600x1200 20fps mode */ 522 .width = 1600, 523 .height = 1200, 524 .reg_seq = gc2145_mode_1600_1200_regs, 525 .reg_seq_size = ARRAY_SIZE(gc2145_mode_1600_1200_regs), 526 .pixel_rate = GC2145_1600_1200_PIXELRATE, 527 .crop = { 528 .top = 0, 529 .left = 0, 530 .width = 1600, 531 .height = 1200, 532 }, 533 .hblank = GC2145_1600_1200_HBLANK, 534 .vblank = GC2145_1600_1200_VBLANK, 535 .link_freq_index = GC2145_MODE_1600X1200, 536 }, 537 }; 538 539 /** 540 * struct gc2145_format - GC2145 pixel format description 541 * @code: media bus (MBUS) associated code 542 * @colorspace: V4L2 colorspace 543 * @datatype: MIPI CSI2 data type 544 * @output_fmt: GC2145 output format 545 * @switch_bit: GC2145 first/second switch 546 * @row_col_switch: GC2145 switch row and/or column 547 */ 548 struct gc2145_format { 549 unsigned int code; 550 unsigned int colorspace; 551 unsigned char datatype; 552 unsigned char output_fmt; 553 bool switch_bit; 554 unsigned char row_col_switch; 555 }; 556 557 /* All supported formats */ 558 static const struct gc2145_format supported_formats[] = { 559 { 560 .code = MEDIA_BUS_FMT_UYVY8_1X16, 561 .colorspace = V4L2_COLORSPACE_SRGB, 562 .datatype = MIPI_CSI2_DT_YUV422_8B, 563 .output_fmt = 0x00, 564 }, 565 { 566 .code = MEDIA_BUS_FMT_VYUY8_1X16, 567 .colorspace = V4L2_COLORSPACE_SRGB, 568 .datatype = MIPI_CSI2_DT_YUV422_8B, 569 .output_fmt = 0x01, 570 }, 571 { 572 .code = MEDIA_BUS_FMT_YUYV8_1X16, 573 .colorspace = V4L2_COLORSPACE_SRGB, 574 .datatype = MIPI_CSI2_DT_YUV422_8B, 575 .output_fmt = 0x02, 576 }, 577 { 578 .code = MEDIA_BUS_FMT_YVYU8_1X16, 579 .colorspace = V4L2_COLORSPACE_SRGB, 580 .datatype = MIPI_CSI2_DT_YUV422_8B, 581 .output_fmt = 0x03, 582 }, 583 { 584 .code = MEDIA_BUS_FMT_RGB565_1X16, 585 .colorspace = V4L2_COLORSPACE_SRGB, 586 .datatype = MIPI_CSI2_DT_RGB565, 587 .output_fmt = 0x06, 588 .switch_bit = true, 589 }, 590 { 591 .code = MEDIA_BUS_FMT_SGRBG8_1X8, 592 .colorspace = V4L2_COLORSPACE_RAW, 593 .datatype = MIPI_CSI2_DT_RAW8, 594 .output_fmt = 0x17, 595 .row_col_switch = GC2145_SYNC_MODE_COL_SWITCH, 596 }, 597 { 598 .code = MEDIA_BUS_FMT_SRGGB8_1X8, 599 .colorspace = V4L2_COLORSPACE_RAW, 600 .datatype = MIPI_CSI2_DT_RAW8, 601 .output_fmt = 0x17, 602 .row_col_switch = GC2145_SYNC_MODE_COL_SWITCH | GC2145_SYNC_MODE_ROW_SWITCH, 603 }, 604 { 605 .code = MEDIA_BUS_FMT_SBGGR8_1X8, 606 .colorspace = V4L2_COLORSPACE_RAW, 607 .datatype = MIPI_CSI2_DT_RAW8, 608 .output_fmt = 0x17, 609 .row_col_switch = 0, 610 }, 611 { 612 .code = MEDIA_BUS_FMT_SGBRG8_1X8, 613 .colorspace = V4L2_COLORSPACE_RAW, 614 .datatype = MIPI_CSI2_DT_RAW8, 615 .output_fmt = 0x17, 616 .row_col_switch = GC2145_SYNC_MODE_ROW_SWITCH, 617 }, 618 }; 619 620 struct gc2145_ctrls { 621 struct v4l2_ctrl_handler handler; 622 struct v4l2_ctrl *pixel_rate; 623 struct v4l2_ctrl *link_freq; 624 struct v4l2_ctrl *test_pattern; 625 struct v4l2_ctrl *hflip; 626 struct v4l2_ctrl *vflip; 627 struct v4l2_ctrl *hblank; 628 struct v4l2_ctrl *vblank; 629 }; 630 631 struct gc2145 { 632 struct v4l2_subdev sd; 633 struct media_pad pad; 634 635 struct regmap *regmap; 636 struct clk *xclk; 637 638 struct gpio_desc *reset_gpio; 639 struct gpio_desc *powerdown_gpio; 640 struct regulator_bulk_data supplies[GC2145_NUM_SUPPLIES]; 641 642 /* V4L2 controls */ 643 struct gc2145_ctrls ctrls; 644 645 /* Current mode */ 646 const struct gc2145_mode *mode; 647 }; 648 649 static inline struct gc2145 *to_gc2145(struct v4l2_subdev *_sd) 650 { 651 return container_of(_sd, struct gc2145, sd); 652 } 653 654 static inline struct v4l2_subdev *gc2145_ctrl_to_sd(struct v4l2_ctrl *ctrl) 655 { 656 return &container_of(ctrl->handler, struct gc2145, 657 ctrls.handler)->sd; 658 } 659 660 static const struct gc2145_format * 661 gc2145_get_format_code(struct gc2145 *gc2145, u32 code) 662 { 663 unsigned int i; 664 665 for (i = 0; i < ARRAY_SIZE(supported_formats); i++) { 666 if (supported_formats[i].code == code) 667 break; 668 } 669 670 if (i >= ARRAY_SIZE(supported_formats)) 671 i = 0; 672 673 return &supported_formats[i]; 674 } 675 676 static void gc2145_update_pad_format(struct gc2145 *gc2145, 677 const struct gc2145_mode *mode, 678 struct v4l2_mbus_framefmt *fmt, u32 code, 679 u32 colorspace) 680 { 681 fmt->code = code; 682 fmt->width = mode->width; 683 fmt->height = mode->height; 684 fmt->field = V4L2_FIELD_NONE; 685 fmt->colorspace = V4L2_COLORSPACE_SRGB; 686 fmt->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 687 fmt->quantization = V4L2_QUANTIZATION_DEFAULT; 688 fmt->xfer_func = V4L2_XFER_FUNC_DEFAULT; 689 } 690 691 static int gc2145_init_state(struct v4l2_subdev *sd, 692 struct v4l2_subdev_state *state) 693 { 694 struct gc2145 *gc2145 = to_gc2145(sd); 695 struct v4l2_mbus_framefmt *format; 696 struct v4l2_rect *crop; 697 698 /* Initialize pad format */ 699 format = v4l2_subdev_state_get_format(state, 0); 700 gc2145_update_pad_format(gc2145, &supported_modes[0], format, 701 MEDIA_BUS_FMT_RGB565_1X16, 702 V4L2_COLORSPACE_SRGB); 703 704 /* Initialize crop rectangle. */ 705 crop = v4l2_subdev_state_get_crop(state, 0); 706 *crop = supported_modes[0].crop; 707 708 return 0; 709 } 710 711 static int gc2145_get_selection(struct v4l2_subdev *sd, 712 struct v4l2_subdev_state *sd_state, 713 struct v4l2_subdev_selection *sel) 714 { 715 switch (sel->target) { 716 case V4L2_SEL_TGT_CROP: 717 sel->r = *v4l2_subdev_state_get_crop(sd_state, 0); 718 return 0; 719 720 case V4L2_SEL_TGT_NATIVE_SIZE: 721 sel->r.top = 0; 722 sel->r.left = 0; 723 sel->r.width = GC2145_NATIVE_WIDTH; 724 sel->r.height = GC2145_NATIVE_HEIGHT; 725 726 return 0; 727 728 case V4L2_SEL_TGT_CROP_DEFAULT: 729 case V4L2_SEL_TGT_CROP_BOUNDS: 730 sel->r.top = 0; 731 sel->r.left = 0; 732 sel->r.width = 1600; 733 sel->r.height = 1200; 734 735 return 0; 736 } 737 738 return -EINVAL; 739 } 740 741 static int gc2145_enum_mbus_code(struct v4l2_subdev *sd, 742 struct v4l2_subdev_state *sd_state, 743 struct v4l2_subdev_mbus_code_enum *code) 744 { 745 if (code->index >= ARRAY_SIZE(supported_formats)) 746 return -EINVAL; 747 748 code->code = supported_formats[code->index].code; 749 return 0; 750 } 751 752 static int gc2145_enum_frame_size(struct v4l2_subdev *sd, 753 struct v4l2_subdev_state *sd_state, 754 struct v4l2_subdev_frame_size_enum *fse) 755 { 756 struct gc2145 *gc2145 = to_gc2145(sd); 757 const struct gc2145_format *gc2145_format; 758 u32 code; 759 760 if (fse->index >= ARRAY_SIZE(supported_modes)) 761 return -EINVAL; 762 763 gc2145_format = gc2145_get_format_code(gc2145, fse->code); 764 code = gc2145_format->code; 765 if (fse->code != code) 766 return -EINVAL; 767 768 fse->min_width = supported_modes[fse->index].width; 769 fse->max_width = fse->min_width; 770 fse->min_height = supported_modes[fse->index].height; 771 fse->max_height = fse->min_height; 772 773 return 0; 774 } 775 776 static int gc2145_set_pad_format(struct v4l2_subdev *sd, 777 struct v4l2_subdev_state *sd_state, 778 struct v4l2_subdev_format *fmt) 779 { 780 struct gc2145 *gc2145 = to_gc2145(sd); 781 const struct gc2145_mode *mode; 782 const struct gc2145_format *gc2145_fmt; 783 struct v4l2_mbus_framefmt *framefmt; 784 struct gc2145_ctrls *ctrls = &gc2145->ctrls; 785 struct v4l2_rect *crop; 786 787 gc2145_fmt = gc2145_get_format_code(gc2145, fmt->format.code); 788 mode = v4l2_find_nearest_size(supported_modes, 789 ARRAY_SIZE(supported_modes), 790 width, height, 791 fmt->format.width, fmt->format.height); 792 793 /* In RAW mode, VGA is not possible so use 720p instead */ 794 if (gc2145_fmt->colorspace == V4L2_COLORSPACE_RAW && 795 mode == &supported_modes[GC2145_MODE_640X480]) 796 mode = &supported_modes[GC2145_MODE_1280X720]; 797 798 gc2145_update_pad_format(gc2145, mode, &fmt->format, gc2145_fmt->code, 799 gc2145_fmt->colorspace); 800 framefmt = v4l2_subdev_state_get_format(sd_state, fmt->pad); 801 if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 802 gc2145->mode = mode; 803 /* Update pixel_rate based on the mode */ 804 __v4l2_ctrl_s_ctrl_int64(ctrls->pixel_rate, mode->pixel_rate); 805 /* Update link_freq based on the mode */ 806 __v4l2_ctrl_s_ctrl(ctrls->link_freq, mode->link_freq_index); 807 /* Update hblank/vblank based on the mode */ 808 __v4l2_ctrl_s_ctrl(ctrls->hblank, mode->hblank); 809 __v4l2_ctrl_s_ctrl(ctrls->vblank, mode->vblank); 810 } 811 *framefmt = fmt->format; 812 crop = v4l2_subdev_state_get_crop(sd_state, fmt->pad); 813 *crop = mode->crop; 814 815 return 0; 816 } 817 818 static const struct cci_reg_sequence gc2145_common_mipi_regs[] = { 819 {GC2145_REG_PAGE_SELECT, 0x03}, 820 {GC2145_REG_DPHY_ANALOG_MODE1, GC2145_DPHY_MODE_PHY_CLK_EN | 821 GC2145_DPHY_MODE_PHY_LANE0_EN | 822 GC2145_DPHY_MODE_PHY_LANE1_EN | 823 GC2145_DPHY_MODE_PHY_CLK_LANE_P2S_SEL}, 824 {GC2145_REG_DPHY_ANALOG_MODE2, GC2145_DPHY_CLK_DIFF(2) | 825 GC2145_DPHY_LANE0_DIFF(2)}, 826 {GC2145_REG_DPHY_ANALOG_MODE3, GC2145_DPHY_LANE1_DIFF(0) | 827 GC2145_DPHY_CLK_DELAY}, 828 {GC2145_REG_FIFO_MODE, GC2145_FIFO_MODE_READ_GATE | 829 GC2145_FIFO_MODE_MIPI_CLK_MODULE}, 830 {GC2145_REG_DPHY_MODE, GC2145_DPHY_MODE_TRIGGER_PROG}, 831 /* Clock & Data lanes timing */ 832 {GC2145_REG_T_LPX, 0x10}, 833 {GC2145_REG_T_CLK_HS_PREPARE, 0x04}, {GC2145_REG_T_CLK_ZERO, 0x10}, 834 {GC2145_REG_T_CLK_PRE, 0x10}, {GC2145_REG_T_CLK_POST, 0x10}, 835 {GC2145_REG_T_CLK_TRAIL, 0x05}, 836 {GC2145_REG_T_HS_PREPARE, 0x03}, {GC2145_REG_T_HS_ZERO, 0x0a}, 837 {GC2145_REG_T_HS_TRAIL, 0x06}, 838 }; 839 840 static int gc2145_config_mipi_mode(struct gc2145 *gc2145, 841 const struct gc2145_format *gc2145_format) 842 { 843 u16 lwc, fifo_full_lvl; 844 int ret = 0; 845 846 /* Common MIPI settings */ 847 cci_multi_reg_write(gc2145->regmap, gc2145_common_mipi_regs, 848 ARRAY_SIZE(gc2145_common_mipi_regs), &ret); 849 850 /* 851 * Adjust the MIPI buffer settings. 852 * For YUV/RGB, LWC = image width * 2 853 * For RAW8, LWC = image width 854 * For RAW10, LWC = image width * 1.25 855 */ 856 if (gc2145_format->colorspace != V4L2_COLORSPACE_RAW) 857 lwc = gc2145->mode->width * 2; 858 else 859 lwc = gc2145->mode->width; 860 861 cci_write(gc2145->regmap, GC2145_REG_LWC, lwc, &ret); 862 863 /* 864 * Adjust the MIPI FIFO Full Level 865 * 640x480 RGB: 0x0190 866 * 1280x720 / 1600x1200 (aka no scaler) non RAW: 0x0001 867 * 1600x1200 RAW: 0x0190 868 */ 869 if (gc2145_format->colorspace != V4L2_COLORSPACE_RAW) { 870 if (gc2145->mode->width == 1280 || gc2145->mode->width == 1600) 871 fifo_full_lvl = 0x0001; 872 else 873 fifo_full_lvl = 0x0190; 874 } else { 875 fifo_full_lvl = 0x0190; 876 } 877 878 cci_write(gc2145->regmap, GC2145_REG_FIFO_FULL_LVL, 879 fifo_full_lvl, &ret); 880 881 /* 882 * Set the FIFO gate mode / MIPI wdiv set: 883 * 0xf1 in case of RAW mode and 0xf0 otherwise 884 */ 885 cci_write(gc2145->regmap, GC2145_REG_FIFO_GATE_MODE, 886 gc2145_format->colorspace == V4L2_COLORSPACE_RAW ? 887 0xf1 : 0xf0, &ret); 888 889 /* Set the MIPI data type */ 890 cci_write(gc2145->regmap, GC2145_REG_MIPI_DT, 891 gc2145_format->datatype, &ret); 892 893 /* Configure mode and enable CSI */ 894 cci_write(gc2145->regmap, GC2145_REG_BUF_CSI2_MODE, 895 GC2145_CSI2_MODE_RAW8 | GC2145_CSI2_MODE_DOUBLE | 896 GC2145_CSI2_MODE_EN | GC2145_CSI2_MODE_MIPI_EN, &ret); 897 898 return ret; 899 } 900 901 static int gc2145_enable_streams(struct v4l2_subdev *sd, 902 struct v4l2_subdev_state *state, u32 pad, 903 u64 streams_mask) 904 { 905 struct gc2145 *gc2145 = to_gc2145(sd); 906 struct i2c_client *client = v4l2_get_subdevdata(&gc2145->sd); 907 const struct gc2145_format *gc2145_format; 908 struct v4l2_mbus_framefmt *fmt; 909 int ret; 910 911 ret = pm_runtime_resume_and_get(&client->dev); 912 if (ret < 0) 913 return ret; 914 915 /* Apply default values of current mode */ 916 cci_multi_reg_write(gc2145->regmap, gc2145->mode->reg_seq, 917 gc2145->mode->reg_seq_size, &ret); 918 cci_multi_reg_write(gc2145->regmap, gc2145_common_regs, 919 ARRAY_SIZE(gc2145_common_regs), &ret); 920 if (ret) { 921 dev_err(&client->dev, "%s failed to write regs\n", __func__); 922 goto err_rpm_put; 923 } 924 925 fmt = v4l2_subdev_state_get_format(state, 0); 926 gc2145_format = gc2145_get_format_code(gc2145, fmt->code); 927 928 /* Set the output format */ 929 cci_write(gc2145->regmap, GC2145_REG_PAGE_SELECT, 0x00, &ret); 930 931 cci_write(gc2145->regmap, GC2145_REG_OUTPUT_FMT, 932 gc2145_format->output_fmt, &ret); 933 cci_update_bits(gc2145->regmap, GC2145_REG_BYPASS_MODE, 934 GC2145_BYPASS_MODE_SWITCH, 935 gc2145_format->switch_bit ? GC2145_BYPASS_MODE_SWITCH 936 : 0, &ret); 937 cci_update_bits(gc2145->regmap, GC2145_REG_SYNC_MODE, 938 GC2145_SYNC_MODE_COL_SWITCH | 939 GC2145_SYNC_MODE_ROW_SWITCH, 940 gc2145_format->row_col_switch, &ret); 941 if (ret) { 942 dev_err(&client->dev, "%s failed to write regs\n", __func__); 943 goto err_rpm_put; 944 } 945 946 /* Apply customized values from user */ 947 ret = __v4l2_ctrl_handler_setup(&gc2145->ctrls.handler); 948 if (ret) { 949 dev_err(&client->dev, "%s failed to apply ctrls\n", __func__); 950 goto err_rpm_put; 951 } 952 953 /* Perform MIPI specific configuration */ 954 ret = gc2145_config_mipi_mode(gc2145, gc2145_format); 955 if (ret) { 956 dev_err(&client->dev, "%s failed to write mipi conf\n", 957 __func__); 958 goto err_rpm_put; 959 } 960 961 cci_write(gc2145->regmap, GC2145_REG_PAGE_SELECT, 0x00, &ret); 962 963 return 0; 964 965 err_rpm_put: 966 pm_runtime_mark_last_busy(&client->dev); 967 pm_runtime_put_autosuspend(&client->dev); 968 return ret; 969 } 970 971 static int gc2145_disable_streams(struct v4l2_subdev *sd, 972 struct v4l2_subdev_state *state, u32 pad, 973 u64 streams_mask) 974 { 975 struct gc2145 *gc2145 = to_gc2145(sd); 976 struct i2c_client *client = v4l2_get_subdevdata(&gc2145->sd); 977 int ret = 0; 978 979 /* Disable lanes & mipi streaming */ 980 cci_write(gc2145->regmap, GC2145_REG_PAGE_SELECT, 0x03, &ret); 981 cci_update_bits(gc2145->regmap, GC2145_REG_BUF_CSI2_MODE, 982 GC2145_CSI2_MODE_EN | GC2145_CSI2_MODE_MIPI_EN, 0, 983 &ret); 984 cci_write(gc2145->regmap, GC2145_REG_PAGE_SELECT, 0x00, &ret); 985 if (ret) 986 dev_err(&client->dev, "%s failed to write regs\n", __func__); 987 988 pm_runtime_mark_last_busy(&client->dev); 989 pm_runtime_put_autosuspend(&client->dev); 990 991 return ret; 992 } 993 994 /* Power/clock management functions */ 995 static int gc2145_power_on(struct device *dev) 996 { 997 struct v4l2_subdev *sd = dev_get_drvdata(dev); 998 struct gc2145 *gc2145 = to_gc2145(sd); 999 int ret; 1000 1001 ret = regulator_bulk_enable(GC2145_NUM_SUPPLIES, gc2145->supplies); 1002 if (ret) { 1003 dev_err(dev, "failed to enable regulators\n"); 1004 return ret; 1005 } 1006 1007 ret = clk_prepare_enable(gc2145->xclk); 1008 if (ret) { 1009 dev_err(dev, "failed to enable clock\n"); 1010 goto reg_off; 1011 } 1012 1013 gpiod_set_value_cansleep(gc2145->powerdown_gpio, 0); 1014 gpiod_set_value_cansleep(gc2145->reset_gpio, 0); 1015 1016 /* 1017 * Datasheet doesn't mention timing between PWDN/RESETB control and 1018 * i2c access however, experimentation shows that a rather big delay is 1019 * needed. 1020 */ 1021 msleep(41); 1022 1023 return 0; 1024 1025 reg_off: 1026 regulator_bulk_disable(GC2145_NUM_SUPPLIES, gc2145->supplies); 1027 1028 return ret; 1029 } 1030 1031 static int gc2145_power_off(struct device *dev) 1032 { 1033 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1034 struct gc2145 *gc2145 = to_gc2145(sd); 1035 1036 gpiod_set_value_cansleep(gc2145->powerdown_gpio, 1); 1037 gpiod_set_value_cansleep(gc2145->reset_gpio, 1); 1038 clk_disable_unprepare(gc2145->xclk); 1039 regulator_bulk_disable(GC2145_NUM_SUPPLIES, gc2145->supplies); 1040 1041 return 0; 1042 } 1043 1044 static int gc2145_get_regulators(struct gc2145 *gc2145) 1045 { 1046 struct i2c_client *client = v4l2_get_subdevdata(&gc2145->sd); 1047 unsigned int i; 1048 1049 for (i = 0; i < GC2145_NUM_SUPPLIES; i++) 1050 gc2145->supplies[i].supply = gc2145_supply_name[i]; 1051 1052 return devm_regulator_bulk_get(&client->dev, GC2145_NUM_SUPPLIES, 1053 gc2145->supplies); 1054 } 1055 1056 /* Verify chip ID */ 1057 static int gc2145_identify_module(struct gc2145 *gc2145) 1058 { 1059 struct i2c_client *client = v4l2_get_subdevdata(&gc2145->sd); 1060 int ret; 1061 u64 chip_id; 1062 1063 ret = cci_read(gc2145->regmap, GC2145_REG_CHIP_ID, &chip_id, NULL); 1064 if (ret) { 1065 dev_err(&client->dev, "failed to read chip id (%d)\n", ret); 1066 return ret; 1067 } 1068 1069 if (chip_id != GC2145_CHIP_ID) { 1070 dev_err(&client->dev, "chip id mismatch: %x!=%llx\n", 1071 GC2145_CHIP_ID, chip_id); 1072 return -EIO; 1073 } 1074 1075 return 0; 1076 } 1077 1078 static const char * const test_pattern_menu[] = { 1079 "Disabled", 1080 "Colored patterns", 1081 "Uniform white", 1082 "Uniform yellow", 1083 "Uniform cyan", 1084 "Uniform green", 1085 "Uniform magenta", 1086 "Uniform red", 1087 "Uniform black", 1088 }; 1089 1090 #define GC2145_TEST_PATTERN_ENABLE BIT(0) 1091 #define GC2145_TEST_PATTERN_UXGA BIT(3) 1092 1093 #define GC2145_TEST_UNIFORM BIT(3) 1094 #define GC2145_TEST_WHITE (4 << 4) 1095 #define GC2145_TEST_YELLOW (8 << 4) 1096 #define GC2145_TEST_CYAN (9 << 4) 1097 #define GC2145_TEST_GREEN (6 << 4) 1098 #define GC2145_TEST_MAGENTA (10 << 4) 1099 #define GC2145_TEST_RED (5 << 4) 1100 #define GC2145_TEST_BLACK (0) 1101 1102 static const u8 test_pattern_val[] = { 1103 0, 1104 GC2145_TEST_PATTERN_ENABLE, 1105 GC2145_TEST_UNIFORM | GC2145_TEST_WHITE, 1106 GC2145_TEST_UNIFORM | GC2145_TEST_YELLOW, 1107 GC2145_TEST_UNIFORM | GC2145_TEST_CYAN, 1108 GC2145_TEST_UNIFORM | GC2145_TEST_GREEN, 1109 GC2145_TEST_UNIFORM | GC2145_TEST_MAGENTA, 1110 GC2145_TEST_UNIFORM | GC2145_TEST_RED, 1111 GC2145_TEST_UNIFORM | GC2145_TEST_BLACK, 1112 }; 1113 1114 static const struct v4l2_subdev_video_ops gc2145_video_ops = { 1115 .s_stream = v4l2_subdev_s_stream_helper, 1116 }; 1117 1118 static const struct v4l2_subdev_pad_ops gc2145_pad_ops = { 1119 .enum_mbus_code = gc2145_enum_mbus_code, 1120 .get_fmt = v4l2_subdev_get_fmt, 1121 .set_fmt = gc2145_set_pad_format, 1122 .get_selection = gc2145_get_selection, 1123 .enum_frame_size = gc2145_enum_frame_size, 1124 .enable_streams = gc2145_enable_streams, 1125 .disable_streams = gc2145_disable_streams, 1126 }; 1127 1128 static const struct v4l2_subdev_ops gc2145_subdev_ops = { 1129 .video = &gc2145_video_ops, 1130 .pad = &gc2145_pad_ops, 1131 }; 1132 1133 static const struct v4l2_subdev_internal_ops gc2145_subdev_internal_ops = { 1134 .init_state = gc2145_init_state, 1135 }; 1136 1137 static int gc2145_set_ctrl_test_pattern(struct gc2145 *gc2145, int value) 1138 { 1139 int ret = 0; 1140 1141 if (!value) { 1142 /* Disable test pattern */ 1143 cci_write(gc2145->regmap, GC2145_REG_DEBUG_MODE2, 0, &ret); 1144 return cci_write(gc2145->regmap, GC2145_REG_DEBUG_MODE3, 0, 1145 &ret); 1146 } 1147 1148 /* Enable test pattern, colored or uniform */ 1149 cci_write(gc2145->regmap, GC2145_REG_DEBUG_MODE2, 1150 GC2145_TEST_PATTERN_ENABLE | GC2145_TEST_PATTERN_UXGA, &ret); 1151 1152 if (!(test_pattern_val[value] & GC2145_TEST_UNIFORM)) 1153 return cci_write(gc2145->regmap, GC2145_REG_DEBUG_MODE3, 0, 1154 &ret); 1155 1156 /* Uniform */ 1157 return cci_write(gc2145->regmap, GC2145_REG_DEBUG_MODE3, 1158 test_pattern_val[value], &ret); 1159 } 1160 1161 static int gc2145_s_ctrl(struct v4l2_ctrl *ctrl) 1162 { 1163 struct v4l2_subdev *sd = gc2145_ctrl_to_sd(ctrl); 1164 struct i2c_client *client = v4l2_get_subdevdata(sd); 1165 struct gc2145 *gc2145 = to_gc2145(sd); 1166 int ret; 1167 1168 if (pm_runtime_get_if_in_use(&client->dev) == 0) 1169 return 0; 1170 1171 switch (ctrl->id) { 1172 case V4L2_CID_HBLANK: 1173 ret = cci_write(gc2145->regmap, GC2145_REG_HBLANK, ctrl->val, 1174 NULL); 1175 break; 1176 case V4L2_CID_VBLANK: 1177 ret = cci_write(gc2145->regmap, GC2145_REG_VBLANK, ctrl->val, 1178 NULL); 1179 break; 1180 case V4L2_CID_TEST_PATTERN: 1181 ret = gc2145_set_ctrl_test_pattern(gc2145, ctrl->val); 1182 break; 1183 case V4L2_CID_HFLIP: 1184 ret = cci_update_bits(gc2145->regmap, GC2145_REG_ANALOG_MODE1, 1185 BIT(0), (ctrl->val ? BIT(0) : 0), NULL); 1186 break; 1187 case V4L2_CID_VFLIP: 1188 ret = cci_update_bits(gc2145->regmap, GC2145_REG_ANALOG_MODE1, 1189 BIT(1), (ctrl->val ? BIT(1) : 0), NULL); 1190 break; 1191 default: 1192 ret = -EINVAL; 1193 break; 1194 } 1195 1196 pm_runtime_mark_last_busy(&client->dev); 1197 pm_runtime_put_autosuspend(&client->dev); 1198 1199 return ret; 1200 } 1201 1202 static const struct v4l2_ctrl_ops gc2145_ctrl_ops = { 1203 .s_ctrl = gc2145_s_ctrl, 1204 }; 1205 1206 /* Initialize control handlers */ 1207 static int gc2145_init_controls(struct gc2145 *gc2145) 1208 { 1209 struct i2c_client *client = v4l2_get_subdevdata(&gc2145->sd); 1210 const struct v4l2_ctrl_ops *ops = &gc2145_ctrl_ops; 1211 struct gc2145_ctrls *ctrls = &gc2145->ctrls; 1212 struct v4l2_ctrl_handler *hdl = &ctrls->handler; 1213 struct v4l2_fwnode_device_properties props; 1214 int ret; 1215 1216 ret = v4l2_ctrl_handler_init(hdl, 12); 1217 if (ret) 1218 return ret; 1219 1220 ctrls->pixel_rate = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_PIXEL_RATE, 1221 GC2145_640_480_PIXELRATE, 1222 GC2145_1600_1200_PIXELRATE, 1, 1223 supported_modes[0].pixel_rate); 1224 1225 ctrls->link_freq = v4l2_ctrl_new_int_menu(hdl, ops, V4L2_CID_LINK_FREQ, 1226 ARRAY_SIZE(gc2145_link_freq_menu) - 1, 1227 0, gc2145_link_freq_menu); 1228 if (ctrls->link_freq) 1229 ctrls->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1230 1231 ctrls->hblank = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HBLANK, 1232 0, 0xfff, 1, GC2145_640_480_HBLANK); 1233 1234 ctrls->vblank = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_VBLANK, 1235 0, 0x1fff, 1, GC2145_640_480_VBLANK); 1236 1237 ctrls->test_pattern = 1238 v4l2_ctrl_new_std_menu_items(hdl, ops, V4L2_CID_TEST_PATTERN, 1239 ARRAY_SIZE(test_pattern_menu) - 1, 1240 0, 0, test_pattern_menu); 1241 ctrls->hflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HFLIP, 1242 0, 1, 1, 0); 1243 ctrls->vflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_VFLIP, 1244 0, 1, 1, 0); 1245 1246 if (hdl->error) { 1247 ret = hdl->error; 1248 dev_err(&client->dev, "control init failed (%d)\n", ret); 1249 goto error; 1250 } 1251 1252 ret = v4l2_fwnode_device_parse(&client->dev, &props); 1253 if (ret) 1254 goto error; 1255 1256 ret = v4l2_ctrl_new_fwnode_properties(hdl, &gc2145_ctrl_ops, 1257 &props); 1258 if (ret) 1259 goto error; 1260 1261 gc2145->sd.ctrl_handler = hdl; 1262 1263 return 0; 1264 1265 error: 1266 v4l2_ctrl_handler_free(hdl); 1267 1268 return ret; 1269 } 1270 1271 static int gc2145_check_hwcfg(struct device *dev) 1272 { 1273 struct fwnode_handle *endpoint; 1274 struct v4l2_fwnode_endpoint ep_cfg = { 1275 .bus_type = V4L2_MBUS_CSI2_DPHY 1276 }; 1277 int ret; 1278 1279 endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL); 1280 if (!endpoint) { 1281 dev_err(dev, "endpoint node not found\n"); 1282 return -EINVAL; 1283 } 1284 1285 ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &ep_cfg); 1286 fwnode_handle_put(endpoint); 1287 if (ret) 1288 return ret; 1289 1290 /* Check the number of MIPI CSI2 data lanes */ 1291 if (ep_cfg.bus.mipi_csi2.num_data_lanes != 2) { 1292 dev_err(dev, "only 2 data lanes are currently supported\n"); 1293 ret = -EINVAL; 1294 goto out; 1295 } 1296 1297 /* Check the link frequency set in device tree */ 1298 if (!ep_cfg.nr_of_link_frequencies) { 1299 dev_err(dev, "link-frequency property not found in DT\n"); 1300 ret = -EINVAL; 1301 goto out; 1302 } 1303 1304 if (ep_cfg.nr_of_link_frequencies != 3 || 1305 ep_cfg.link_frequencies[0] != GC2145_640_480_LINKFREQ || 1306 ep_cfg.link_frequencies[1] != GC2145_1280_720_LINKFREQ || 1307 ep_cfg.link_frequencies[2] != GC2145_1600_1200_LINKFREQ) { 1308 dev_err(dev, "Invalid link-frequencies provided\n"); 1309 ret = -EINVAL; 1310 } 1311 1312 out: 1313 v4l2_fwnode_endpoint_free(&ep_cfg); 1314 1315 return ret; 1316 } 1317 1318 static int gc2145_probe(struct i2c_client *client) 1319 { 1320 struct device *dev = &client->dev; 1321 unsigned int xclk_freq; 1322 struct gc2145 *gc2145; 1323 int ret; 1324 1325 gc2145 = devm_kzalloc(&client->dev, sizeof(*gc2145), GFP_KERNEL); 1326 if (!gc2145) 1327 return -ENOMEM; 1328 1329 v4l2_i2c_subdev_init(&gc2145->sd, client, &gc2145_subdev_ops); 1330 gc2145->sd.internal_ops = &gc2145_subdev_internal_ops; 1331 1332 /* Check the hardware configuration in device tree */ 1333 if (gc2145_check_hwcfg(dev)) 1334 return -EINVAL; 1335 1336 /* Get system clock (xclk) */ 1337 gc2145->xclk = devm_clk_get(dev, NULL); 1338 if (IS_ERR(gc2145->xclk)) 1339 return dev_err_probe(dev, PTR_ERR(gc2145->xclk), 1340 "failed to get xclk\n"); 1341 1342 xclk_freq = clk_get_rate(gc2145->xclk); 1343 if (xclk_freq != GC2145_XCLK_FREQ) { 1344 dev_err(dev, "xclk frequency not supported: %d Hz\n", 1345 xclk_freq); 1346 return -EINVAL; 1347 } 1348 1349 ret = gc2145_get_regulators(gc2145); 1350 if (ret) 1351 return dev_err_probe(dev, ret, 1352 "failed to get regulators\n"); 1353 1354 /* Request optional reset pin */ 1355 gc2145->reset_gpio = devm_gpiod_get_optional(dev, "reset", 1356 GPIOD_OUT_HIGH); 1357 if (IS_ERR(gc2145->reset_gpio)) 1358 return dev_err_probe(dev, PTR_ERR(gc2145->reset_gpio), 1359 "failed to get reset_gpio\n"); 1360 1361 /* Request optional powerdown pin */ 1362 gc2145->powerdown_gpio = devm_gpiod_get_optional(dev, "powerdown", 1363 GPIOD_OUT_HIGH); 1364 if (IS_ERR(gc2145->powerdown_gpio)) 1365 return dev_err_probe(dev, PTR_ERR(gc2145->powerdown_gpio), 1366 "failed to get powerdown_gpio\n"); 1367 1368 /* Initialise the regmap for further cci access */ 1369 gc2145->regmap = devm_cci_regmap_init_i2c(client, 8); 1370 if (IS_ERR(gc2145->regmap)) 1371 return dev_err_probe(dev, PTR_ERR(gc2145->regmap), 1372 "failed to get cci regmap\n"); 1373 1374 /* 1375 * The sensor must be powered for gc2145_identify_module() 1376 * to be able to read the CHIP_ID register 1377 */ 1378 ret = gc2145_power_on(dev); 1379 if (ret) 1380 return ret; 1381 1382 ret = gc2145_identify_module(gc2145); 1383 if (ret) 1384 goto error_power_off; 1385 1386 /* Set default mode */ 1387 gc2145->mode = &supported_modes[0]; 1388 1389 ret = gc2145_init_controls(gc2145); 1390 if (ret) 1391 goto error_power_off; 1392 1393 /* Initialize subdev */ 1394 gc2145->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1395 gc2145->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1396 1397 /* Initialize source pad */ 1398 gc2145->pad.flags = MEDIA_PAD_FL_SOURCE; 1399 1400 ret = media_entity_pads_init(&gc2145->sd.entity, 1, &gc2145->pad); 1401 if (ret) { 1402 dev_err(dev, "failed to init entity pads: %d\n", ret); 1403 goto error_handler_free; 1404 } 1405 1406 gc2145->sd.state_lock = gc2145->ctrls.handler.lock; 1407 ret = v4l2_subdev_init_finalize(&gc2145->sd); 1408 if (ret < 0) { 1409 dev_err(dev, "subdev init error: %d\n", ret); 1410 goto error_media_entity; 1411 } 1412 1413 /* Enable runtime PM and turn off the device */ 1414 pm_runtime_set_active(dev); 1415 pm_runtime_get_noresume(&client->dev); 1416 pm_runtime_enable(dev); 1417 1418 pm_runtime_set_autosuspend_delay(&client->dev, 1000); 1419 pm_runtime_use_autosuspend(&client->dev); 1420 pm_runtime_put_autosuspend(&client->dev); 1421 1422 ret = v4l2_async_register_subdev_sensor(&gc2145->sd); 1423 if (ret < 0) { 1424 dev_err(dev, "failed to register sensor sub-device: %d\n", ret); 1425 goto error_subdev_cleanup; 1426 } 1427 1428 return 0; 1429 1430 error_subdev_cleanup: 1431 v4l2_subdev_cleanup(&gc2145->sd); 1432 pm_runtime_disable(&client->dev); 1433 pm_runtime_set_suspended(&client->dev); 1434 1435 error_media_entity: 1436 media_entity_cleanup(&gc2145->sd.entity); 1437 1438 error_handler_free: 1439 v4l2_ctrl_handler_free(&gc2145->ctrls.handler); 1440 1441 error_power_off: 1442 gc2145_power_off(dev); 1443 1444 return ret; 1445 } 1446 1447 static void gc2145_remove(struct i2c_client *client) 1448 { 1449 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1450 struct gc2145 *gc2145 = to_gc2145(sd); 1451 1452 v4l2_subdev_cleanup(sd); 1453 v4l2_async_unregister_subdev(sd); 1454 media_entity_cleanup(&sd->entity); 1455 v4l2_ctrl_handler_free(&gc2145->ctrls.handler); 1456 1457 pm_runtime_disable(&client->dev); 1458 if (!pm_runtime_status_suspended(&client->dev)) 1459 gc2145_power_off(&client->dev); 1460 pm_runtime_set_suspended(&client->dev); 1461 } 1462 1463 static const struct of_device_id gc2145_dt_ids[] = { 1464 { .compatible = "galaxycore,gc2145" }, 1465 { /* sentinel */ } 1466 }; 1467 MODULE_DEVICE_TABLE(of, gc2145_dt_ids); 1468 1469 static const struct dev_pm_ops gc2145_pm_ops = { 1470 RUNTIME_PM_OPS(gc2145_power_off, gc2145_power_on, NULL) 1471 }; 1472 1473 static struct i2c_driver gc2145_i2c_driver = { 1474 .driver = { 1475 .name = "gc2145", 1476 .of_match_table = gc2145_dt_ids, 1477 .pm = pm_ptr(&gc2145_pm_ops), 1478 }, 1479 .probe = gc2145_probe, 1480 .remove = gc2145_remove, 1481 }; 1482 1483 module_i2c_driver(gc2145_i2c_driver); 1484 1485 MODULE_AUTHOR("Alain Volmat <alain.volmat@foss.st.com>"); 1486 MODULE_DESCRIPTION("GalaxyCore GC2145 sensor driver"); 1487 MODULE_LICENSE("GPL"); 1488