1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for GalaxyCore gc05a2 image sensor 4 * 5 * Copyright 2024 MediaTek 6 * 7 * Zhi Mao <zhi.mao@mediatek.com> 8 */ 9 #include <linux/array_size.h> 10 #include <linux/bits.h> 11 #include <linux/clk.h> 12 #include <linux/container_of.h> 13 #include <linux/delay.h> 14 #include <linux/device.h> 15 #include <linux/err.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/math64.h> 18 #include <linux/mod_devicetable.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/property.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/types.h> 23 #include <linux/units.h> 24 25 #include <media/v4l2-cci.h> 26 #include <media/v4l2-ctrls.h> 27 #include <media/v4l2-event.h> 28 #include <media/v4l2-fwnode.h> 29 #include <media/v4l2-subdev.h> 30 31 #define GC05A2_REG_TEST_PATTERN_EN CCI_REG8(0x008c) 32 #define GC05A2_REG_TEST_PATTERN_IDX CCI_REG8(0x008d) 33 #define GC05A2_TEST_PATTERN_EN 0x01 34 35 #define GC05A2_STREAMING_REG CCI_REG8(0x0100) 36 37 #define GC05A2_FLIP_REG CCI_REG8(0x0101) 38 #define GC05A2_FLIP_H_MASK BIT(0) 39 #define GC05A2_FLIP_V_MASK BIT(1) 40 41 #define GC05A2_EXP_REG CCI_REG16(0x0202) 42 #define GC05A2_EXP_MARGIN 16 43 #define GC05A2_EXP_MIN 4 44 #define GC05A2_EXP_STEP 1 45 46 #define GC05A2_AGAIN_REG CCI_REG16(0x0204) 47 #define GC05A2_AGAIN_MIN 1024 48 #define GC05A2_AGAIN_MAX (1024 * 16) 49 #define GC05A2_AGAIN_STEP 1 50 51 #define GC05A2_FRAME_LENGTH_REG CCI_REG16(0x0340) 52 #define GC05A2_VTS_MAX 0xffff 53 54 #define GC05A2_REG_CHIP_ID CCI_REG16(0x03f0) 55 #define GC05A2_CHIP_ID 0x05a2 56 57 #define GC05A2_NATIVE_WIDTH 2592 58 #define GC05A2_NATIVE_HEIGHT 1944 59 60 #define GC05A2_DEFAULT_CLK_FREQ (24 * HZ_PER_MHZ) 61 #define GC05A2_MBUS_CODE MEDIA_BUS_FMT_SGRBG10_1X10 62 #define GC05A2_DATA_LANES 2 63 #define GC05A2_RGB_DEPTH 10 64 #define GC05A2_SLEEP_US (2 * USEC_PER_MSEC) 65 66 static const char *const gc05a2_test_pattern_menu[] = { 67 "No Pattern", "Fade_to_gray_Color Bar", "Color Bar", 68 "PN9", "Horizental_gradient", "Checkboard Pattern", 69 "Slant", "Resolution", "Solid Black", 70 "Solid White", 71 }; 72 73 static const s64 gc05a2_link_freq_menu_items[] = { 74 (448 * HZ_PER_MHZ), 75 (224 * HZ_PER_MHZ), 76 }; 77 78 static const char *const gc05a2_supply_name[] = { 79 "avdd", 80 "dvdd", 81 "dovdd", 82 }; 83 84 struct gc05a2 { 85 struct device *dev; 86 struct v4l2_subdev sd; 87 struct media_pad pad; 88 89 struct clk *xclk; 90 struct regulator_bulk_data supplies[ARRAY_SIZE(gc05a2_supply_name)]; 91 struct gpio_desc *reset_gpio; 92 93 struct v4l2_ctrl_handler ctrls; 94 struct v4l2_ctrl *pixel_rate; 95 struct v4l2_ctrl *link_freq; 96 struct v4l2_ctrl *exposure; 97 struct v4l2_ctrl *vblank; 98 struct v4l2_ctrl *hblank; 99 struct v4l2_ctrl *hflip; 100 struct v4l2_ctrl *vflip; 101 102 struct regmap *regmap; 103 unsigned long link_freq_bitmap; 104 105 /* True if the device has been identified */ 106 bool identified; 107 const struct gc05a2_mode *cur_mode; 108 }; 109 110 struct gc05a2_reg_list { 111 u32 num_of_regs; 112 const struct cci_reg_sequence *regs; 113 }; 114 115 static const struct cci_reg_sequence mode_2592x1944[] = { 116 /* system */ 117 { CCI_REG8(0x0135), 0x01 }, 118 { CCI_REG8(0x0084), 0x21 }, 119 { CCI_REG8(0x0d05), 0xcc }, 120 { CCI_REG8(0x0218), 0x00 }, 121 { CCI_REG8(0x005e), 0x48 }, 122 { CCI_REG8(0x0d06), 0x01 }, 123 { CCI_REG8(0x0007), 0x16 }, 124 { CCI_REG8(0x0101), 0x00 }, 125 126 /* analog */ 127 { CCI_REG8(0x0342), 0x07 }, 128 { CCI_REG8(0x0343), 0x28 }, 129 { CCI_REG8(0x0220), 0x07 }, 130 { CCI_REG8(0x0221), 0xd0 }, 131 { CCI_REG8(0x0202), 0x07 }, 132 { CCI_REG8(0x0203), 0x32 }, 133 { CCI_REG8(0x0340), 0x07 }, 134 { CCI_REG8(0x0341), 0xf0 }, 135 { CCI_REG8(0x0219), 0x00 }, 136 { CCI_REG8(0x0346), 0x00 }, 137 { CCI_REG8(0x0347), 0x04 }, 138 { CCI_REG8(0x0d14), 0x00 }, 139 { CCI_REG8(0x0d13), 0x05 }, 140 { CCI_REG8(0x0d16), 0x05 }, 141 { CCI_REG8(0x0d15), 0x1d }, 142 { CCI_REG8(0x00c0), 0x0a }, 143 { CCI_REG8(0x00c1), 0x30 }, 144 { CCI_REG8(0x034a), 0x07 }, 145 { CCI_REG8(0x034b), 0xa8 }, 146 { CCI_REG8(0x0e0a), 0x00 }, 147 { CCI_REG8(0x0e0b), 0x00 }, 148 { CCI_REG8(0x0e0e), 0x03 }, 149 { CCI_REG8(0x0e0f), 0x00 }, 150 { CCI_REG8(0x0e06), 0x0a }, 151 { CCI_REG8(0x0e23), 0x15 }, 152 { CCI_REG8(0x0e24), 0x15 }, 153 { CCI_REG8(0x0e2a), 0x10 }, 154 { CCI_REG8(0x0e2b), 0x10 }, 155 { CCI_REG8(0x0e17), 0x49 }, 156 { CCI_REG8(0x0e1b), 0x1c }, 157 { CCI_REG8(0x0e3a), 0x36 }, 158 { CCI_REG8(0x0d11), 0x84 }, 159 { CCI_REG8(0x0e52), 0x14 }, 160 { CCI_REG8(0x000b), 0x10 }, 161 { CCI_REG8(0x0008), 0x08 }, 162 { CCI_REG8(0x0223), 0x17 }, 163 { CCI_REG8(0x0d27), 0x39 }, 164 { CCI_REG8(0x0d22), 0x00 }, 165 { CCI_REG8(0x03f6), 0x0d }, 166 { CCI_REG8(0x0d04), 0x07 }, 167 { CCI_REG8(0x03f3), 0x72 }, 168 { CCI_REG8(0x03f4), 0xb8 }, 169 { CCI_REG8(0x03f5), 0xbc }, 170 { CCI_REG8(0x0d02), 0x73 }, 171 172 /* auto load start */ 173 { CCI_REG8(0x00cb), 0x00 }, 174 175 /* OUT 2592*1944 */ 176 { CCI_REG8(0x0350), 0x01 }, 177 { CCI_REG8(0x0353), 0x00 }, 178 { CCI_REG8(0x0354), 0x08 }, 179 { CCI_REG16(0x034c), 2592 }, /* Width */ 180 { CCI_REG8(0x021f), 0x14 }, 181 182 /* MIPI */ 183 { CCI_REG8(0x0107), 0x05 }, 184 { CCI_REG8(0x0117), 0x01 }, 185 { CCI_REG8(0x0d81), 0x00 }, 186 { CCI_REG8(0x0d84), 0x0c }, 187 { CCI_REG8(0x0d85), 0xa8 }, 188 { CCI_REG8(0x0d86), 0x06 }, 189 { CCI_REG8(0x0d87), 0x55 }, 190 { CCI_REG8(0x0db3), 0x06 }, 191 { CCI_REG8(0x0db4), 0x08 }, 192 { CCI_REG8(0x0db5), 0x1e }, 193 { CCI_REG8(0x0db6), 0x02 }, 194 { CCI_REG8(0x0db8), 0x12 }, 195 { CCI_REG8(0x0db9), 0x0a }, 196 { CCI_REG8(0x0d93), 0x06 }, 197 { CCI_REG8(0x0d94), 0x09 }, 198 { CCI_REG8(0x0d95), 0x0d }, 199 { CCI_REG8(0x0d99), 0x0b }, 200 { CCI_REG8(0x0084), 0x01 }, 201 { CCI_REG8(0x0110), 0x01 }, 202 }; 203 204 static const struct cci_reg_sequence mode_1280x720[] = { 205 /* system */ 206 { CCI_REG8(0x0135), 0x05 }, 207 { CCI_REG8(0x0084), 0x21 }, 208 { CCI_REG8(0x0d05), 0xcc }, 209 { CCI_REG8(0x0218), 0x80 }, 210 { CCI_REG8(0x005e), 0x49 }, 211 { CCI_REG8(0x0d06), 0x81 }, 212 { CCI_REG8(0x0007), 0x16 }, 213 { CCI_REG8(0x0101), 0x00 }, 214 215 /* analog */ 216 { CCI_REG8(0x0342), 0x07 }, 217 { CCI_REG8(0x0343), 0x10 }, 218 { CCI_REG8(0x0220), 0x07 }, 219 { CCI_REG8(0x0221), 0xd0 }, 220 { CCI_REG8(0x0202), 0x03 }, 221 { CCI_REG8(0x0203), 0x32 }, 222 { CCI_REG8(0x0340), 0x04 }, 223 { CCI_REG8(0x0341), 0x08 }, 224 { CCI_REG8(0x0219), 0x00 }, 225 { CCI_REG8(0x0346), 0x01 }, 226 { CCI_REG8(0x0347), 0x00 }, 227 { CCI_REG8(0x0d14), 0x00 }, 228 { CCI_REG8(0x0d13), 0x05 }, 229 { CCI_REG8(0x0d16), 0x05 }, 230 { CCI_REG8(0x0d15), 0x1d }, 231 { CCI_REG8(0x00c0), 0x0a }, 232 { CCI_REG8(0x00c1), 0x30 }, 233 { CCI_REG8(0x034a), 0x05 }, 234 { CCI_REG8(0x034b), 0xb0 }, 235 { CCI_REG8(0x0e0a), 0x00 }, 236 { CCI_REG8(0x0e0b), 0x00 }, 237 { CCI_REG8(0x0e0e), 0x03 }, 238 { CCI_REG8(0x0e0f), 0x00 }, 239 { CCI_REG8(0x0e06), 0x0a }, 240 { CCI_REG8(0x0e23), 0x15 }, 241 { CCI_REG8(0x0e24), 0x15 }, 242 { CCI_REG8(0x0e2a), 0x10 }, 243 { CCI_REG8(0x0e2b), 0x10 }, 244 { CCI_REG8(0x0e17), 0x49 }, 245 { CCI_REG8(0x0e1b), 0x1c }, 246 { CCI_REG8(0x0e3a), 0x36 }, 247 { CCI_REG8(0x0d11), 0x84 }, 248 { CCI_REG8(0x0e52), 0x14 }, 249 { CCI_REG8(0x000b), 0x0e }, 250 { CCI_REG8(0x0008), 0x03 }, 251 { CCI_REG8(0x0223), 0x16 }, 252 { CCI_REG8(0x0d27), 0x39 }, 253 { CCI_REG8(0x0d22), 0x00 }, 254 { CCI_REG8(0x03f6), 0x0d }, 255 { CCI_REG8(0x0d04), 0x07 }, 256 { CCI_REG8(0x03f3), 0x72 }, 257 { CCI_REG8(0x03f4), 0xb8 }, 258 { CCI_REG8(0x03f5), 0xbc }, 259 { CCI_REG8(0x0d02), 0x73 }, 260 261 /* auto load start */ 262 { CCI_REG8(0x00cb), 0xfc }, 263 264 /* OUT 1280x720 */ 265 { CCI_REG8(0x0350), 0x01 }, 266 { CCI_REG8(0x0353), 0x00 }, 267 { CCI_REG8(0x0354), 0x0c }, 268 { CCI_REG16(0x034c), 1280 }, /* Width */ 269 { CCI_REG8(0x021f), 0x14 }, 270 271 /* MIPI */ 272 { CCI_REG8(0x0107), 0x05 }, 273 { CCI_REG8(0x0117), 0x01 }, 274 { CCI_REG8(0x0d81), 0x00 }, 275 { CCI_REG8(0x0d84), 0x06 }, 276 { CCI_REG8(0x0d85), 0x40 }, 277 { CCI_REG8(0x0d86), 0x03 }, 278 { CCI_REG8(0x0d87), 0x21 }, 279 { CCI_REG8(0x0db3), 0x03 }, 280 { CCI_REG8(0x0db4), 0x04 }, 281 { CCI_REG8(0x0db5), 0x0d }, 282 { CCI_REG8(0x0db6), 0x01 }, 283 { CCI_REG8(0x0db8), 0x04 }, 284 { CCI_REG8(0x0db9), 0x06 }, 285 { CCI_REG8(0x0d93), 0x03 }, 286 { CCI_REG8(0x0d94), 0x04 }, 287 { CCI_REG8(0x0d95), 0x05 }, 288 { CCI_REG8(0x0d99), 0x06 }, 289 { CCI_REG8(0x0084), 0x01 }, 290 { CCI_REG8(0x0110), 0x01 }, 291 }; 292 293 static const struct cci_reg_sequence mode_table_common[] = { 294 { GC05A2_STREAMING_REG, 0x00 }, 295 /* system */ 296 { CCI_REG8(0x0315), 0xd4 }, 297 { CCI_REG8(0x0d06), 0x01 }, 298 { CCI_REG8(0x0a70), 0x80 }, 299 { CCI_REG8(0x031a), 0x00 }, 300 { CCI_REG8(0x0314), 0x00 }, 301 { CCI_REG8(0x0130), 0x08 }, 302 { CCI_REG8(0x0132), 0x01 }, 303 { CCI_REG8(0x0136), 0x38 }, 304 { CCI_REG8(0x0137), 0x03 }, 305 { CCI_REG8(0x0134), 0x5b }, 306 { CCI_REG8(0x031c), 0xe0 }, 307 { CCI_REG8(0x0d82), 0x14 }, 308 { CCI_REG8(0x0dd1), 0x56 }, 309 { CCI_REG8(0x0af4), 0x01 }, 310 { CCI_REG8(0x0002), 0x10 }, 311 { CCI_REG8(0x00c3), 0x34 }, 312 { CCI_REG8(0x00c4), 0x00 }, 313 { CCI_REG8(0x00c5), 0x01 }, 314 { CCI_REG8(0x0af6), 0x00 }, 315 { CCI_REG8(0x0ba0), 0x17 }, 316 { CCI_REG8(0x0ba1), 0x00 }, 317 { CCI_REG8(0x0ba2), 0x00 }, 318 { CCI_REG8(0x0ba3), 0x00 }, 319 { CCI_REG8(0x0ba4), 0x03 }, 320 { CCI_REG8(0x0ba5), 0x00 }, 321 { CCI_REG8(0x0ba6), 0x00 }, 322 { CCI_REG8(0x0ba7), 0x00 }, 323 { CCI_REG8(0x0ba8), 0x40 }, 324 { CCI_REG8(0x0ba9), 0x00 }, 325 { CCI_REG8(0x0baa), 0x00 }, 326 { CCI_REG8(0x0bab), 0x00 }, 327 { CCI_REG8(0x0bac), 0x40 }, 328 { CCI_REG8(0x0bad), 0x00 }, 329 { CCI_REG8(0x0bae), 0x00 }, 330 { CCI_REG8(0x0baf), 0x00 }, 331 { CCI_REG8(0x0bb0), 0x02 }, 332 { CCI_REG8(0x0bb1), 0x00 }, 333 { CCI_REG8(0x0bb2), 0x00 }, 334 { CCI_REG8(0x0bb3), 0x00 }, 335 { CCI_REG8(0x0bb8), 0x02 }, 336 { CCI_REG8(0x0bb9), 0x00 }, 337 { CCI_REG8(0x0bba), 0x00 }, 338 { CCI_REG8(0x0bbb), 0x00 }, 339 { CCI_REG8(0x0a70), 0x80 }, 340 { CCI_REG8(0x0a71), 0x00 }, 341 { CCI_REG8(0x0a72), 0x00 }, 342 { CCI_REG8(0x0a66), 0x00 }, 343 { CCI_REG8(0x0a67), 0x80 }, 344 { CCI_REG8(0x0a4d), 0x4e }, 345 { CCI_REG8(0x0a50), 0x00 }, 346 { CCI_REG8(0x0a4f), 0x0c }, 347 { CCI_REG8(0x0a66), 0x00 }, 348 { CCI_REG8(0x00ca), 0x00 }, 349 { CCI_REG8(0x00cc), 0x00 }, 350 { CCI_REG8(0x00cd), 0x00 }, 351 { CCI_REG8(0x0aa1), 0x00 }, 352 { CCI_REG8(0x0aa2), 0xe0 }, 353 { CCI_REG8(0x0aa3), 0x00 }, 354 { CCI_REG8(0x0aa4), 0x40 }, 355 { CCI_REG8(0x0a90), 0x03 }, 356 { CCI_REG8(0x0a91), 0x0e }, 357 { CCI_REG8(0x0a94), 0x80 }, 358 { CCI_REG8(0x0af6), 0x20 }, 359 { CCI_REG8(0x0b00), 0x91 }, 360 { CCI_REG8(0x0b01), 0x17 }, 361 { CCI_REG8(0x0b02), 0x01 }, 362 { CCI_REG8(0x0b03), 0x00 }, 363 { CCI_REG8(0x0b04), 0x01 }, 364 { CCI_REG8(0x0b05), 0x17 }, 365 { CCI_REG8(0x0b06), 0x01 }, 366 { CCI_REG8(0x0b07), 0x00 }, 367 { CCI_REG8(0x0ae9), 0x01 }, 368 { CCI_REG8(0x0aea), 0x02 }, 369 { CCI_REG8(0x0ae8), 0x53 }, 370 { CCI_REG8(0x0ae8), 0x43 }, 371 { CCI_REG8(0x0af6), 0x30 }, 372 { CCI_REG8(0x0b00), 0x08 }, 373 { CCI_REG8(0x0b01), 0x0f }, 374 { CCI_REG8(0x0b02), 0x00 }, 375 { CCI_REG8(0x0b04), 0x1c }, 376 { CCI_REG8(0x0b05), 0x24 }, 377 { CCI_REG8(0x0b06), 0x00 }, 378 { CCI_REG8(0x0b08), 0x30 }, 379 { CCI_REG8(0x0b09), 0x40 }, 380 { CCI_REG8(0x0b0a), 0x00 }, 381 { CCI_REG8(0x0b0c), 0x0e }, 382 { CCI_REG8(0x0b0d), 0x2a }, 383 { CCI_REG8(0x0b0e), 0x00 }, 384 { CCI_REG8(0x0b10), 0x0e }, 385 { CCI_REG8(0x0b11), 0x2b }, 386 { CCI_REG8(0x0b12), 0x00 }, 387 { CCI_REG8(0x0b14), 0x0e }, 388 { CCI_REG8(0x0b15), 0x23 }, 389 { CCI_REG8(0x0b16), 0x00 }, 390 { CCI_REG8(0x0b18), 0x0e }, 391 { CCI_REG8(0x0b19), 0x24 }, 392 { CCI_REG8(0x0b1a), 0x00 }, 393 { CCI_REG8(0x0b1c), 0x0c }, 394 { CCI_REG8(0x0b1d), 0x0c }, 395 { CCI_REG8(0x0b1e), 0x00 }, 396 { CCI_REG8(0x0b20), 0x03 }, 397 { CCI_REG8(0x0b21), 0x03 }, 398 { CCI_REG8(0x0b22), 0x00 }, 399 { CCI_REG8(0x0b24), 0x0e }, 400 { CCI_REG8(0x0b25), 0x0e }, 401 { CCI_REG8(0x0b26), 0x00 }, 402 { CCI_REG8(0x0b28), 0x03 }, 403 { CCI_REG8(0x0b29), 0x03 }, 404 { CCI_REG8(0x0b2a), 0x00 }, 405 { CCI_REG8(0x0b2c), 0x12 }, 406 { CCI_REG8(0x0b2d), 0x12 }, 407 { CCI_REG8(0x0b2e), 0x00 }, 408 { CCI_REG8(0x0b30), 0x08 }, 409 { CCI_REG8(0x0b31), 0x08 }, 410 { CCI_REG8(0x0b32), 0x00 }, 411 { CCI_REG8(0x0b34), 0x14 }, 412 { CCI_REG8(0x0b35), 0x14 }, 413 { CCI_REG8(0x0b36), 0x00 }, 414 { CCI_REG8(0x0b38), 0x10 }, 415 { CCI_REG8(0x0b39), 0x10 }, 416 { CCI_REG8(0x0b3a), 0x00 }, 417 { CCI_REG8(0x0b3c), 0x16 }, 418 { CCI_REG8(0x0b3d), 0x16 }, 419 { CCI_REG8(0x0b3e), 0x00 }, 420 { CCI_REG8(0x0b40), 0x10 }, 421 { CCI_REG8(0x0b41), 0x10 }, 422 { CCI_REG8(0x0b42), 0x00 }, 423 { CCI_REG8(0x0b44), 0x19 }, 424 { CCI_REG8(0x0b45), 0x19 }, 425 { CCI_REG8(0x0b46), 0x00 }, 426 { CCI_REG8(0x0b48), 0x16 }, 427 { CCI_REG8(0x0b49), 0x16 }, 428 { CCI_REG8(0x0b4a), 0x00 }, 429 { CCI_REG8(0x0b4c), 0x19 }, 430 { CCI_REG8(0x0b4d), 0x19 }, 431 { CCI_REG8(0x0b4e), 0x00 }, 432 { CCI_REG8(0x0b50), 0x16 }, 433 { CCI_REG8(0x0b51), 0x16 }, 434 { CCI_REG8(0x0b52), 0x00 }, 435 { CCI_REG8(0x0b80), 0x01 }, 436 { CCI_REG8(0x0b81), 0x00 }, 437 { CCI_REG8(0x0b82), 0x00 }, 438 { CCI_REG8(0x0b84), 0x00 }, 439 { CCI_REG8(0x0b85), 0x00 }, 440 { CCI_REG8(0x0b86), 0x00 }, 441 { CCI_REG8(0x0b88), 0x01 }, 442 { CCI_REG8(0x0b89), 0x6a }, 443 { CCI_REG8(0x0b8a), 0x00 }, 444 { CCI_REG8(0x0b8c), 0x00 }, 445 { CCI_REG8(0x0b8d), 0x01 }, 446 { CCI_REG8(0x0b8e), 0x00 }, 447 { CCI_REG8(0x0b90), 0x01 }, 448 { CCI_REG8(0x0b91), 0xf6 }, 449 { CCI_REG8(0x0b92), 0x00 }, 450 { CCI_REG8(0x0b94), 0x00 }, 451 { CCI_REG8(0x0b95), 0x02 }, 452 { CCI_REG8(0x0b96), 0x00 }, 453 { CCI_REG8(0x0b98), 0x02 }, 454 { CCI_REG8(0x0b99), 0xc4 }, 455 { CCI_REG8(0x0b9a), 0x00 }, 456 { CCI_REG8(0x0b9c), 0x00 }, 457 { CCI_REG8(0x0b9d), 0x03 }, 458 { CCI_REG8(0x0b9e), 0x00 }, 459 { CCI_REG8(0x0ba0), 0x03 }, 460 { CCI_REG8(0x0ba1), 0xd8 }, 461 { CCI_REG8(0x0ba2), 0x00 }, 462 { CCI_REG8(0x0ba4), 0x00 }, 463 { CCI_REG8(0x0ba5), 0x04 }, 464 { CCI_REG8(0x0ba6), 0x00 }, 465 { CCI_REG8(0x0ba8), 0x05 }, 466 { CCI_REG8(0x0ba9), 0x4d }, 467 { CCI_REG8(0x0baa), 0x00 }, 468 { CCI_REG8(0x0bac), 0x00 }, 469 { CCI_REG8(0x0bad), 0x05 }, 470 { CCI_REG8(0x0bae), 0x00 }, 471 { CCI_REG8(0x0bb0), 0x07 }, 472 { CCI_REG8(0x0bb1), 0x3e }, 473 { CCI_REG8(0x0bb2), 0x00 }, 474 { CCI_REG8(0x0bb4), 0x00 }, 475 { CCI_REG8(0x0bb5), 0x06 }, 476 { CCI_REG8(0x0bb6), 0x00 }, 477 { CCI_REG8(0x0bb8), 0x0a }, 478 { CCI_REG8(0x0bb9), 0x1a }, 479 { CCI_REG8(0x0bba), 0x00 }, 480 { CCI_REG8(0x0bbc), 0x09 }, 481 { CCI_REG8(0x0bbd), 0x36 }, 482 { CCI_REG8(0x0bbe), 0x00 }, 483 { CCI_REG8(0x0bc0), 0x0e }, 484 { CCI_REG8(0x0bc1), 0x66 }, 485 { CCI_REG8(0x0bc2), 0x00 }, 486 { CCI_REG8(0x0bc4), 0x10 }, 487 { CCI_REG8(0x0bc5), 0x06 }, 488 { CCI_REG8(0x0bc6), 0x00 }, 489 { CCI_REG8(0x02c1), 0xe0 }, 490 { CCI_REG8(0x0207), 0x04 }, 491 { CCI_REG8(0x02c2), 0x10 }, 492 { CCI_REG8(0x02c3), 0x74 }, 493 { CCI_REG8(0x02c5), 0x09 }, 494 { CCI_REG8(0x02c1), 0xe0 }, 495 { CCI_REG8(0x0207), 0x04 }, 496 { CCI_REG8(0x02c2), 0x10 }, 497 { CCI_REG8(0x02c5), 0x09 }, 498 { CCI_REG8(0x02c1), 0xe0 }, 499 { CCI_REG8(0x0207), 0x04 }, 500 { CCI_REG8(0x02c2), 0x10 }, 501 { CCI_REG8(0x02c5), 0x09 }, 502 { CCI_REG8(0x0aa1), 0x15 }, 503 { CCI_REG8(0x0aa2), 0x50 }, 504 { CCI_REG8(0x0aa3), 0x00 }, 505 { CCI_REG8(0x0aa4), 0x09 }, 506 { CCI_REG8(0x0a90), 0x25 }, 507 { CCI_REG8(0x0a91), 0x0e }, 508 { CCI_REG8(0x0a94), 0x80 }, 509 510 /* ISP */ 511 { CCI_REG8(0x0050), 0x00 }, 512 { CCI_REG8(0x0089), 0x83 }, 513 { CCI_REG8(0x005a), 0x40 }, 514 { CCI_REG8(0x00c3), 0x35 }, 515 { CCI_REG8(0x00c4), 0x80 }, 516 { CCI_REG8(0x0080), 0x10 }, 517 { CCI_REG8(0x0040), 0x12 }, 518 { CCI_REG8(0x0053), 0x0a }, 519 { CCI_REG8(0x0054), 0x44 }, 520 { CCI_REG8(0x0055), 0x32 }, 521 { CCI_REG8(0x0058), 0x89 }, 522 { CCI_REG8(0x004a), 0x03 }, 523 { CCI_REG8(0x0048), 0xf0 }, 524 { CCI_REG8(0x0049), 0x0f }, 525 { CCI_REG8(0x0041), 0x20 }, 526 { CCI_REG8(0x0043), 0x0a }, 527 { CCI_REG8(0x009d), 0x08 }, 528 { CCI_REG8(0x0236), 0x40 }, 529 { CCI_REG8(0x0204), 0x04 }, 530 { CCI_REG8(0x0205), 0x00 }, 531 { CCI_REG8(0x02b3), 0x00 }, 532 { CCI_REG8(0x02b4), 0x00 }, 533 { CCI_REG8(0x009e), 0x01 }, 534 { CCI_REG8(0x009f), 0x94 }, 535 536 /* auto load REG */ 537 { CCI_REG8(0x0aa1), 0x10 }, 538 { CCI_REG8(0x0aa2), 0xf8 }, 539 { CCI_REG8(0x0aa3), 0x00 }, 540 { CCI_REG8(0x0aa4), 0x1f }, 541 { CCI_REG8(0x0a90), 0x11 }, 542 { CCI_REG8(0x0a91), 0x0e }, 543 { CCI_REG8(0x0a94), 0x80 }, 544 { CCI_REG8(0x03fe), 0x00 }, 545 { CCI_REG8(0x0a90), 0x00 }, 546 { CCI_REG8(0x0a70), 0x00 }, 547 { CCI_REG8(0x0a67), 0x00 }, 548 { CCI_REG8(0x0af4), 0x29 }, 549 550 /* DPHY */ 551 { CCI_REG8(0x0d80), 0x07 }, 552 { CCI_REG8(0x0dd3), 0x18 }, 553 554 /* CISCTL_Reset */ 555 { CCI_REG8(0x031c), 0x80 }, 556 { CCI_REG8(0x03fe), 0x30 }, 557 { CCI_REG8(0x0d17), 0x06 }, 558 { CCI_REG8(0x03fe), 0x00 }, 559 { CCI_REG8(0x0d17), 0x00 }, 560 { CCI_REG8(0x031c), 0x93 }, 561 { CCI_REG8(0x03fe), 0x00 }, 562 { CCI_REG8(0x031c), 0x80 }, 563 { CCI_REG8(0x03fe), 0x30 }, 564 { CCI_REG8(0x0d17), 0x06 }, 565 { CCI_REG8(0x03fe), 0x00 }, 566 { CCI_REG8(0x0d17), 0x00 }, 567 { CCI_REG8(0x031c), 0x93 }, 568 }; 569 570 struct gc05a2_mode { 571 u32 width; 572 u32 height; 573 const struct gc05a2_reg_list reg_list; 574 575 u32 hts; /* Horizontal timining size */ 576 u32 vts_def; /* Default vertical timining size */ 577 u32 vts_min; /* Min vertical timining size */ 578 }; 579 580 /* Declare modes in order, from biggest to smallest height. */ 581 static const struct gc05a2_mode gc05a2_modes[] = { 582 { 583 /* 2592*1944@30fps */ 584 .width = GC05A2_NATIVE_WIDTH, 585 .height = GC05A2_NATIVE_HEIGHT, 586 .reg_list = { 587 .num_of_regs = ARRAY_SIZE(mode_2592x1944), 588 .regs = mode_2592x1944, 589 }, 590 .hts = 3664, 591 .vts_def = 2032, 592 .vts_min = 2032, 593 }, 594 { 595 /* 1280*720@60fps */ 596 .width = 1280, 597 .height = 720, 598 .reg_list = { 599 .num_of_regs = ARRAY_SIZE(mode_1280x720), 600 .regs = mode_1280x720, 601 }, 602 .hts = 3616, 603 .vts_def = 1032, 604 .vts_min = 1032, 605 }, 606 }; 607 608 static inline struct gc05a2 *to_gc05a2(struct v4l2_subdev *sd) 609 { 610 return container_of(sd, struct gc05a2, sd); 611 } 612 613 static int gc05a2_power_on(struct device *dev) 614 { 615 struct v4l2_subdev *sd = dev_get_drvdata(dev); 616 struct gc05a2 *gc05a2 = to_gc05a2(sd); 617 int ret; 618 619 ret = regulator_bulk_enable(ARRAY_SIZE(gc05a2_supply_name), 620 gc05a2->supplies); 621 if (ret < 0) { 622 dev_err(gc05a2->dev, "failed to enable regulators: %d\n", ret); 623 return ret; 624 } 625 626 ret = clk_prepare_enable(gc05a2->xclk); 627 if (ret < 0) { 628 regulator_bulk_disable(ARRAY_SIZE(gc05a2_supply_name), 629 gc05a2->supplies); 630 dev_err(gc05a2->dev, "clk prepare enable failed\n"); 631 return ret; 632 } 633 634 fsleep(GC05A2_SLEEP_US); 635 636 gpiod_set_value_cansleep(gc05a2->reset_gpio, 0); 637 fsleep(GC05A2_SLEEP_US); 638 639 return 0; 640 } 641 642 static int gc05a2_power_off(struct device *dev) 643 { 644 struct v4l2_subdev *sd = dev_get_drvdata(dev); 645 struct gc05a2 *gc05a2 = to_gc05a2(sd); 646 647 clk_disable_unprepare(gc05a2->xclk); 648 gpiod_set_value_cansleep(gc05a2->reset_gpio, 1); 649 regulator_bulk_disable(ARRAY_SIZE(gc05a2_supply_name), 650 gc05a2->supplies); 651 652 return 0; 653 } 654 655 static int gc05a2_enum_mbus_code(struct v4l2_subdev *sd, 656 struct v4l2_subdev_state *sd_state, 657 struct v4l2_subdev_mbus_code_enum *code) 658 { 659 if (code->index > 0) 660 return -EINVAL; 661 662 code->code = GC05A2_MBUS_CODE; 663 664 return 0; 665 } 666 667 static int gc05a2_enum_frame_size(struct v4l2_subdev *subdev, 668 struct v4l2_subdev_state *sd_state, 669 struct v4l2_subdev_frame_size_enum *fse) 670 { 671 if (fse->code != GC05A2_MBUS_CODE) 672 return -EINVAL; 673 674 if (fse->index >= ARRAY_SIZE(gc05a2_modes)) 675 return -EINVAL; 676 677 fse->min_width = gc05a2_modes[fse->index].width; 678 fse->max_width = gc05a2_modes[fse->index].width; 679 fse->min_height = gc05a2_modes[fse->index].height; 680 fse->max_height = gc05a2_modes[fse->index].height; 681 682 return 0; 683 } 684 685 static int gc05a2_update_cur_mode_controls(struct gc05a2 *gc05a2, 686 const struct gc05a2_mode *mode) 687 { 688 s64 exposure_max, h_blank; 689 int ret; 690 691 ret = __v4l2_ctrl_modify_range(gc05a2->vblank, 692 mode->vts_min - mode->height, 693 GC05A2_VTS_MAX - mode->height, 1, 694 mode->vts_def - mode->height); 695 if (ret) { 696 dev_err(gc05a2->dev, "VB ctrl range update failed\n"); 697 return ret; 698 } 699 700 h_blank = mode->hts - mode->width; 701 ret = __v4l2_ctrl_modify_range(gc05a2->hblank, h_blank, h_blank, 1, 702 h_blank); 703 if (ret) { 704 dev_err(gc05a2->dev, "HB ctrl range update failed\n"); 705 return ret; 706 } 707 708 exposure_max = mode->vts_def - GC05A2_EXP_MARGIN; 709 ret = __v4l2_ctrl_modify_range(gc05a2->exposure, GC05A2_EXP_MIN, 710 exposure_max, GC05A2_EXP_STEP, 711 exposure_max); 712 if (ret) { 713 dev_err(gc05a2->dev, "exposure ctrl range update failed\n"); 714 return ret; 715 } 716 717 return 0; 718 } 719 720 static void gc05a2_update_pad_format(struct gc05a2 *gc08a3, 721 const struct gc05a2_mode *mode, 722 struct v4l2_mbus_framefmt *fmt) 723 { 724 fmt->width = mode->width; 725 fmt->height = mode->height; 726 fmt->code = GC05A2_MBUS_CODE; 727 fmt->field = V4L2_FIELD_NONE; 728 fmt->colorspace = V4L2_COLORSPACE_RAW; 729 fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt->colorspace); 730 fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE; 731 fmt->xfer_func = V4L2_XFER_FUNC_NONE; 732 } 733 734 static int gc05a2_set_format(struct v4l2_subdev *sd, 735 struct v4l2_subdev_state *state, 736 struct v4l2_subdev_format *fmt) 737 { 738 struct gc05a2 *gc05a2 = to_gc05a2(sd); 739 struct v4l2_mbus_framefmt *mbus_fmt; 740 struct v4l2_rect *crop; 741 const struct gc05a2_mode *mode; 742 743 mode = v4l2_find_nearest_size(gc05a2_modes, ARRAY_SIZE(gc05a2_modes), 744 width, height, fmt->format.width, 745 fmt->format.height); 746 747 /* update crop info to subdev state */ 748 crop = v4l2_subdev_state_get_crop(state, 0); 749 crop->width = mode->width; 750 crop->height = mode->height; 751 752 /* update fmt info to subdev state */ 753 gc05a2_update_pad_format(gc05a2, mode, &fmt->format); 754 mbus_fmt = v4l2_subdev_state_get_format(state, 0); 755 *mbus_fmt = fmt->format; 756 757 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) 758 return 0; 759 gc05a2->cur_mode = mode; 760 gc05a2_update_cur_mode_controls(gc05a2, mode); 761 762 return 0; 763 } 764 765 static int gc05a2_get_selection(struct v4l2_subdev *sd, 766 struct v4l2_subdev_state *state, 767 struct v4l2_subdev_selection *sel) 768 { 769 switch (sel->target) { 770 case V4L2_SEL_TGT_CROP_DEFAULT: 771 case V4L2_SEL_TGT_CROP: 772 sel->r = *v4l2_subdev_state_get_crop(state, 0); 773 break; 774 case V4L2_SEL_TGT_CROP_BOUNDS: 775 sel->r.top = 0; 776 sel->r.left = 0; 777 sel->r.width = GC05A2_NATIVE_WIDTH; 778 sel->r.height = GC05A2_NATIVE_HEIGHT; 779 break; 780 default: 781 return -EINVAL; 782 } 783 784 return 0; 785 } 786 787 static int gc05a2_init_state(struct v4l2_subdev *sd, 788 struct v4l2_subdev_state *state) 789 { 790 struct v4l2_subdev_format fmt = { 791 .which = V4L2_SUBDEV_FORMAT_TRY, 792 .pad = 0, 793 .format = { 794 .code = GC05A2_MBUS_CODE, 795 .width = gc05a2_modes[0].width, 796 .height = gc05a2_modes[0].height, 797 }, 798 }; 799 800 gc05a2_set_format(sd, state, &fmt); 801 802 return 0; 803 } 804 805 static int gc05a2_set_ctrl_hflip(struct gc05a2 *gc05a2, u32 ctrl_val) 806 { 807 int ret; 808 u64 val; 809 810 ret = cci_read(gc05a2->regmap, GC05A2_FLIP_REG, &val, NULL); 811 if (ret) { 812 dev_err(gc05a2->dev, "read hflip register failed: %d\n", ret); 813 return ret; 814 } 815 816 return cci_update_bits(gc05a2->regmap, GC05A2_FLIP_REG, 817 GC05A2_FLIP_H_MASK, 818 ctrl_val ? GC05A2_FLIP_H_MASK : 0, NULL); 819 } 820 821 static int gc05a2_set_ctrl_vflip(struct gc05a2 *gc05a2, u32 ctrl_val) 822 { 823 int ret; 824 u64 val; 825 826 ret = cci_read(gc05a2->regmap, GC05A2_FLIP_REG, &val, NULL); 827 if (ret) { 828 dev_err(gc05a2->dev, "read vflip register failed: %d\n", ret); 829 return ret; 830 } 831 832 return cci_update_bits(gc05a2->regmap, GC05A2_FLIP_REG, 833 GC05A2_FLIP_V_MASK, 834 ctrl_val ? GC05A2_FLIP_V_MASK : 0, NULL); 835 } 836 837 static int gc05a2_test_pattern(struct gc05a2 *gc05a2, u32 pattern_menu) 838 { 839 u32 pattern; 840 int ret; 841 842 if (pattern_menu) { 843 switch (pattern_menu) { 844 case 1: 845 case 2: 846 case 3: 847 case 4: 848 case 5: 849 case 6: 850 case 7: 851 pattern = pattern_menu << 4; 852 break; 853 854 case 8: 855 pattern = 0; 856 break; 857 858 case 9: 859 pattern = 4; 860 break; 861 862 default: 863 /* Set pattern to 0, it's a safe default. */ 864 pattern = 0; 865 break; 866 } 867 868 ret = cci_write(gc05a2->regmap, GC05A2_REG_TEST_PATTERN_IDX, 869 pattern, NULL); 870 if (ret) 871 return ret; 872 873 return cci_write(gc05a2->regmap, GC05A2_REG_TEST_PATTERN_EN, 874 GC05A2_TEST_PATTERN_EN, NULL); 875 } else { 876 return cci_write(gc05a2->regmap, GC05A2_REG_TEST_PATTERN_EN, 877 0x00, NULL); 878 } 879 } 880 881 static int gc05a2_set_ctrl(struct v4l2_ctrl *ctrl) 882 { 883 struct gc05a2 *gc05a2 = 884 container_of(ctrl->handler, struct gc05a2, ctrls); 885 int ret = 0; 886 s64 exposure_max; 887 struct v4l2_subdev_state *state; 888 const struct v4l2_mbus_framefmt *format; 889 890 state = v4l2_subdev_get_locked_active_state(&gc05a2->sd); 891 format = v4l2_subdev_state_get_format(state, 0); 892 893 if (ctrl->id == V4L2_CID_VBLANK) { 894 /* Update max exposure while meeting expected vblanking */ 895 exposure_max = format->height + ctrl->val - GC05A2_EXP_MARGIN; 896 __v4l2_ctrl_modify_range(gc05a2->exposure, 897 gc05a2->exposure->minimum, 898 exposure_max, gc05a2->exposure->step, 899 exposure_max); 900 } 901 902 /* 903 * Applying V4L2 control value only happens 904 * when power is on for streaming. 905 */ 906 if (!pm_runtime_get_if_active(gc05a2->dev)) 907 return 0; 908 909 switch (ctrl->id) { 910 case V4L2_CID_EXPOSURE: 911 ret = cci_write(gc05a2->regmap, GC05A2_EXP_REG, 912 ctrl->val, NULL); 913 break; 914 915 case V4L2_CID_ANALOGUE_GAIN: 916 ret = cci_write(gc05a2->regmap, GC05A2_AGAIN_REG, 917 ctrl->val, NULL); 918 break; 919 920 case V4L2_CID_VBLANK: 921 ret = cci_write(gc05a2->regmap, GC05A2_FRAME_LENGTH_REG, 922 gc05a2->cur_mode->height + ctrl->val, NULL); 923 break; 924 925 case V4L2_CID_HFLIP: 926 ret = gc05a2_set_ctrl_hflip(gc05a2, ctrl->val); 927 break; 928 929 case V4L2_CID_VFLIP: 930 ret = gc05a2_set_ctrl_vflip(gc05a2, ctrl->val); 931 break; 932 933 case V4L2_CID_TEST_PATTERN: 934 ret = gc05a2_test_pattern(gc05a2, ctrl->val); 935 break; 936 937 default: 938 break; 939 } 940 941 pm_runtime_put(gc05a2->dev); 942 943 return ret; 944 } 945 946 static const struct v4l2_ctrl_ops gc05a2_ctrl_ops = { 947 .s_ctrl = gc05a2_set_ctrl, 948 }; 949 950 static int gc05a2_identify_module(struct gc05a2 *gc05a2) 951 { 952 u64 val; 953 int ret; 954 955 if (gc05a2->identified) 956 return 0; 957 958 ret = cci_read(gc05a2->regmap, GC05A2_REG_CHIP_ID, &val, NULL); 959 if (ret) 960 return ret; 961 962 if (val != GC05A2_CHIP_ID) { 963 dev_err(gc05a2->dev, "chip id mismatch: 0x%x!=0x%llx", 964 GC05A2_CHIP_ID, val); 965 return -ENXIO; 966 } 967 968 gc05a2->identified = true; 969 970 return 0; 971 } 972 973 static int gc05a2_start_streaming(struct gc05a2 *gc05a2) 974 { 975 const struct gc05a2_mode *mode; 976 const struct gc05a2_reg_list *reg_list; 977 int ret; 978 979 ret = pm_runtime_resume_and_get(gc05a2->dev); 980 if (ret < 0) 981 return ret; 982 983 ret = gc05a2_identify_module(gc05a2); 984 if (ret) 985 goto err_rpm_put; 986 987 ret = cci_multi_reg_write(gc05a2->regmap, 988 mode_table_common, 989 ARRAY_SIZE(mode_table_common), NULL); 990 if (ret) 991 goto err_rpm_put; 992 993 mode = gc05a2->cur_mode; 994 reg_list = &mode->reg_list; 995 996 ret = cci_multi_reg_write(gc05a2->regmap, 997 reg_list->regs, reg_list->num_of_regs, NULL); 998 if (ret < 0) 999 goto err_rpm_put; 1000 1001 ret = __v4l2_ctrl_handler_setup(&gc05a2->ctrls); 1002 if (ret < 0) { 1003 dev_err(gc05a2->dev, "could not sync v4l2 controls\n"); 1004 goto err_rpm_put; 1005 } 1006 1007 ret = cci_write(gc05a2->regmap, GC05A2_STREAMING_REG, 1, NULL); 1008 if (ret < 0) { 1009 dev_err(gc05a2->dev, "write STREAMING_REG failed: %d\n", ret); 1010 goto err_rpm_put; 1011 } 1012 1013 return 0; 1014 1015 err_rpm_put: 1016 pm_runtime_put(gc05a2->dev); 1017 return ret; 1018 } 1019 1020 static int gc05a2_stop_streaming(struct gc05a2 *gc05a2) 1021 { 1022 int ret; 1023 1024 ret = cci_write(gc05a2->regmap, GC05A2_STREAMING_REG, 0, NULL); 1025 if (ret < 0) 1026 dev_err(gc05a2->dev, "could not sent stop streaming %d\n", ret); 1027 1028 pm_runtime_put(gc05a2->dev); 1029 return ret; 1030 } 1031 1032 static int gc05a2_s_stream(struct v4l2_subdev *subdev, int enable) 1033 { 1034 struct gc05a2 *gc05a2 = to_gc05a2(subdev); 1035 struct v4l2_subdev_state *state; 1036 int ret; 1037 1038 state = v4l2_subdev_lock_and_get_active_state(subdev); 1039 1040 if (enable) 1041 ret = gc05a2_start_streaming(gc05a2); 1042 else 1043 ret = gc05a2_stop_streaming(gc05a2); 1044 1045 v4l2_subdev_unlock_state(state); 1046 1047 return ret; 1048 } 1049 1050 static const struct v4l2_subdev_video_ops gc05a2_video_ops = { 1051 .s_stream = gc05a2_s_stream, 1052 }; 1053 1054 static const struct v4l2_subdev_pad_ops gc05a2_subdev_pad_ops = { 1055 .enum_mbus_code = gc05a2_enum_mbus_code, 1056 .enum_frame_size = gc05a2_enum_frame_size, 1057 .get_fmt = v4l2_subdev_get_fmt, 1058 .set_fmt = gc05a2_set_format, 1059 .get_selection = gc05a2_get_selection, 1060 }; 1061 1062 static const struct v4l2_subdev_core_ops gc05a2_core_ops = { 1063 .subscribe_event = v4l2_ctrl_subdev_subscribe_event, 1064 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 1065 }; 1066 1067 static const struct v4l2_subdev_ops gc05a2_subdev_ops = { 1068 .core = &gc05a2_core_ops, 1069 .video = &gc05a2_video_ops, 1070 .pad = &gc05a2_subdev_pad_ops, 1071 }; 1072 1073 static const struct v4l2_subdev_internal_ops gc05a2_internal_ops = { 1074 .init_state = gc05a2_init_state, 1075 }; 1076 1077 static int gc05a2_get_regulators(struct device *dev, struct gc05a2 *gc05a2) 1078 { 1079 unsigned int i; 1080 1081 for (i = 0; i < ARRAY_SIZE(gc05a2_supply_name); i++) 1082 gc05a2->supplies[i].supply = gc05a2_supply_name[i]; 1083 1084 return devm_regulator_bulk_get(dev, ARRAY_SIZE(gc05a2_supply_name), 1085 gc05a2->supplies); 1086 } 1087 1088 static int gc05a2_parse_fwnode(struct gc05a2 *gc05a2) 1089 { 1090 struct fwnode_handle *endpoint; 1091 struct v4l2_fwnode_endpoint bus_cfg = { 1092 .bus_type = V4L2_MBUS_CSI2_DPHY, 1093 }; 1094 int ret; 1095 struct device *dev = gc05a2->dev; 1096 1097 endpoint = 1098 fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 0, 0, 1099 FWNODE_GRAPH_ENDPOINT_NEXT); 1100 if (!endpoint) 1101 return dev_err_probe(dev, -EINVAL, "Missing endpoint node\n"); 1102 1103 ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &bus_cfg); 1104 if (ret) { 1105 dev_err_probe(dev, ret, "parsing endpoint node failed\n"); 1106 goto done; 1107 } 1108 1109 ret = v4l2_link_freq_to_bitmap(dev, bus_cfg.link_frequencies, 1110 bus_cfg.nr_of_link_frequencies, 1111 gc05a2_link_freq_menu_items, 1112 ARRAY_SIZE(gc05a2_link_freq_menu_items), 1113 &gc05a2->link_freq_bitmap); 1114 if (ret) 1115 goto done; 1116 1117 done: 1118 v4l2_fwnode_endpoint_free(&bus_cfg); 1119 fwnode_handle_put(endpoint); 1120 return ret; 1121 } 1122 1123 static u64 gc05a2_to_pixel_rate(u32 f_index) 1124 { 1125 u64 pixel_rate = 1126 gc05a2_link_freq_menu_items[f_index] * 2 * GC05A2_DATA_LANES; 1127 1128 return div_u64(pixel_rate, GC05A2_RGB_DEPTH); 1129 } 1130 1131 static int gc05a2_init_controls(struct gc05a2 *gc05a2) 1132 { 1133 struct i2c_client *client = v4l2_get_subdevdata(&gc05a2->sd); 1134 const struct gc05a2_mode *mode = &gc05a2_modes[0]; 1135 const struct v4l2_ctrl_ops *ops = &gc05a2_ctrl_ops; 1136 struct v4l2_fwnode_device_properties props; 1137 struct v4l2_ctrl_handler *ctrl_hdlr; 1138 s64 exposure_max, h_blank; 1139 int ret; 1140 1141 ctrl_hdlr = &gc05a2->ctrls; 1142 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 9); 1143 if (ret) 1144 return ret; 1145 1146 gc05a2->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &gc05a2_ctrl_ops, 1147 V4L2_CID_HFLIP, 0, 1, 1, 0); 1148 gc05a2->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &gc05a2_ctrl_ops, 1149 V4L2_CID_VFLIP, 0, 1, 1, 0); 1150 v4l2_ctrl_cluster(2, &gc05a2->hflip); 1151 1152 gc05a2->link_freq = 1153 v4l2_ctrl_new_int_menu(ctrl_hdlr, 1154 &gc05a2_ctrl_ops, 1155 V4L2_CID_LINK_FREQ, 1156 ARRAY_SIZE(gc05a2_link_freq_menu_items) - 1, 1157 0, 1158 gc05a2_link_freq_menu_items); 1159 if (gc05a2->link_freq) 1160 gc05a2->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1161 1162 gc05a2->pixel_rate = 1163 v4l2_ctrl_new_std(ctrl_hdlr, 1164 &gc05a2_ctrl_ops, 1165 V4L2_CID_PIXEL_RATE, 0, 1166 gc05a2_to_pixel_rate(0), 1167 1, 1168 gc05a2_to_pixel_rate(0)); 1169 1170 gc05a2->vblank = 1171 v4l2_ctrl_new_std(ctrl_hdlr, 1172 &gc05a2_ctrl_ops, V4L2_CID_VBLANK, 1173 mode->vts_min - mode->height, 1174 GC05A2_VTS_MAX - mode->height, 1, 1175 mode->vts_def - mode->height); 1176 1177 h_blank = mode->hts - mode->width; 1178 gc05a2->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &gc05a2_ctrl_ops, 1179 V4L2_CID_HBLANK, h_blank, h_blank, 1, 1180 h_blank); 1181 if (gc05a2->hblank) 1182 gc05a2->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1183 1184 v4l2_ctrl_new_std(ctrl_hdlr, &gc05a2_ctrl_ops, 1185 V4L2_CID_ANALOGUE_GAIN, GC05A2_AGAIN_MIN, 1186 GC05A2_AGAIN_MAX, GC05A2_AGAIN_STEP, 1187 GC05A2_AGAIN_MIN); 1188 1189 exposure_max = mode->vts_def - GC05A2_EXP_MARGIN; 1190 gc05a2->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &gc05a2_ctrl_ops, 1191 V4L2_CID_EXPOSURE, GC05A2_EXP_MIN, 1192 exposure_max, GC05A2_EXP_STEP, 1193 exposure_max); 1194 1195 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &gc05a2_ctrl_ops, 1196 V4L2_CID_TEST_PATTERN, 1197 ARRAY_SIZE(gc05a2_test_pattern_menu) - 1, 1198 0, 0, gc05a2_test_pattern_menu); 1199 1200 /* register properties to fwnode (e.g. rotation, orientation) */ 1201 ret = v4l2_fwnode_device_parse(&client->dev, &props); 1202 if (ret) 1203 goto error_ctrls; 1204 1205 ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, ops, &props); 1206 if (ret) 1207 goto error_ctrls; 1208 1209 if (ctrl_hdlr->error) { 1210 ret = ctrl_hdlr->error; 1211 goto error_ctrls; 1212 } 1213 1214 gc05a2->sd.ctrl_handler = ctrl_hdlr; 1215 1216 return 0; 1217 1218 error_ctrls: 1219 v4l2_ctrl_handler_free(ctrl_hdlr); 1220 1221 return ret; 1222 } 1223 1224 static int gc05a2_probe(struct i2c_client *client) 1225 { 1226 struct device *dev = &client->dev; 1227 struct gc05a2 *gc05a2; 1228 int ret; 1229 1230 gc05a2 = devm_kzalloc(dev, sizeof(*gc05a2), GFP_KERNEL); 1231 if (!gc05a2) 1232 return -ENOMEM; 1233 1234 gc05a2->dev = dev; 1235 1236 ret = gc05a2_parse_fwnode(gc05a2); 1237 if (ret) 1238 return ret; 1239 1240 gc05a2->regmap = devm_cci_regmap_init_i2c(client, 16); 1241 if (IS_ERR(gc05a2->regmap)) 1242 return dev_err_probe(dev, PTR_ERR(gc05a2->regmap), 1243 "failed to init CCI\n"); 1244 1245 gc05a2->xclk = devm_clk_get(dev, NULL); 1246 if (IS_ERR(gc05a2->xclk)) 1247 return dev_err_probe(dev, PTR_ERR(gc05a2->xclk), 1248 "failed to get xclk\n"); 1249 1250 ret = clk_set_rate(gc05a2->xclk, GC05A2_DEFAULT_CLK_FREQ); 1251 if (ret) 1252 return dev_err_probe(dev, ret, 1253 "failed to set xclk frequency\n"); 1254 1255 ret = gc05a2_get_regulators(dev, gc05a2); 1256 if (ret < 0) 1257 return dev_err_probe(dev, ret, 1258 "failed to get regulators\n"); 1259 1260 gc05a2->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); 1261 if (IS_ERR(gc05a2->reset_gpio)) 1262 return dev_err_probe(dev, PTR_ERR(gc05a2->reset_gpio), 1263 "failed to get gpio\n"); 1264 1265 v4l2_i2c_subdev_init(&gc05a2->sd, client, &gc05a2_subdev_ops); 1266 gc05a2->sd.internal_ops = &gc05a2_internal_ops; 1267 gc05a2->cur_mode = &gc05a2_modes[0]; 1268 1269 ret = gc05a2_init_controls(gc05a2); 1270 if (ret) 1271 return dev_err_probe(dev, ret, 1272 "failed to init controls\n"); 1273 1274 gc05a2->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | 1275 V4L2_SUBDEV_FL_HAS_EVENTS; 1276 gc05a2->pad.flags = MEDIA_PAD_FL_SOURCE; 1277 gc05a2->sd.dev = &client->dev; 1278 gc05a2->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1279 1280 ret = media_entity_pads_init(&gc05a2->sd.entity, 1, &gc05a2->pad); 1281 if (ret < 0) { 1282 dev_err_probe(dev, ret, "could not register media entity\n"); 1283 goto err_v4l2_ctrl_handler_free; 1284 } 1285 1286 gc05a2->sd.state_lock = gc05a2->ctrls.lock; 1287 ret = v4l2_subdev_init_finalize(&gc05a2->sd); 1288 if (ret < 0) { 1289 dev_err_probe(dev, ret, "v4l2 subdev init error\n"); 1290 goto err_media_entity_cleanup; 1291 } 1292 1293 pm_runtime_enable(gc05a2->dev); 1294 pm_runtime_set_autosuspend_delay(gc05a2->dev, 1000); 1295 pm_runtime_use_autosuspend(gc05a2->dev); 1296 pm_runtime_idle(gc05a2->dev); 1297 1298 ret = v4l2_async_register_subdev_sensor(&gc05a2->sd); 1299 if (ret < 0) { 1300 dev_err_probe(dev, ret, "could not register v4l2 device\n"); 1301 goto err_rpm; 1302 } 1303 1304 return 0; 1305 1306 err_rpm: 1307 pm_runtime_disable(gc05a2->dev); 1308 v4l2_subdev_cleanup(&gc05a2->sd); 1309 1310 err_media_entity_cleanup: 1311 media_entity_cleanup(&gc05a2->sd.entity); 1312 1313 err_v4l2_ctrl_handler_free: 1314 v4l2_ctrl_handler_free(&gc05a2->ctrls); 1315 1316 return ret; 1317 } 1318 1319 static void gc05a2_remove(struct i2c_client *client) 1320 { 1321 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1322 struct gc05a2 *gc05a2 = to_gc05a2(sd); 1323 1324 v4l2_async_unregister_subdev(&gc05a2->sd); 1325 v4l2_subdev_cleanup(sd); 1326 media_entity_cleanup(&gc05a2->sd.entity); 1327 v4l2_ctrl_handler_free(&gc05a2->ctrls); 1328 1329 pm_runtime_disable(&client->dev); 1330 if (!pm_runtime_status_suspended(&client->dev)) 1331 gc05a2_power_off(gc05a2->dev); 1332 pm_runtime_set_suspended(&client->dev); 1333 } 1334 1335 static const struct of_device_id gc05a2_of_match[] = { 1336 { .compatible = "galaxycore,gc05a2" }, 1337 {} 1338 }; 1339 MODULE_DEVICE_TABLE(of, gc05a2_of_match); 1340 1341 static DEFINE_RUNTIME_DEV_PM_OPS(gc05a2_pm_ops, 1342 gc05a2_power_off, 1343 gc05a2_power_on, 1344 NULL); 1345 1346 static struct i2c_driver gc05a2_i2c_driver = { 1347 .driver = { 1348 .of_match_table = gc05a2_of_match, 1349 .pm = pm_ptr(&gc05a2_pm_ops), 1350 .name = "gc05a2", 1351 }, 1352 .probe = gc05a2_probe, 1353 .remove = gc05a2_remove, 1354 }; 1355 module_i2c_driver(gc05a2_i2c_driver); 1356 1357 MODULE_DESCRIPTION("GalaxyCore gc05a2 Camera driver"); 1358 MODULE_AUTHOR("Zhi Mao <zhi.mao@mediatek.com>"); 1359 MODULE_LICENSE("GPL"); 1360