1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the Texas Instruments DS90UB960-Q1 video deserializer 4 * 5 * Copyright (c) 2019 Luca Ceresoli <luca@lucaceresoli.net> 6 * Copyright (c) 2023 Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> 7 */ 8 9 /* 10 * (Possible) TODOs: 11 * 12 * - PM for serializer and remote peripherals. We need to manage: 13 * - VPOC 14 * - Power domain? Regulator? Somehow any remote device should be able to 15 * cause the VPOC to be turned on. 16 * - Link between the deserializer and the serializer 17 * - Related to VPOC management. We probably always want to turn on the VPOC 18 * and then enable the link. 19 * - Serializer's services: i2c, gpios, power 20 * - The serializer needs to resume before the remote peripherals can 21 * e.g. use the i2c. 22 * - How to handle gpios? Reserving a gpio essentially keeps the provider 23 * (serializer) always powered on. 24 * - Do we need a new bus for the FPD-Link? At the moment the serializers 25 * are children of the same i2c-adapter where the deserializer resides. 26 * - i2c-atr could be made embeddable instead of allocatable. 27 */ 28 29 #include <linux/bitops.h> 30 #include <linux/clk.h> 31 #include <linux/delay.h> 32 #include <linux/fwnode.h> 33 #include <linux/gpio/consumer.h> 34 #include <linux/i2c-atr.h> 35 #include <linux/i2c.h> 36 #include <linux/init.h> 37 #include <linux/interrupt.h> 38 #include <linux/kernel.h> 39 #include <linux/kthread.h> 40 #include <linux/module.h> 41 #include <linux/mutex.h> 42 #include <linux/property.h> 43 #include <linux/regmap.h> 44 #include <linux/regulator/consumer.h> 45 #include <linux/slab.h> 46 #include <linux/units.h> 47 #include <linux/workqueue.h> 48 49 #include <media/i2c/ds90ub9xx.h> 50 #include <media/mipi-csi2.h> 51 #include <media/v4l2-ctrls.h> 52 #include <media/v4l2-fwnode.h> 53 #include <media/v4l2-subdev.h> 54 55 #include "ds90ub953.h" 56 57 #define MHZ(v) ((u32)((v) * HZ_PER_MHZ)) 58 59 /* 60 * If this is defined, the i2c addresses from UB960_DEBUG_I2C_RX_ID to 61 * UB960_DEBUG_I2C_RX_ID + 3 can be used to access the paged RX port registers 62 * directly. 63 * 64 * Only for debug purposes. 65 */ 66 /* #define UB960_DEBUG_I2C_RX_ID 0x40 */ 67 68 #define UB960_POLL_TIME_MS 500 69 70 #define UB960_MAX_RX_NPORTS 4 71 #define UB960_MAX_TX_NPORTS 2 72 #define UB960_MAX_NPORTS (UB960_MAX_RX_NPORTS + UB960_MAX_TX_NPORTS) 73 74 #define UB960_MAX_PORT_ALIASES 8 75 76 #define UB960_NUM_BC_GPIOS 4 77 78 /* 79 * Register map 80 * 81 * 0x00-0x32 Shared (UB960_SR) 82 * 0x33-0x3a CSI-2 TX (per-port paged on DS90UB960, shared on 954) (UB960_TR) 83 * 0x4c Shared (UB960_SR) 84 * 0x4d-0x7f FPD-Link RX, per-port paged (UB960_RR) 85 * 0xb0-0xbf Shared (UB960_SR) 86 * 0xd0-0xdf FPD-Link RX, per-port paged (UB960_RR) 87 * 0xf0-0xf5 Shared (UB960_SR) 88 * 0xf8-0xfb Shared (UB960_SR) 89 * All others Reserved 90 * 91 * Register prefixes: 92 * UB960_SR_* = Shared register 93 * UB960_RR_* = FPD-Link RX, per-port paged register 94 * UB960_TR_* = CSI-2 TX, per-port paged register 95 * UB960_XR_* = Reserved register 96 * UB960_IR_* = Indirect register 97 */ 98 99 #define UB960_SR_I2C_DEV_ID 0x00 100 #define UB960_SR_RESET 0x01 101 #define UB960_SR_RESET_DIGITAL_RESET1 BIT(1) 102 #define UB960_SR_RESET_DIGITAL_RESET0 BIT(0) 103 #define UB960_SR_RESET_GPIO_LOCK_RELEASE BIT(5) 104 105 #define UB960_SR_GEN_CONFIG 0x02 106 #define UB960_SR_REV_MASK 0x03 107 #define UB960_SR_DEVICE_STS 0x04 108 #define UB960_SR_PAR_ERR_THOLD_HI 0x05 109 #define UB960_SR_PAR_ERR_THOLD_LO 0x06 110 #define UB960_SR_BCC_WDOG_CTL 0x07 111 #define UB960_SR_I2C_CTL1 0x08 112 #define UB960_SR_I2C_CTL2 0x09 113 #define UB960_SR_SCL_HIGH_TIME 0x0a 114 #define UB960_SR_SCL_LOW_TIME 0x0b 115 #define UB960_SR_RX_PORT_CTL 0x0c 116 #define UB960_SR_IO_CTL 0x0d 117 #define UB960_SR_GPIO_PIN_STS 0x0e 118 #define UB960_SR_GPIO_INPUT_CTL 0x0f 119 #define UB960_SR_GPIO_PIN_CTL(n) (0x10 + (n)) /* n < UB960_NUM_GPIOS */ 120 #define UB960_SR_GPIO_PIN_CTL_GPIO_OUT_SEL 5 121 #define UB960_SR_GPIO_PIN_CTL_GPIO_OUT_SRC_SHIFT 2 122 #define UB960_SR_GPIO_PIN_CTL_GPIO_OUT_EN BIT(0) 123 124 #define UB960_SR_FS_CTL 0x18 125 #define UB960_SR_FS_HIGH_TIME_1 0x19 126 #define UB960_SR_FS_HIGH_TIME_0 0x1a 127 #define UB960_SR_FS_LOW_TIME_1 0x1b 128 #define UB960_SR_FS_LOW_TIME_0 0x1c 129 #define UB960_SR_MAX_FRM_HI 0x1d 130 #define UB960_SR_MAX_FRM_LO 0x1e 131 #define UB960_SR_CSI_PLL_CTL 0x1f 132 133 #define UB960_SR_FWD_CTL1 0x20 134 #define UB960_SR_FWD_CTL1_PORT_DIS(n) BIT((n) + 4) 135 136 #define UB960_SR_FWD_CTL2 0x21 137 #define UB960_SR_FWD_STS 0x22 138 139 #define UB960_SR_INTERRUPT_CTL 0x23 140 #define UB960_SR_INTERRUPT_CTL_INT_EN BIT(7) 141 #define UB960_SR_INTERRUPT_CTL_IE_CSI_TX0 BIT(4) 142 #define UB960_SR_INTERRUPT_CTL_IE_RX(n) BIT((n)) /* rxport[n] IRQ */ 143 144 #define UB960_SR_INTERRUPT_STS 0x24 145 #define UB960_SR_INTERRUPT_STS_INT BIT(7) 146 #define UB960_SR_INTERRUPT_STS_IS_CSI_TX(n) BIT(4 + (n)) /* txport[n] IRQ */ 147 #define UB960_SR_INTERRUPT_STS_IS_RX(n) BIT((n)) /* rxport[n] IRQ */ 148 149 #define UB960_SR_TS_CONFIG 0x25 150 #define UB960_SR_TS_CONTROL 0x26 151 #define UB960_SR_TS_LINE_HI 0x27 152 #define UB960_SR_TS_LINE_LO 0x28 153 #define UB960_SR_TS_STATUS 0x29 154 #define UB960_SR_TIMESTAMP_P0_HI 0x2a 155 #define UB960_SR_TIMESTAMP_P0_LO 0x2b 156 #define UB960_SR_TIMESTAMP_P1_HI 0x2c 157 #define UB960_SR_TIMESTAMP_P1_LO 0x2d 158 159 #define UB960_SR_CSI_PORT_SEL 0x32 160 161 #define UB960_TR_CSI_CTL 0x33 162 #define UB960_TR_CSI_CTL_CSI_CAL_EN BIT(6) 163 #define UB960_TR_CSI_CTL_CSI_CONTS_CLOCK BIT(1) 164 #define UB960_TR_CSI_CTL_CSI_ENABLE BIT(0) 165 166 #define UB960_TR_CSI_CTL2 0x34 167 #define UB960_TR_CSI_STS 0x35 168 #define UB960_TR_CSI_TX_ICR 0x36 169 170 #define UB960_TR_CSI_TX_ISR 0x37 171 #define UB960_TR_CSI_TX_ISR_IS_CSI_SYNC_ERROR BIT(3) 172 #define UB960_TR_CSI_TX_ISR_IS_CSI_PASS_ERROR BIT(1) 173 174 #define UB960_TR_CSI_TEST_CTL 0x38 175 #define UB960_TR_CSI_TEST_PATT_HI 0x39 176 #define UB960_TR_CSI_TEST_PATT_LO 0x3a 177 178 #define UB960_XR_SFILTER_CFG 0x41 179 #define UB960_XR_SFILTER_CFG_SFILTER_MAX_SHIFT 4 180 #define UB960_XR_SFILTER_CFG_SFILTER_MIN_SHIFT 0 181 182 #define UB960_XR_AEQ_CTL1 0x42 183 #define UB960_XR_AEQ_CTL1_AEQ_ERR_CTL_FPD_CLK BIT(6) 184 #define UB960_XR_AEQ_CTL1_AEQ_ERR_CTL_ENCODING BIT(5) 185 #define UB960_XR_AEQ_CTL1_AEQ_ERR_CTL_PARITY BIT(4) 186 #define UB960_XR_AEQ_CTL1_AEQ_ERR_CTL_MASK \ 187 (UB960_XR_AEQ_CTL1_AEQ_ERR_CTL_FPD_CLK | \ 188 UB960_XR_AEQ_CTL1_AEQ_ERR_CTL_ENCODING | \ 189 UB960_XR_AEQ_CTL1_AEQ_ERR_CTL_PARITY) 190 #define UB960_XR_AEQ_CTL1_AEQ_SFILTER_EN BIT(0) 191 192 #define UB960_XR_AEQ_ERR_THOLD 0x43 193 194 #define UB960_RR_BCC_ERR_CTL 0x46 195 #define UB960_RR_BCC_STATUS 0x47 196 #define UB960_RR_BCC_STATUS_SEQ_ERROR BIT(5) 197 #define UB960_RR_BCC_STATUS_MASTER_ERR BIT(4) 198 #define UB960_RR_BCC_STATUS_MASTER_TO BIT(3) 199 #define UB960_RR_BCC_STATUS_SLAVE_ERR BIT(2) 200 #define UB960_RR_BCC_STATUS_SLAVE_TO BIT(1) 201 #define UB960_RR_BCC_STATUS_RESP_ERR BIT(0) 202 #define UB960_RR_BCC_STATUS_ERROR_MASK \ 203 (UB960_RR_BCC_STATUS_SEQ_ERROR | UB960_RR_BCC_STATUS_MASTER_ERR | \ 204 UB960_RR_BCC_STATUS_MASTER_TO | UB960_RR_BCC_STATUS_SLAVE_ERR | \ 205 UB960_RR_BCC_STATUS_SLAVE_TO | UB960_RR_BCC_STATUS_RESP_ERR) 206 207 #define UB960_RR_FPD3_CAP 0x4a 208 #define UB960_RR_RAW_EMBED_DTYPE 0x4b 209 #define UB960_RR_RAW_EMBED_DTYPE_LINES_SHIFT 6 210 211 #define UB960_SR_FPD3_PORT_SEL 0x4c 212 213 #define UB960_RR_RX_PORT_STS1 0x4d 214 #define UB960_RR_RX_PORT_STS1_BCC_CRC_ERROR BIT(5) 215 #define UB960_RR_RX_PORT_STS1_LOCK_STS_CHG BIT(4) 216 #define UB960_RR_RX_PORT_STS1_BCC_SEQ_ERROR BIT(3) 217 #define UB960_RR_RX_PORT_STS1_PARITY_ERROR BIT(2) 218 #define UB960_RR_RX_PORT_STS1_PORT_PASS BIT(1) 219 #define UB960_RR_RX_PORT_STS1_LOCK_STS BIT(0) 220 #define UB960_RR_RX_PORT_STS1_ERROR_MASK \ 221 (UB960_RR_RX_PORT_STS1_BCC_CRC_ERROR | \ 222 UB960_RR_RX_PORT_STS1_BCC_SEQ_ERROR | \ 223 UB960_RR_RX_PORT_STS1_PARITY_ERROR) 224 225 #define UB960_RR_RX_PORT_STS2 0x4e 226 #define UB960_RR_RX_PORT_STS2_LINE_LEN_UNSTABLE BIT(7) 227 #define UB960_RR_RX_PORT_STS2_LINE_LEN_CHG BIT(6) 228 #define UB960_RR_RX_PORT_STS2_FPD3_ENCODE_ERROR BIT(5) 229 #define UB960_RR_RX_PORT_STS2_BUFFER_ERROR BIT(4) 230 #define UB960_RR_RX_PORT_STS2_CSI_ERROR BIT(3) 231 #define UB960_RR_RX_PORT_STS2_FREQ_STABLE BIT(2) 232 #define UB960_RR_RX_PORT_STS2_CABLE_FAULT BIT(1) 233 #define UB960_RR_RX_PORT_STS2_LINE_CNT_CHG BIT(0) 234 #define UB960_RR_RX_PORT_STS2_ERROR_MASK \ 235 UB960_RR_RX_PORT_STS2_BUFFER_ERROR 236 237 #define UB960_RR_RX_FREQ_HIGH 0x4f 238 #define UB960_RR_RX_FREQ_LOW 0x50 239 #define UB960_RR_SENSOR_STS_0 0x51 240 #define UB960_RR_SENSOR_STS_1 0x52 241 #define UB960_RR_SENSOR_STS_2 0x53 242 #define UB960_RR_SENSOR_STS_3 0x54 243 #define UB960_RR_RX_PAR_ERR_HI 0x55 244 #define UB960_RR_RX_PAR_ERR_LO 0x56 245 #define UB960_RR_BIST_ERR_COUNT 0x57 246 247 #define UB960_RR_BCC_CONFIG 0x58 248 #define UB960_RR_BCC_CONFIG_BC_ALWAYS_ON BIT(4) 249 #define UB960_RR_BCC_CONFIG_AUTO_ACK_ALL BIT(5) 250 #define UB960_RR_BCC_CONFIG_I2C_PASS_THROUGH BIT(6) 251 #define UB960_RR_BCC_CONFIG_BC_FREQ_SEL_MASK GENMASK(2, 0) 252 253 #define UB960_RR_DATAPATH_CTL1 0x59 254 #define UB960_RR_DATAPATH_CTL2 0x5a 255 #define UB960_RR_SER_ID 0x5b 256 #define UB960_RR_SER_ID_FREEZE_DEVICE_ID BIT(0) 257 #define UB960_RR_SER_ALIAS_ID 0x5c 258 #define UB960_RR_SER_ALIAS_ID_AUTO_ACK BIT(0) 259 260 /* For these two register sets: n < UB960_MAX_PORT_ALIASES */ 261 #define UB960_RR_SLAVE_ID(n) (0x5d + (n)) 262 #define UB960_RR_SLAVE_ALIAS(n) (0x65 + (n)) 263 264 #define UB960_RR_PORT_CONFIG 0x6d 265 #define UB960_RR_PORT_CONFIG_FPD3_MODE_MASK GENMASK(1, 0) 266 267 #define UB960_RR_BC_GPIO_CTL(n) (0x6e + (n)) /* n < 2 */ 268 #define UB960_RR_RAW10_ID 0x70 269 #define UB960_RR_RAW10_ID_VC_SHIFT 6 270 #define UB960_RR_RAW10_ID_DT_SHIFT 0 271 272 #define UB960_RR_RAW12_ID 0x71 273 #define UB960_RR_CSI_VC_MAP 0x72 274 #define UB960_RR_CSI_VC_MAP_SHIFT(x) ((x) * 2) 275 276 #define UB960_RR_LINE_COUNT_HI 0x73 277 #define UB960_RR_LINE_COUNT_LO 0x74 278 #define UB960_RR_LINE_LEN_1 0x75 279 #define UB960_RR_LINE_LEN_0 0x76 280 #define UB960_RR_FREQ_DET_CTL 0x77 281 #define UB960_RR_MAILBOX_1 0x78 282 #define UB960_RR_MAILBOX_2 0x79 283 284 #define UB960_RR_CSI_RX_STS 0x7a 285 #define UB960_RR_CSI_RX_STS_LENGTH_ERR BIT(3) 286 #define UB960_RR_CSI_RX_STS_CKSUM_ERR BIT(2) 287 #define UB960_RR_CSI_RX_STS_ECC2_ERR BIT(1) 288 #define UB960_RR_CSI_RX_STS_ECC1_ERR BIT(0) 289 #define UB960_RR_CSI_RX_STS_ERROR_MASK \ 290 (UB960_RR_CSI_RX_STS_LENGTH_ERR | UB960_RR_CSI_RX_STS_CKSUM_ERR | \ 291 UB960_RR_CSI_RX_STS_ECC2_ERR | UB960_RR_CSI_RX_STS_ECC1_ERR) 292 293 #define UB960_RR_CSI_ERR_COUNTER 0x7b 294 #define UB960_RR_PORT_CONFIG2 0x7c 295 #define UB960_RR_PORT_CONFIG2_RAW10_8BIT_CTL_MASK GENMASK(7, 6) 296 #define UB960_RR_PORT_CONFIG2_RAW10_8BIT_CTL_SHIFT 6 297 298 #define UB960_RR_PORT_CONFIG2_LV_POL_LOW BIT(1) 299 #define UB960_RR_PORT_CONFIG2_FV_POL_LOW BIT(0) 300 301 #define UB960_RR_PORT_PASS_CTL 0x7d 302 #define UB960_RR_SEN_INT_RISE_CTL 0x7e 303 #define UB960_RR_SEN_INT_FALL_CTL 0x7f 304 305 #define UB960_SR_CSI_FRAME_COUNT_HI(n) (0x90 + 8 * (n)) 306 #define UB960_SR_CSI_FRAME_COUNT_LO(n) (0x91 + 8 * (n)) 307 #define UB960_SR_CSI_FRAME_ERR_COUNT_HI(n) (0x92 + 8 * (n)) 308 #define UB960_SR_CSI_FRAME_ERR_COUNT_LO(n) (0x93 + 8 * (n)) 309 #define UB960_SR_CSI_LINE_COUNT_HI(n) (0x94 + 8 * (n)) 310 #define UB960_SR_CSI_LINE_COUNT_LO(n) (0x95 + 8 * (n)) 311 #define UB960_SR_CSI_LINE_ERR_COUNT_HI(n) (0x96 + 8 * (n)) 312 #define UB960_SR_CSI_LINE_ERR_COUNT_LO(n) (0x97 + 8 * (n)) 313 314 #define UB960_XR_REFCLK_FREQ 0xa5 /* UB960 */ 315 316 #define UB960_SR_IND_ACC_CTL 0xb0 317 #define UB960_SR_IND_ACC_CTL_IA_AUTO_INC BIT(1) 318 319 #define UB960_SR_IND_ACC_ADDR 0xb1 320 #define UB960_SR_IND_ACC_DATA 0xb2 321 #define UB960_SR_BIST_CONTROL 0xb3 322 #define UB960_SR_MODE_IDX_STS 0xb8 323 #define UB960_SR_LINK_ERROR_COUNT 0xb9 324 #define UB960_SR_FPD3_ENC_CTL 0xba 325 #define UB960_SR_FV_MIN_TIME 0xbc 326 #define UB960_SR_GPIO_PD_CTL 0xbe 327 328 #define UB960_RR_PORT_DEBUG 0xd0 329 #define UB960_RR_AEQ_CTL2 0xd2 330 #define UB960_RR_AEQ_CTL2_SET_AEQ_FLOOR BIT(2) 331 332 #define UB960_RR_AEQ_STATUS 0xd3 333 #define UB960_RR_AEQ_STATUS_STATUS_2 GENMASK(5, 3) 334 #define UB960_RR_AEQ_STATUS_STATUS_1 GENMASK(2, 0) 335 336 #define UB960_RR_AEQ_BYPASS 0xd4 337 #define UB960_RR_AEQ_BYPASS_EQ_STAGE1_VALUE_SHIFT 5 338 #define UB960_RR_AEQ_BYPASS_EQ_STAGE1_VALUE_MASK GENMASK(7, 5) 339 #define UB960_RR_AEQ_BYPASS_EQ_STAGE2_VALUE_SHIFT 1 340 #define UB960_RR_AEQ_BYPASS_EQ_STAGE2_VALUE_MASK GENMASK(3, 1) 341 #define UB960_RR_AEQ_BYPASS_ENABLE BIT(0) 342 343 #define UB960_RR_AEQ_MIN_MAX 0xd5 344 #define UB960_RR_AEQ_MIN_MAX_AEQ_MAX_SHIFT 4 345 #define UB960_RR_AEQ_MIN_MAX_AEQ_FLOOR_SHIFT 0 346 347 #define UB960_RR_SFILTER_STS_0 0xd6 348 #define UB960_RR_SFILTER_STS_1 0xd7 349 #define UB960_RR_PORT_ICR_HI 0xd8 350 #define UB960_RR_PORT_ICR_LO 0xd9 351 #define UB960_RR_PORT_ISR_HI 0xda 352 #define UB960_RR_PORT_ISR_LO 0xdb 353 #define UB960_RR_FC_GPIO_STS 0xdc 354 #define UB960_RR_FC_GPIO_ICR 0xdd 355 #define UB960_RR_SEN_INT_RISE_STS 0xde 356 #define UB960_RR_SEN_INT_FALL_STS 0xdf 357 358 359 #define UB960_SR_FPD3_RX_ID(n) (0xf0 + (n)) 360 #define UB960_SR_FPD3_RX_ID_LEN 6 361 362 #define UB960_SR_I2C_RX_ID(n) (0xf8 + (n)) 363 364 /* Indirect register blocks */ 365 #define UB960_IND_TARGET_PAT_GEN 0x00 366 #define UB960_IND_TARGET_RX_ANA(n) (0x01 + (n)) 367 #define UB960_IND_TARGET_CSI_ANA 0x07 368 369 /* UB960_IR_PGEN_*: Indirect Registers for Test Pattern Generator */ 370 371 #define UB960_IR_PGEN_CTL 0x01 372 #define UB960_IR_PGEN_CTL_PGEN_ENABLE BIT(0) 373 374 #define UB960_IR_PGEN_CFG 0x02 375 #define UB960_IR_PGEN_CSI_DI 0x03 376 #define UB960_IR_PGEN_LINE_SIZE1 0x04 377 #define UB960_IR_PGEN_LINE_SIZE0 0x05 378 #define UB960_IR_PGEN_BAR_SIZE1 0x06 379 #define UB960_IR_PGEN_BAR_SIZE0 0x07 380 #define UB960_IR_PGEN_ACT_LPF1 0x08 381 #define UB960_IR_PGEN_ACT_LPF0 0x09 382 #define UB960_IR_PGEN_TOT_LPF1 0x0a 383 #define UB960_IR_PGEN_TOT_LPF0 0x0b 384 #define UB960_IR_PGEN_LINE_PD1 0x0c 385 #define UB960_IR_PGEN_LINE_PD0 0x0d 386 #define UB960_IR_PGEN_VBP 0x0e 387 #define UB960_IR_PGEN_VFP 0x0f 388 #define UB960_IR_PGEN_COLOR(n) (0x10 + (n)) /* n < 15 */ 389 390 #define UB960_IR_RX_ANA_STROBE_SET_CLK 0x08 391 #define UB960_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY BIT(3) 392 #define UB960_IR_RX_ANA_STROBE_SET_CLK_DELAY_MASK GENMASK(2, 0) 393 394 #define UB960_IR_RX_ANA_STROBE_SET_DATA 0x09 395 #define UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY BIT(3) 396 #define UB960_IR_RX_ANA_STROBE_SET_DATA_DELAY_MASK GENMASK(2, 0) 397 398 /* UB9702 Registers */ 399 400 #define UB9702_SR_CSI_EXCLUSIVE_FWD2 0x3c 401 #define UB9702_SR_REFCLK_FREQ 0x3d 402 #define UB9702_RR_RX_CTL_1 0x80 403 #define UB9702_RR_RX_CTL_2 0x87 404 #define UB9702_RR_VC_ID_MAP(x) (0xa0 + (x)) 405 #define UB9702_SR_FPD_RATE_CFG 0xc2 406 #define UB9702_SR_CSI_PLL_DIV 0xc9 407 #define UB9702_RR_RX_SM_SEL_2 0xd4 408 #define UB9702_RR_CHANNEL_MODE 0xe4 409 410 #define UB9702_IND_TARGET_SAR_ADC 0x0a 411 412 #define UB9702_IR_RX_ANA_FPD_BC_CTL0 0x04 413 #define UB9702_IR_RX_ANA_FPD_BC_CTL1 0x0d 414 #define UB9702_IR_RX_ANA_FPD_BC_CTL2 0x1b 415 #define UB9702_IR_RX_ANA_SYSTEM_INIT_REG0 0x21 416 #define UB9702_IR_RX_ANA_AEQ_ALP_SEL6 0x27 417 #define UB9702_IR_RX_ANA_AEQ_ALP_SEL7 0x28 418 #define UB9702_IR_RX_ANA_AEQ_ALP_SEL10 0x2b 419 #define UB9702_IR_RX_ANA_AEQ_ALP_SEL11 0x2c 420 #define UB9702_IR_RX_ANA_EQ_ADAPT_CTRL 0x2e 421 #define UB9702_IR_RX_ANA_AEQ_CFG_1 0x34 422 #define UB9702_IR_RX_ANA_AEQ_CFG_2 0x4d 423 #define UB9702_IR_RX_ANA_GAIN_CTRL_0 0x71 424 #define UB9702_IR_RX_ANA_GAIN_CTRL_0 0x71 425 #define UB9702_IR_RX_ANA_VGA_CTRL_SEL_1 0x72 426 #define UB9702_IR_RX_ANA_VGA_CTRL_SEL_2 0x73 427 #define UB9702_IR_RX_ANA_VGA_CTRL_SEL_3 0x74 428 #define UB9702_IR_RX_ANA_VGA_CTRL_SEL_6 0x77 429 #define UB9702_IR_RX_ANA_AEQ_CFG_3 0x79 430 #define UB9702_IR_RX_ANA_AEQ_CFG_4 0x85 431 #define UB9702_IR_RX_ANA_EQ_CTRL_SEL_15 0x87 432 #define UB9702_IR_RX_ANA_EQ_CTRL_SEL_24 0x90 433 #define UB9702_IR_RX_ANA_EQ_CTRL_SEL_38 0x9e 434 #define UB9702_IR_RX_ANA_FPD3_CDR_CTRL_SEL_5 0xa5 435 #define UB9702_IR_RX_ANA_FPD3_AEQ_CTRL_SEL_1 0xa8 436 #define UB9702_IR_RX_ANA_EQ_OVERRIDE_CTRL 0xf0 437 #define UB9702_IR_RX_ANA_VGA_CTRL_SEL_8 0xf1 438 439 #define UB9702_IR_CSI_ANA_CSIPLL_REG_1 0x92 440 441 /* EQ related */ 442 443 #define UB960_MIN_AEQ_STROBE_POS -7 444 #define UB960_MAX_AEQ_STROBE_POS 7 445 446 #define UB960_MANUAL_STROBE_EXTRA_DELAY 6 447 448 #define UB960_MIN_MANUAL_STROBE_POS -(7 + UB960_MANUAL_STROBE_EXTRA_DELAY) 449 #define UB960_MAX_MANUAL_STROBE_POS (7 + UB960_MANUAL_STROBE_EXTRA_DELAY) 450 #define UB960_NUM_MANUAL_STROBE_POS (UB960_MAX_MANUAL_STROBE_POS - UB960_MIN_MANUAL_STROBE_POS + 1) 451 452 #define UB960_MIN_EQ_LEVEL 0 453 #define UB960_MAX_EQ_LEVEL 14 454 #define UB960_NUM_EQ_LEVELS (UB960_MAX_EQ_LEVEL - UB960_MIN_EQ_LEVEL + 1) 455 456 struct ub960_hw_data { 457 const char *model; 458 u8 num_rxports; 459 u8 num_txports; 460 bool is_ub9702; 461 bool is_fpdlink4; 462 }; 463 464 enum ub960_rxport_mode { 465 RXPORT_MODE_RAW10 = 0, 466 RXPORT_MODE_RAW12_HF = 1, 467 RXPORT_MODE_RAW12_LF = 2, 468 RXPORT_MODE_CSI2_SYNC = 3, 469 RXPORT_MODE_CSI2_NONSYNC = 4, 470 RXPORT_MODE_LAST = RXPORT_MODE_CSI2_NONSYNC, 471 }; 472 473 enum ub960_rxport_cdr { 474 RXPORT_CDR_FPD3 = 0, 475 RXPORT_CDR_FPD4 = 1, 476 RXPORT_CDR_LAST = RXPORT_CDR_FPD4, 477 }; 478 479 struct ub960_rxport { 480 struct ub960_data *priv; 481 u8 nport; /* RX port number, and index in priv->rxport[] */ 482 483 struct { 484 struct v4l2_subdev *sd; 485 u16 pad; 486 struct fwnode_handle *ep_fwnode; 487 } source; 488 489 /* Serializer */ 490 struct { 491 struct fwnode_handle *fwnode; 492 struct i2c_client *client; 493 unsigned short alias; /* I2C alias (lower 7 bits) */ 494 short addr; /* Local I2C address (lower 7 bits) */ 495 struct ds90ub9xx_platform_data pdata; 496 struct regmap *regmap; 497 } ser; 498 499 enum ub960_rxport_mode rx_mode; 500 enum ub960_rxport_cdr cdr_mode; 501 502 u8 lv_fv_pol; /* LV and FV polarities */ 503 504 struct regulator *vpoc; 505 506 /* EQ settings */ 507 struct { 508 bool manual_eq; 509 510 s8 strobe_pos; 511 512 union { 513 struct { 514 u8 eq_level_min; 515 u8 eq_level_max; 516 } aeq; 517 518 struct { 519 u8 eq_level; 520 } manual; 521 }; 522 } eq; 523 524 const struct i2c_client *aliased_clients[UB960_MAX_PORT_ALIASES]; 525 }; 526 527 struct ub960_asd { 528 struct v4l2_async_connection base; 529 struct ub960_rxport *rxport; 530 }; 531 532 static inline struct ub960_asd *to_ub960_asd(struct v4l2_async_connection *asd) 533 { 534 return container_of(asd, struct ub960_asd, base); 535 } 536 537 struct ub960_txport { 538 struct ub960_data *priv; 539 u8 nport; /* TX port number, and index in priv->txport[] */ 540 541 u32 num_data_lanes; 542 bool non_continous_clk; 543 }; 544 545 struct ub960_data { 546 const struct ub960_hw_data *hw_data; 547 struct i2c_client *client; /* for shared local registers */ 548 struct regmap *regmap; 549 550 /* lock for register access */ 551 struct mutex reg_lock; 552 553 struct clk *refclk; 554 555 struct regulator *vddio; 556 557 struct gpio_desc *pd_gpio; 558 struct delayed_work poll_work; 559 struct ub960_rxport *rxports[UB960_MAX_RX_NPORTS]; 560 struct ub960_txport *txports[UB960_MAX_TX_NPORTS]; 561 562 struct v4l2_subdev sd; 563 struct media_pad pads[UB960_MAX_NPORTS]; 564 565 struct v4l2_ctrl_handler ctrl_handler; 566 struct v4l2_async_notifier notifier; 567 568 u32 tx_data_rate; /* Nominal data rate (Gb/s) */ 569 s64 tx_link_freq[1]; 570 571 struct i2c_atr *atr; 572 573 struct { 574 u8 rxport; 575 u8 txport; 576 u8 indirect_target; 577 } reg_current; 578 579 bool streaming; 580 581 u8 stored_fwd_ctl; 582 583 u64 stream_enable_mask[UB960_MAX_NPORTS]; 584 585 /* These are common to all ports */ 586 struct { 587 bool manual; 588 589 s8 min; 590 s8 max; 591 } strobe; 592 }; 593 594 static inline struct ub960_data *sd_to_ub960(struct v4l2_subdev *sd) 595 { 596 return container_of(sd, struct ub960_data, sd); 597 } 598 599 static inline bool ub960_pad_is_sink(struct ub960_data *priv, u32 pad) 600 { 601 return pad < priv->hw_data->num_rxports; 602 } 603 604 static inline bool ub960_pad_is_source(struct ub960_data *priv, u32 pad) 605 { 606 return pad >= priv->hw_data->num_rxports; 607 } 608 609 static inline unsigned int ub960_pad_to_port(struct ub960_data *priv, u32 pad) 610 { 611 if (ub960_pad_is_sink(priv, pad)) 612 return pad; 613 else 614 return pad - priv->hw_data->num_rxports; 615 } 616 617 struct ub960_format_info { 618 u32 code; 619 u32 bpp; 620 u8 datatype; 621 bool meta; 622 }; 623 624 static const struct ub960_format_info ub960_formats[] = { 625 { .code = MEDIA_BUS_FMT_RGB888_1X24, .bpp = 24, .datatype = MIPI_CSI2_DT_RGB888, }, 626 627 { .code = MEDIA_BUS_FMT_YUYV8_1X16, .bpp = 16, .datatype = MIPI_CSI2_DT_YUV422_8B, }, 628 { .code = MEDIA_BUS_FMT_UYVY8_1X16, .bpp = 16, .datatype = MIPI_CSI2_DT_YUV422_8B, }, 629 { .code = MEDIA_BUS_FMT_VYUY8_1X16, .bpp = 16, .datatype = MIPI_CSI2_DT_YUV422_8B, }, 630 { .code = MEDIA_BUS_FMT_YVYU8_1X16, .bpp = 16, .datatype = MIPI_CSI2_DT_YUV422_8B, }, 631 632 { .code = MEDIA_BUS_FMT_SBGGR8_1X8, .bpp = 8, .datatype = MIPI_CSI2_DT_RAW8, }, 633 { .code = MEDIA_BUS_FMT_SGBRG8_1X8, .bpp = 8, .datatype = MIPI_CSI2_DT_RAW8, }, 634 { .code = MEDIA_BUS_FMT_SGRBG8_1X8, .bpp = 8, .datatype = MIPI_CSI2_DT_RAW8, }, 635 { .code = MEDIA_BUS_FMT_SRGGB8_1X8, .bpp = 8, .datatype = MIPI_CSI2_DT_RAW8, }, 636 637 { .code = MEDIA_BUS_FMT_SBGGR10_1X10, .bpp = 10, .datatype = MIPI_CSI2_DT_RAW10, }, 638 { .code = MEDIA_BUS_FMT_SGBRG10_1X10, .bpp = 10, .datatype = MIPI_CSI2_DT_RAW10, }, 639 { .code = MEDIA_BUS_FMT_SGRBG10_1X10, .bpp = 10, .datatype = MIPI_CSI2_DT_RAW10, }, 640 { .code = MEDIA_BUS_FMT_SRGGB10_1X10, .bpp = 10, .datatype = MIPI_CSI2_DT_RAW10, }, 641 642 { .code = MEDIA_BUS_FMT_SBGGR12_1X12, .bpp = 12, .datatype = MIPI_CSI2_DT_RAW12, }, 643 { .code = MEDIA_BUS_FMT_SGBRG12_1X12, .bpp = 12, .datatype = MIPI_CSI2_DT_RAW12, }, 644 { .code = MEDIA_BUS_FMT_SGRBG12_1X12, .bpp = 12, .datatype = MIPI_CSI2_DT_RAW12, }, 645 { .code = MEDIA_BUS_FMT_SRGGB12_1X12, .bpp = 12, .datatype = MIPI_CSI2_DT_RAW12, }, 646 }; 647 648 static const struct ub960_format_info *ub960_find_format(u32 code) 649 { 650 unsigned int i; 651 652 for (i = 0; i < ARRAY_SIZE(ub960_formats); i++) { 653 if (ub960_formats[i].code == code) 654 return &ub960_formats[i]; 655 } 656 657 return NULL; 658 } 659 660 struct ub960_rxport_iter { 661 unsigned int nport; 662 struct ub960_rxport *rxport; 663 }; 664 665 enum ub960_iter_flags { 666 UB960_ITER_ACTIVE_ONLY = BIT(0), 667 UB960_ITER_FPD4_ONLY = BIT(1), 668 }; 669 670 static struct ub960_rxport_iter ub960_iter_rxport(struct ub960_data *priv, 671 struct ub960_rxport_iter it, 672 enum ub960_iter_flags flags) 673 { 674 for (; it.nport < priv->hw_data->num_rxports; it.nport++) { 675 it.rxport = priv->rxports[it.nport]; 676 677 if ((flags & UB960_ITER_ACTIVE_ONLY) && !it.rxport) 678 continue; 679 680 if ((flags & UB960_ITER_FPD4_ONLY) && 681 it.rxport->cdr_mode != RXPORT_CDR_FPD4) 682 continue; 683 684 return it; 685 } 686 687 it.rxport = NULL; 688 689 return it; 690 } 691 692 #define for_each_rxport(priv, it) \ 693 for (struct ub960_rxport_iter it = \ 694 ub960_iter_rxport(priv, (struct ub960_rxport_iter){ 0 }, \ 695 0); \ 696 it.nport < (priv)->hw_data->num_rxports; \ 697 it.nport++, it = ub960_iter_rxport(priv, it, 0)) 698 699 #define for_each_active_rxport(priv, it) \ 700 for (struct ub960_rxport_iter it = \ 701 ub960_iter_rxport(priv, (struct ub960_rxport_iter){ 0 }, \ 702 UB960_ITER_ACTIVE_ONLY); \ 703 it.nport < (priv)->hw_data->num_rxports; \ 704 it.nport++, it = ub960_iter_rxport(priv, it, \ 705 UB960_ITER_ACTIVE_ONLY)) 706 707 #define for_each_active_rxport_fpd4(priv, it) \ 708 for (struct ub960_rxport_iter it = \ 709 ub960_iter_rxport(priv, (struct ub960_rxport_iter){ 0 }, \ 710 UB960_ITER_ACTIVE_ONLY | \ 711 UB960_ITER_FPD4_ONLY); \ 712 it.nport < (priv)->hw_data->num_rxports; \ 713 it.nport++, it = ub960_iter_rxport(priv, it, \ 714 UB960_ITER_ACTIVE_ONLY | \ 715 UB960_ITER_FPD4_ONLY)) 716 717 /* ----------------------------------------------------------------------------- 718 * Basic device access 719 */ 720 721 static int ub960_read(struct ub960_data *priv, u8 reg, u8 *val, int *err) 722 { 723 struct device *dev = &priv->client->dev; 724 unsigned int v; 725 int ret; 726 727 if (err && *err) 728 return *err; 729 730 mutex_lock(&priv->reg_lock); 731 732 ret = regmap_read(priv->regmap, reg, &v); 733 if (ret) { 734 dev_err(dev, "%s: cannot read register 0x%02x (%d)!\n", 735 __func__, reg, ret); 736 goto out_unlock; 737 } 738 739 *val = v; 740 741 out_unlock: 742 mutex_unlock(&priv->reg_lock); 743 744 if (ret && err) 745 *err = ret; 746 747 return ret; 748 } 749 750 static int ub960_write(struct ub960_data *priv, u8 reg, u8 val, int *err) 751 { 752 struct device *dev = &priv->client->dev; 753 int ret; 754 755 if (err && *err) 756 return *err; 757 758 mutex_lock(&priv->reg_lock); 759 760 ret = regmap_write(priv->regmap, reg, val); 761 if (ret) 762 dev_err(dev, "%s: cannot write register 0x%02x (%d)!\n", 763 __func__, reg, ret); 764 765 mutex_unlock(&priv->reg_lock); 766 767 if (ret && err) 768 *err = ret; 769 770 return ret; 771 } 772 773 static int ub960_update_bits(struct ub960_data *priv, u8 reg, u8 mask, u8 val, 774 int *err) 775 { 776 struct device *dev = &priv->client->dev; 777 int ret; 778 779 if (err && *err) 780 return *err; 781 782 mutex_lock(&priv->reg_lock); 783 784 ret = regmap_update_bits(priv->regmap, reg, mask, val); 785 if (ret) 786 dev_err(dev, "%s: cannot update register 0x%02x (%d)!\n", 787 __func__, reg, ret); 788 789 mutex_unlock(&priv->reg_lock); 790 791 if (ret && err) 792 *err = ret; 793 794 return ret; 795 } 796 797 static int ub960_read16(struct ub960_data *priv, u8 reg, u16 *val, int *err) 798 { 799 struct device *dev = &priv->client->dev; 800 __be16 __v; 801 int ret; 802 803 if (err && *err) 804 return *err; 805 806 mutex_lock(&priv->reg_lock); 807 808 ret = regmap_bulk_read(priv->regmap, reg, &__v, sizeof(__v)); 809 if (ret) { 810 dev_err(dev, "%s: cannot read register 0x%02x (%d)!\n", 811 __func__, reg, ret); 812 goto out_unlock; 813 } 814 815 *val = be16_to_cpu(__v); 816 817 out_unlock: 818 mutex_unlock(&priv->reg_lock); 819 820 if (ret && err) 821 *err = ret; 822 823 return ret; 824 } 825 826 static int ub960_rxport_select(struct ub960_data *priv, u8 nport) 827 { 828 struct device *dev = &priv->client->dev; 829 int ret; 830 831 lockdep_assert_held(&priv->reg_lock); 832 833 if (priv->reg_current.rxport == nport) 834 return 0; 835 836 ret = regmap_write(priv->regmap, UB960_SR_FPD3_PORT_SEL, 837 (nport << 4) | BIT(nport)); 838 if (ret) { 839 dev_err(dev, "%s: cannot select rxport %d (%d)!\n", __func__, 840 nport, ret); 841 return ret; 842 } 843 844 priv->reg_current.rxport = nport; 845 846 return 0; 847 } 848 849 static int ub960_rxport_read(struct ub960_data *priv, u8 nport, u8 reg, 850 u8 *val, int *err) 851 { 852 struct device *dev = &priv->client->dev; 853 unsigned int v; 854 int ret; 855 856 if (err && *err) 857 return *err; 858 859 mutex_lock(&priv->reg_lock); 860 861 ret = ub960_rxport_select(priv, nport); 862 if (ret) 863 goto out_unlock; 864 865 ret = regmap_read(priv->regmap, reg, &v); 866 if (ret) { 867 dev_err(dev, "%s: cannot read register 0x%02x (%d)!\n", 868 __func__, reg, ret); 869 goto out_unlock; 870 } 871 872 *val = v; 873 874 out_unlock: 875 mutex_unlock(&priv->reg_lock); 876 877 if (ret && err) 878 *err = ret; 879 880 return ret; 881 } 882 883 static int ub960_rxport_write(struct ub960_data *priv, u8 nport, u8 reg, 884 u8 val, int *err) 885 { 886 struct device *dev = &priv->client->dev; 887 int ret; 888 889 if (err && *err) 890 return *err; 891 892 mutex_lock(&priv->reg_lock); 893 894 ret = ub960_rxport_select(priv, nport); 895 if (ret) 896 goto out_unlock; 897 898 ret = regmap_write(priv->regmap, reg, val); 899 if (ret) 900 dev_err(dev, "%s: cannot write register 0x%02x (%d)!\n", 901 __func__, reg, ret); 902 903 out_unlock: 904 mutex_unlock(&priv->reg_lock); 905 906 if (ret && err) 907 *err = ret; 908 909 return ret; 910 } 911 912 static int ub960_rxport_update_bits(struct ub960_data *priv, u8 nport, u8 reg, 913 u8 mask, u8 val, int *err) 914 { 915 struct device *dev = &priv->client->dev; 916 int ret; 917 918 if (err && *err) 919 return *err; 920 921 mutex_lock(&priv->reg_lock); 922 923 ret = ub960_rxport_select(priv, nport); 924 if (ret) 925 goto out_unlock; 926 927 ret = regmap_update_bits(priv->regmap, reg, mask, val); 928 if (ret) 929 dev_err(dev, "%s: cannot update register 0x%02x (%d)!\n", 930 __func__, reg, ret); 931 932 out_unlock: 933 mutex_unlock(&priv->reg_lock); 934 935 if (ret && err) 936 *err = ret; 937 938 return ret; 939 } 940 941 static int ub960_rxport_read16(struct ub960_data *priv, u8 nport, u8 reg, 942 u16 *val, int *err) 943 { 944 struct device *dev = &priv->client->dev; 945 __be16 __v; 946 int ret; 947 948 if (err && *err) 949 return *err; 950 951 mutex_lock(&priv->reg_lock); 952 953 ret = ub960_rxport_select(priv, nport); 954 if (ret) 955 goto out_unlock; 956 957 ret = regmap_bulk_read(priv->regmap, reg, &__v, sizeof(__v)); 958 if (ret) { 959 dev_err(dev, "%s: cannot read register 0x%02x (%d)!\n", 960 __func__, reg, ret); 961 goto out_unlock; 962 } 963 964 *val = be16_to_cpu(__v); 965 966 out_unlock: 967 mutex_unlock(&priv->reg_lock); 968 969 if (ret && err) 970 *err = ret; 971 972 return ret; 973 } 974 975 static int ub960_txport_select(struct ub960_data *priv, u8 nport) 976 { 977 struct device *dev = &priv->client->dev; 978 int ret; 979 980 lockdep_assert_held(&priv->reg_lock); 981 982 if (priv->reg_current.txport == nport) 983 return 0; 984 985 ret = regmap_write(priv->regmap, UB960_SR_CSI_PORT_SEL, 986 (nport << 4) | BIT(nport)); 987 if (ret) { 988 dev_err(dev, "%s: cannot select tx port %d (%d)!\n", __func__, 989 nport, ret); 990 return ret; 991 } 992 993 priv->reg_current.txport = nport; 994 995 return 0; 996 } 997 998 static int ub960_txport_read(struct ub960_data *priv, u8 nport, u8 reg, 999 u8 *val, int *err) 1000 { 1001 struct device *dev = &priv->client->dev; 1002 unsigned int v; 1003 int ret; 1004 1005 if (err && *err) 1006 return *err; 1007 1008 mutex_lock(&priv->reg_lock); 1009 1010 ret = ub960_txport_select(priv, nport); 1011 if (ret) 1012 goto out_unlock; 1013 1014 ret = regmap_read(priv->regmap, reg, &v); 1015 if (ret) { 1016 dev_err(dev, "%s: cannot read register 0x%02x (%d)!\n", 1017 __func__, reg, ret); 1018 goto out_unlock; 1019 } 1020 1021 *val = v; 1022 1023 out_unlock: 1024 mutex_unlock(&priv->reg_lock); 1025 1026 if (ret && err) 1027 *err = ret; 1028 1029 return ret; 1030 } 1031 1032 static int ub960_txport_write(struct ub960_data *priv, u8 nport, u8 reg, 1033 u8 val, int *err) 1034 { 1035 struct device *dev = &priv->client->dev; 1036 int ret; 1037 1038 if (err && *err) 1039 return *err; 1040 1041 mutex_lock(&priv->reg_lock); 1042 1043 ret = ub960_txport_select(priv, nport); 1044 if (ret) 1045 goto out_unlock; 1046 1047 ret = regmap_write(priv->regmap, reg, val); 1048 if (ret) 1049 dev_err(dev, "%s: cannot write register 0x%02x (%d)!\n", 1050 __func__, reg, ret); 1051 1052 out_unlock: 1053 mutex_unlock(&priv->reg_lock); 1054 1055 if (ret && err) 1056 *err = ret; 1057 1058 return ret; 1059 } 1060 1061 static int ub960_txport_update_bits(struct ub960_data *priv, u8 nport, u8 reg, 1062 u8 mask, u8 val, int *err) 1063 { 1064 struct device *dev = &priv->client->dev; 1065 int ret; 1066 1067 if (err && *err) 1068 return *err; 1069 1070 mutex_lock(&priv->reg_lock); 1071 1072 ret = ub960_txport_select(priv, nport); 1073 if (ret) 1074 goto out_unlock; 1075 1076 ret = regmap_update_bits(priv->regmap, reg, mask, val); 1077 if (ret) 1078 dev_err(dev, "%s: cannot update register 0x%02x (%d)!\n", 1079 __func__, reg, ret); 1080 1081 out_unlock: 1082 mutex_unlock(&priv->reg_lock); 1083 1084 if (ret && err) 1085 *err = ret; 1086 1087 return ret; 1088 } 1089 1090 static int ub960_select_ind_reg_block(struct ub960_data *priv, u8 block) 1091 { 1092 struct device *dev = &priv->client->dev; 1093 int ret; 1094 1095 lockdep_assert_held(&priv->reg_lock); 1096 1097 if (priv->reg_current.indirect_target == block) 1098 return 0; 1099 1100 ret = regmap_write(priv->regmap, UB960_SR_IND_ACC_CTL, block << 2); 1101 if (ret) { 1102 dev_err(dev, "%s: cannot select indirect target %u (%d)!\n", 1103 __func__, block, ret); 1104 return ret; 1105 } 1106 1107 priv->reg_current.indirect_target = block; 1108 1109 return 0; 1110 } 1111 1112 static int ub960_read_ind(struct ub960_data *priv, u8 block, u8 reg, u8 *val, 1113 int *err) 1114 { 1115 struct device *dev = &priv->client->dev; 1116 unsigned int v; 1117 int ret; 1118 1119 if (err && *err) 1120 return *err; 1121 1122 mutex_lock(&priv->reg_lock); 1123 1124 ret = ub960_select_ind_reg_block(priv, block); 1125 if (ret) 1126 goto out_unlock; 1127 1128 ret = regmap_write(priv->regmap, UB960_SR_IND_ACC_ADDR, reg); 1129 if (ret) { 1130 dev_err(dev, 1131 "Write to IND_ACC_ADDR failed when reading %u:%x02x: %d\n", 1132 block, reg, ret); 1133 goto out_unlock; 1134 } 1135 1136 ret = regmap_read(priv->regmap, UB960_SR_IND_ACC_DATA, &v); 1137 if (ret) { 1138 dev_err(dev, 1139 "Write to IND_ACC_DATA failed when reading %u:%x02x: %d\n", 1140 block, reg, ret); 1141 goto out_unlock; 1142 } 1143 1144 *val = v; 1145 1146 out_unlock: 1147 mutex_unlock(&priv->reg_lock); 1148 1149 if (ret && err) 1150 *err = ret; 1151 1152 return ret; 1153 } 1154 1155 static int ub960_write_ind(struct ub960_data *priv, u8 block, u8 reg, u8 val, 1156 int *err) 1157 { 1158 struct device *dev = &priv->client->dev; 1159 int ret; 1160 1161 if (err && *err) 1162 return *err; 1163 1164 mutex_lock(&priv->reg_lock); 1165 1166 ret = ub960_select_ind_reg_block(priv, block); 1167 if (ret) 1168 goto out_unlock; 1169 1170 ret = regmap_write(priv->regmap, UB960_SR_IND_ACC_ADDR, reg); 1171 if (ret) { 1172 dev_err(dev, 1173 "Write to IND_ACC_ADDR failed when writing %u:%x02x: %d\n", 1174 block, reg, ret); 1175 goto out_unlock; 1176 } 1177 1178 ret = regmap_write(priv->regmap, UB960_SR_IND_ACC_DATA, val); 1179 if (ret) { 1180 dev_err(dev, 1181 "Write to IND_ACC_DATA failed when writing %u:%x02x: %d\n", 1182 block, reg, ret); 1183 goto out_unlock; 1184 } 1185 1186 out_unlock: 1187 mutex_unlock(&priv->reg_lock); 1188 1189 if (ret && err) 1190 *err = ret; 1191 1192 return ret; 1193 } 1194 1195 static int ub960_ind_update_bits(struct ub960_data *priv, u8 block, u8 reg, 1196 u8 mask, u8 val, int *err) 1197 { 1198 struct device *dev = &priv->client->dev; 1199 int ret; 1200 1201 if (err && *err) 1202 return *err; 1203 1204 mutex_lock(&priv->reg_lock); 1205 1206 ret = ub960_select_ind_reg_block(priv, block); 1207 if (ret) 1208 goto out_unlock; 1209 1210 ret = regmap_write(priv->regmap, UB960_SR_IND_ACC_ADDR, reg); 1211 if (ret) { 1212 dev_err(dev, 1213 "Write to IND_ACC_ADDR failed when updating %u:%x02x: %d\n", 1214 block, reg, ret); 1215 goto out_unlock; 1216 } 1217 1218 ret = regmap_update_bits(priv->regmap, UB960_SR_IND_ACC_DATA, mask, 1219 val); 1220 if (ret) { 1221 dev_err(dev, 1222 "Write to IND_ACC_DATA failed when updating %u:%x02x: %d\n", 1223 block, reg, ret); 1224 goto out_unlock; 1225 } 1226 1227 out_unlock: 1228 mutex_unlock(&priv->reg_lock); 1229 1230 if (ret && err) 1231 *err = ret; 1232 1233 return ret; 1234 } 1235 1236 static int ub960_reset(struct ub960_data *priv, bool reset_regs) 1237 { 1238 struct device *dev = &priv->client->dev; 1239 unsigned int v; 1240 int ret; 1241 u8 bit; 1242 1243 bit = reset_regs ? UB960_SR_RESET_DIGITAL_RESET1 : 1244 UB960_SR_RESET_DIGITAL_RESET0; 1245 1246 ret = ub960_write(priv, UB960_SR_RESET, bit, NULL); 1247 if (ret) 1248 return ret; 1249 1250 mutex_lock(&priv->reg_lock); 1251 1252 ret = regmap_read_poll_timeout(priv->regmap, UB960_SR_RESET, v, 1253 (v & bit) == 0, 2000, 100000); 1254 1255 mutex_unlock(&priv->reg_lock); 1256 1257 if (ret) 1258 dev_err(dev, "reset failed: %d\n", ret); 1259 1260 return ret; 1261 } 1262 1263 /* ----------------------------------------------------------------------------- 1264 * I2C-ATR (address translator) 1265 */ 1266 1267 static int ub960_atr_attach_client(struct i2c_atr *atr, u32 chan_id, 1268 const struct i2c_client *client, u16 alias) 1269 { 1270 struct ub960_data *priv = i2c_atr_get_driver_data(atr); 1271 struct ub960_rxport *rxport = priv->rxports[chan_id]; 1272 struct device *dev = &priv->client->dev; 1273 unsigned int reg_idx; 1274 int ret = 0; 1275 1276 for (reg_idx = 0; reg_idx < ARRAY_SIZE(rxport->aliased_clients); reg_idx++) { 1277 if (!rxport->aliased_clients[reg_idx]) 1278 break; 1279 } 1280 1281 if (reg_idx == ARRAY_SIZE(rxport->aliased_clients)) { 1282 dev_err(dev, "rx%u: alias pool exhausted\n", rxport->nport); 1283 return -EADDRNOTAVAIL; 1284 } 1285 1286 rxport->aliased_clients[reg_idx] = client; 1287 1288 ub960_rxport_write(priv, chan_id, UB960_RR_SLAVE_ID(reg_idx), 1289 client->addr << 1, &ret); 1290 ub960_rxport_write(priv, chan_id, UB960_RR_SLAVE_ALIAS(reg_idx), 1291 alias << 1, &ret); 1292 1293 if (ret) 1294 return ret; 1295 1296 dev_dbg(dev, "rx%u: client 0x%02x assigned alias 0x%02x at slot %u\n", 1297 rxport->nport, client->addr, alias, reg_idx); 1298 1299 return 0; 1300 } 1301 1302 static void ub960_atr_detach_client(struct i2c_atr *atr, u32 chan_id, 1303 const struct i2c_client *client) 1304 { 1305 struct ub960_data *priv = i2c_atr_get_driver_data(atr); 1306 struct ub960_rxport *rxport = priv->rxports[chan_id]; 1307 struct device *dev = &priv->client->dev; 1308 unsigned int reg_idx; 1309 int ret; 1310 1311 for (reg_idx = 0; reg_idx < ARRAY_SIZE(rxport->aliased_clients); reg_idx++) { 1312 if (rxport->aliased_clients[reg_idx] == client) 1313 break; 1314 } 1315 1316 if (reg_idx == ARRAY_SIZE(rxport->aliased_clients)) { 1317 dev_err(dev, "rx%u: client 0x%02x is not mapped!\n", 1318 rxport->nport, client->addr); 1319 return; 1320 } 1321 1322 rxport->aliased_clients[reg_idx] = NULL; 1323 1324 ret = ub960_rxport_write(priv, chan_id, UB960_RR_SLAVE_ALIAS(reg_idx), 1325 0, NULL); 1326 if (ret) { 1327 dev_err(dev, "rx%u: unable to fully unmap client 0x%02x: %d\n", 1328 rxport->nport, client->addr, ret); 1329 return; 1330 } 1331 1332 dev_dbg(dev, "rx%u: client 0x%02x released at slot %u\n", rxport->nport, 1333 client->addr, reg_idx); 1334 } 1335 1336 static const struct i2c_atr_ops ub960_atr_ops = { 1337 .attach_client = ub960_atr_attach_client, 1338 .detach_client = ub960_atr_detach_client, 1339 }; 1340 1341 static int ub960_init_atr(struct ub960_data *priv) 1342 { 1343 struct device *dev = &priv->client->dev; 1344 struct i2c_adapter *parent_adap = priv->client->adapter; 1345 1346 priv->atr = i2c_atr_new(parent_adap, dev, &ub960_atr_ops, 1347 priv->hw_data->num_rxports); 1348 if (IS_ERR(priv->atr)) 1349 return PTR_ERR(priv->atr); 1350 1351 i2c_atr_set_driver_data(priv->atr, priv); 1352 1353 return 0; 1354 } 1355 1356 static void ub960_uninit_atr(struct ub960_data *priv) 1357 { 1358 i2c_atr_delete(priv->atr); 1359 priv->atr = NULL; 1360 } 1361 1362 /* ----------------------------------------------------------------------------- 1363 * TX ports 1364 */ 1365 1366 static int ub960_parse_dt_txport(struct ub960_data *priv, 1367 struct fwnode_handle *ep_fwnode, 1368 u8 nport) 1369 { 1370 struct device *dev = &priv->client->dev; 1371 struct v4l2_fwnode_endpoint vep = {}; 1372 struct ub960_txport *txport; 1373 int ret; 1374 1375 txport = kzalloc(sizeof(*txport), GFP_KERNEL); 1376 if (!txport) 1377 return -ENOMEM; 1378 1379 txport->priv = priv; 1380 txport->nport = nport; 1381 1382 vep.bus_type = V4L2_MBUS_CSI2_DPHY; 1383 ret = v4l2_fwnode_endpoint_alloc_parse(ep_fwnode, &vep); 1384 if (ret) { 1385 dev_err(dev, "tx%u: failed to parse endpoint data\n", nport); 1386 goto err_free_txport; 1387 } 1388 1389 txport->non_continous_clk = vep.bus.mipi_csi2.flags & 1390 V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK; 1391 1392 txport->num_data_lanes = vep.bus.mipi_csi2.num_data_lanes; 1393 1394 if (vep.nr_of_link_frequencies != 1) { 1395 ret = -EINVAL; 1396 goto err_free_vep; 1397 } 1398 1399 priv->tx_link_freq[0] = vep.link_frequencies[0]; 1400 priv->tx_data_rate = priv->tx_link_freq[0] * 2; 1401 1402 if (priv->tx_data_rate != MHZ(1600) && 1403 priv->tx_data_rate != MHZ(1200) && 1404 priv->tx_data_rate != MHZ(800) && 1405 priv->tx_data_rate != MHZ(400)) { 1406 dev_err(dev, "tx%u: invalid 'link-frequencies' value\n", nport); 1407 ret = -EINVAL; 1408 goto err_free_vep; 1409 } 1410 1411 v4l2_fwnode_endpoint_free(&vep); 1412 1413 priv->txports[nport] = txport; 1414 1415 return 0; 1416 1417 err_free_vep: 1418 v4l2_fwnode_endpoint_free(&vep); 1419 err_free_txport: 1420 kfree(txport); 1421 1422 return ret; 1423 } 1424 1425 static int ub960_csi_handle_events(struct ub960_data *priv, u8 nport) 1426 { 1427 struct device *dev = &priv->client->dev; 1428 u8 csi_tx_isr; 1429 int ret; 1430 1431 ret = ub960_txport_read(priv, nport, UB960_TR_CSI_TX_ISR, &csi_tx_isr, 1432 NULL); 1433 if (ret) 1434 return ret; 1435 1436 if (csi_tx_isr & UB960_TR_CSI_TX_ISR_IS_CSI_SYNC_ERROR) 1437 dev_warn(dev, "TX%u: CSI_SYNC_ERROR\n", nport); 1438 1439 if (csi_tx_isr & UB960_TR_CSI_TX_ISR_IS_CSI_PASS_ERROR) 1440 dev_warn(dev, "TX%u: CSI_PASS_ERROR\n", nport); 1441 1442 return 0; 1443 } 1444 1445 /* ----------------------------------------------------------------------------- 1446 * RX ports 1447 */ 1448 1449 static int ub960_rxport_enable_vpocs(struct ub960_data *priv) 1450 { 1451 unsigned int failed_nport; 1452 int ret; 1453 1454 for_each_active_rxport(priv, it) { 1455 if (!it.rxport->vpoc) 1456 continue; 1457 1458 ret = regulator_enable(it.rxport->vpoc); 1459 if (ret) { 1460 failed_nport = it.nport; 1461 goto err_disable_vpocs; 1462 } 1463 } 1464 1465 return 0; 1466 1467 err_disable_vpocs: 1468 while (failed_nport--) { 1469 struct ub960_rxport *rxport = priv->rxports[failed_nport]; 1470 1471 if (!rxport || !rxport->vpoc) 1472 continue; 1473 1474 regulator_disable(rxport->vpoc); 1475 } 1476 1477 return ret; 1478 } 1479 1480 static void ub960_rxport_disable_vpocs(struct ub960_data *priv) 1481 { 1482 for_each_active_rxport(priv, it) { 1483 if (!it.rxport->vpoc) 1484 continue; 1485 1486 regulator_disable(it.rxport->vpoc); 1487 } 1488 } 1489 1490 static int ub960_rxport_clear_errors(struct ub960_data *priv, 1491 unsigned int nport) 1492 { 1493 int ret = 0; 1494 u8 v; 1495 1496 ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS1, &v, &ret); 1497 ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS2, &v, &ret); 1498 ub960_rxport_read(priv, nport, UB960_RR_CSI_RX_STS, &v, &ret); 1499 ub960_rxport_read(priv, nport, UB960_RR_BCC_STATUS, &v, &ret); 1500 1501 ub960_rxport_read(priv, nport, UB960_RR_RX_PAR_ERR_HI, &v, &ret); 1502 ub960_rxport_read(priv, nport, UB960_RR_RX_PAR_ERR_LO, &v, &ret); 1503 1504 ub960_rxport_read(priv, nport, UB960_RR_CSI_ERR_COUNTER, &v, &ret); 1505 1506 return ret; 1507 } 1508 1509 static int ub960_clear_rx_errors(struct ub960_data *priv) 1510 { 1511 int ret; 1512 1513 for_each_rxport(priv, it) { 1514 ret = ub960_rxport_clear_errors(priv, it.nport); 1515 if (ret) 1516 return ret; 1517 } 1518 1519 return 0; 1520 } 1521 1522 static int ub960_rxport_get_strobe_pos(struct ub960_data *priv, 1523 unsigned int nport, s8 *strobe_pos) 1524 { 1525 u8 v; 1526 u8 clk_delay, data_delay; 1527 int ret; 1528 1529 ret = ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 1530 UB960_IR_RX_ANA_STROBE_SET_CLK, &v, NULL); 1531 if (ret) 1532 return ret; 1533 1534 clk_delay = (v & UB960_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY) ? 1535 0 : UB960_MANUAL_STROBE_EXTRA_DELAY; 1536 1537 ret = ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 1538 UB960_IR_RX_ANA_STROBE_SET_DATA, &v, NULL); 1539 if (ret) 1540 return ret; 1541 1542 data_delay = (v & UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY) ? 1543 0 : UB960_MANUAL_STROBE_EXTRA_DELAY; 1544 1545 ret = ub960_rxport_read(priv, nport, UB960_RR_SFILTER_STS_0, &v, NULL); 1546 if (ret) 1547 return ret; 1548 1549 clk_delay += v & UB960_IR_RX_ANA_STROBE_SET_CLK_DELAY_MASK; 1550 1551 ret = ub960_rxport_read(priv, nport, UB960_RR_SFILTER_STS_1, &v, NULL); 1552 if (ret) 1553 return ret; 1554 1555 data_delay += v & UB960_IR_RX_ANA_STROBE_SET_DATA_DELAY_MASK; 1556 1557 *strobe_pos = data_delay - clk_delay; 1558 1559 return 0; 1560 } 1561 1562 static int ub960_rxport_set_strobe_pos(struct ub960_data *priv, 1563 unsigned int nport, s8 strobe_pos) 1564 { 1565 u8 clk_delay, data_delay; 1566 int ret = 0; 1567 1568 clk_delay = UB960_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY; 1569 data_delay = UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY; 1570 1571 if (strobe_pos < UB960_MIN_AEQ_STROBE_POS) 1572 clk_delay = abs(strobe_pos) - UB960_MANUAL_STROBE_EXTRA_DELAY; 1573 else if (strobe_pos > UB960_MAX_AEQ_STROBE_POS) 1574 data_delay = strobe_pos - UB960_MANUAL_STROBE_EXTRA_DELAY; 1575 else if (strobe_pos < 0) 1576 clk_delay = abs(strobe_pos) | UB960_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY; 1577 else if (strobe_pos > 0) 1578 data_delay = strobe_pos | UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY; 1579 1580 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 1581 UB960_IR_RX_ANA_STROBE_SET_CLK, clk_delay, &ret); 1582 1583 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 1584 UB960_IR_RX_ANA_STROBE_SET_DATA, data_delay, &ret); 1585 1586 return ret; 1587 } 1588 1589 static int ub960_rxport_set_strobe_range(struct ub960_data *priv, s8 strobe_min, 1590 s8 strobe_max) 1591 { 1592 /* Convert the signed strobe pos to positive zero based value */ 1593 strobe_min -= UB960_MIN_AEQ_STROBE_POS; 1594 strobe_max -= UB960_MIN_AEQ_STROBE_POS; 1595 1596 return ub960_write(priv, UB960_XR_SFILTER_CFG, 1597 ((u8)strobe_min << UB960_XR_SFILTER_CFG_SFILTER_MIN_SHIFT) | 1598 ((u8)strobe_max << UB960_XR_SFILTER_CFG_SFILTER_MAX_SHIFT), 1599 NULL); 1600 } 1601 1602 static int ub960_rxport_get_eq_level(struct ub960_data *priv, 1603 unsigned int nport, u8 *eq_level) 1604 { 1605 int ret; 1606 u8 v; 1607 1608 ret = ub960_rxport_read(priv, nport, UB960_RR_AEQ_STATUS, &v, NULL); 1609 if (ret) 1610 return ret; 1611 1612 *eq_level = (v & UB960_RR_AEQ_STATUS_STATUS_1) + 1613 (v & UB960_RR_AEQ_STATUS_STATUS_2); 1614 1615 return 0; 1616 } 1617 1618 static int ub960_rxport_set_eq_level(struct ub960_data *priv, 1619 unsigned int nport, u8 eq_level) 1620 { 1621 u8 eq_stage_1_select_value, eq_stage_2_select_value; 1622 const unsigned int eq_stage_max = 7; 1623 int ret; 1624 u8 v; 1625 1626 if (eq_level <= eq_stage_max) { 1627 eq_stage_1_select_value = eq_level; 1628 eq_stage_2_select_value = 0; 1629 } else { 1630 eq_stage_1_select_value = eq_stage_max; 1631 eq_stage_2_select_value = eq_level - eq_stage_max; 1632 } 1633 1634 ret = ub960_rxport_read(priv, nport, UB960_RR_AEQ_BYPASS, &v, NULL); 1635 if (ret) 1636 return ret; 1637 1638 v &= ~(UB960_RR_AEQ_BYPASS_EQ_STAGE1_VALUE_MASK | 1639 UB960_RR_AEQ_BYPASS_EQ_STAGE2_VALUE_MASK); 1640 v |= eq_stage_1_select_value << UB960_RR_AEQ_BYPASS_EQ_STAGE1_VALUE_SHIFT; 1641 v |= eq_stage_2_select_value << UB960_RR_AEQ_BYPASS_EQ_STAGE2_VALUE_SHIFT; 1642 v |= UB960_RR_AEQ_BYPASS_ENABLE; 1643 1644 ret = ub960_rxport_write(priv, nport, UB960_RR_AEQ_BYPASS, v, NULL); 1645 if (ret) 1646 return ret; 1647 1648 return 0; 1649 } 1650 1651 static int ub960_rxport_set_eq_range(struct ub960_data *priv, 1652 unsigned int nport, u8 eq_min, u8 eq_max) 1653 { 1654 int ret = 0; 1655 1656 ub960_rxport_write(priv, nport, UB960_RR_AEQ_MIN_MAX, 1657 (eq_min << UB960_RR_AEQ_MIN_MAX_AEQ_FLOOR_SHIFT) | 1658 (eq_max << UB960_RR_AEQ_MIN_MAX_AEQ_MAX_SHIFT), 1659 &ret); 1660 1661 /* Enable AEQ min setting */ 1662 ub960_rxport_update_bits(priv, nport, UB960_RR_AEQ_CTL2, 1663 UB960_RR_AEQ_CTL2_SET_AEQ_FLOOR, 1664 UB960_RR_AEQ_CTL2_SET_AEQ_FLOOR, &ret); 1665 1666 return ret; 1667 } 1668 1669 static int ub960_rxport_config_eq(struct ub960_data *priv, unsigned int nport) 1670 { 1671 struct ub960_rxport *rxport = priv->rxports[nport]; 1672 int ret; 1673 1674 /* We also set common settings here. Should be moved elsewhere. */ 1675 1676 if (priv->strobe.manual) { 1677 /* Disable AEQ_SFILTER_EN */ 1678 ret = ub960_update_bits(priv, UB960_XR_AEQ_CTL1, 1679 UB960_XR_AEQ_CTL1_AEQ_SFILTER_EN, 0, 1680 NULL); 1681 if (ret) 1682 return ret; 1683 } else { 1684 /* Enable SFILTER and error control */ 1685 ret = ub960_write(priv, UB960_XR_AEQ_CTL1, 1686 UB960_XR_AEQ_CTL1_AEQ_ERR_CTL_MASK | 1687 UB960_XR_AEQ_CTL1_AEQ_SFILTER_EN, 1688 NULL); 1689 1690 if (ret) 1691 return ret; 1692 1693 /* Set AEQ strobe range */ 1694 ret = ub960_rxport_set_strobe_range(priv, priv->strobe.min, 1695 priv->strobe.max); 1696 if (ret) 1697 return ret; 1698 } 1699 1700 /* The rest are port specific */ 1701 1702 if (priv->strobe.manual) 1703 ret = ub960_rxport_set_strobe_pos(priv, nport, 1704 rxport->eq.strobe_pos); 1705 else 1706 ret = ub960_rxport_set_strobe_pos(priv, nport, 0); 1707 1708 if (ret) 1709 return ret; 1710 1711 if (rxport->eq.manual_eq) { 1712 ret = ub960_rxport_set_eq_level(priv, nport, 1713 rxport->eq.manual.eq_level); 1714 if (ret) 1715 return ret; 1716 1717 /* Enable AEQ Bypass */ 1718 ret = ub960_rxport_update_bits(priv, nport, UB960_RR_AEQ_BYPASS, 1719 UB960_RR_AEQ_BYPASS_ENABLE, 1720 UB960_RR_AEQ_BYPASS_ENABLE, 1721 NULL); 1722 if (ret) 1723 return ret; 1724 } else { 1725 ret = ub960_rxport_set_eq_range(priv, nport, 1726 rxport->eq.aeq.eq_level_min, 1727 rxport->eq.aeq.eq_level_max); 1728 if (ret) 1729 return ret; 1730 1731 /* Disable AEQ Bypass */ 1732 ret = ub960_rxport_update_bits(priv, nport, UB960_RR_AEQ_BYPASS, 1733 UB960_RR_AEQ_BYPASS_ENABLE, 0, 1734 NULL); 1735 if (ret) 1736 return ret; 1737 } 1738 1739 return 0; 1740 } 1741 1742 static int ub960_rxport_link_ok(struct ub960_data *priv, unsigned int nport, 1743 bool *ok) 1744 { 1745 u8 rx_port_sts1, rx_port_sts2; 1746 u16 parity_errors; 1747 u8 csi_rx_sts; 1748 u8 csi_err_cnt; 1749 u8 bcc_sts; 1750 int ret; 1751 bool errors; 1752 1753 ret = ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS1, 1754 &rx_port_sts1, NULL); 1755 if (ret) 1756 return ret; 1757 1758 if (!(rx_port_sts1 & UB960_RR_RX_PORT_STS1_LOCK_STS)) { 1759 *ok = false; 1760 return 0; 1761 } 1762 1763 ret = ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS2, 1764 &rx_port_sts2, NULL); 1765 if (ret) 1766 return ret; 1767 1768 ret = ub960_rxport_read(priv, nport, UB960_RR_CSI_RX_STS, &csi_rx_sts, 1769 NULL); 1770 if (ret) 1771 return ret; 1772 1773 ret = ub960_rxport_read(priv, nport, UB960_RR_CSI_ERR_COUNTER, 1774 &csi_err_cnt, NULL); 1775 if (ret) 1776 return ret; 1777 1778 ret = ub960_rxport_read(priv, nport, UB960_RR_BCC_STATUS, &bcc_sts, 1779 NULL); 1780 if (ret) 1781 return ret; 1782 1783 ret = ub960_rxport_read16(priv, nport, UB960_RR_RX_PAR_ERR_HI, 1784 &parity_errors, NULL); 1785 if (ret) 1786 return ret; 1787 1788 errors = (rx_port_sts1 & UB960_RR_RX_PORT_STS1_ERROR_MASK) || 1789 (rx_port_sts2 & UB960_RR_RX_PORT_STS2_ERROR_MASK) || 1790 (bcc_sts & UB960_RR_BCC_STATUS_ERROR_MASK) || 1791 (csi_rx_sts & UB960_RR_CSI_RX_STS_ERROR_MASK) || csi_err_cnt || 1792 parity_errors; 1793 1794 *ok = !errors; 1795 1796 return 0; 1797 } 1798 1799 static int ub960_rxport_lockup_wa_ub9702(struct ub960_data *priv) 1800 { 1801 int ret; 1802 1803 /* Toggle PI_MODE to avoid possible FPD RX lockup */ 1804 1805 ret = ub960_update_bits(priv, UB9702_RR_CHANNEL_MODE, GENMASK(4, 3), 1806 2 << 3, NULL); 1807 if (ret) 1808 return ret; 1809 1810 usleep_range(1000, 5000); 1811 1812 return ub960_update_bits(priv, UB9702_RR_CHANNEL_MODE, GENMASK(4, 3), 1813 0, NULL); 1814 } 1815 1816 /* 1817 * Wait for the RX ports to lock, have no errors and have stable strobe position 1818 * and EQ level. 1819 */ 1820 static int ub960_rxport_wait_locks(struct ub960_data *priv, 1821 unsigned long port_mask, 1822 unsigned int *lock_mask) 1823 { 1824 struct device *dev = &priv->client->dev; 1825 unsigned long timeout; 1826 unsigned int link_ok_mask; 1827 unsigned int missing; 1828 unsigned int loops; 1829 u8 nport; 1830 int ret; 1831 1832 if (port_mask == 0) { 1833 if (lock_mask) 1834 *lock_mask = 0; 1835 return 0; 1836 } 1837 1838 if (port_mask >= BIT(priv->hw_data->num_rxports)) 1839 return -EINVAL; 1840 1841 timeout = jiffies + msecs_to_jiffies(1000); 1842 loops = 0; 1843 link_ok_mask = 0; 1844 1845 while (time_before(jiffies, timeout)) { 1846 bool fpd4_wa = false; 1847 missing = 0; 1848 1849 for_each_set_bit(nport, &port_mask, 1850 priv->hw_data->num_rxports) { 1851 struct ub960_rxport *rxport = priv->rxports[nport]; 1852 bool ok; 1853 1854 if (!rxport) 1855 continue; 1856 1857 ret = ub960_rxport_link_ok(priv, nport, &ok); 1858 if (ret) 1859 return ret; 1860 1861 if (!ok && rxport->cdr_mode == RXPORT_CDR_FPD4) 1862 fpd4_wa = true; 1863 1864 /* 1865 * We want the link to be ok for two consecutive loops, 1866 * as a link could get established just before our test 1867 * and drop soon after. 1868 */ 1869 if (!ok || !(link_ok_mask & BIT(nport))) 1870 missing++; 1871 1872 if (ok) 1873 link_ok_mask |= BIT(nport); 1874 else 1875 link_ok_mask &= ~BIT(nport); 1876 } 1877 1878 loops++; 1879 1880 if (missing == 0) 1881 break; 1882 1883 if (fpd4_wa) { 1884 ret = ub960_rxport_lockup_wa_ub9702(priv); 1885 if (ret) 1886 return ret; 1887 } 1888 1889 /* 1890 * The sleep time of 10 ms was found by testing to give a lock 1891 * with a few iterations. It can be decreased if on some setups 1892 * the lock can be achieved much faster. 1893 */ 1894 fsleep(10 * USEC_PER_MSEC); 1895 } 1896 1897 if (lock_mask) 1898 *lock_mask = link_ok_mask; 1899 1900 dev_dbg(dev, "Wait locks done in %u loops\n", loops); 1901 for_each_set_bit(nport, &port_mask, priv->hw_data->num_rxports) { 1902 struct ub960_rxport *rxport = priv->rxports[nport]; 1903 s8 strobe_pos, eq_level; 1904 u16 v; 1905 1906 if (!rxport) 1907 continue; 1908 1909 if (!(link_ok_mask & BIT(nport))) { 1910 dev_dbg(dev, "\trx%u: not locked\n", nport); 1911 continue; 1912 } 1913 1914 ret = ub960_rxport_read16(priv, nport, UB960_RR_RX_FREQ_HIGH, 1915 &v, NULL); 1916 1917 if (ret) 1918 return ret; 1919 1920 if (priv->hw_data->is_ub9702) { 1921 dev_dbg(dev, "\trx%u: locked, freq %llu Hz\n", 1922 nport, ((u64)v * HZ_PER_MHZ) >> 8); 1923 } else { 1924 ret = ub960_rxport_get_strobe_pos(priv, nport, 1925 &strobe_pos); 1926 if (ret) 1927 return ret; 1928 1929 ret = ub960_rxport_get_eq_level(priv, nport, &eq_level); 1930 if (ret) 1931 return ret; 1932 1933 dev_dbg(dev, 1934 "\trx%u: locked, SP: %d, EQ: %u, freq %llu Hz\n", 1935 nport, strobe_pos, eq_level, 1936 ((u64)v * HZ_PER_MHZ) >> 8); 1937 } 1938 } 1939 1940 return 0; 1941 } 1942 1943 static unsigned long ub960_calc_bc_clk_rate_ub960(struct ub960_data *priv, 1944 struct ub960_rxport *rxport) 1945 { 1946 unsigned int mult; 1947 unsigned int div; 1948 1949 switch (rxport->rx_mode) { 1950 case RXPORT_MODE_RAW10: 1951 case RXPORT_MODE_RAW12_HF: 1952 case RXPORT_MODE_RAW12_LF: 1953 mult = 1; 1954 div = 10; 1955 break; 1956 1957 case RXPORT_MODE_CSI2_SYNC: 1958 mult = 2; 1959 div = 1; 1960 break; 1961 1962 case RXPORT_MODE_CSI2_NONSYNC: 1963 mult = 2; 1964 div = 5; 1965 break; 1966 1967 default: 1968 return 0; 1969 } 1970 1971 return clk_get_rate(priv->refclk) * mult / div; 1972 } 1973 1974 static unsigned long ub960_calc_bc_clk_rate_ub9702(struct ub960_data *priv, 1975 struct ub960_rxport *rxport) 1976 { 1977 switch (rxport->rx_mode) { 1978 case RXPORT_MODE_RAW10: 1979 case RXPORT_MODE_RAW12_HF: 1980 case RXPORT_MODE_RAW12_LF: 1981 return 2359400; 1982 1983 case RXPORT_MODE_CSI2_SYNC: 1984 return 47187500; 1985 1986 case RXPORT_MODE_CSI2_NONSYNC: 1987 return 9437500; 1988 1989 default: 1990 return 0; 1991 } 1992 } 1993 1994 static int ub960_rxport_serializer_write(struct ub960_rxport *rxport, u8 reg, 1995 u8 val, int *err) 1996 { 1997 struct ub960_data *priv = rxport->priv; 1998 struct device *dev = &priv->client->dev; 1999 union i2c_smbus_data data; 2000 int ret; 2001 2002 if (err && *err) 2003 return *err; 2004 2005 data.byte = val; 2006 2007 ret = i2c_smbus_xfer(priv->client->adapter, rxport->ser.alias, 0, 2008 I2C_SMBUS_WRITE, reg, I2C_SMBUS_BYTE_DATA, &data); 2009 if (ret) 2010 dev_err(dev, 2011 "rx%u: cannot write serializer register 0x%02x (%d)!\n", 2012 rxport->nport, reg, ret); 2013 2014 if (ret && err) 2015 *err = ret; 2016 2017 return ret; 2018 } 2019 2020 static int ub960_rxport_serializer_read(struct ub960_rxport *rxport, u8 reg, 2021 u8 *val, int *err) 2022 { 2023 struct ub960_data *priv = rxport->priv; 2024 struct device *dev = &priv->client->dev; 2025 union i2c_smbus_data data = { 0 }; 2026 int ret; 2027 2028 if (err && *err) 2029 return *err; 2030 2031 ret = i2c_smbus_xfer(priv->client->adapter, rxport->ser.alias, 2032 priv->client->flags, I2C_SMBUS_READ, reg, 2033 I2C_SMBUS_BYTE_DATA, &data); 2034 if (ret) 2035 dev_err(dev, 2036 "rx%u: cannot read serializer register 0x%02x (%d)!\n", 2037 rxport->nport, reg, ret); 2038 else 2039 *val = data.byte; 2040 2041 if (ret && err) 2042 *err = ret; 2043 2044 return ret; 2045 } 2046 2047 static int ub960_serializer_temp_ramp(struct ub960_rxport *rxport) 2048 { 2049 struct ub960_data *priv = rxport->priv; 2050 short temp_dynamic_offset[] = {-1, -1, 0, 0, 1, 1, 1, 3}; 2051 u8 temp_dynamic_cfg; 2052 u8 nport = rxport->nport; 2053 u8 ser_temp_code; 2054 int ret = 0; 2055 2056 /* Configure temp ramp only on UB953 */ 2057 if (!fwnode_device_is_compatible(rxport->ser.fwnode, "ti,ds90ub953-q1")) 2058 return 0; 2059 2060 /* Read current serializer die temperature */ 2061 ub960_rxport_read(priv, nport, UB960_RR_SENSOR_STS_2, &ser_temp_code, 2062 &ret); 2063 2064 /* Enable I2C passthrough on back channel */ 2065 ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG, 2066 UB960_RR_BCC_CONFIG_I2C_PASS_THROUGH, 2067 UB960_RR_BCC_CONFIG_I2C_PASS_THROUGH, &ret); 2068 2069 if (ret) 2070 return ret; 2071 2072 /* Select indirect page for analog regs on the serializer */ 2073 ub960_rxport_serializer_write(rxport, UB953_REG_IND_ACC_CTL, 2074 UB953_IND_TARGET_ANALOG << 2, &ret); 2075 2076 /* Set temperature ramp dynamic and static config */ 2077 ub960_rxport_serializer_write(rxport, UB953_REG_IND_ACC_ADDR, 2078 UB953_IND_ANA_TEMP_DYNAMIC_CFG, &ret); 2079 ub960_rxport_serializer_read(rxport, UB953_REG_IND_ACC_DATA, 2080 &temp_dynamic_cfg, &ret); 2081 2082 if (ret) 2083 return ret; 2084 2085 temp_dynamic_cfg |= UB953_IND_ANA_TEMP_DYNAMIC_CFG_OV; 2086 temp_dynamic_cfg += temp_dynamic_offset[ser_temp_code]; 2087 2088 /* Update temp static config */ 2089 ub960_rxport_serializer_write(rxport, UB953_REG_IND_ACC_ADDR, 2090 UB953_IND_ANA_TEMP_STATIC_CFG, &ret); 2091 ub960_rxport_serializer_write(rxport, UB953_REG_IND_ACC_DATA, 2092 UB953_IND_ANA_TEMP_STATIC_CFG_MASK, &ret); 2093 2094 /* Update temperature ramp dynamic config */ 2095 ub960_rxport_serializer_write(rxport, UB953_REG_IND_ACC_ADDR, 2096 UB953_IND_ANA_TEMP_DYNAMIC_CFG, &ret); 2097 2098 /* Enable I2C auto ack on BC before we set dynamic cfg and reset */ 2099 ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG, 2100 UB960_RR_BCC_CONFIG_AUTO_ACK_ALL, 2101 UB960_RR_BCC_CONFIG_AUTO_ACK_ALL, &ret); 2102 2103 ub960_rxport_serializer_write(rxport, UB953_REG_IND_ACC_DATA, 2104 temp_dynamic_cfg, &ret); 2105 2106 if (ret) 2107 return ret; 2108 2109 /* Soft reset to apply PLL updates */ 2110 ub960_rxport_serializer_write(rxport, UB953_REG_RESET_CTL, 2111 UB953_REG_RESET_CTL_DIGITAL_RESET_0, 2112 &ret); 2113 msleep(20); 2114 2115 /* Disable I2C passthrough and auto-ack on BC */ 2116 ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG, 2117 UB960_RR_BCC_CONFIG_I2C_PASS_THROUGH | 2118 UB960_RR_BCC_CONFIG_AUTO_ACK_ALL, 2119 0x0, &ret); 2120 2121 return ret; 2122 } 2123 2124 static int ub960_rxport_bc_ser_config(struct ub960_rxport *rxport) 2125 { 2126 struct ub960_data *priv = rxport->priv; 2127 struct device *dev = &priv->client->dev; 2128 u8 nport = rxport->nport; 2129 int ret = 0; 2130 2131 /* Skip port if serializer's address is not known */ 2132 if (rxport->ser.addr < 0) { 2133 dev_dbg(dev, 2134 "rx%u: serializer address missing, skip configuration\n", 2135 nport); 2136 return 0; 2137 } 2138 2139 /* 2140 * Note: the code here probably only works for CSI-2 serializers in 2141 * sync mode. To support other serializers the BC related configuration 2142 * should be done before calling this function. 2143 */ 2144 2145 /* Enable I2C passthrough and auto-ack on BC */ 2146 ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG, 2147 UB960_RR_BCC_CONFIG_I2C_PASS_THROUGH | 2148 UB960_RR_BCC_CONFIG_AUTO_ACK_ALL, 2149 UB960_RR_BCC_CONFIG_I2C_PASS_THROUGH | 2150 UB960_RR_BCC_CONFIG_AUTO_ACK_ALL, 2151 &ret); 2152 2153 if (ret) 2154 return ret; 2155 2156 /* Disable BC alternate mode auto detect */ 2157 ub960_rxport_serializer_write(rxport, UB971_ENH_BC_CHK, 0x02, &ret); 2158 /* Decrease link detect timer */ 2159 ub960_rxport_serializer_write(rxport, UB953_REG_BC_CTRL, 0x06, &ret); 2160 2161 /* Disable I2C passthrough and auto-ack on BC */ 2162 ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG, 2163 UB960_RR_BCC_CONFIG_I2C_PASS_THROUGH | 2164 UB960_RR_BCC_CONFIG_AUTO_ACK_ALL, 2165 0x0, &ret); 2166 2167 return ret; 2168 } 2169 2170 static int ub960_rxport_add_serializer(struct ub960_data *priv, u8 nport) 2171 { 2172 struct ub960_rxport *rxport = priv->rxports[nport]; 2173 struct device *dev = &priv->client->dev; 2174 struct ds90ub9xx_platform_data *ser_pdata = &rxport->ser.pdata; 2175 struct i2c_board_info ser_info = { 2176 .of_node = to_of_node(rxport->ser.fwnode), 2177 .fwnode = rxport->ser.fwnode, 2178 .platform_data = ser_pdata, 2179 }; 2180 2181 ser_pdata->port = nport; 2182 ser_pdata->atr = priv->atr; 2183 if (priv->hw_data->is_ub9702) 2184 ser_pdata->bc_rate = ub960_calc_bc_clk_rate_ub9702(priv, rxport); 2185 else 2186 ser_pdata->bc_rate = ub960_calc_bc_clk_rate_ub960(priv, rxport); 2187 2188 /* 2189 * The serializer is added under the same i2c adapter as the 2190 * deserializer. This is not quite right, as the serializer is behind 2191 * the FPD-Link. 2192 */ 2193 ser_info.addr = rxport->ser.alias; 2194 rxport->ser.client = 2195 i2c_new_client_device(priv->client->adapter, &ser_info); 2196 if (IS_ERR(rxport->ser.client)) { 2197 dev_err(dev, "rx%u: cannot add %s i2c device", nport, 2198 ser_info.type); 2199 return PTR_ERR(rxport->ser.client); 2200 } 2201 2202 dev_dbg(dev, "rx%u: remote serializer at alias 0x%02x (%u-%04x)\n", 2203 nport, rxport->ser.client->addr, 2204 rxport->ser.client->adapter->nr, rxport->ser.client->addr); 2205 2206 return 0; 2207 } 2208 2209 static void ub960_rxport_remove_serializer(struct ub960_data *priv, u8 nport) 2210 { 2211 struct ub960_rxport *rxport = priv->rxports[nport]; 2212 2213 i2c_unregister_device(rxport->ser.client); 2214 rxport->ser.client = NULL; 2215 } 2216 2217 /* Add serializer i2c devices for all initialized ports */ 2218 static int ub960_rxport_add_serializers(struct ub960_data *priv) 2219 { 2220 unsigned int failed_nport; 2221 int ret; 2222 2223 for_each_active_rxport(priv, it) { 2224 ret = ub960_rxport_add_serializer(priv, it.nport); 2225 if (ret) { 2226 failed_nport = it.nport; 2227 goto err_remove_sers; 2228 } 2229 } 2230 2231 return 0; 2232 2233 err_remove_sers: 2234 while (failed_nport--) { 2235 struct ub960_rxport *rxport = priv->rxports[failed_nport]; 2236 2237 if (!rxport) 2238 continue; 2239 2240 ub960_rxport_remove_serializer(priv, failed_nport); 2241 } 2242 2243 return ret; 2244 } 2245 2246 static void ub960_rxport_remove_serializers(struct ub960_data *priv) 2247 { 2248 for_each_active_rxport(priv, it) 2249 ub960_rxport_remove_serializer(priv, it.nport); 2250 } 2251 2252 static int ub960_init_tx_port(struct ub960_data *priv, 2253 struct ub960_txport *txport) 2254 { 2255 unsigned int nport = txport->nport; 2256 u8 csi_ctl = 0; 2257 2258 /* 2259 * From the datasheet: "initial CSI Skew-Calibration 2260 * sequence [...] should be set when operating at 1.6 Gbps" 2261 */ 2262 if (priv->tx_data_rate == MHZ(1600)) 2263 csi_ctl |= UB960_TR_CSI_CTL_CSI_CAL_EN; 2264 2265 csi_ctl |= (4 - txport->num_data_lanes) << 4; 2266 2267 if (!txport->non_continous_clk) 2268 csi_ctl |= UB960_TR_CSI_CTL_CSI_CONTS_CLOCK; 2269 2270 return ub960_txport_write(priv, nport, UB960_TR_CSI_CTL, csi_ctl, NULL); 2271 } 2272 2273 static int ub960_init_tx_ports_ub960(struct ub960_data *priv) 2274 { 2275 u8 speed_select; 2276 2277 switch (priv->tx_data_rate) { 2278 case MHZ(400): 2279 speed_select = 3; 2280 break; 2281 case MHZ(800): 2282 speed_select = 2; 2283 break; 2284 case MHZ(1200): 2285 speed_select = 1; 2286 break; 2287 case MHZ(1600): 2288 default: 2289 speed_select = 0; 2290 break; 2291 } 2292 2293 return ub960_write(priv, UB960_SR_CSI_PLL_CTL, speed_select, NULL); 2294 } 2295 2296 static int ub960_init_tx_ports_ub9702(struct ub960_data *priv) 2297 { 2298 u8 speed_select; 2299 u8 ana_pll_div; 2300 u8 pll_div; 2301 int ret = 0; 2302 2303 switch (priv->tx_data_rate) { 2304 case MHZ(400): 2305 speed_select = 3; 2306 pll_div = 0x10; 2307 ana_pll_div = 0xa2; 2308 break; 2309 case MHZ(800): 2310 speed_select = 2; 2311 pll_div = 0x10; 2312 ana_pll_div = 0x92; 2313 break; 2314 case MHZ(1200): 2315 speed_select = 1; 2316 pll_div = 0x18; 2317 ana_pll_div = 0x90; 2318 break; 2319 case MHZ(1500): 2320 speed_select = 0; 2321 pll_div = 0x0f; 2322 ana_pll_div = 0x82; 2323 break; 2324 case MHZ(1600): 2325 default: 2326 speed_select = 0; 2327 pll_div = 0x10; 2328 ana_pll_div = 0x82; 2329 break; 2330 case MHZ(2500): 2331 speed_select = 0x10; 2332 pll_div = 0x19; 2333 ana_pll_div = 0x80; 2334 break; 2335 } 2336 2337 ub960_write(priv, UB960_SR_CSI_PLL_CTL, speed_select, &ret); 2338 ub960_write(priv, UB9702_SR_CSI_PLL_DIV, pll_div, &ret); 2339 ub960_write_ind(priv, UB960_IND_TARGET_CSI_ANA, 2340 UB9702_IR_CSI_ANA_CSIPLL_REG_1, ana_pll_div, &ret); 2341 2342 return ret; 2343 } 2344 2345 static int ub960_init_tx_ports(struct ub960_data *priv) 2346 { 2347 int ret; 2348 2349 if (priv->hw_data->is_ub9702) 2350 ret = ub960_init_tx_ports_ub9702(priv); 2351 else 2352 ret = ub960_init_tx_ports_ub960(priv); 2353 2354 if (ret) 2355 return ret; 2356 2357 for (unsigned int nport = 0; nport < priv->hw_data->num_txports; 2358 nport++) { 2359 struct ub960_txport *txport = priv->txports[nport]; 2360 2361 if (!txport) 2362 continue; 2363 2364 ret = ub960_init_tx_port(priv, txport); 2365 if (ret) 2366 return ret; 2367 } 2368 2369 return 0; 2370 } 2371 2372 static int ub960_init_rx_port_ub960(struct ub960_data *priv, 2373 struct ub960_rxport *rxport) 2374 { 2375 unsigned int nport = rxport->nport; 2376 u32 bc_freq_val; 2377 int ret = 0; 2378 2379 /* 2380 * Back channel frequency select. 2381 * Override FREQ_SELECT from the strap. 2382 * 0 - 2.5 Mbps (DS90UB913A-Q1 / DS90UB933-Q1) 2383 * 2 - 10 Mbps 2384 * 6 - 50 Mbps (DS90UB953-Q1) 2385 * 2386 * Note that changing this setting will result in some errors on the back 2387 * channel for a short period of time. 2388 */ 2389 2390 switch (rxport->rx_mode) { 2391 case RXPORT_MODE_RAW10: 2392 case RXPORT_MODE_RAW12_HF: 2393 case RXPORT_MODE_RAW12_LF: 2394 bc_freq_val = 0; 2395 break; 2396 2397 case RXPORT_MODE_CSI2_NONSYNC: 2398 bc_freq_val = 2; 2399 break; 2400 2401 case RXPORT_MODE_CSI2_SYNC: 2402 bc_freq_val = 6; 2403 break; 2404 2405 default: 2406 return -EINVAL; 2407 } 2408 2409 ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG, 2410 UB960_RR_BCC_CONFIG_BC_FREQ_SEL_MASK, 2411 bc_freq_val, &ret); 2412 2413 switch (rxport->rx_mode) { 2414 case RXPORT_MODE_RAW10: 2415 /* FPD3_MODE = RAW10 Mode (DS90UB913A-Q1 / DS90UB933-Q1 compatible) */ 2416 ub960_rxport_update_bits(priv, nport, UB960_RR_PORT_CONFIG, 2417 UB960_RR_PORT_CONFIG_FPD3_MODE_MASK, 2418 0x3, &ret); 2419 2420 /* 2421 * RAW10_8BIT_CTL = 0b10 : 8-bit processing using upper 8 bits 2422 */ 2423 ub960_rxport_update_bits(priv, nport, UB960_RR_PORT_CONFIG2, 2424 UB960_RR_PORT_CONFIG2_RAW10_8BIT_CTL_MASK, 2425 0x2 << UB960_RR_PORT_CONFIG2_RAW10_8BIT_CTL_SHIFT, 2426 &ret); 2427 2428 break; 2429 2430 case RXPORT_MODE_RAW12_HF: 2431 case RXPORT_MODE_RAW12_LF: 2432 /* Not implemented */ 2433 return -EINVAL; 2434 2435 case RXPORT_MODE_CSI2_SYNC: 2436 case RXPORT_MODE_CSI2_NONSYNC: 2437 /* CSI-2 Mode (DS90UB953-Q1 compatible) */ 2438 ub960_rxport_update_bits(priv, nport, UB960_RR_PORT_CONFIG, 0x3, 2439 0x0, &ret); 2440 2441 break; 2442 } 2443 2444 /* LV_POLARITY & FV_POLARITY */ 2445 ub960_rxport_update_bits(priv, nport, UB960_RR_PORT_CONFIG2, 0x3, 2446 rxport->lv_fv_pol, &ret); 2447 2448 /* Enable all interrupt sources from this port */ 2449 ub960_rxport_write(priv, nport, UB960_RR_PORT_ICR_HI, 0x07, &ret); 2450 ub960_rxport_write(priv, nport, UB960_RR_PORT_ICR_LO, 0x7f, &ret); 2451 2452 /* Enable I2C_PASS_THROUGH */ 2453 ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG, 2454 UB960_RR_BCC_CONFIG_I2C_PASS_THROUGH, 2455 UB960_RR_BCC_CONFIG_I2C_PASS_THROUGH, &ret); 2456 2457 /* Enable I2C communication to the serializer via the alias addr */ 2458 ub960_rxport_write(priv, nport, UB960_RR_SER_ALIAS_ID, 2459 rxport->ser.alias << 1, &ret); 2460 2461 /* Configure EQ related settings */ 2462 ub960_rxport_config_eq(priv, nport); 2463 2464 /* Enable RX port */ 2465 ub960_update_bits(priv, UB960_SR_RX_PORT_CTL, BIT(nport), BIT(nport), 2466 &ret); 2467 2468 return ret; 2469 } 2470 2471 static int ub960_init_rx_ports_ub960(struct ub960_data *priv) 2472 { 2473 struct device *dev = &priv->client->dev; 2474 unsigned int port_lock_mask; 2475 unsigned int port_mask; 2476 int ret; 2477 2478 for_each_active_rxport(priv, it) { 2479 ret = ub960_init_rx_port_ub960(priv, it.rxport); 2480 if (ret) 2481 return ret; 2482 } 2483 2484 ret = ub960_reset(priv, false); 2485 if (ret) 2486 return ret; 2487 2488 port_mask = 0; 2489 2490 for_each_active_rxport(priv, it) 2491 port_mask |= BIT(it.nport); 2492 2493 ret = ub960_rxport_wait_locks(priv, port_mask, &port_lock_mask); 2494 if (ret) 2495 return ret; 2496 2497 if (port_mask != port_lock_mask) { 2498 ret = -EIO; 2499 dev_err_probe(dev, ret, "Failed to lock all RX ports\n"); 2500 return ret; 2501 } 2502 2503 /* Set temperature ramp on serializer */ 2504 for_each_active_rxport(priv, it) { 2505 ret = ub960_serializer_temp_ramp(it.rxport); 2506 if (ret) 2507 return ret; 2508 2509 ub960_rxport_update_bits(priv, it.nport, UB960_RR_BCC_CONFIG, 2510 UB960_RR_BCC_CONFIG_I2C_PASS_THROUGH, 2511 UB960_RR_BCC_CONFIG_I2C_PASS_THROUGH, 2512 &ret); 2513 if (ret) 2514 return ret; 2515 } 2516 2517 /* 2518 * Clear any errors caused by switching the RX port settings while 2519 * probing. 2520 */ 2521 ret = ub960_clear_rx_errors(priv); 2522 if (ret) 2523 return ret; 2524 2525 return 0; 2526 } 2527 2528 /* 2529 * UB9702 specific initial RX port configuration 2530 */ 2531 2532 static int ub960_turn_off_rxport_ub9702(struct ub960_data *priv, 2533 unsigned int nport) 2534 { 2535 int ret = 0; 2536 2537 /* Disable RX port */ 2538 ub960_update_bits(priv, UB960_SR_RX_PORT_CTL, BIT(nport), 0, &ret); 2539 2540 /* Disable FPD Rx and FPD BC CMR */ 2541 ub960_rxport_write(priv, nport, UB9702_RR_RX_CTL_2, 0x1b, &ret); 2542 2543 /* Disable FPD BC Tx */ 2544 ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG, BIT(4), 0, 2545 &ret); 2546 2547 /* Disable internal RX blocks */ 2548 ub960_rxport_write(priv, nport, UB9702_RR_RX_CTL_1, 0x15, &ret); 2549 2550 /* Disable AEQ */ 2551 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 2552 UB9702_IR_RX_ANA_AEQ_CFG_2, 0x03, &ret); 2553 2554 /* PI disabled and oDAC disabled */ 2555 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 2556 UB9702_IR_RX_ANA_AEQ_CFG_4, 0x09, &ret); 2557 2558 /* AEQ configured for disabled link */ 2559 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 2560 UB9702_IR_RX_ANA_AEQ_CFG_1, 0x20, &ret); 2561 2562 /* disable AEQ clock and DFE */ 2563 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 2564 UB9702_IR_RX_ANA_AEQ_CFG_3, 0x45, &ret); 2565 2566 /* Powerdown FPD3 CDR */ 2567 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 2568 UB9702_IR_RX_ANA_FPD3_CDR_CTRL_SEL_5, 0x82, &ret); 2569 2570 return ret; 2571 } 2572 2573 static int ub960_set_bc_drv_config_ub9702(struct ub960_data *priv, 2574 unsigned int nport) 2575 { 2576 u8 fpd_bc_ctl0; 2577 u8 fpd_bc_ctl1; 2578 u8 fpd_bc_ctl2; 2579 int ret = 0; 2580 2581 if (priv->rxports[nport]->cdr_mode == RXPORT_CDR_FPD4) { 2582 /* Set FPD PBC drv into FPD IV mode */ 2583 2584 fpd_bc_ctl0 = 0; 2585 fpd_bc_ctl1 = 0; 2586 fpd_bc_ctl2 = 0; 2587 } else { 2588 /* Set FPD PBC drv into FPD III mode */ 2589 2590 fpd_bc_ctl0 = 2; 2591 fpd_bc_ctl1 = 1; 2592 fpd_bc_ctl2 = 5; 2593 } 2594 2595 ub960_ind_update_bits(priv, UB960_IND_TARGET_RX_ANA(nport), 2596 UB9702_IR_RX_ANA_FPD_BC_CTL0, GENMASK(7, 5), 2597 fpd_bc_ctl0 << 5, &ret); 2598 2599 ub960_ind_update_bits(priv, UB960_IND_TARGET_RX_ANA(nport), 2600 UB9702_IR_RX_ANA_FPD_BC_CTL1, BIT(6), 2601 fpd_bc_ctl1 << 6, &ret); 2602 2603 ub960_ind_update_bits(priv, UB960_IND_TARGET_RX_ANA(nport), 2604 UB9702_IR_RX_ANA_FPD_BC_CTL2, GENMASK(6, 3), 2605 fpd_bc_ctl2 << 3, &ret); 2606 2607 return ret; 2608 } 2609 2610 static int ub960_set_fpd4_sync_mode_ub9702(struct ub960_data *priv, 2611 unsigned int nport) 2612 { 2613 int ret = 0; 2614 2615 /* FPD4 Sync Mode */ 2616 ub960_rxport_write(priv, nport, UB9702_RR_CHANNEL_MODE, 0x0, &ret); 2617 2618 /* BC_FREQ_SELECT = (PLL_FREQ/3200) Mbps */ 2619 ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG, 2620 UB960_RR_BCC_CONFIG_BC_FREQ_SEL_MASK, 6, &ret); 2621 2622 if (ret) 2623 return ret; 2624 2625 ret = ub960_set_bc_drv_config_ub9702(priv, nport); 2626 if (ret) 2627 return ret; 2628 2629 /* Set AEQ timer to 400us/step */ 2630 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 2631 UB9702_IR_RX_ANA_SYSTEM_INIT_REG0, 0x2f, &ret); 2632 2633 /* Disable FPD4 Auto Recovery */ 2634 ub960_update_bits(priv, UB9702_SR_CSI_EXCLUSIVE_FWD2, GENMASK(5, 4), 0, 2635 &ret); 2636 2637 /* Enable RX port */ 2638 ub960_update_bits(priv, UB960_SR_RX_PORT_CTL, BIT(nport), BIT(nport), 2639 &ret); 2640 2641 /* Enable FPD4 Auto Recovery */ 2642 ub960_update_bits(priv, UB9702_SR_CSI_EXCLUSIVE_FWD2, GENMASK(5, 4), 2643 BIT(4), &ret); 2644 2645 return ret; 2646 } 2647 2648 static int ub960_set_fpd4_async_mode_ub9702(struct ub960_data *priv, 2649 unsigned int nport) 2650 { 2651 int ret = 0; 2652 2653 /* FPD4 ASync Mode */ 2654 ub960_rxport_write(priv, nport, UB9702_RR_CHANNEL_MODE, 0x1, &ret); 2655 2656 /* 10Mbps w/ BC enabled */ 2657 /* BC_FREQ_SELECT=(PLL_FREQ/3200) Mbps */ 2658 ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG, 2659 UB960_RR_BCC_CONFIG_BC_FREQ_SEL_MASK, 2, &ret); 2660 2661 if (ret) 2662 return ret; 2663 2664 ret = ub960_set_bc_drv_config_ub9702(priv, nport); 2665 if (ret) 2666 return ret; 2667 2668 /* Set AEQ timer to 400us/step */ 2669 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 2670 UB9702_IR_RX_ANA_SYSTEM_INIT_REG0, 0x2f, &ret); 2671 2672 /* Disable FPD4 Auto Recover */ 2673 ub960_update_bits(priv, UB9702_SR_CSI_EXCLUSIVE_FWD2, GENMASK(5, 4), 0, 2674 &ret); 2675 2676 /* Enable RX port */ 2677 ub960_update_bits(priv, UB960_SR_RX_PORT_CTL, BIT(nport), BIT(nport), 2678 &ret); 2679 2680 /* Enable FPD4 Auto Recovery */ 2681 ub960_update_bits(priv, UB9702_SR_CSI_EXCLUSIVE_FWD2, GENMASK(5, 4), 2682 BIT(4), &ret); 2683 2684 return ret; 2685 } 2686 2687 static int ub960_set_fpd3_sync_mode_ub9702(struct ub960_data *priv, 2688 unsigned int nport) 2689 { 2690 int ret = 0; 2691 2692 /* FPD3 Sync Mode */ 2693 ub960_rxport_write(priv, nport, UB9702_RR_CHANNEL_MODE, 0x2, &ret); 2694 2695 /* BC_FREQ_SELECT=(PLL_FREQ/3200) Mbps */ 2696 ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG, 2697 UB960_RR_BCC_CONFIG_BC_FREQ_SEL_MASK, 6, &ret); 2698 2699 /* Set AEQ_LOCK_MODE = 1 */ 2700 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 2701 UB9702_IR_RX_ANA_FPD3_AEQ_CTRL_SEL_1, BIT(7), &ret); 2702 2703 if (ret) 2704 return ret; 2705 2706 ret = ub960_set_bc_drv_config_ub9702(priv, nport); 2707 if (ret) 2708 return ret; 2709 2710 /* Enable RX port */ 2711 ub960_update_bits(priv, UB960_SR_RX_PORT_CTL, BIT(nport), BIT(nport), 2712 &ret); 2713 2714 return ret; 2715 } 2716 2717 static int ub960_set_raw10_dvp_mode_ub9702(struct ub960_data *priv, 2718 unsigned int nport) 2719 { 2720 int ret = 0; 2721 2722 /* FPD3 RAW10 Mode */ 2723 ub960_rxport_write(priv, nport, UB9702_RR_CHANNEL_MODE, 0x5, &ret); 2724 2725 ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG, 2726 UB960_RR_BCC_CONFIG_BC_FREQ_SEL_MASK, 0, &ret); 2727 2728 /* Set AEQ_LOCK_MODE = 1 */ 2729 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 2730 UB9702_IR_RX_ANA_FPD3_AEQ_CTRL_SEL_1, BIT(7), &ret); 2731 2732 /* 2733 * RAW10_8BIT_CTL = 0b11 : 8-bit processing using lower 8 bits 2734 * 0b10 : 8-bit processing using upper 8 bits 2735 */ 2736 ub960_rxport_update_bits(priv, nport, UB960_RR_PORT_CONFIG2, 0x3 << 6, 2737 0x2 << 6, &ret); 2738 2739 /* LV_POLARITY & FV_POLARITY */ 2740 ub960_rxport_update_bits(priv, nport, UB960_RR_PORT_CONFIG2, 0x3, 2741 priv->rxports[nport]->lv_fv_pol, &ret); 2742 2743 if (ret) 2744 return ret; 2745 2746 ret = ub960_set_bc_drv_config_ub9702(priv, nport); 2747 if (ret) 2748 return ret; 2749 2750 /* Enable RX port */ 2751 ub960_update_bits(priv, UB960_SR_RX_PORT_CTL, BIT(nport), BIT(nport), 2752 &ret); 2753 2754 return ret; 2755 } 2756 2757 static int ub960_configure_rx_port_ub9702(struct ub960_data *priv, 2758 unsigned int nport) 2759 { 2760 struct device *dev = &priv->client->dev; 2761 struct ub960_rxport *rxport = priv->rxports[nport]; 2762 int ret; 2763 2764 if (!rxport) { 2765 ret = ub960_turn_off_rxport_ub9702(priv, nport); 2766 if (ret) 2767 return ret; 2768 2769 dev_dbg(dev, "rx%u: disabled\n", nport); 2770 return 0; 2771 } 2772 2773 switch (rxport->cdr_mode) { 2774 case RXPORT_CDR_FPD4: 2775 switch (rxport->rx_mode) { 2776 case RXPORT_MODE_CSI2_SYNC: 2777 ret = ub960_set_fpd4_sync_mode_ub9702(priv, nport); 2778 if (ret) 2779 return ret; 2780 2781 dev_dbg(dev, "rx%u: FPD-Link IV SYNC mode\n", nport); 2782 break; 2783 case RXPORT_MODE_CSI2_NONSYNC: 2784 ret = ub960_set_fpd4_async_mode_ub9702(priv, nport); 2785 if (ret) 2786 return ret; 2787 2788 dev_dbg(dev, "rx%u: FPD-Link IV ASYNC mode\n", nport); 2789 break; 2790 default: 2791 dev_err(dev, "rx%u: unsupported FPD4 mode %u\n", nport, 2792 rxport->rx_mode); 2793 return -EINVAL; 2794 } 2795 break; 2796 2797 case RXPORT_CDR_FPD3: 2798 switch (rxport->rx_mode) { 2799 case RXPORT_MODE_CSI2_SYNC: 2800 ret = ub960_set_fpd3_sync_mode_ub9702(priv, nport); 2801 if (ret) 2802 return ret; 2803 2804 dev_dbg(dev, "rx%u: FPD-Link III SYNC mode\n", nport); 2805 break; 2806 case RXPORT_MODE_RAW10: 2807 ret = ub960_set_raw10_dvp_mode_ub9702(priv, nport); 2808 if (ret) 2809 return ret; 2810 2811 dev_dbg(dev, "rx%u: FPD-Link III RAW10 DVP mode\n", 2812 nport); 2813 break; 2814 default: 2815 dev_err(&priv->client->dev, 2816 "rx%u: unsupported FPD3 mode %u\n", nport, 2817 rxport->rx_mode); 2818 return -EINVAL; 2819 } 2820 break; 2821 2822 default: 2823 dev_err(&priv->client->dev, "rx%u: unsupported CDR mode %u\n", 2824 nport, rxport->cdr_mode); 2825 return -EINVAL; 2826 } 2827 2828 return 0; 2829 } 2830 2831 static int ub960_lock_recovery_ub9702(struct ub960_data *priv, 2832 unsigned int nport) 2833 { 2834 struct device *dev = &priv->client->dev; 2835 /* Assumption that max AEQ should be under 16 */ 2836 const u8 rx_aeq_limit = 16; 2837 u8 prev_aeq = 0xff; 2838 bool rx_lock; 2839 2840 for (unsigned int retry = 0; retry < 3; ++retry) { 2841 u8 port_sts1; 2842 u8 rx_aeq; 2843 int ret; 2844 2845 ret = ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS1, 2846 &port_sts1, NULL); 2847 if (ret) 2848 return ret; 2849 2850 rx_lock = port_sts1 & UB960_RR_RX_PORT_STS1_PORT_PASS; 2851 2852 if (!rx_lock) { 2853 ret = ub960_rxport_lockup_wa_ub9702(priv); 2854 if (ret) 2855 return ret; 2856 2857 /* Restart AEQ by changing max to 0 --> 0x23 */ 2858 ret = ub960_write_ind(priv, 2859 UB960_IND_TARGET_RX_ANA(nport), 2860 UB9702_IR_RX_ANA_AEQ_ALP_SEL7, 0, 2861 NULL); 2862 if (ret) 2863 return ret; 2864 2865 msleep(20); 2866 2867 /* AEQ Restart */ 2868 ret = ub960_write_ind(priv, 2869 UB960_IND_TARGET_RX_ANA(nport), 2870 UB9702_IR_RX_ANA_AEQ_ALP_SEL7, 2871 0x23, NULL); 2872 2873 if (ret) 2874 return ret; 2875 2876 msleep(20); 2877 dev_dbg(dev, "rx%u: no lock, retry = %u\n", nport, 2878 retry); 2879 2880 continue; 2881 } 2882 2883 ret = ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 2884 UB9702_IR_RX_ANA_AEQ_ALP_SEL11, &rx_aeq, 2885 NULL); 2886 if (ret) 2887 return ret; 2888 2889 if (rx_aeq < rx_aeq_limit) { 2890 dev_dbg(dev, 2891 "rx%u: locked and AEQ normal before setting AEQ window\n", 2892 nport); 2893 return 0; 2894 } 2895 2896 if (rx_aeq != prev_aeq) { 2897 ret = ub960_rxport_lockup_wa_ub9702(priv); 2898 if (ret) 2899 return ret; 2900 2901 /* Restart AEQ by changing max to 0 --> 0x23 */ 2902 ret = ub960_write_ind(priv, 2903 UB960_IND_TARGET_RX_ANA(nport), 2904 UB9702_IR_RX_ANA_AEQ_ALP_SEL7, 2905 0, NULL); 2906 if (ret) 2907 return ret; 2908 2909 msleep(20); 2910 2911 /* AEQ Restart */ 2912 ret = ub960_write_ind(priv, 2913 UB960_IND_TARGET_RX_ANA(nport), 2914 UB9702_IR_RX_ANA_AEQ_ALP_SEL7, 2915 0x23, NULL); 2916 if (ret) 2917 return ret; 2918 2919 msleep(20); 2920 2921 dev_dbg(dev, 2922 "rx%u: high AEQ at initial check recovery loop, retry=%u\n", 2923 nport, retry); 2924 2925 prev_aeq = rx_aeq; 2926 } else { 2927 dev_dbg(dev, 2928 "rx%u: lossy cable detected, RX_AEQ %#x, RX_AEQ_LIMIT %#x, retry %u\n", 2929 nport, rx_aeq, rx_aeq_limit, retry); 2930 dev_dbg(dev, 2931 "rx%u: will continue with initiation sequence but high AEQ\n", 2932 nport); 2933 return 0; 2934 } 2935 } 2936 2937 dev_err(dev, "rx%u: max number of retries: %s\n", nport, 2938 rx_lock ? "unstable AEQ" : "no lock"); 2939 2940 return -EIO; 2941 } 2942 2943 static int ub960_enable_aeq_lms_ub9702(struct ub960_data *priv, 2944 unsigned int nport) 2945 { 2946 struct device *dev = &priv->client->dev; 2947 u8 read_aeq_init; 2948 int ret; 2949 2950 ret = ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 2951 UB9702_IR_RX_ANA_AEQ_ALP_SEL11, &read_aeq_init, 2952 NULL); 2953 if (ret) 2954 return ret; 2955 2956 dev_dbg(dev, "rx%u: initial AEQ = %#x\n", nport, read_aeq_init); 2957 2958 /* Set AEQ Min */ 2959 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 2960 UB9702_IR_RX_ANA_AEQ_ALP_SEL6, read_aeq_init, &ret); 2961 /* Set AEQ Max */ 2962 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 2963 UB9702_IR_RX_ANA_AEQ_ALP_SEL7, read_aeq_init + 1, &ret); 2964 /* Set AEQ offset to 0 */ 2965 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 2966 UB9702_IR_RX_ANA_AEQ_ALP_SEL10, 0x0, &ret); 2967 2968 /* Enable AEQ tap2 */ 2969 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 2970 UB9702_IR_RX_ANA_EQ_CTRL_SEL_38, 0x00, &ret); 2971 /* Set VGA Gain 1 Gain 2 override to 0 */ 2972 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 2973 UB9702_IR_RX_ANA_VGA_CTRL_SEL_8, 0x00, &ret); 2974 /* Set VGA Initial Sweep Gain to 0 */ 2975 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 2976 UB9702_IR_RX_ANA_VGA_CTRL_SEL_6, 0x80, &ret); 2977 /* Set VGA_Adapt (VGA Gain) override to 0 (thermometer encoded) */ 2978 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 2979 UB9702_IR_RX_ANA_VGA_CTRL_SEL_3, 0x00, &ret); 2980 /* Enable VGA_SWEEP */ 2981 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 2982 UB9702_IR_RX_ANA_EQ_ADAPT_CTRL, 0x40, &ret); 2983 /* Disable VGA_SWEEP_GAIN_OV, disable VGA_TUNE_OV */ 2984 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 2985 UB9702_IR_RX_ANA_EQ_OVERRIDE_CTRL, 0x00, &ret); 2986 2987 /* Set VGA HIGH Threshold to 43 */ 2988 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 2989 UB9702_IR_RX_ANA_VGA_CTRL_SEL_1, 0x2b, &ret); 2990 /* Set VGA LOW Threshold to 18 */ 2991 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 2992 UB9702_IR_RX_ANA_VGA_CTRL_SEL_2, 0x12, &ret); 2993 /* Set vga_sweep_th to 32 */ 2994 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 2995 UB9702_IR_RX_ANA_EQ_CTRL_SEL_15, 0x20, &ret); 2996 /* Set AEQ timer to 400us/step and parity threshold to 7 */ 2997 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 2998 UB9702_IR_RX_ANA_SYSTEM_INIT_REG0, 0xef, &ret); 2999 3000 if (ret) 3001 return ret; 3002 3003 dev_dbg(dev, "rx%u: enable FPD-Link IV AEQ LMS\n", nport); 3004 3005 return 0; 3006 } 3007 3008 static int ub960_enable_dfe_lms_ub9702(struct ub960_data *priv, 3009 unsigned int nport) 3010 { 3011 struct device *dev = &priv->client->dev; 3012 int ret = 0; 3013 3014 /* Enable DFE LMS */ 3015 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 3016 UB9702_IR_RX_ANA_EQ_CTRL_SEL_24, 0x40, &ret); 3017 /* Disable VGA Gain1 override */ 3018 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 3019 UB9702_IR_RX_ANA_GAIN_CTRL_0, 0x20, &ret); 3020 3021 if (ret) 3022 return ret; 3023 3024 usleep_range(1000, 5000); 3025 3026 /* Disable VGA Gain2 override */ 3027 ret = ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 3028 UB9702_IR_RX_ANA_GAIN_CTRL_0, 0x00, NULL); 3029 if (ret) 3030 return ret; 3031 3032 dev_dbg(dev, "rx%u: enabled FPD-Link IV DFE LMS", nport); 3033 3034 return 0; 3035 } 3036 3037 static int ub960_init_rx_ports_ub9702(struct ub960_data *priv) 3038 { 3039 struct device *dev = &priv->client->dev; 3040 unsigned int port_lock_mask; 3041 unsigned int port_mask = 0; 3042 bool have_fpd4 = false; 3043 int ret; 3044 3045 for_each_active_rxport(priv, it) { 3046 ret = ub960_rxport_update_bits(priv, it.nport, 3047 UB960_RR_BCC_CONFIG, 3048 UB960_RR_BCC_CONFIG_BC_ALWAYS_ON, 3049 UB960_RR_BCC_CONFIG_BC_ALWAYS_ON, 3050 NULL); 3051 if (ret) 3052 return ret; 3053 } 3054 3055 /* Disable FPD4 Auto Recovery */ 3056 ret = ub960_write(priv, UB9702_SR_CSI_EXCLUSIVE_FWD2, 0x0f, NULL); 3057 if (ret) 3058 return ret; 3059 3060 for_each_active_rxport(priv, it) { 3061 if (it.rxport->ser.addr >= 0) { 3062 /* 3063 * Set serializer's I2C address if set in the dts file, 3064 * and freeze it to prevent updates from the FC. 3065 */ 3066 ub960_rxport_write(priv, it.nport, UB960_RR_SER_ID, 3067 it.rxport->ser.addr << 1 | 3068 UB960_RR_SER_ID_FREEZE_DEVICE_ID, 3069 &ret); 3070 } 3071 3072 /* Set serializer I2C alias with auto-ack */ 3073 ub960_rxport_write(priv, it.nport, UB960_RR_SER_ALIAS_ID, 3074 it.rxport->ser.alias << 1 | 3075 UB960_RR_SER_ALIAS_ID_AUTO_ACK, &ret); 3076 3077 if (ret) 3078 return ret; 3079 } 3080 3081 for_each_active_rxport(priv, it) { 3082 if (fwnode_device_is_compatible(it.rxport->ser.fwnode, 3083 "ti,ds90ub971-q1")) { 3084 ret = ub960_rxport_bc_ser_config(it.rxport); 3085 if (ret) 3086 return ret; 3087 } 3088 } 3089 3090 for_each_active_rxport_fpd4(priv, it) { 3091 /* Hold state machine in reset */ 3092 ub960_rxport_write(priv, it.nport, UB9702_RR_RX_SM_SEL_2, 0x10, 3093 &ret); 3094 3095 /* Set AEQ max to 0 */ 3096 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(it.nport), 3097 UB9702_IR_RX_ANA_AEQ_ALP_SEL7, 0, &ret); 3098 3099 if (ret) 3100 return ret; 3101 3102 dev_dbg(dev, 3103 "rx%u: holding state machine and adjusting AEQ max to 0", 3104 it.nport); 3105 } 3106 3107 for_each_active_rxport(priv, it) { 3108 port_mask |= BIT(it.nport); 3109 3110 if (it.rxport->cdr_mode == RXPORT_CDR_FPD4) 3111 have_fpd4 = true; 3112 } 3113 3114 for_each_rxport(priv, it) { 3115 ret = ub960_configure_rx_port_ub9702(priv, it.nport); 3116 if (ret) 3117 return ret; 3118 } 3119 3120 ret = ub960_reset(priv, false); 3121 if (ret) 3122 return ret; 3123 3124 if (have_fpd4) { 3125 for_each_active_rxport_fpd4(priv, it) { 3126 /* Release state machine */ 3127 ret = ub960_rxport_write(priv, it.nport, 3128 UB9702_RR_RX_SM_SEL_2, 0x0, 3129 NULL); 3130 if (ret) 3131 return ret; 3132 3133 dev_dbg(dev, "rx%u: state machine released\n", 3134 it.nport); 3135 } 3136 3137 /* Wait for SM to resume */ 3138 fsleep(5000); 3139 3140 for_each_active_rxport_fpd4(priv, it) { 3141 ret = ub960_write_ind(priv, 3142 UB960_IND_TARGET_RX_ANA(it.nport), 3143 UB9702_IR_RX_ANA_AEQ_ALP_SEL7, 3144 0x23, NULL); 3145 if (ret) 3146 return ret; 3147 3148 dev_dbg(dev, "rx%u: AEQ restart\n", it.nport); 3149 } 3150 3151 /* Wait for lock */ 3152 fsleep(20000); 3153 3154 for_each_active_rxport_fpd4(priv, it) { 3155 ret = ub960_lock_recovery_ub9702(priv, it.nport); 3156 if (ret) 3157 return ret; 3158 } 3159 3160 for_each_active_rxport_fpd4(priv, it) { 3161 ret = ub960_enable_aeq_lms_ub9702(priv, it.nport); 3162 if (ret) 3163 return ret; 3164 } 3165 3166 for_each_active_rxport_fpd4(priv, it) { 3167 /* Hold state machine in reset */ 3168 ret = ub960_rxport_write(priv, it.nport, 3169 UB9702_RR_RX_SM_SEL_2, 0x10, 3170 NULL); 3171 if (ret) 3172 return ret; 3173 } 3174 3175 ret = ub960_reset(priv, false); 3176 if (ret) 3177 return ret; 3178 3179 for_each_active_rxport_fpd4(priv, it) { 3180 /* Release state machine */ 3181 ret = ub960_rxport_write(priv, it.nport, 3182 UB9702_RR_RX_SM_SEL_2, 0, 3183 NULL); 3184 if (ret) 3185 return ret; 3186 } 3187 } 3188 3189 /* Wait time for stable lock */ 3190 fsleep(15000); 3191 3192 /* Set temperature ramp on serializer */ 3193 for_each_active_rxport(priv, it) { 3194 ret = ub960_serializer_temp_ramp(it.rxport); 3195 if (ret) 3196 return ret; 3197 } 3198 3199 for_each_active_rxport_fpd4(priv, it) { 3200 ret = ub960_enable_dfe_lms_ub9702(priv, it.nport); 3201 if (ret) 3202 return ret; 3203 } 3204 3205 /* Wait for DFE and LMS to adapt */ 3206 fsleep(5000); 3207 3208 ret = ub960_rxport_wait_locks(priv, port_mask, &port_lock_mask); 3209 if (ret) 3210 return ret; 3211 3212 if (port_mask != port_lock_mask) { 3213 ret = -EIO; 3214 dev_err_probe(dev, ret, "Failed to lock all RX ports\n"); 3215 return ret; 3216 } 3217 3218 for_each_active_rxport(priv, it) { 3219 /* Enable all interrupt sources from this port */ 3220 ub960_rxport_write(priv, it.nport, UB960_RR_PORT_ICR_HI, 0x07, 3221 &ret); 3222 ub960_rxport_write(priv, it.nport, UB960_RR_PORT_ICR_LO, 0x7f, 3223 &ret); 3224 3225 /* Clear serializer I2C alias auto-ack */ 3226 ub960_rxport_update_bits(priv, it.nport, UB960_RR_SER_ALIAS_ID, 3227 UB960_RR_SER_ALIAS_ID_AUTO_ACK, 0, 3228 &ret); 3229 3230 /* Enable I2C_PASS_THROUGH */ 3231 ub960_rxport_update_bits(priv, it.nport, UB960_RR_BCC_CONFIG, 3232 UB960_RR_BCC_CONFIG_I2C_PASS_THROUGH, 3233 UB960_RR_BCC_CONFIG_I2C_PASS_THROUGH, 3234 &ret); 3235 3236 if (ret) 3237 return ret; 3238 } 3239 3240 /* Enable FPD4 Auto Recovery, Recovery loop active */ 3241 ret = ub960_write(priv, UB9702_SR_CSI_EXCLUSIVE_FWD2, 0x18, NULL); 3242 if (ret) 3243 return ret; 3244 3245 for_each_active_rxport_fpd4(priv, it) { 3246 u8 final_aeq; 3247 3248 ret = ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(it.nport), 3249 UB9702_IR_RX_ANA_AEQ_ALP_SEL11, &final_aeq, 3250 NULL); 3251 if (ret) 3252 return ret; 3253 3254 dev_dbg(dev, "rx%u: final AEQ = %#x\n", it.nport, final_aeq); 3255 } 3256 3257 /* 3258 * Clear any errors caused by switching the RX port settings while 3259 * probing. 3260 */ 3261 3262 ret = ub960_clear_rx_errors(priv); 3263 if (ret) 3264 return ret; 3265 3266 return 0; 3267 } 3268 3269 static int ub960_rxport_handle_events(struct ub960_data *priv, u8 nport) 3270 { 3271 struct device *dev = &priv->client->dev; 3272 u8 rx_port_sts1; 3273 u8 rx_port_sts2; 3274 u8 csi_rx_sts; 3275 u8 bcc_sts; 3276 int ret = 0; 3277 3278 /* Read interrupts (also clears most of them) */ 3279 ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS1, &rx_port_sts1, 3280 &ret); 3281 ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS2, &rx_port_sts2, 3282 &ret); 3283 ub960_rxport_read(priv, nport, UB960_RR_CSI_RX_STS, &csi_rx_sts, &ret); 3284 ub960_rxport_read(priv, nport, UB960_RR_BCC_STATUS, &bcc_sts, &ret); 3285 3286 if (ret) 3287 return ret; 3288 3289 if (rx_port_sts1 & UB960_RR_RX_PORT_STS1_PARITY_ERROR) { 3290 u16 v; 3291 3292 ret = ub960_rxport_read16(priv, nport, UB960_RR_RX_PAR_ERR_HI, 3293 &v, NULL); 3294 if (!ret) 3295 dev_err(dev, "rx%u parity errors: %u\n", nport, v); 3296 } 3297 3298 if (rx_port_sts1 & UB960_RR_RX_PORT_STS1_BCC_CRC_ERROR) 3299 dev_err(dev, "rx%u BCC CRC error\n", nport); 3300 3301 if (rx_port_sts1 & UB960_RR_RX_PORT_STS1_BCC_SEQ_ERROR) 3302 dev_err(dev, "rx%u BCC SEQ error\n", nport); 3303 3304 if (rx_port_sts2 & UB960_RR_RX_PORT_STS2_LINE_LEN_UNSTABLE) 3305 dev_err(dev, "rx%u line length unstable\n", nport); 3306 3307 if (rx_port_sts2 & UB960_RR_RX_PORT_STS2_FPD3_ENCODE_ERROR) 3308 dev_err(dev, "rx%u FPD3 encode error\n", nport); 3309 3310 if (rx_port_sts2 & UB960_RR_RX_PORT_STS2_BUFFER_ERROR) 3311 dev_err(dev, "rx%u buffer error\n", nport); 3312 3313 if (csi_rx_sts) 3314 dev_err(dev, "rx%u CSI error: %#02x\n", nport, csi_rx_sts); 3315 3316 if (csi_rx_sts & UB960_RR_CSI_RX_STS_ECC1_ERR) 3317 dev_err(dev, "rx%u CSI ECC1 error\n", nport); 3318 3319 if (csi_rx_sts & UB960_RR_CSI_RX_STS_ECC2_ERR) 3320 dev_err(dev, "rx%u CSI ECC2 error\n", nport); 3321 3322 if (csi_rx_sts & UB960_RR_CSI_RX_STS_CKSUM_ERR) 3323 dev_err(dev, "rx%u CSI checksum error\n", nport); 3324 3325 if (csi_rx_sts & UB960_RR_CSI_RX_STS_LENGTH_ERR) 3326 dev_err(dev, "rx%u CSI length error\n", nport); 3327 3328 if (bcc_sts) 3329 dev_err(dev, "rx%u BCC error: %#02x\n", nport, bcc_sts); 3330 3331 if (bcc_sts & UB960_RR_BCC_STATUS_RESP_ERR) 3332 dev_err(dev, "rx%u BCC response error", nport); 3333 3334 if (bcc_sts & UB960_RR_BCC_STATUS_SLAVE_TO) 3335 dev_err(dev, "rx%u BCC slave timeout", nport); 3336 3337 if (bcc_sts & UB960_RR_BCC_STATUS_SLAVE_ERR) 3338 dev_err(dev, "rx%u BCC slave error", nport); 3339 3340 if (bcc_sts & UB960_RR_BCC_STATUS_MASTER_TO) 3341 dev_err(dev, "rx%u BCC master timeout", nport); 3342 3343 if (bcc_sts & UB960_RR_BCC_STATUS_MASTER_ERR) 3344 dev_err(dev, "rx%u BCC master error", nport); 3345 3346 if (bcc_sts & UB960_RR_BCC_STATUS_SEQ_ERROR) 3347 dev_err(dev, "rx%u BCC sequence error", nport); 3348 3349 if (rx_port_sts2 & UB960_RR_RX_PORT_STS2_LINE_LEN_CHG) { 3350 u16 v; 3351 3352 ret = ub960_rxport_read16(priv, nport, UB960_RR_LINE_LEN_1, 3353 &v, NULL); 3354 if (!ret) 3355 dev_dbg(dev, "rx%u line len changed: %u\n", nport, v); 3356 } 3357 3358 if (rx_port_sts2 & UB960_RR_RX_PORT_STS2_LINE_CNT_CHG) { 3359 u16 v; 3360 3361 ret = ub960_rxport_read16(priv, nport, UB960_RR_LINE_COUNT_HI, 3362 &v, NULL); 3363 if (!ret) 3364 dev_dbg(dev, "rx%u line count changed: %u\n", nport, v); 3365 } 3366 3367 if (rx_port_sts1 & UB960_RR_RX_PORT_STS1_LOCK_STS_CHG) { 3368 dev_dbg(dev, "rx%u: %s, %s, %s, %s\n", nport, 3369 (rx_port_sts1 & UB960_RR_RX_PORT_STS1_LOCK_STS) ? 3370 "locked" : 3371 "unlocked", 3372 (rx_port_sts1 & UB960_RR_RX_PORT_STS1_PORT_PASS) ? 3373 "passed" : 3374 "not passed", 3375 (rx_port_sts2 & UB960_RR_RX_PORT_STS2_CABLE_FAULT) ? 3376 "no clock" : 3377 "clock ok", 3378 (rx_port_sts2 & UB960_RR_RX_PORT_STS2_FREQ_STABLE) ? 3379 "stable freq" : 3380 "unstable freq"); 3381 } 3382 3383 return 0; 3384 } 3385 3386 /* ----------------------------------------------------------------------------- 3387 * V4L2 3388 */ 3389 3390 /* 3391 * The current implementation only supports a simple VC mapping, where all VCs 3392 * from a one RX port will be mapped to the same VC. Also, the hardware 3393 * dictates that all streams from an RX port must go to a single TX port. 3394 * 3395 * This function decides the target VC numbers for each RX port with a simple 3396 * algorithm, so that for each TX port, we get VC numbers starting from 0, 3397 * and counting up. 3398 * 3399 * E.g. if all four RX ports are in use, of which the first two go to the 3400 * first TX port and the secont two go to the second TX port, we would get 3401 * the following VCs for the four RX ports: 0, 1, 0, 1. 3402 * 3403 * TODO: implement a more sophisticated VC mapping. As the driver cannot know 3404 * what VCs the sinks expect (say, an FPGA with hardcoded VC routing), this 3405 * probably needs to be somehow configurable. Device tree? 3406 */ 3407 static void ub960_get_vc_maps(struct ub960_data *priv, 3408 struct v4l2_subdev_state *state, u8 *vc) 3409 { 3410 u8 cur_vc[UB960_MAX_TX_NPORTS] = {}; 3411 struct v4l2_subdev_route *route; 3412 u8 handled_mask = 0; 3413 3414 for_each_active_route(&state->routing, route) { 3415 unsigned int rx, tx; 3416 3417 rx = ub960_pad_to_port(priv, route->sink_pad); 3418 if (BIT(rx) & handled_mask) 3419 continue; 3420 3421 tx = ub960_pad_to_port(priv, route->source_pad); 3422 3423 vc[rx] = cur_vc[tx]++; 3424 handled_mask |= BIT(rx); 3425 } 3426 } 3427 3428 static int ub960_enable_tx_port(struct ub960_data *priv, unsigned int nport) 3429 { 3430 struct device *dev = &priv->client->dev; 3431 3432 dev_dbg(dev, "enable TX port %u\n", nport); 3433 3434 return ub960_txport_update_bits(priv, nport, UB960_TR_CSI_CTL, 3435 UB960_TR_CSI_CTL_CSI_ENABLE, 3436 UB960_TR_CSI_CTL_CSI_ENABLE, NULL); 3437 } 3438 3439 static int ub960_disable_tx_port(struct ub960_data *priv, unsigned int nport) 3440 { 3441 struct device *dev = &priv->client->dev; 3442 3443 dev_dbg(dev, "disable TX port %u\n", nport); 3444 3445 return ub960_txport_update_bits(priv, nport, UB960_TR_CSI_CTL, 3446 UB960_TR_CSI_CTL_CSI_ENABLE, 0, NULL); 3447 } 3448 3449 static int ub960_enable_rx_port(struct ub960_data *priv, unsigned int nport) 3450 { 3451 struct device *dev = &priv->client->dev; 3452 3453 dev_dbg(dev, "enable RX port %u\n", nport); 3454 3455 /* Enable forwarding */ 3456 return ub960_update_bits(priv, UB960_SR_FWD_CTL1, 3457 UB960_SR_FWD_CTL1_PORT_DIS(nport), 0, NULL); 3458 } 3459 3460 static int ub960_disable_rx_port(struct ub960_data *priv, unsigned int nport) 3461 { 3462 struct device *dev = &priv->client->dev; 3463 3464 dev_dbg(dev, "disable RX port %u\n", nport); 3465 3466 /* Disable forwarding */ 3467 return ub960_update_bits(priv, UB960_SR_FWD_CTL1, 3468 UB960_SR_FWD_CTL1_PORT_DIS(nport), 3469 UB960_SR_FWD_CTL1_PORT_DIS(nport), NULL); 3470 } 3471 3472 /* 3473 * The driver only supports using a single VC for each source. This function 3474 * checks that each source only provides streams using a single VC. 3475 */ 3476 static int ub960_validate_stream_vcs(struct ub960_data *priv) 3477 { 3478 for_each_active_rxport(priv, it) { 3479 struct v4l2_mbus_frame_desc desc; 3480 int ret; 3481 u8 vc; 3482 3483 ret = v4l2_subdev_call(it.rxport->source.sd, pad, 3484 get_frame_desc, it.rxport->source.pad, 3485 &desc); 3486 if (ret) 3487 return ret; 3488 3489 if (desc.type != V4L2_MBUS_FRAME_DESC_TYPE_CSI2) 3490 continue; 3491 3492 if (desc.num_entries == 0) 3493 continue; 3494 3495 vc = desc.entry[0].bus.csi2.vc; 3496 3497 for (unsigned int i = 1; i < desc.num_entries; i++) { 3498 if (vc == desc.entry[i].bus.csi2.vc) 3499 continue; 3500 3501 dev_err(&priv->client->dev, 3502 "rx%u: source with multiple virtual-channels is not supported\n", 3503 it.nport); 3504 return -ENODEV; 3505 } 3506 } 3507 3508 return 0; 3509 } 3510 3511 static int ub960_configure_ports_for_streaming(struct ub960_data *priv, 3512 struct v4l2_subdev_state *state) 3513 { 3514 u8 fwd_ctl; 3515 struct { 3516 u32 num_streams; 3517 u8 pixel_dt; 3518 u8 meta_dt; 3519 u32 meta_lines; 3520 u32 tx_port; 3521 } rx_data[UB960_MAX_RX_NPORTS] = {}; 3522 u8 vc_map[UB960_MAX_RX_NPORTS] = {}; 3523 struct v4l2_subdev_route *route; 3524 int ret; 3525 3526 ret = ub960_validate_stream_vcs(priv); 3527 if (ret) 3528 return ret; 3529 3530 ub960_get_vc_maps(priv, state, vc_map); 3531 3532 for_each_active_route(&state->routing, route) { 3533 struct ub960_rxport *rxport; 3534 struct ub960_txport *txport; 3535 struct v4l2_mbus_framefmt *fmt; 3536 const struct ub960_format_info *ub960_fmt; 3537 unsigned int nport; 3538 3539 nport = ub960_pad_to_port(priv, route->sink_pad); 3540 3541 rxport = priv->rxports[nport]; 3542 if (!rxport) 3543 return -EINVAL; 3544 3545 txport = priv->txports[ub960_pad_to_port(priv, route->source_pad)]; 3546 if (!txport) 3547 return -EINVAL; 3548 3549 rx_data[nport].tx_port = ub960_pad_to_port(priv, route->source_pad); 3550 3551 rx_data[nport].num_streams++; 3552 3553 /* For the rest, we are only interested in parallel busses */ 3554 if (rxport->rx_mode == RXPORT_MODE_CSI2_SYNC || 3555 rxport->rx_mode == RXPORT_MODE_CSI2_NONSYNC) 3556 continue; 3557 3558 if (rx_data[nport].num_streams > 2) 3559 return -EPIPE; 3560 3561 fmt = v4l2_subdev_state_get_format(state, route->sink_pad, 3562 route->sink_stream); 3563 if (!fmt) 3564 return -EPIPE; 3565 3566 ub960_fmt = ub960_find_format(fmt->code); 3567 if (!ub960_fmt) 3568 return -EPIPE; 3569 3570 if (ub960_fmt->meta) { 3571 if (fmt->height > 3) { 3572 dev_err(&priv->client->dev, 3573 "rx%u: unsupported metadata height %u\n", 3574 nport, fmt->height); 3575 return -EPIPE; 3576 } 3577 3578 rx_data[nport].meta_dt = ub960_fmt->datatype; 3579 rx_data[nport].meta_lines = fmt->height; 3580 } else { 3581 rx_data[nport].pixel_dt = ub960_fmt->datatype; 3582 } 3583 } 3584 3585 /* Configure RX ports */ 3586 3587 /* 3588 * Keep all port forwardings disabled by default. Forwarding will be 3589 * enabled in ub960_enable_rx_port. 3590 */ 3591 fwd_ctl = GENMASK(7, 4); 3592 3593 for_each_active_rxport(priv, it) { 3594 unsigned long nport = it.nport; 3595 3596 u8 vc = vc_map[nport]; 3597 3598 if (rx_data[nport].num_streams == 0) 3599 continue; 3600 3601 switch (it.rxport->rx_mode) { 3602 case RXPORT_MODE_RAW10: 3603 ub960_rxport_write(priv, nport, UB960_RR_RAW10_ID, 3604 rx_data[nport].pixel_dt | (vc << UB960_RR_RAW10_ID_VC_SHIFT), 3605 &ret); 3606 3607 ub960_rxport_write(priv, nport, 3608 UB960_RR_RAW_EMBED_DTYPE, 3609 (rx_data[nport].meta_lines << UB960_RR_RAW_EMBED_DTYPE_LINES_SHIFT) | 3610 rx_data[nport].meta_dt, &ret); 3611 3612 break; 3613 3614 case RXPORT_MODE_RAW12_HF: 3615 case RXPORT_MODE_RAW12_LF: 3616 /* Not implemented */ 3617 break; 3618 3619 case RXPORT_MODE_CSI2_SYNC: 3620 case RXPORT_MODE_CSI2_NONSYNC: 3621 if (!priv->hw_data->is_ub9702) { 3622 /* Map all VCs from this port to the same VC */ 3623 ub960_rxport_write(priv, nport, UB960_RR_CSI_VC_MAP, 3624 (vc << UB960_RR_CSI_VC_MAP_SHIFT(3)) | 3625 (vc << UB960_RR_CSI_VC_MAP_SHIFT(2)) | 3626 (vc << UB960_RR_CSI_VC_MAP_SHIFT(1)) | 3627 (vc << UB960_RR_CSI_VC_MAP_SHIFT(0)), 3628 &ret); 3629 } else { 3630 unsigned int i; 3631 3632 /* Map all VCs from this port to VC(nport) */ 3633 for (i = 0; i < 8; i++) 3634 ub960_rxport_write(priv, nport, 3635 UB9702_RR_VC_ID_MAP(i), 3636 (nport << 4) | nport, 3637 &ret); 3638 } 3639 3640 break; 3641 } 3642 3643 if (rx_data[nport].tx_port == 1) 3644 fwd_ctl |= BIT(nport); /* forward to TX1 */ 3645 else 3646 fwd_ctl &= ~BIT(nport); /* forward to TX0 */ 3647 } 3648 3649 ub960_write(priv, UB960_SR_FWD_CTL1, fwd_ctl, &ret); 3650 3651 return ret; 3652 } 3653 3654 static void ub960_update_streaming_status(struct ub960_data *priv) 3655 { 3656 unsigned int i; 3657 3658 for (i = 0; i < UB960_MAX_NPORTS; i++) { 3659 if (priv->stream_enable_mask[i]) 3660 break; 3661 } 3662 3663 priv->streaming = i < UB960_MAX_NPORTS; 3664 } 3665 3666 static int ub960_enable_streams(struct v4l2_subdev *sd, 3667 struct v4l2_subdev_state *state, u32 source_pad, 3668 u64 source_streams_mask) 3669 { 3670 struct ub960_data *priv = sd_to_ub960(sd); 3671 struct device *dev = &priv->client->dev; 3672 u64 sink_streams[UB960_MAX_RX_NPORTS] = {}; 3673 struct v4l2_subdev_route *route; 3674 unsigned int failed_port; 3675 int ret; 3676 3677 if (!priv->streaming) { 3678 dev_dbg(dev, "Prepare for streaming\n"); 3679 ret = ub960_configure_ports_for_streaming(priv, state); 3680 if (ret) 3681 return ret; 3682 } 3683 3684 /* Enable TX port if not yet enabled */ 3685 if (!priv->stream_enable_mask[source_pad]) { 3686 ret = ub960_enable_tx_port(priv, 3687 ub960_pad_to_port(priv, source_pad)); 3688 if (ret) 3689 return ret; 3690 } 3691 3692 priv->stream_enable_mask[source_pad] |= source_streams_mask; 3693 3694 /* Collect sink streams per pad which we need to enable */ 3695 for_each_active_route(&state->routing, route) { 3696 unsigned int nport; 3697 3698 if (route->source_pad != source_pad) 3699 continue; 3700 3701 if (!(source_streams_mask & BIT_ULL(route->source_stream))) 3702 continue; 3703 3704 nport = ub960_pad_to_port(priv, route->sink_pad); 3705 3706 sink_streams[nport] |= BIT_ULL(route->sink_stream); 3707 } 3708 3709 for_each_rxport(priv, it) { 3710 unsigned int nport = it.nport; 3711 3712 if (!sink_streams[nport]) 3713 continue; 3714 3715 /* Enable the RX port if not yet enabled */ 3716 if (!priv->stream_enable_mask[nport]) { 3717 ret = ub960_enable_rx_port(priv, nport); 3718 if (ret) { 3719 failed_port = nport; 3720 goto err; 3721 } 3722 } 3723 3724 priv->stream_enable_mask[nport] |= sink_streams[nport]; 3725 3726 dev_dbg(dev, "enable RX port %u streams %#llx\n", nport, 3727 sink_streams[nport]); 3728 3729 ret = v4l2_subdev_enable_streams( 3730 priv->rxports[nport]->source.sd, 3731 priv->rxports[nport]->source.pad, 3732 sink_streams[nport]); 3733 if (ret) { 3734 priv->stream_enable_mask[nport] &= ~sink_streams[nport]; 3735 3736 if (!priv->stream_enable_mask[nport]) 3737 ub960_disable_rx_port(priv, nport); 3738 3739 failed_port = nport; 3740 goto err; 3741 } 3742 } 3743 3744 priv->streaming = true; 3745 3746 return 0; 3747 3748 err: 3749 for (unsigned int nport = 0; nport < failed_port; nport++) { 3750 if (!sink_streams[nport]) 3751 continue; 3752 3753 dev_dbg(dev, "disable RX port %u streams %#llx\n", nport, 3754 sink_streams[nport]); 3755 3756 ret = v4l2_subdev_disable_streams( 3757 priv->rxports[nport]->source.sd, 3758 priv->rxports[nport]->source.pad, 3759 sink_streams[nport]); 3760 if (ret) 3761 dev_err(dev, "Failed to disable streams: %d\n", ret); 3762 3763 priv->stream_enable_mask[nport] &= ~sink_streams[nport]; 3764 3765 /* Disable RX port if no active streams */ 3766 if (!priv->stream_enable_mask[nport]) 3767 ub960_disable_rx_port(priv, nport); 3768 } 3769 3770 priv->stream_enable_mask[source_pad] &= ~source_streams_mask; 3771 3772 if (!priv->stream_enable_mask[source_pad]) 3773 ub960_disable_tx_port(priv, 3774 ub960_pad_to_port(priv, source_pad)); 3775 3776 ub960_update_streaming_status(priv); 3777 3778 return ret; 3779 } 3780 3781 static int ub960_disable_streams(struct v4l2_subdev *sd, 3782 struct v4l2_subdev_state *state, 3783 u32 source_pad, u64 source_streams_mask) 3784 { 3785 struct ub960_data *priv = sd_to_ub960(sd); 3786 struct device *dev = &priv->client->dev; 3787 u64 sink_streams[UB960_MAX_RX_NPORTS] = {}; 3788 struct v4l2_subdev_route *route; 3789 int ret; 3790 3791 /* Collect sink streams per pad which we need to disable */ 3792 for_each_active_route(&state->routing, route) { 3793 unsigned int nport; 3794 3795 if (route->source_pad != source_pad) 3796 continue; 3797 3798 if (!(source_streams_mask & BIT_ULL(route->source_stream))) 3799 continue; 3800 3801 nport = ub960_pad_to_port(priv, route->sink_pad); 3802 3803 sink_streams[nport] |= BIT_ULL(route->sink_stream); 3804 } 3805 3806 for_each_rxport(priv, it) { 3807 unsigned int nport = it.nport; 3808 3809 if (!sink_streams[nport]) 3810 continue; 3811 3812 dev_dbg(dev, "disable RX port %u streams %#llx\n", nport, 3813 sink_streams[nport]); 3814 3815 ret = v4l2_subdev_disable_streams( 3816 priv->rxports[nport]->source.sd, 3817 priv->rxports[nport]->source.pad, 3818 sink_streams[nport]); 3819 if (ret) 3820 dev_err(dev, "Failed to disable streams: %d\n", ret); 3821 3822 priv->stream_enable_mask[nport] &= ~sink_streams[nport]; 3823 3824 /* Disable RX port if no active streams */ 3825 if (!priv->stream_enable_mask[nport]) 3826 ub960_disable_rx_port(priv, nport); 3827 } 3828 3829 /* Disable TX port if no active streams */ 3830 3831 priv->stream_enable_mask[source_pad] &= ~source_streams_mask; 3832 3833 if (!priv->stream_enable_mask[source_pad]) 3834 ub960_disable_tx_port(priv, 3835 ub960_pad_to_port(priv, source_pad)); 3836 3837 ub960_update_streaming_status(priv); 3838 3839 return 0; 3840 } 3841 3842 static int _ub960_set_routing(struct v4l2_subdev *sd, 3843 struct v4l2_subdev_state *state, 3844 struct v4l2_subdev_krouting *routing) 3845 { 3846 static const struct v4l2_mbus_framefmt format = { 3847 .width = 640, 3848 .height = 480, 3849 .code = MEDIA_BUS_FMT_UYVY8_1X16, 3850 .field = V4L2_FIELD_NONE, 3851 .colorspace = V4L2_COLORSPACE_SRGB, 3852 .ycbcr_enc = V4L2_YCBCR_ENC_601, 3853 .quantization = V4L2_QUANTIZATION_LIM_RANGE, 3854 .xfer_func = V4L2_XFER_FUNC_SRGB, 3855 }; 3856 int ret; 3857 3858 /* 3859 * Note: we can only support up to V4L2_FRAME_DESC_ENTRY_MAX, until 3860 * frame desc is made dynamically allocated. 3861 */ 3862 3863 if (routing->num_routes > V4L2_FRAME_DESC_ENTRY_MAX) 3864 return -E2BIG; 3865 3866 ret = v4l2_subdev_routing_validate(sd, routing, 3867 V4L2_SUBDEV_ROUTING_ONLY_1_TO_1 | 3868 V4L2_SUBDEV_ROUTING_NO_SINK_STREAM_MIX); 3869 if (ret) 3870 return ret; 3871 3872 ret = v4l2_subdev_set_routing_with_fmt(sd, state, routing, &format); 3873 if (ret) 3874 return ret; 3875 3876 return 0; 3877 } 3878 3879 static int ub960_set_routing(struct v4l2_subdev *sd, 3880 struct v4l2_subdev_state *state, 3881 enum v4l2_subdev_format_whence which, 3882 struct v4l2_subdev_krouting *routing) 3883 { 3884 struct ub960_data *priv = sd_to_ub960(sd); 3885 3886 if (which == V4L2_SUBDEV_FORMAT_ACTIVE && priv->streaming) 3887 return -EBUSY; 3888 3889 return _ub960_set_routing(sd, state, routing); 3890 } 3891 3892 static int ub960_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad, 3893 struct v4l2_mbus_frame_desc *fd) 3894 { 3895 struct ub960_data *priv = sd_to_ub960(sd); 3896 struct v4l2_subdev_route *route; 3897 struct v4l2_subdev_state *state; 3898 int ret = 0; 3899 struct device *dev = &priv->client->dev; 3900 u8 vc_map[UB960_MAX_RX_NPORTS] = {}; 3901 3902 if (!ub960_pad_is_source(priv, pad)) 3903 return -EINVAL; 3904 3905 fd->type = V4L2_MBUS_FRAME_DESC_TYPE_CSI2; 3906 3907 state = v4l2_subdev_lock_and_get_active_state(&priv->sd); 3908 3909 ub960_get_vc_maps(priv, state, vc_map); 3910 3911 for_each_active_route(&state->routing, route) { 3912 struct v4l2_mbus_frame_desc_entry *source_entry = NULL; 3913 struct v4l2_mbus_frame_desc source_fd; 3914 unsigned int nport; 3915 unsigned int i; 3916 3917 if (route->source_pad != pad) 3918 continue; 3919 3920 nport = ub960_pad_to_port(priv, route->sink_pad); 3921 3922 ret = v4l2_subdev_call(priv->rxports[nport]->source.sd, pad, 3923 get_frame_desc, 3924 priv->rxports[nport]->source.pad, 3925 &source_fd); 3926 if (ret) { 3927 dev_err(dev, 3928 "Failed to get source frame desc for pad %u\n", 3929 route->sink_pad); 3930 goto out_unlock; 3931 } 3932 3933 for (i = 0; i < source_fd.num_entries; i++) { 3934 if (source_fd.entry[i].stream == route->sink_stream) { 3935 source_entry = &source_fd.entry[i]; 3936 break; 3937 } 3938 } 3939 3940 if (!source_entry) { 3941 dev_err(dev, 3942 "Failed to find stream from source frame desc\n"); 3943 ret = -EPIPE; 3944 goto out_unlock; 3945 } 3946 3947 fd->entry[fd->num_entries].stream = route->source_stream; 3948 fd->entry[fd->num_entries].flags = source_entry->flags; 3949 fd->entry[fd->num_entries].length = source_entry->length; 3950 fd->entry[fd->num_entries].pixelcode = source_entry->pixelcode; 3951 3952 fd->entry[fd->num_entries].bus.csi2.vc = vc_map[nport]; 3953 3954 if (source_fd.type == V4L2_MBUS_FRAME_DESC_TYPE_CSI2) { 3955 fd->entry[fd->num_entries].bus.csi2.dt = 3956 source_entry->bus.csi2.dt; 3957 } else { 3958 const struct ub960_format_info *ub960_fmt; 3959 struct v4l2_mbus_framefmt *fmt; 3960 3961 fmt = v4l2_subdev_state_get_format(state, pad, 3962 route->source_stream); 3963 3964 if (!fmt) { 3965 ret = -EINVAL; 3966 goto out_unlock; 3967 } 3968 3969 ub960_fmt = ub960_find_format(fmt->code); 3970 if (!ub960_fmt) { 3971 dev_err(dev, "Unable to find format\n"); 3972 ret = -EINVAL; 3973 goto out_unlock; 3974 } 3975 3976 fd->entry[fd->num_entries].bus.csi2.dt = 3977 ub960_fmt->datatype; 3978 } 3979 3980 fd->num_entries++; 3981 } 3982 3983 out_unlock: 3984 v4l2_subdev_unlock_state(state); 3985 3986 return ret; 3987 } 3988 3989 static int ub960_set_fmt(struct v4l2_subdev *sd, 3990 struct v4l2_subdev_state *state, 3991 struct v4l2_subdev_format *format) 3992 { 3993 struct ub960_data *priv = sd_to_ub960(sd); 3994 struct v4l2_mbus_framefmt *fmt; 3995 3996 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE && priv->streaming) 3997 return -EBUSY; 3998 3999 /* No transcoding, source and sink formats must match. */ 4000 if (ub960_pad_is_source(priv, format->pad)) 4001 return v4l2_subdev_get_fmt(sd, state, format); 4002 4003 /* 4004 * Default to the first format if the requested media bus code isn't 4005 * supported. 4006 */ 4007 if (!ub960_find_format(format->format.code)) 4008 format->format.code = ub960_formats[0].code; 4009 4010 fmt = v4l2_subdev_state_get_format(state, format->pad, format->stream); 4011 if (!fmt) 4012 return -EINVAL; 4013 4014 *fmt = format->format; 4015 4016 fmt = v4l2_subdev_state_get_opposite_stream_format(state, format->pad, 4017 format->stream); 4018 if (!fmt) 4019 return -EINVAL; 4020 4021 *fmt = format->format; 4022 4023 return 0; 4024 } 4025 4026 static int ub960_init_state(struct v4l2_subdev *sd, 4027 struct v4l2_subdev_state *state) 4028 { 4029 struct ub960_data *priv = sd_to_ub960(sd); 4030 4031 struct v4l2_subdev_route routes[] = { 4032 { 4033 .sink_pad = 0, 4034 .sink_stream = 0, 4035 .source_pad = priv->hw_data->num_rxports, 4036 .source_stream = 0, 4037 .flags = V4L2_SUBDEV_ROUTE_FL_ACTIVE, 4038 }, 4039 }; 4040 4041 struct v4l2_subdev_krouting routing = { 4042 .num_routes = ARRAY_SIZE(routes), 4043 .routes = routes, 4044 }; 4045 4046 return _ub960_set_routing(sd, state, &routing); 4047 } 4048 4049 static const struct v4l2_subdev_pad_ops ub960_pad_ops = { 4050 .enable_streams = ub960_enable_streams, 4051 .disable_streams = ub960_disable_streams, 4052 4053 .set_routing = ub960_set_routing, 4054 .get_frame_desc = ub960_get_frame_desc, 4055 4056 .get_fmt = v4l2_subdev_get_fmt, 4057 .set_fmt = ub960_set_fmt, 4058 }; 4059 4060 static int ub960_log_status_ub960_sp_eq(struct ub960_data *priv, 4061 unsigned int nport) 4062 { 4063 struct device *dev = &priv->client->dev; 4064 u8 eq_level; 4065 s8 strobe_pos; 4066 int ret; 4067 u8 v; 4068 4069 /* Strobe */ 4070 4071 ret = ub960_read(priv, UB960_XR_AEQ_CTL1, &v, NULL); 4072 if (ret) 4073 return ret; 4074 4075 dev_info(dev, "\t%s strobe\n", 4076 (v & UB960_XR_AEQ_CTL1_AEQ_SFILTER_EN) ? "Adaptive" : 4077 "Manual"); 4078 4079 if (v & UB960_XR_AEQ_CTL1_AEQ_SFILTER_EN) { 4080 ret = ub960_read(priv, UB960_XR_SFILTER_CFG, &v, NULL); 4081 if (ret) 4082 return ret; 4083 4084 dev_info(dev, "\tStrobe range [%d, %d]\n", 4085 ((v >> UB960_XR_SFILTER_CFG_SFILTER_MIN_SHIFT) & 0xf) - 7, 4086 ((v >> UB960_XR_SFILTER_CFG_SFILTER_MAX_SHIFT) & 0xf) - 7); 4087 } 4088 4089 ret = ub960_rxport_get_strobe_pos(priv, nport, &strobe_pos); 4090 if (ret) 4091 return ret; 4092 4093 dev_info(dev, "\tStrobe pos %d\n", strobe_pos); 4094 4095 /* EQ */ 4096 4097 ret = ub960_rxport_read(priv, nport, UB960_RR_AEQ_BYPASS, &v, NULL); 4098 if (ret) 4099 return ret; 4100 4101 dev_info(dev, "\t%s EQ\n", 4102 (v & UB960_RR_AEQ_BYPASS_ENABLE) ? "Manual" : 4103 "Adaptive"); 4104 4105 if (!(v & UB960_RR_AEQ_BYPASS_ENABLE)) { 4106 ret = ub960_rxport_read(priv, nport, UB960_RR_AEQ_MIN_MAX, &v, 4107 NULL); 4108 if (ret) 4109 return ret; 4110 4111 dev_info(dev, "\tEQ range [%u, %u]\n", 4112 (v >> UB960_RR_AEQ_MIN_MAX_AEQ_FLOOR_SHIFT) & 0xf, 4113 (v >> UB960_RR_AEQ_MIN_MAX_AEQ_MAX_SHIFT) & 0xf); 4114 } 4115 4116 ret = ub960_rxport_get_eq_level(priv, nport, &eq_level); 4117 if (ret) 4118 return ret; 4119 4120 dev_info(dev, "\tEQ level %u\n", eq_level); 4121 4122 return 0; 4123 } 4124 4125 static int ub960_log_status(struct v4l2_subdev *sd) 4126 { 4127 struct ub960_data *priv = sd_to_ub960(sd); 4128 struct device *dev = &priv->client->dev; 4129 struct v4l2_subdev_state *state; 4130 u16 v16 = 0; 4131 u8 v = 0; 4132 u8 id[UB960_SR_FPD3_RX_ID_LEN]; 4133 int ret = 0; 4134 4135 state = v4l2_subdev_lock_and_get_active_state(sd); 4136 4137 for (unsigned int i = 0; i < sizeof(id); i++) { 4138 ret = ub960_read(priv, UB960_SR_FPD3_RX_ID(i), &id[i], NULL); 4139 if (ret) 4140 return ret; 4141 } 4142 4143 dev_info(dev, "ID '%.*s'\n", (int)sizeof(id), id); 4144 4145 for (unsigned int nport = 0; nport < priv->hw_data->num_txports; 4146 nport++) { 4147 struct ub960_txport *txport = priv->txports[nport]; 4148 4149 dev_info(dev, "TX %u\n", nport); 4150 4151 if (!txport) { 4152 dev_info(dev, "\tNot initialized\n"); 4153 continue; 4154 } 4155 4156 ret = ub960_txport_read(priv, nport, UB960_TR_CSI_STS, &v, NULL); 4157 if (ret) 4158 return ret; 4159 4160 dev_info(dev, "\tsync %u, pass %u\n", v & (u8)BIT(1), 4161 v & (u8)BIT(0)); 4162 4163 ret = ub960_read16(priv, UB960_SR_CSI_FRAME_COUNT_HI(nport), 4164 &v16, NULL); 4165 if (ret) 4166 return ret; 4167 4168 dev_info(dev, "\tframe counter %u\n", v16); 4169 4170 ret = ub960_read16(priv, UB960_SR_CSI_FRAME_ERR_COUNT_HI(nport), 4171 &v16, NULL); 4172 if (ret) 4173 return ret; 4174 4175 dev_info(dev, "\tframe error counter %u\n", v16); 4176 4177 ret = ub960_read16(priv, UB960_SR_CSI_LINE_COUNT_HI(nport), 4178 &v16, NULL); 4179 if (ret) 4180 return ret; 4181 4182 dev_info(dev, "\tline counter %u\n", v16); 4183 4184 ret = ub960_read16(priv, UB960_SR_CSI_LINE_ERR_COUNT_HI(nport), 4185 &v16, NULL); 4186 if (ret) 4187 return ret; 4188 4189 dev_info(dev, "\tline error counter %u\n", v16); 4190 } 4191 4192 for_each_rxport(priv, it) { 4193 unsigned int nport = it.nport; 4194 4195 dev_info(dev, "RX %u\n", nport); 4196 4197 if (!it.rxport) { 4198 dev_info(dev, "\tNot initialized\n"); 4199 continue; 4200 } 4201 4202 ret = ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS1, &v, 4203 NULL); 4204 if (ret) 4205 return ret; 4206 4207 if (v & UB960_RR_RX_PORT_STS1_LOCK_STS) 4208 dev_info(dev, "\tLocked\n"); 4209 else 4210 dev_info(dev, "\tNot locked\n"); 4211 4212 dev_info(dev, "\trx_port_sts1 %#02x\n", v); 4213 ret = ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS2, &v, 4214 NULL); 4215 if (ret) 4216 return ret; 4217 4218 dev_info(dev, "\trx_port_sts2 %#02x\n", v); 4219 4220 ret = ub960_rxport_read16(priv, nport, UB960_RR_RX_FREQ_HIGH, 4221 &v16, NULL); 4222 if (ret) 4223 return ret; 4224 4225 dev_info(dev, "\tlink freq %llu Hz\n", ((u64)v16 * HZ_PER_MHZ) >> 8); 4226 4227 ret = ub960_rxport_read16(priv, nport, UB960_RR_RX_PAR_ERR_HI, 4228 &v16, NULL); 4229 if (ret) 4230 return ret; 4231 4232 dev_info(dev, "\tparity errors %u\n", v16); 4233 4234 ret = ub960_rxport_read16(priv, nport, UB960_RR_LINE_COUNT_HI, 4235 &v16, NULL); 4236 if (ret) 4237 return ret; 4238 4239 dev_info(dev, "\tlines per frame %u\n", v16); 4240 4241 ret = ub960_rxport_read16(priv, nport, UB960_RR_LINE_LEN_1, 4242 &v16, NULL); 4243 if (ret) 4244 return ret; 4245 4246 dev_info(dev, "\tbytes per line %u\n", v16); 4247 4248 ret = ub960_rxport_read(priv, nport, UB960_RR_CSI_ERR_COUNTER, 4249 &v, NULL); 4250 if (ret) 4251 return ret; 4252 4253 dev_info(dev, "\tcsi_err_counter %u\n", v); 4254 4255 if (!priv->hw_data->is_ub9702) { 4256 ret = ub960_log_status_ub960_sp_eq(priv, nport); 4257 if (ret) 4258 return ret; 4259 } 4260 4261 /* GPIOs */ 4262 for (unsigned int i = 0; i < UB960_NUM_BC_GPIOS; i++) { 4263 u8 ctl_reg; 4264 u8 ctl_shift; 4265 4266 ctl_reg = UB960_RR_BC_GPIO_CTL(i / 2); 4267 ctl_shift = (i % 2) * 4; 4268 4269 ret = ub960_rxport_read(priv, nport, ctl_reg, &v, NULL); 4270 if (ret) 4271 return ret; 4272 4273 dev_info(dev, "\tGPIO%u: mode %u\n", i, 4274 (v >> ctl_shift) & 0xf); 4275 } 4276 } 4277 4278 v4l2_subdev_unlock_state(state); 4279 4280 return 0; 4281 } 4282 4283 static const struct v4l2_subdev_core_ops ub960_subdev_core_ops = { 4284 .log_status = ub960_log_status, 4285 }; 4286 4287 static const struct v4l2_subdev_internal_ops ub960_internal_ops = { 4288 .init_state = ub960_init_state, 4289 }; 4290 4291 static const struct v4l2_subdev_ops ub960_subdev_ops = { 4292 .core = &ub960_subdev_core_ops, 4293 .pad = &ub960_pad_ops, 4294 }; 4295 4296 static const struct media_entity_operations ub960_entity_ops = { 4297 .get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1, 4298 .link_validate = v4l2_subdev_link_validate, 4299 .has_pad_interdep = v4l2_subdev_has_pad_interdep, 4300 }; 4301 4302 /* ----------------------------------------------------------------------------- 4303 * Core 4304 */ 4305 4306 static irqreturn_t ub960_handle_events(int irq, void *arg) 4307 { 4308 struct ub960_data *priv = arg; 4309 u8 int_sts; 4310 u8 fwd_sts; 4311 int ret; 4312 4313 ret = ub960_read(priv, UB960_SR_INTERRUPT_STS, &int_sts, NULL); 4314 if (ret || !int_sts) 4315 return IRQ_NONE; 4316 4317 dev_dbg(&priv->client->dev, "INTERRUPT_STS %x\n", int_sts); 4318 4319 ret = ub960_read(priv, UB960_SR_FWD_STS, &fwd_sts, NULL); 4320 if (ret) 4321 return IRQ_NONE; 4322 4323 dev_dbg(&priv->client->dev, "FWD_STS %#02x\n", fwd_sts); 4324 4325 for (unsigned int i = 0; i < priv->hw_data->num_txports; i++) { 4326 if (int_sts & UB960_SR_INTERRUPT_STS_IS_CSI_TX(i)) { 4327 ret = ub960_csi_handle_events(priv, i); 4328 if (ret) 4329 return IRQ_NONE; 4330 } 4331 } 4332 4333 for_each_active_rxport(priv, it) { 4334 if (int_sts & UB960_SR_INTERRUPT_STS_IS_RX(it.nport)) { 4335 ret = ub960_rxport_handle_events(priv, it.nport); 4336 if (ret) 4337 return IRQ_NONE; 4338 } 4339 } 4340 4341 return IRQ_HANDLED; 4342 } 4343 4344 static void ub960_handler_work(struct work_struct *work) 4345 { 4346 struct delayed_work *dwork = to_delayed_work(work); 4347 struct ub960_data *priv = 4348 container_of(dwork, struct ub960_data, poll_work); 4349 4350 ub960_handle_events(0, priv); 4351 4352 schedule_delayed_work(&priv->poll_work, 4353 msecs_to_jiffies(UB960_POLL_TIME_MS)); 4354 } 4355 4356 static void ub960_txport_free_ports(struct ub960_data *priv) 4357 { 4358 unsigned int nport; 4359 4360 for (nport = 0; nport < priv->hw_data->num_txports; nport++) { 4361 struct ub960_txport *txport = priv->txports[nport]; 4362 4363 if (!txport) 4364 continue; 4365 4366 kfree(txport); 4367 priv->txports[nport] = NULL; 4368 } 4369 } 4370 4371 static void ub960_rxport_free_ports(struct ub960_data *priv) 4372 { 4373 for_each_active_rxport(priv, it) { 4374 fwnode_handle_put(it.rxport->source.ep_fwnode); 4375 fwnode_handle_put(it.rxport->ser.fwnode); 4376 4377 kfree(it.rxport); 4378 priv->rxports[it.nport] = NULL; 4379 } 4380 } 4381 4382 static int 4383 ub960_parse_dt_rxport_link_properties(struct ub960_data *priv, 4384 struct fwnode_handle *link_fwnode, 4385 struct ub960_rxport *rxport) 4386 { 4387 struct device *dev = &priv->client->dev; 4388 unsigned int nport = rxport->nport; 4389 u32 rx_mode; 4390 u32 cdr_mode; 4391 s32 strobe_pos; 4392 u32 eq_level; 4393 u32 ser_i2c_alias; 4394 u32 ser_i2c_addr; 4395 int ret; 4396 4397 cdr_mode = RXPORT_CDR_FPD3; 4398 4399 ret = fwnode_property_read_u32(link_fwnode, "ti,cdr-mode", &cdr_mode); 4400 if (ret < 0 && ret != -EINVAL) { 4401 dev_err(dev, "rx%u: failed to read '%s': %d\n", nport, 4402 "ti,cdr-mode", ret); 4403 return ret; 4404 } 4405 4406 if (cdr_mode > RXPORT_CDR_LAST) { 4407 dev_err(dev, "rx%u: bad 'ti,cdr-mode' %u\n", nport, cdr_mode); 4408 return -EINVAL; 4409 } 4410 4411 if (!priv->hw_data->is_fpdlink4 && cdr_mode == RXPORT_CDR_FPD4) { 4412 dev_err(dev, "rx%u: FPD-Link 4 CDR not supported\n", nport); 4413 return -EINVAL; 4414 } 4415 4416 rxport->cdr_mode = cdr_mode; 4417 4418 ret = fwnode_property_read_u32(link_fwnode, "ti,rx-mode", &rx_mode); 4419 if (ret < 0) { 4420 dev_err(dev, "rx%u: failed to read '%s': %d\n", nport, 4421 "ti,rx-mode", ret); 4422 return ret; 4423 } 4424 4425 if (rx_mode > RXPORT_MODE_LAST) { 4426 dev_err(dev, "rx%u: bad 'ti,rx-mode' %u\n", nport, rx_mode); 4427 return -EINVAL; 4428 } 4429 4430 switch (rx_mode) { 4431 case RXPORT_MODE_RAW12_HF: 4432 case RXPORT_MODE_RAW12_LF: 4433 dev_err(dev, "rx%u: unsupported 'ti,rx-mode' %u\n", nport, 4434 rx_mode); 4435 return -EINVAL; 4436 default: 4437 break; 4438 } 4439 4440 rxport->rx_mode = rx_mode; 4441 4442 /* EQ & Strobe related */ 4443 4444 /* Defaults */ 4445 rxport->eq.manual_eq = false; 4446 rxport->eq.aeq.eq_level_min = UB960_MIN_EQ_LEVEL; 4447 rxport->eq.aeq.eq_level_max = UB960_MAX_EQ_LEVEL; 4448 4449 ret = fwnode_property_read_u32(link_fwnode, "ti,strobe-pos", 4450 &strobe_pos); 4451 if (ret) { 4452 if (ret != -EINVAL) { 4453 dev_err(dev, "rx%u: failed to read '%s': %d\n", nport, 4454 "ti,strobe-pos", ret); 4455 return ret; 4456 } 4457 } else { 4458 if (strobe_pos < UB960_MIN_MANUAL_STROBE_POS || 4459 strobe_pos > UB960_MAX_MANUAL_STROBE_POS) { 4460 dev_err(dev, "rx%u: illegal 'strobe-pos' value: %d\n", 4461 nport, strobe_pos); 4462 return -EINVAL; 4463 } 4464 4465 /* NOTE: ignored unless global manual strobe pos is also set */ 4466 rxport->eq.strobe_pos = strobe_pos; 4467 if (!priv->strobe.manual) 4468 dev_warn(dev, 4469 "rx%u: 'ti,strobe-pos' ignored as 'ti,manual-strobe' not set\n", 4470 nport); 4471 } 4472 4473 ret = fwnode_property_read_u32(link_fwnode, "ti,eq-level", &eq_level); 4474 if (ret) { 4475 if (ret != -EINVAL) { 4476 dev_err(dev, "rx%u: failed to read '%s': %d\n", nport, 4477 "ti,eq-level", ret); 4478 return ret; 4479 } 4480 } else { 4481 if (eq_level > UB960_MAX_EQ_LEVEL) { 4482 dev_err(dev, "rx%u: illegal 'ti,eq-level' value: %d\n", 4483 nport, eq_level); 4484 return -EINVAL; 4485 } 4486 4487 rxport->eq.manual_eq = true; 4488 rxport->eq.manual.eq_level = eq_level; 4489 } 4490 4491 ret = fwnode_property_read_u32(link_fwnode, "i2c-alias", 4492 &ser_i2c_alias); 4493 if (ret) { 4494 dev_err(dev, "rx%u: failed to read '%s': %d\n", nport, 4495 "i2c-alias", ret); 4496 return ret; 4497 } 4498 rxport->ser.alias = ser_i2c_alias; 4499 4500 rxport->ser.fwnode = fwnode_get_named_child_node(link_fwnode, "serializer"); 4501 if (!rxport->ser.fwnode) { 4502 dev_err(dev, "rx%u: missing 'serializer' node\n", nport); 4503 return -EINVAL; 4504 } 4505 4506 ret = fwnode_property_read_u32(rxport->ser.fwnode, "reg", 4507 &ser_i2c_addr); 4508 if (ret) 4509 rxport->ser.addr = -EINVAL; 4510 else 4511 rxport->ser.addr = ser_i2c_addr; 4512 4513 return 0; 4514 } 4515 4516 static int ub960_parse_dt_rxport_ep_properties(struct ub960_data *priv, 4517 struct fwnode_handle *ep_fwnode, 4518 struct ub960_rxport *rxport) 4519 { 4520 struct device *dev = &priv->client->dev; 4521 struct v4l2_fwnode_endpoint vep = {}; 4522 unsigned int nport = rxport->nport; 4523 bool hsync_hi; 4524 bool vsync_hi; 4525 int ret; 4526 4527 rxport->source.ep_fwnode = fwnode_graph_get_remote_endpoint(ep_fwnode); 4528 if (!rxport->source.ep_fwnode) { 4529 dev_err(dev, "rx%u: no remote endpoint\n", nport); 4530 return -ENODEV; 4531 } 4532 4533 /* We currently have properties only for RAW modes */ 4534 4535 switch (rxport->rx_mode) { 4536 case RXPORT_MODE_RAW10: 4537 case RXPORT_MODE_RAW12_HF: 4538 case RXPORT_MODE_RAW12_LF: 4539 break; 4540 default: 4541 return 0; 4542 } 4543 4544 vep.bus_type = V4L2_MBUS_PARALLEL; 4545 ret = v4l2_fwnode_endpoint_parse(ep_fwnode, &vep); 4546 if (ret) { 4547 dev_err(dev, "rx%u: failed to parse endpoint data\n", nport); 4548 goto err_put_source_ep_fwnode; 4549 } 4550 4551 hsync_hi = !!(vep.bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH); 4552 vsync_hi = !!(vep.bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH); 4553 4554 /* LineValid and FrameValid are inverse to the h/vsync active */ 4555 rxport->lv_fv_pol = (hsync_hi ? UB960_RR_PORT_CONFIG2_LV_POL_LOW : 0) | 4556 (vsync_hi ? UB960_RR_PORT_CONFIG2_FV_POL_LOW : 0); 4557 4558 return 0; 4559 4560 err_put_source_ep_fwnode: 4561 fwnode_handle_put(rxport->source.ep_fwnode); 4562 return ret; 4563 } 4564 4565 static int ub960_parse_dt_rxport(struct ub960_data *priv, unsigned int nport, 4566 struct fwnode_handle *link_fwnode, 4567 struct fwnode_handle *ep_fwnode) 4568 { 4569 static const char *vpoc_names[UB960_MAX_RX_NPORTS] = { 4570 "vpoc0", "vpoc1", "vpoc2", "vpoc3" 4571 }; 4572 struct device *dev = &priv->client->dev; 4573 struct ub960_rxport *rxport; 4574 int ret; 4575 4576 rxport = kzalloc(sizeof(*rxport), GFP_KERNEL); 4577 if (!rxport) 4578 return -ENOMEM; 4579 4580 priv->rxports[nport] = rxport; 4581 4582 rxport->nport = nport; 4583 rxport->priv = priv; 4584 4585 ret = ub960_parse_dt_rxport_link_properties(priv, link_fwnode, rxport); 4586 if (ret) 4587 goto err_free_rxport; 4588 4589 rxport->vpoc = devm_regulator_get_optional(dev, vpoc_names[nport]); 4590 if (IS_ERR(rxport->vpoc)) { 4591 ret = PTR_ERR(rxport->vpoc); 4592 if (ret == -ENODEV) { 4593 rxport->vpoc = NULL; 4594 } else { 4595 dev_err(dev, "rx%u: failed to get VPOC supply: %d\n", 4596 nport, ret); 4597 goto err_put_remote_fwnode; 4598 } 4599 } 4600 4601 ret = ub960_parse_dt_rxport_ep_properties(priv, ep_fwnode, rxport); 4602 if (ret) 4603 goto err_put_remote_fwnode; 4604 4605 return 0; 4606 4607 err_put_remote_fwnode: 4608 fwnode_handle_put(rxport->ser.fwnode); 4609 err_free_rxport: 4610 priv->rxports[nport] = NULL; 4611 kfree(rxport); 4612 return ret; 4613 } 4614 4615 static struct fwnode_handle * 4616 ub960_fwnode_get_link_by_regs(struct fwnode_handle *links_fwnode, 4617 unsigned int nport) 4618 { 4619 struct fwnode_handle *link_fwnode; 4620 int ret; 4621 4622 fwnode_for_each_child_node(links_fwnode, link_fwnode) { 4623 u32 link_num; 4624 4625 if (!str_has_prefix(fwnode_get_name(link_fwnode), "link@")) 4626 continue; 4627 4628 ret = fwnode_property_read_u32(link_fwnode, "reg", &link_num); 4629 if (ret) { 4630 fwnode_handle_put(link_fwnode); 4631 return NULL; 4632 } 4633 4634 if (nport == link_num) 4635 return link_fwnode; 4636 } 4637 4638 return NULL; 4639 } 4640 4641 static int ub960_parse_dt_rxports(struct ub960_data *priv) 4642 { 4643 struct device *dev = &priv->client->dev; 4644 struct fwnode_handle *links_fwnode; 4645 int ret; 4646 4647 links_fwnode = fwnode_get_named_child_node(dev_fwnode(dev), "links"); 4648 if (!links_fwnode) { 4649 dev_err(dev, "'links' node missing\n"); 4650 return -ENODEV; 4651 } 4652 4653 /* Defaults, recommended by TI */ 4654 priv->strobe.min = 2; 4655 priv->strobe.max = 3; 4656 4657 priv->strobe.manual = fwnode_property_read_bool(links_fwnode, "ti,manual-strobe"); 4658 4659 for_each_rxport(priv, it) { 4660 struct fwnode_handle *link_fwnode; 4661 struct fwnode_handle *ep_fwnode; 4662 unsigned int nport = it.nport; 4663 4664 link_fwnode = ub960_fwnode_get_link_by_regs(links_fwnode, nport); 4665 if (!link_fwnode) 4666 continue; 4667 4668 ep_fwnode = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 4669 nport, 0, 0); 4670 if (!ep_fwnode) { 4671 fwnode_handle_put(link_fwnode); 4672 continue; 4673 } 4674 4675 ret = ub960_parse_dt_rxport(priv, nport, link_fwnode, 4676 ep_fwnode); 4677 4678 fwnode_handle_put(link_fwnode); 4679 fwnode_handle_put(ep_fwnode); 4680 4681 if (ret) { 4682 dev_err(dev, "rx%u: failed to parse RX port\n", nport); 4683 goto err_put_links; 4684 } 4685 } 4686 4687 fwnode_handle_put(links_fwnode); 4688 4689 return 0; 4690 4691 err_put_links: 4692 fwnode_handle_put(links_fwnode); 4693 4694 return ret; 4695 } 4696 4697 static int ub960_parse_dt_txports(struct ub960_data *priv) 4698 { 4699 struct device *dev = &priv->client->dev; 4700 u32 nport; 4701 int ret; 4702 4703 for (nport = 0; nport < priv->hw_data->num_txports; nport++) { 4704 unsigned int port = nport + priv->hw_data->num_rxports; 4705 struct fwnode_handle *ep_fwnode; 4706 4707 ep_fwnode = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 4708 port, 0, 0); 4709 if (!ep_fwnode) 4710 continue; 4711 4712 ret = ub960_parse_dt_txport(priv, ep_fwnode, nport); 4713 4714 fwnode_handle_put(ep_fwnode); 4715 4716 if (ret) 4717 break; 4718 } 4719 4720 return 0; 4721 } 4722 4723 static int ub960_parse_dt(struct ub960_data *priv) 4724 { 4725 int ret; 4726 4727 ret = ub960_parse_dt_rxports(priv); 4728 if (ret) 4729 return ret; 4730 4731 ret = ub960_parse_dt_txports(priv); 4732 if (ret) 4733 goto err_free_rxports; 4734 4735 return 0; 4736 4737 err_free_rxports: 4738 ub960_rxport_free_ports(priv); 4739 4740 return ret; 4741 } 4742 4743 static int ub960_notify_bound(struct v4l2_async_notifier *notifier, 4744 struct v4l2_subdev *subdev, 4745 struct v4l2_async_connection *asd) 4746 { 4747 struct ub960_data *priv = sd_to_ub960(notifier->sd); 4748 struct ub960_rxport *rxport = to_ub960_asd(asd)->rxport; 4749 struct device *dev = &priv->client->dev; 4750 u8 nport = rxport->nport; 4751 int ret; 4752 4753 ret = media_entity_get_fwnode_pad(&subdev->entity, 4754 rxport->source.ep_fwnode, 4755 MEDIA_PAD_FL_SOURCE); 4756 if (ret < 0) { 4757 dev_err(dev, "Failed to find pad for %s\n", subdev->name); 4758 return ret; 4759 } 4760 4761 rxport->source.sd = subdev; 4762 rxport->source.pad = ret; 4763 4764 ret = media_create_pad_link(&rxport->source.sd->entity, 4765 rxport->source.pad, &priv->sd.entity, nport, 4766 MEDIA_LNK_FL_ENABLED | 4767 MEDIA_LNK_FL_IMMUTABLE); 4768 if (ret) { 4769 dev_err(dev, "Unable to link %s:%u -> %s:%u\n", 4770 rxport->source.sd->name, rxport->source.pad, 4771 priv->sd.name, nport); 4772 return ret; 4773 } 4774 4775 for_each_active_rxport(priv, it) { 4776 if (!it.rxport->source.sd) { 4777 dev_dbg(dev, "Waiting for more subdevs to be bound\n"); 4778 return 0; 4779 } 4780 } 4781 4782 return 0; 4783 } 4784 4785 static void ub960_notify_unbind(struct v4l2_async_notifier *notifier, 4786 struct v4l2_subdev *subdev, 4787 struct v4l2_async_connection *asd) 4788 { 4789 struct ub960_rxport *rxport = to_ub960_asd(asd)->rxport; 4790 4791 rxport->source.sd = NULL; 4792 } 4793 4794 static const struct v4l2_async_notifier_operations ub960_notify_ops = { 4795 .bound = ub960_notify_bound, 4796 .unbind = ub960_notify_unbind, 4797 }; 4798 4799 static int ub960_v4l2_notifier_register(struct ub960_data *priv) 4800 { 4801 struct device *dev = &priv->client->dev; 4802 int ret; 4803 4804 v4l2_async_subdev_nf_init(&priv->notifier, &priv->sd); 4805 4806 for_each_active_rxport(priv, it) { 4807 struct ub960_asd *asd; 4808 4809 asd = v4l2_async_nf_add_fwnode(&priv->notifier, 4810 it.rxport->source.ep_fwnode, 4811 struct ub960_asd); 4812 if (IS_ERR(asd)) { 4813 dev_err(dev, "Failed to add subdev for source %u: %pe", 4814 it.nport, asd); 4815 v4l2_async_nf_cleanup(&priv->notifier); 4816 return PTR_ERR(asd); 4817 } 4818 4819 asd->rxport = it.rxport; 4820 } 4821 4822 priv->notifier.ops = &ub960_notify_ops; 4823 4824 ret = v4l2_async_nf_register(&priv->notifier); 4825 if (ret) { 4826 dev_err(dev, "Failed to register subdev_notifier"); 4827 v4l2_async_nf_cleanup(&priv->notifier); 4828 return ret; 4829 } 4830 4831 return 0; 4832 } 4833 4834 static void ub960_v4l2_notifier_unregister(struct ub960_data *priv) 4835 { 4836 v4l2_async_nf_unregister(&priv->notifier); 4837 v4l2_async_nf_cleanup(&priv->notifier); 4838 } 4839 4840 static int ub960_create_subdev(struct ub960_data *priv) 4841 { 4842 struct device *dev = &priv->client->dev; 4843 unsigned int i; 4844 int ret; 4845 4846 v4l2_i2c_subdev_init(&priv->sd, priv->client, &ub960_subdev_ops); 4847 priv->sd.internal_ops = &ub960_internal_ops; 4848 4849 v4l2_ctrl_handler_init(&priv->ctrl_handler, 1); 4850 priv->sd.ctrl_handler = &priv->ctrl_handler; 4851 4852 v4l2_ctrl_new_int_menu(&priv->ctrl_handler, NULL, V4L2_CID_LINK_FREQ, 4853 ARRAY_SIZE(priv->tx_link_freq) - 1, 0, 4854 priv->tx_link_freq); 4855 4856 if (priv->ctrl_handler.error) { 4857 ret = priv->ctrl_handler.error; 4858 goto err_free_ctrl; 4859 } 4860 4861 priv->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | 4862 V4L2_SUBDEV_FL_STREAMS; 4863 priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 4864 priv->sd.entity.ops = &ub960_entity_ops; 4865 4866 for (i = 0; i < priv->hw_data->num_rxports + priv->hw_data->num_txports; i++) { 4867 priv->pads[i].flags = ub960_pad_is_sink(priv, i) ? 4868 MEDIA_PAD_FL_SINK : 4869 MEDIA_PAD_FL_SOURCE; 4870 } 4871 4872 ret = media_entity_pads_init(&priv->sd.entity, 4873 priv->hw_data->num_rxports + 4874 priv->hw_data->num_txports, 4875 priv->pads); 4876 if (ret) 4877 goto err_free_ctrl; 4878 4879 priv->sd.state_lock = priv->sd.ctrl_handler->lock; 4880 4881 ret = v4l2_subdev_init_finalize(&priv->sd); 4882 if (ret) 4883 goto err_entity_cleanup; 4884 4885 ret = ub960_v4l2_notifier_register(priv); 4886 if (ret) { 4887 dev_err(dev, "v4l2 subdev notifier register failed: %d\n", ret); 4888 goto err_subdev_cleanup; 4889 } 4890 4891 ret = v4l2_async_register_subdev(&priv->sd); 4892 if (ret) { 4893 dev_err(dev, "v4l2_async_register_subdev error: %d\n", ret); 4894 goto err_unreg_notif; 4895 } 4896 4897 return 0; 4898 4899 err_unreg_notif: 4900 ub960_v4l2_notifier_unregister(priv); 4901 err_subdev_cleanup: 4902 v4l2_subdev_cleanup(&priv->sd); 4903 err_entity_cleanup: 4904 media_entity_cleanup(&priv->sd.entity); 4905 err_free_ctrl: 4906 v4l2_ctrl_handler_free(&priv->ctrl_handler); 4907 4908 return ret; 4909 } 4910 4911 static void ub960_destroy_subdev(struct ub960_data *priv) 4912 { 4913 ub960_v4l2_notifier_unregister(priv); 4914 v4l2_async_unregister_subdev(&priv->sd); 4915 4916 v4l2_subdev_cleanup(&priv->sd); 4917 4918 media_entity_cleanup(&priv->sd.entity); 4919 v4l2_ctrl_handler_free(&priv->ctrl_handler); 4920 } 4921 4922 static const struct regmap_config ub960_regmap_config = { 4923 .name = "ds90ub960", 4924 4925 .reg_bits = 8, 4926 .val_bits = 8, 4927 4928 .max_register = 0xff, 4929 4930 /* 4931 * We do locking in the driver to cover the TX/RX port selection and the 4932 * indirect register access. 4933 */ 4934 .disable_locking = true, 4935 }; 4936 4937 static int ub960_get_hw_resources(struct ub960_data *priv) 4938 { 4939 struct device *dev = &priv->client->dev; 4940 4941 priv->regmap = devm_regmap_init_i2c(priv->client, &ub960_regmap_config); 4942 if (IS_ERR(priv->regmap)) 4943 return PTR_ERR(priv->regmap); 4944 4945 priv->vddio = devm_regulator_get(dev, "vddio"); 4946 if (IS_ERR(priv->vddio)) 4947 return dev_err_probe(dev, PTR_ERR(priv->vddio), 4948 "cannot get VDDIO regulator\n"); 4949 4950 /* get power-down pin from DT */ 4951 priv->pd_gpio = 4952 devm_gpiod_get_optional(dev, "powerdown", GPIOD_OUT_HIGH); 4953 if (IS_ERR(priv->pd_gpio)) 4954 return dev_err_probe(dev, PTR_ERR(priv->pd_gpio), 4955 "Cannot get powerdown GPIO\n"); 4956 4957 priv->refclk = devm_clk_get(dev, "refclk"); 4958 if (IS_ERR(priv->refclk)) 4959 return dev_err_probe(dev, PTR_ERR(priv->refclk), 4960 "Cannot get REFCLK\n"); 4961 4962 return 0; 4963 } 4964 4965 static int ub960_enable_core_hw(struct ub960_data *priv) 4966 { 4967 struct device *dev = &priv->client->dev; 4968 u8 rev_mask; 4969 int ret; 4970 u8 dev_sts; 4971 u8 refclk_freq; 4972 4973 ret = regulator_enable(priv->vddio); 4974 if (ret) 4975 return dev_err_probe(dev, ret, 4976 "failed to enable VDDIO regulator\n"); 4977 4978 ret = clk_prepare_enable(priv->refclk); 4979 if (ret) { 4980 dev_err_probe(dev, ret, "Failed to enable refclk\n"); 4981 goto err_disable_vddio; 4982 } 4983 4984 if (priv->pd_gpio) { 4985 gpiod_set_value_cansleep(priv->pd_gpio, 1); 4986 /* wait min 2 ms for reset to complete */ 4987 fsleep(2000); 4988 gpiod_set_value_cansleep(priv->pd_gpio, 0); 4989 /* wait min 2 ms for power up to finish */ 4990 fsleep(2000); 4991 } 4992 4993 ret = ub960_reset(priv, true); 4994 if (ret) 4995 goto err_pd_gpio; 4996 4997 /* Runtime check register accessibility */ 4998 ret = ub960_read(priv, UB960_SR_REV_MASK, &rev_mask, NULL); 4999 if (ret) { 5000 dev_err_probe(dev, ret, "Cannot read first register, abort\n"); 5001 goto err_pd_gpio; 5002 } 5003 5004 dev_dbg(dev, "Found %s (rev/mask %#04x)\n", priv->hw_data->model, 5005 rev_mask); 5006 5007 ret = ub960_read(priv, UB960_SR_DEVICE_STS, &dev_sts, NULL); 5008 if (ret) 5009 goto err_pd_gpio; 5010 5011 if (priv->hw_data->is_ub9702) 5012 ret = ub960_read(priv, UB9702_SR_REFCLK_FREQ, &refclk_freq, 5013 NULL); 5014 else 5015 ret = ub960_read(priv, UB960_XR_REFCLK_FREQ, &refclk_freq, 5016 NULL); 5017 if (ret) 5018 goto err_pd_gpio; 5019 5020 dev_dbg(dev, "refclk valid %u freq %u MHz (clk fw freq %lu MHz)\n", 5021 !!(dev_sts & BIT(4)), refclk_freq, 5022 clk_get_rate(priv->refclk) / HZ_PER_MHZ); 5023 5024 /* Disable all RX ports by default */ 5025 ret = ub960_write(priv, UB960_SR_RX_PORT_CTL, 0, NULL); 5026 if (ret) 5027 goto err_pd_gpio; 5028 5029 /* release GPIO lock */ 5030 if (priv->hw_data->is_ub9702) { 5031 ret = ub960_update_bits(priv, UB960_SR_RESET, 5032 UB960_SR_RESET_GPIO_LOCK_RELEASE, 5033 UB960_SR_RESET_GPIO_LOCK_RELEASE, 5034 NULL); 5035 if (ret) 5036 goto err_pd_gpio; 5037 } 5038 5039 return 0; 5040 5041 err_pd_gpio: 5042 gpiod_set_value_cansleep(priv->pd_gpio, 1); 5043 clk_disable_unprepare(priv->refclk); 5044 err_disable_vddio: 5045 regulator_disable(priv->vddio); 5046 5047 return ret; 5048 } 5049 5050 static void ub960_disable_core_hw(struct ub960_data *priv) 5051 { 5052 gpiod_set_value_cansleep(priv->pd_gpio, 1); 5053 clk_disable_unprepare(priv->refclk); 5054 regulator_disable(priv->vddio); 5055 } 5056 5057 static int ub960_probe(struct i2c_client *client) 5058 { 5059 struct device *dev = &client->dev; 5060 struct ub960_data *priv; 5061 int ret; 5062 5063 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 5064 if (!priv) 5065 return -ENOMEM; 5066 5067 priv->client = client; 5068 5069 priv->hw_data = device_get_match_data(dev); 5070 5071 mutex_init(&priv->reg_lock); 5072 5073 INIT_DELAYED_WORK(&priv->poll_work, ub960_handler_work); 5074 5075 /* 5076 * Initialize these to invalid values so that the first reg writes will 5077 * configure the target. 5078 */ 5079 priv->reg_current.indirect_target = 0xff; 5080 priv->reg_current.rxport = 0xff; 5081 priv->reg_current.txport = 0xff; 5082 5083 ret = ub960_get_hw_resources(priv); 5084 if (ret) 5085 goto err_mutex_destroy; 5086 5087 ret = ub960_enable_core_hw(priv); 5088 if (ret) 5089 goto err_mutex_destroy; 5090 5091 ret = ub960_parse_dt(priv); 5092 if (ret) 5093 goto err_disable_core_hw; 5094 5095 ret = ub960_init_tx_ports(priv); 5096 if (ret) 5097 goto err_free_ports; 5098 5099 ret = ub960_rxport_enable_vpocs(priv); 5100 if (ret) 5101 goto err_free_ports; 5102 5103 if (priv->hw_data->is_ub9702) 5104 ret = ub960_init_rx_ports_ub9702(priv); 5105 else 5106 ret = ub960_init_rx_ports_ub960(priv); 5107 5108 if (ret) 5109 goto err_disable_vpocs; 5110 5111 ret = ub960_init_atr(priv); 5112 if (ret) 5113 goto err_disable_vpocs; 5114 5115 ret = ub960_rxport_add_serializers(priv); 5116 if (ret) 5117 goto err_uninit_atr; 5118 5119 ret = ub960_create_subdev(priv); 5120 if (ret) 5121 goto err_free_sers; 5122 5123 if (client->irq) 5124 dev_warn(dev, "irq support not implemented, using polling\n"); 5125 5126 schedule_delayed_work(&priv->poll_work, 5127 msecs_to_jiffies(UB960_POLL_TIME_MS)); 5128 5129 #ifdef UB960_DEBUG_I2C_RX_ID 5130 for_each_rxport(priv, it) 5131 ub960_write(priv, UB960_SR_I2C_RX_ID(it.nport), 5132 (UB960_DEBUG_I2C_RX_ID + it.nport) << 1, NULL); 5133 #endif 5134 5135 return 0; 5136 5137 err_free_sers: 5138 ub960_rxport_remove_serializers(priv); 5139 err_uninit_atr: 5140 ub960_uninit_atr(priv); 5141 err_disable_vpocs: 5142 ub960_rxport_disable_vpocs(priv); 5143 err_free_ports: 5144 ub960_rxport_free_ports(priv); 5145 ub960_txport_free_ports(priv); 5146 err_disable_core_hw: 5147 ub960_disable_core_hw(priv); 5148 err_mutex_destroy: 5149 mutex_destroy(&priv->reg_lock); 5150 return ret; 5151 } 5152 5153 static void ub960_remove(struct i2c_client *client) 5154 { 5155 struct v4l2_subdev *sd = i2c_get_clientdata(client); 5156 struct ub960_data *priv = sd_to_ub960(sd); 5157 5158 cancel_delayed_work_sync(&priv->poll_work); 5159 5160 ub960_destroy_subdev(priv); 5161 ub960_rxport_remove_serializers(priv); 5162 ub960_uninit_atr(priv); 5163 ub960_rxport_disable_vpocs(priv); 5164 ub960_rxport_free_ports(priv); 5165 ub960_txport_free_ports(priv); 5166 ub960_disable_core_hw(priv); 5167 mutex_destroy(&priv->reg_lock); 5168 } 5169 5170 static const struct ub960_hw_data ds90ub960_hw = { 5171 .model = "ub960", 5172 .num_rxports = 4, 5173 .num_txports = 2, 5174 }; 5175 5176 static const struct ub960_hw_data ds90ub9702_hw = { 5177 .model = "ub9702", 5178 .num_rxports = 4, 5179 .num_txports = 2, 5180 .is_ub9702 = true, 5181 .is_fpdlink4 = true, 5182 }; 5183 5184 static const struct i2c_device_id ub960_id[] = { 5185 { "ds90ub960-q1", (kernel_ulong_t)&ds90ub960_hw }, 5186 { "ds90ub9702-q1", (kernel_ulong_t)&ds90ub9702_hw }, 5187 {} 5188 }; 5189 MODULE_DEVICE_TABLE(i2c, ub960_id); 5190 5191 static const struct of_device_id ub960_dt_ids[] = { 5192 { .compatible = "ti,ds90ub960-q1", .data = &ds90ub960_hw }, 5193 { .compatible = "ti,ds90ub9702-q1", .data = &ds90ub9702_hw }, 5194 {} 5195 }; 5196 MODULE_DEVICE_TABLE(of, ub960_dt_ids); 5197 5198 static struct i2c_driver ds90ub960_driver = { 5199 .probe = ub960_probe, 5200 .remove = ub960_remove, 5201 .id_table = ub960_id, 5202 .driver = { 5203 .name = "ds90ub960", 5204 .of_match_table = ub960_dt_ids, 5205 }, 5206 }; 5207 module_i2c_driver(ds90ub960_driver); 5208 5209 MODULE_LICENSE("GPL"); 5210 MODULE_DESCRIPTION("Texas Instruments FPD-Link III/IV Deserializers Driver"); 5211 MODULE_AUTHOR("Luca Ceresoli <luca@lucaceresoli.net>"); 5212 MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>"); 5213 MODULE_IMPORT_NS("I2C_ATR"); 5214