1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the Texas Instruments DS90UB953 video serializer 4 * 5 * Based on a driver from Luca Ceresoli <luca@lucaceresoli.net> 6 * 7 * Copyright (c) 2019 Luca Ceresoli <luca@lucaceresoli.net> 8 * Copyright (c) 2023 Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> 9 */ 10 11 #include <linux/clk-provider.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/gpio/driver.h> 15 #include <linux/i2c-atr.h> 16 #include <linux/i2c.h> 17 #include <linux/kernel.h> 18 #include <linux/math64.h> 19 #include <linux/module.h> 20 #include <linux/property.h> 21 #include <linux/rational.h> 22 #include <linux/regmap.h> 23 24 #include <media/i2c/ds90ub9xx.h> 25 #include <media/v4l2-ctrls.h> 26 #include <media/v4l2-fwnode.h> 27 #include <media/v4l2-mediabus.h> 28 #include <media/v4l2-subdev.h> 29 30 #include "ds90ub953.h" 31 32 #define UB953_PAD_SINK 0 33 #define UB953_PAD_SOURCE 1 34 35 #define UB953_NUM_GPIOS 4 36 37 #define UB953_DEFAULT_CLKOUT_RATE 25000000UL 38 39 /* Note: Only sync mode supported for now */ 40 enum ub953_mode { 41 /* FPD-Link III CSI-2 synchronous mode */ 42 UB953_MODE_SYNC, 43 /* FPD-Link III CSI-2 non-synchronous mode, external ref clock */ 44 UB953_MODE_NONSYNC_EXT, 45 /* FPD-Link III CSI-2 non-synchronous mode, internal ref clock */ 46 UB953_MODE_NONSYNC_INT, 47 /* FPD-Link III DVP mode */ 48 UB953_MODE_DVP, 49 }; 50 51 struct ub953_hw_data { 52 const char *model; 53 bool is_ub971; 54 }; 55 56 struct ub953_clkout_data { 57 u32 hs_div; 58 u32 m; 59 u32 n; 60 unsigned long rate; 61 }; 62 63 struct ub953_data { 64 const struct ub953_hw_data *hw_data; 65 66 struct i2c_client *client; 67 struct regmap *regmap; 68 struct clk *clkin; 69 70 u32 num_data_lanes; 71 bool non_continous_clk; 72 73 struct gpio_chip gpio_chip; 74 75 struct v4l2_subdev sd; 76 struct media_pad pads[2]; 77 78 struct v4l2_async_notifier notifier; 79 80 struct v4l2_subdev *source_sd; 81 u16 source_sd_pad; 82 83 u64 enabled_source_streams; 84 85 /* lock for register access */ 86 struct mutex reg_lock; 87 88 u8 current_indirect_target; 89 90 struct clk_hw clkout_clk_hw; 91 92 enum ub953_mode mode; 93 94 const struct ds90ub9xx_platform_data *plat_data; 95 }; 96 97 static inline struct ub953_data *sd_to_ub953(struct v4l2_subdev *sd) 98 { 99 return container_of(sd, struct ub953_data, sd); 100 } 101 102 /* 103 * HW Access 104 */ 105 106 static int ub953_read(struct ub953_data *priv, u8 reg, u8 *val, int *err) 107 { 108 unsigned int v; 109 int ret; 110 111 if (err && *err) 112 return *err; 113 114 mutex_lock(&priv->reg_lock); 115 116 ret = regmap_read(priv->regmap, reg, &v); 117 if (ret) { 118 dev_err(&priv->client->dev, "Cannot read register 0x%02x: %d\n", 119 reg, ret); 120 goto out_unlock; 121 } 122 123 *val = v; 124 125 out_unlock: 126 mutex_unlock(&priv->reg_lock); 127 128 if (ret && err) 129 *err = ret; 130 131 return ret; 132 } 133 134 static int ub953_write(struct ub953_data *priv, u8 reg, u8 val, int *err) 135 { 136 int ret; 137 138 if (err && *err) 139 return *err; 140 141 mutex_lock(&priv->reg_lock); 142 143 ret = regmap_write(priv->regmap, reg, val); 144 if (ret) 145 dev_err(&priv->client->dev, 146 "Cannot write register 0x%02x: %d\n", reg, ret); 147 148 mutex_unlock(&priv->reg_lock); 149 150 if (ret && err) 151 *err = ret; 152 153 return ret; 154 } 155 156 static int ub953_select_ind_reg_block(struct ub953_data *priv, u8 block) 157 { 158 struct device *dev = &priv->client->dev; 159 int ret; 160 161 if (priv->current_indirect_target == block) 162 return 0; 163 164 ret = regmap_write(priv->regmap, UB953_REG_IND_ACC_CTL, block << 2); 165 if (ret) { 166 dev_err(dev, "%s: cannot select indirect target %u (%d)\n", 167 __func__, block, ret); 168 return ret; 169 } 170 171 priv->current_indirect_target = block; 172 173 return 0; 174 } 175 176 __maybe_unused 177 static int ub953_read_ind(struct ub953_data *priv, u8 block, u8 reg, u8 *val, 178 int *err) 179 { 180 unsigned int v; 181 int ret; 182 183 if (err && *err) 184 return *err; 185 186 mutex_lock(&priv->reg_lock); 187 188 ret = ub953_select_ind_reg_block(priv, block); 189 if (ret) 190 goto out_unlock; 191 192 ret = regmap_write(priv->regmap, UB953_REG_IND_ACC_ADDR, reg); 193 if (ret) { 194 dev_err(&priv->client->dev, 195 "Write to IND_ACC_ADDR failed when reading %u:0x%02x: %d\n", 196 block, reg, ret); 197 goto out_unlock; 198 } 199 200 ret = regmap_read(priv->regmap, UB953_REG_IND_ACC_DATA, &v); 201 if (ret) { 202 dev_err(&priv->client->dev, 203 "Write to IND_ACC_DATA failed when reading %u:0x%02x: %d\n", 204 block, reg, ret); 205 goto out_unlock; 206 } 207 208 *val = v; 209 210 out_unlock: 211 mutex_unlock(&priv->reg_lock); 212 213 if (ret && err) 214 *err = ret; 215 216 return ret; 217 } 218 219 __maybe_unused 220 static int ub953_write_ind(struct ub953_data *priv, u8 block, u8 reg, u8 val, 221 int *err) 222 { 223 int ret; 224 225 if (err && *err) 226 return *err; 227 228 mutex_lock(&priv->reg_lock); 229 230 ret = ub953_select_ind_reg_block(priv, block); 231 if (ret) 232 goto out_unlock; 233 234 ret = regmap_write(priv->regmap, UB953_REG_IND_ACC_ADDR, reg); 235 if (ret) { 236 dev_err(&priv->client->dev, 237 "Write to IND_ACC_ADDR failed when writing %u:0x%02x: %d\n", 238 block, reg, ret); 239 goto out_unlock; 240 } 241 242 ret = regmap_write(priv->regmap, UB953_REG_IND_ACC_DATA, val); 243 if (ret) { 244 dev_err(&priv->client->dev, 245 "Write to IND_ACC_DATA failed when writing %u:0x%02x: %d\n", 246 block, reg, ret); 247 } 248 249 out_unlock: 250 mutex_unlock(&priv->reg_lock); 251 252 if (ret && err) 253 *err = ret; 254 255 return ret; 256 } 257 258 /* 259 * GPIO chip 260 */ 261 static int ub953_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 262 { 263 struct ub953_data *priv = gpiochip_get_data(gc); 264 int ret; 265 u8 v; 266 267 ret = ub953_read(priv, UB953_REG_GPIO_INPUT_CTRL, &v, NULL); 268 if (ret) 269 return ret; 270 271 if (v & UB953_REG_GPIO_INPUT_CTRL_INPUT_EN(offset)) 272 return GPIO_LINE_DIRECTION_IN; 273 else 274 return GPIO_LINE_DIRECTION_OUT; 275 } 276 277 static int ub953_gpio_direction_in(struct gpio_chip *gc, unsigned int offset) 278 { 279 struct ub953_data *priv = gpiochip_get_data(gc); 280 281 return regmap_update_bits(priv->regmap, UB953_REG_GPIO_INPUT_CTRL, 282 UB953_REG_GPIO_INPUT_CTRL_INPUT_EN(offset) | 283 UB953_REG_GPIO_INPUT_CTRL_OUT_EN(offset), 284 UB953_REG_GPIO_INPUT_CTRL_INPUT_EN(offset)); 285 } 286 287 static int ub953_gpio_direction_out(struct gpio_chip *gc, unsigned int offset, 288 int value) 289 { 290 struct ub953_data *priv = gpiochip_get_data(gc); 291 int ret; 292 293 ret = regmap_update_bits(priv->regmap, UB953_REG_LOCAL_GPIO_DATA, 294 UB953_REG_LOCAL_GPIO_DATA_GPIO_OUT_SRC(offset), 295 value ? UB953_REG_LOCAL_GPIO_DATA_GPIO_OUT_SRC(offset) : 296 0); 297 298 if (ret) 299 return ret; 300 301 return regmap_update_bits(priv->regmap, UB953_REG_GPIO_INPUT_CTRL, 302 UB953_REG_GPIO_INPUT_CTRL_INPUT_EN(offset) | 303 UB953_REG_GPIO_INPUT_CTRL_OUT_EN(offset), 304 UB953_REG_GPIO_INPUT_CTRL_OUT_EN(offset)); 305 } 306 307 static int ub953_gpio_get(struct gpio_chip *gc, unsigned int offset) 308 { 309 struct ub953_data *priv = gpiochip_get_data(gc); 310 int ret; 311 u8 v; 312 313 ret = ub953_read(priv, UB953_REG_GPIO_PIN_STS, &v, NULL); 314 if (ret) 315 return ret; 316 317 return !!(v & UB953_REG_GPIO_PIN_STS_GPIO_STS(offset)); 318 } 319 320 static int ub953_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 321 { 322 struct ub953_data *priv = gpiochip_get_data(gc); 323 324 return regmap_update_bits(priv->regmap, UB953_REG_LOCAL_GPIO_DATA, 325 UB953_REG_LOCAL_GPIO_DATA_GPIO_OUT_SRC(offset), 326 value ? UB953_REG_LOCAL_GPIO_DATA_GPIO_OUT_SRC(offset) : 0); 327 } 328 329 static int ub953_gpio_of_xlate(struct gpio_chip *gc, 330 const struct of_phandle_args *gpiospec, 331 u32 *flags) 332 { 333 if (flags) 334 *flags = gpiospec->args[1]; 335 336 return gpiospec->args[0]; 337 } 338 339 static int ub953_gpiochip_probe(struct ub953_data *priv) 340 { 341 struct device *dev = &priv->client->dev; 342 struct gpio_chip *gc = &priv->gpio_chip; 343 int ret; 344 345 /* Set all GPIOs to local input mode */ 346 ret = ub953_write(priv, UB953_REG_LOCAL_GPIO_DATA, 0, NULL); 347 if (ret) 348 return ret; 349 350 ret = ub953_write(priv, UB953_REG_GPIO_INPUT_CTRL, 0xf, NULL); 351 if (ret) 352 return ret; 353 354 gc->label = dev_name(dev); 355 gc->parent = dev; 356 gc->owner = THIS_MODULE; 357 gc->base = -1; 358 gc->can_sleep = true; 359 gc->ngpio = UB953_NUM_GPIOS; 360 gc->get_direction = ub953_gpio_get_direction; 361 gc->direction_input = ub953_gpio_direction_in; 362 gc->direction_output = ub953_gpio_direction_out; 363 gc->get = ub953_gpio_get; 364 gc->set = ub953_gpio_set; 365 gc->of_xlate = ub953_gpio_of_xlate; 366 gc->of_gpio_n_cells = 2; 367 368 ret = gpiochip_add_data(gc, priv); 369 if (ret) { 370 dev_err(dev, "Failed to add GPIOs: %d\n", ret); 371 return ret; 372 } 373 374 return 0; 375 } 376 377 static void ub953_gpiochip_remove(struct ub953_data *priv) 378 { 379 gpiochip_remove(&priv->gpio_chip); 380 } 381 382 /* 383 * V4L2 384 */ 385 386 static int _ub953_set_routing(struct v4l2_subdev *sd, 387 struct v4l2_subdev_state *state, 388 struct v4l2_subdev_krouting *routing) 389 { 390 static const struct v4l2_mbus_framefmt format = { 391 .width = 640, 392 .height = 480, 393 .code = MEDIA_BUS_FMT_UYVY8_1X16, 394 .field = V4L2_FIELD_NONE, 395 .colorspace = V4L2_COLORSPACE_SRGB, 396 .ycbcr_enc = V4L2_YCBCR_ENC_601, 397 .quantization = V4L2_QUANTIZATION_LIM_RANGE, 398 .xfer_func = V4L2_XFER_FUNC_SRGB, 399 }; 400 int ret; 401 402 ret = v4l2_subdev_routing_validate(sd, routing, 403 V4L2_SUBDEV_ROUTING_ONLY_1_TO_1); 404 if (ret) 405 return ret; 406 407 ret = v4l2_subdev_set_routing_with_fmt(sd, state, routing, &format); 408 if (ret) 409 return ret; 410 411 return 0; 412 } 413 414 static int ub953_set_routing(struct v4l2_subdev *sd, 415 struct v4l2_subdev_state *state, 416 enum v4l2_subdev_format_whence which, 417 struct v4l2_subdev_krouting *routing) 418 { 419 struct ub953_data *priv = sd_to_ub953(sd); 420 421 if (which == V4L2_SUBDEV_FORMAT_ACTIVE && priv->enabled_source_streams) 422 return -EBUSY; 423 424 return _ub953_set_routing(sd, state, routing); 425 } 426 427 428 static int ub953_set_fmt(struct v4l2_subdev *sd, 429 struct v4l2_subdev_state *state, 430 struct v4l2_subdev_format *format) 431 { 432 struct ub953_data *priv = sd_to_ub953(sd); 433 struct v4l2_mbus_framefmt *fmt; 434 435 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE && 436 priv->enabled_source_streams) 437 return -EBUSY; 438 439 /* No transcoding, source and sink formats must match. */ 440 if (format->pad == UB953_PAD_SOURCE) 441 return v4l2_subdev_get_fmt(sd, state, format); 442 443 /* Set sink format */ 444 fmt = v4l2_subdev_state_get_format(state, format->pad, format->stream); 445 if (!fmt) 446 return -EINVAL; 447 448 *fmt = format->format; 449 450 /* Propagate to source format */ 451 fmt = v4l2_subdev_state_get_opposite_stream_format(state, format->pad, 452 format->stream); 453 if (!fmt) 454 return -EINVAL; 455 456 *fmt = format->format; 457 458 return 0; 459 } 460 461 static int ub953_init_state(struct v4l2_subdev *sd, 462 struct v4l2_subdev_state *state) 463 { 464 struct v4l2_subdev_route routes[] = { 465 { 466 .sink_pad = UB953_PAD_SINK, 467 .sink_stream = 0, 468 .source_pad = UB953_PAD_SOURCE, 469 .source_stream = 0, 470 .flags = V4L2_SUBDEV_ROUTE_FL_ACTIVE, 471 }, 472 }; 473 474 struct v4l2_subdev_krouting routing = { 475 .num_routes = ARRAY_SIZE(routes), 476 .routes = routes, 477 }; 478 479 return _ub953_set_routing(sd, state, &routing); 480 } 481 482 static int ub953_log_status(struct v4l2_subdev *sd) 483 { 484 struct ub953_data *priv = sd_to_ub953(sd); 485 struct device *dev = &priv->client->dev; 486 char id[UB953_REG_FPD3_RX_ID_LEN]; 487 u8 gpio_local_data; 488 u8 gpio_input_ctrl; 489 u8 gpio_pin_sts; 490 unsigned int i; 491 u8 v, v1, v2; 492 int ret; 493 494 for (i = 0; i < sizeof(id); i++) { 495 ret = ub953_read(priv, UB953_REG_FPD3_RX_ID(i), &id[i], NULL); 496 if (ret) 497 return ret; 498 } 499 500 dev_info(dev, "ID '%.*s'\n", (int)sizeof(id), id); 501 502 ret = ub953_read(priv, UB953_REG_GENERAL_STATUS, &v, NULL); 503 if (ret) 504 return ret; 505 506 dev_info(dev, "GENERAL_STATUS %#02x\n", v); 507 508 ub953_read(priv, UB953_REG_CRC_ERR_CNT1, &v1, &ret); 509 ub953_read(priv, UB953_REG_CRC_ERR_CNT2, &v2, &ret); 510 if (ret) 511 return ret; 512 513 dev_info(dev, "CRC error count %u\n", v1 | (v2 << 8)); 514 515 /* Clear CRC error counter */ 516 if (v1 || v2) 517 regmap_update_bits(priv->regmap, UB953_REG_BC_CTRL, 518 UB953_REG_BC_CTRL_CRC_ERR_CLR, 519 UB953_REG_BC_CTRL_CRC_ERR_CLR); 520 521 ret = ub953_read(priv, UB953_REG_CSI_ERR_CNT, &v, NULL); 522 if (ret) 523 return ret; 524 525 dev_info(dev, "CSI error count %u\n", v); 526 527 ret = ub953_read(priv, UB953_REG_CSI_ERR_STATUS, &v, NULL); 528 if (ret) 529 return ret; 530 531 dev_info(dev, "CSI_ERR_STATUS %#02x\n", v); 532 533 ret = ub953_read(priv, UB953_REG_CSI_ERR_DLANE01, &v, NULL); 534 if (ret) 535 return ret; 536 537 dev_info(dev, "CSI_ERR_DLANE01 %#02x\n", v); 538 539 ret = ub953_read(priv, UB953_REG_CSI_ERR_DLANE23, &v, NULL); 540 if (ret) 541 return ret; 542 543 dev_info(dev, "CSI_ERR_DLANE23 %#02x\n", v); 544 545 ret = ub953_read(priv, UB953_REG_CSI_ERR_CLK_LANE, &v, NULL); 546 if (ret) 547 return ret; 548 549 dev_info(dev, "CSI_ERR_CLK_LANE %#02x\n", v); 550 551 ret = ub953_read(priv, UB953_REG_CSI_PKT_HDR_VC_ID, &v, NULL); 552 if (ret) 553 return ret; 554 555 dev_info(dev, "CSI packet header VC %u ID %u\n", v >> 6, v & 0x3f); 556 557 ub953_read(priv, UB953_REG_PKT_HDR_WC_LSB, &v1, &ret); 558 ub953_read(priv, UB953_REG_PKT_HDR_WC_MSB, &v2, &ret); 559 if (ret) 560 return ret; 561 562 dev_info(dev, "CSI packet header WC %u\n", (v2 << 8) | v1); 563 564 ret = ub953_read(priv, UB953_REG_CSI_ECC, &v, NULL); 565 if (ret) 566 return ret; 567 568 dev_info(dev, "CSI ECC %#02x\n", v); 569 570 ub953_read(priv, UB953_REG_LOCAL_GPIO_DATA, &gpio_local_data, &ret); 571 ub953_read(priv, UB953_REG_GPIO_INPUT_CTRL, &gpio_input_ctrl, &ret); 572 ub953_read(priv, UB953_REG_GPIO_PIN_STS, &gpio_pin_sts, &ret); 573 if (ret) 574 return ret; 575 576 for (i = 0; i < UB953_NUM_GPIOS; i++) { 577 dev_info(dev, 578 "GPIO%u: remote: %u is_input: %u is_output: %u val: %u sts: %u\n", 579 i, 580 !!(gpio_local_data & UB953_REG_LOCAL_GPIO_DATA_GPIO_RMTEN(i)), 581 !!(gpio_input_ctrl & UB953_REG_GPIO_INPUT_CTRL_INPUT_EN(i)), 582 !!(gpio_input_ctrl & UB953_REG_GPIO_INPUT_CTRL_OUT_EN(i)), 583 !!(gpio_local_data & UB953_REG_LOCAL_GPIO_DATA_GPIO_OUT_SRC(i)), 584 !!(gpio_pin_sts & UB953_REG_GPIO_PIN_STS_GPIO_STS(i))); 585 } 586 587 return 0; 588 } 589 590 static int ub953_enable_streams(struct v4l2_subdev *sd, 591 struct v4l2_subdev_state *state, u32 pad, 592 u64 streams_mask) 593 { 594 struct ub953_data *priv = sd_to_ub953(sd); 595 u64 sink_streams; 596 int ret; 597 598 sink_streams = v4l2_subdev_state_xlate_streams(state, UB953_PAD_SOURCE, 599 UB953_PAD_SINK, 600 &streams_mask); 601 602 ret = v4l2_subdev_enable_streams(priv->source_sd, priv->source_sd_pad, 603 sink_streams); 604 if (ret) 605 return ret; 606 607 priv->enabled_source_streams |= streams_mask; 608 609 return 0; 610 } 611 612 static int ub953_disable_streams(struct v4l2_subdev *sd, 613 struct v4l2_subdev_state *state, u32 pad, 614 u64 streams_mask) 615 { 616 struct ub953_data *priv = sd_to_ub953(sd); 617 u64 sink_streams; 618 int ret; 619 620 sink_streams = v4l2_subdev_state_xlate_streams(state, UB953_PAD_SOURCE, 621 UB953_PAD_SINK, 622 &streams_mask); 623 624 ret = v4l2_subdev_disable_streams(priv->source_sd, priv->source_sd_pad, 625 sink_streams); 626 if (ret) 627 return ret; 628 629 priv->enabled_source_streams &= ~streams_mask; 630 631 return 0; 632 } 633 634 static const struct v4l2_subdev_pad_ops ub953_pad_ops = { 635 .enable_streams = ub953_enable_streams, 636 .disable_streams = ub953_disable_streams, 637 .set_routing = ub953_set_routing, 638 .get_frame_desc = v4l2_subdev_get_frame_desc_passthrough, 639 .get_fmt = v4l2_subdev_get_fmt, 640 .set_fmt = ub953_set_fmt, 641 }; 642 643 static const struct v4l2_subdev_core_ops ub953_subdev_core_ops = { 644 .log_status = ub953_log_status, 645 }; 646 647 static const struct v4l2_subdev_ops ub953_subdev_ops = { 648 .core = &ub953_subdev_core_ops, 649 .pad = &ub953_pad_ops, 650 }; 651 652 static const struct v4l2_subdev_internal_ops ub953_internal_ops = { 653 .init_state = ub953_init_state, 654 }; 655 656 static const struct media_entity_operations ub953_entity_ops = { 657 .link_validate = v4l2_subdev_link_validate, 658 }; 659 660 static int ub953_notify_bound(struct v4l2_async_notifier *notifier, 661 struct v4l2_subdev *source_subdev, 662 struct v4l2_async_connection *asd) 663 { 664 struct ub953_data *priv = sd_to_ub953(notifier->sd); 665 struct device *dev = &priv->client->dev; 666 int ret; 667 668 ret = media_entity_get_fwnode_pad(&source_subdev->entity, 669 source_subdev->fwnode, 670 MEDIA_PAD_FL_SOURCE); 671 if (ret < 0) { 672 dev_err(dev, "Failed to find pad for %s\n", 673 source_subdev->name); 674 return ret; 675 } 676 677 priv->source_sd = source_subdev; 678 priv->source_sd_pad = ret; 679 680 ret = media_create_pad_link(&source_subdev->entity, priv->source_sd_pad, 681 &priv->sd.entity, 0, 682 MEDIA_LNK_FL_ENABLED | 683 MEDIA_LNK_FL_IMMUTABLE); 684 if (ret) { 685 dev_err(dev, "Unable to link %s:%u -> %s:0\n", 686 source_subdev->name, priv->source_sd_pad, 687 priv->sd.name); 688 return ret; 689 } 690 691 return 0; 692 } 693 694 static const struct v4l2_async_notifier_operations ub953_notify_ops = { 695 .bound = ub953_notify_bound, 696 }; 697 698 static int ub953_v4l2_notifier_register(struct ub953_data *priv) 699 { 700 struct device *dev = &priv->client->dev; 701 struct v4l2_async_connection *asd; 702 struct fwnode_handle *ep_fwnode; 703 int ret; 704 705 ep_fwnode = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 706 UB953_PAD_SINK, 0, 0); 707 if (!ep_fwnode) { 708 dev_err(dev, "No graph endpoint\n"); 709 return -ENODEV; 710 } 711 712 v4l2_async_subdev_nf_init(&priv->notifier, &priv->sd); 713 714 asd = v4l2_async_nf_add_fwnode_remote(&priv->notifier, ep_fwnode, 715 struct v4l2_async_connection); 716 717 fwnode_handle_put(ep_fwnode); 718 719 if (IS_ERR(asd)) { 720 dev_err(dev, "Failed to add subdev: %pe", asd); 721 v4l2_async_nf_cleanup(&priv->notifier); 722 return PTR_ERR(asd); 723 } 724 725 priv->notifier.ops = &ub953_notify_ops; 726 727 ret = v4l2_async_nf_register(&priv->notifier); 728 if (ret) { 729 dev_err(dev, "Failed to register subdev_notifier"); 730 v4l2_async_nf_cleanup(&priv->notifier); 731 return ret; 732 } 733 734 return 0; 735 } 736 737 static void ub953_v4l2_notifier_unregister(struct ub953_data *priv) 738 { 739 v4l2_async_nf_unregister(&priv->notifier); 740 v4l2_async_nf_cleanup(&priv->notifier); 741 } 742 743 /* 744 * Probing 745 */ 746 747 static int ub953_i2c_master_init(struct ub953_data *priv) 748 { 749 /* i2c fast mode */ 750 u32 ref = 26250000; 751 u32 scl_high = 915; /* ns */ 752 u32 scl_low = 1641; /* ns */ 753 int ret; 754 755 scl_high = div64_u64((u64)scl_high * ref, 1000000000) - 5; 756 scl_low = div64_u64((u64)scl_low * ref, 1000000000) - 5; 757 758 ret = ub953_write(priv, UB953_REG_SCL_HIGH_TIME, scl_high, NULL); 759 if (ret) 760 return ret; 761 762 ret = ub953_write(priv, UB953_REG_SCL_LOW_TIME, scl_low, NULL); 763 if (ret) 764 return ret; 765 766 return 0; 767 } 768 769 static u64 ub953_get_fc_rate(struct ub953_data *priv) 770 { 771 switch (priv->mode) { 772 case UB953_MODE_SYNC: 773 if (priv->hw_data->is_ub971) 774 return priv->plat_data->bc_rate * 160ull; 775 else 776 return priv->plat_data->bc_rate / 2 * 160ull; 777 778 case UB953_MODE_NONSYNC_EXT: 779 /* CLKIN_DIV = 1 always */ 780 return clk_get_rate(priv->clkin) * 80ull; 781 782 default: 783 /* Not supported */ 784 return 0; 785 } 786 } 787 788 static unsigned long ub953_calc_clkout_ub953(struct ub953_data *priv, 789 unsigned long target, u64 fc, 790 u8 *hs_div, u8 *m, u8 *n) 791 { 792 /* 793 * We always use 4 as a pre-divider (HS_CLK_DIV = 2). 794 * 795 * According to the datasheet: 796 * - "HS_CLK_DIV typically should be set to either 16, 8, or 4 (default)." 797 * - "if it is not possible to have an integer ratio of N/M, it is best to 798 * select a smaller value for HS_CLK_DIV. 799 * 800 * For above reasons the default HS_CLK_DIV seems the best in the average 801 * case. Use always that value to keep the code simple. 802 */ 803 static const unsigned long hs_clk_div = 4; 804 805 u64 fc_divided; 806 unsigned long mul, div; 807 unsigned long res; 808 809 /* clkout = fc / hs_clk_div * m / n */ 810 811 fc_divided = div_u64(fc, hs_clk_div); 812 813 rational_best_approximation(target, fc_divided, (1 << 5) - 1, 814 (1 << 8) - 1, &mul, &div); 815 816 res = div_u64(fc_divided * mul, div); 817 818 *hs_div = hs_clk_div; 819 *m = mul; 820 *n = div; 821 822 return res; 823 } 824 825 static unsigned long ub953_calc_clkout_ub971(struct ub953_data *priv, 826 unsigned long target, u64 fc, 827 u8 *m, u8 *n) 828 { 829 u64 fc_divided; 830 unsigned long mul, div; 831 unsigned long res; 832 833 /* clkout = fc * m / (8 * n) */ 834 835 fc_divided = div_u64(fc, 8); 836 837 rational_best_approximation(target, fc_divided, (1 << 5) - 1, 838 (1 << 8) - 1, &mul, &div); 839 840 res = div_u64(fc_divided * mul, div); 841 842 *m = mul; 843 *n = div; 844 845 return res; 846 } 847 848 static void ub953_calc_clkout_params(struct ub953_data *priv, 849 unsigned long target_rate, 850 struct ub953_clkout_data *clkout_data) 851 { 852 struct device *dev = &priv->client->dev; 853 unsigned long clkout_rate; 854 u64 fc_rate; 855 856 fc_rate = ub953_get_fc_rate(priv); 857 858 if (priv->hw_data->is_ub971) { 859 u8 m, n; 860 861 clkout_rate = ub953_calc_clkout_ub971(priv, target_rate, 862 fc_rate, &m, &n); 863 864 clkout_data->m = m; 865 clkout_data->n = n; 866 867 dev_dbg(dev, "%s %llu * %u / (8 * %u) = %lu (requested %lu)", 868 __func__, fc_rate, m, n, clkout_rate, target_rate); 869 } else { 870 u8 hs_div, m, n; 871 872 clkout_rate = ub953_calc_clkout_ub953(priv, target_rate, 873 fc_rate, &hs_div, &m, &n); 874 875 clkout_data->hs_div = hs_div; 876 clkout_data->m = m; 877 clkout_data->n = n; 878 879 dev_dbg(dev, "%s %llu / %u * %u / %u = %lu (requested %lu)", 880 __func__, fc_rate, hs_div, m, n, clkout_rate, 881 target_rate); 882 } 883 884 clkout_data->rate = clkout_rate; 885 } 886 887 static int ub953_write_clkout_regs(struct ub953_data *priv, 888 const struct ub953_clkout_data *clkout_data) 889 { 890 u8 clkout_ctrl0, clkout_ctrl1; 891 int ret; 892 893 if (priv->hw_data->is_ub971) 894 clkout_ctrl0 = clkout_data->m; 895 else 896 clkout_ctrl0 = (__ffs(clkout_data->hs_div) << 5) | 897 clkout_data->m; 898 899 clkout_ctrl1 = clkout_data->n; 900 901 ret = ub953_write(priv, UB953_REG_CLKOUT_CTRL0, clkout_ctrl0, NULL); 902 if (ret) 903 return ret; 904 905 ret = ub953_write(priv, UB953_REG_CLKOUT_CTRL1, clkout_ctrl1, NULL); 906 if (ret) 907 return ret; 908 909 return 0; 910 } 911 912 static unsigned long ub953_clkout_recalc_rate(struct clk_hw *hw, 913 unsigned long parent_rate) 914 { 915 struct ub953_data *priv = container_of(hw, struct ub953_data, clkout_clk_hw); 916 struct device *dev = &priv->client->dev; 917 u8 ctrl0, ctrl1; 918 u32 mul, div; 919 u64 fc_rate; 920 u32 hs_clk_div; 921 u64 rate; 922 int ret; 923 924 ret = ub953_read(priv, UB953_REG_CLKOUT_CTRL0, &ctrl0, NULL); 925 if (ret) { 926 dev_err(dev, "Failed to read CLKOUT_CTRL0: %d\n", ret); 927 return 0; 928 } 929 930 ret = ub953_read(priv, UB953_REG_CLKOUT_CTRL1, &ctrl1, NULL); 931 if (ret) { 932 dev_err(dev, "Failed to read CLKOUT_CTRL1: %d\n", ret); 933 return 0; 934 } 935 936 fc_rate = ub953_get_fc_rate(priv); 937 938 if (priv->hw_data->is_ub971) { 939 mul = ctrl0 & 0x1f; 940 div = ctrl1; 941 942 if (div == 0) 943 return 0; 944 945 rate = div_u64(fc_rate * mul, 8 * div); 946 947 dev_dbg(dev, "clkout: fc rate %llu, mul %u, div %u = %llu\n", 948 fc_rate, mul, div, rate); 949 } else { 950 mul = ctrl0 & 0x1f; 951 hs_clk_div = 1 << (ctrl0 >> 5); 952 div = ctrl1; 953 954 if (div == 0) 955 return 0; 956 957 rate = div_u64(div_u64(fc_rate, hs_clk_div) * mul, div); 958 959 dev_dbg(dev, 960 "clkout: fc rate %llu, hs_clk_div %u, mul %u, div %u = %llu\n", 961 fc_rate, hs_clk_div, mul, div, rate); 962 } 963 964 return rate; 965 } 966 967 static int ub953_clkout_determine_rate(struct clk_hw *hw, 968 struct clk_rate_request *req) 969 { 970 struct ub953_data *priv = container_of(hw, struct ub953_data, clkout_clk_hw); 971 struct ub953_clkout_data clkout_data; 972 973 ub953_calc_clkout_params(priv, req->rate, &clkout_data); 974 975 req->rate = clkout_data.rate; 976 977 return 0; 978 } 979 980 static int ub953_clkout_set_rate(struct clk_hw *hw, unsigned long rate, 981 unsigned long parent_rate) 982 { 983 struct ub953_data *priv = container_of(hw, struct ub953_data, clkout_clk_hw); 984 struct ub953_clkout_data clkout_data; 985 986 ub953_calc_clkout_params(priv, rate, &clkout_data); 987 988 dev_dbg(&priv->client->dev, "%s %lu (requested %lu)\n", __func__, 989 clkout_data.rate, rate); 990 991 return ub953_write_clkout_regs(priv, &clkout_data); 992 } 993 994 static const struct clk_ops ub953_clkout_ops = { 995 .recalc_rate = ub953_clkout_recalc_rate, 996 .determine_rate = ub953_clkout_determine_rate, 997 .set_rate = ub953_clkout_set_rate, 998 }; 999 1000 static int ub953_register_clkout(struct ub953_data *priv) 1001 { 1002 struct device *dev = &priv->client->dev; 1003 const struct clk_init_data init = { 1004 .name = kasprintf(GFP_KERNEL, "ds90%s.%s.clk_out", 1005 priv->hw_data->model, dev_name(dev)), 1006 .ops = &ub953_clkout_ops, 1007 }; 1008 struct ub953_clkout_data clkout_data; 1009 int ret; 1010 1011 if (!init.name) 1012 return -ENOMEM; 1013 1014 /* Initialize clkout to 25MHz by default */ 1015 ub953_calc_clkout_params(priv, UB953_DEFAULT_CLKOUT_RATE, &clkout_data); 1016 ret = ub953_write_clkout_regs(priv, &clkout_data); 1017 if (ret) 1018 return ret; 1019 1020 priv->clkout_clk_hw.init = &init; 1021 1022 ret = devm_clk_hw_register(dev, &priv->clkout_clk_hw); 1023 kfree(init.name); 1024 if (ret) 1025 return dev_err_probe(dev, ret, "Cannot register clock HW\n"); 1026 1027 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 1028 &priv->clkout_clk_hw); 1029 if (ret) 1030 return dev_err_probe(dev, ret, 1031 "Cannot add OF clock provider\n"); 1032 1033 return 0; 1034 } 1035 1036 static int ub953_add_i2c_adapter(struct ub953_data *priv) 1037 { 1038 struct device *dev = &priv->client->dev; 1039 struct i2c_atr_adap_desc desc = { }; 1040 struct fwnode_handle *i2c_handle; 1041 int ret; 1042 1043 i2c_handle = device_get_named_child_node(dev, "i2c"); 1044 if (!i2c_handle) 1045 return 0; 1046 1047 desc.chan_id = priv->plat_data->port; 1048 desc.parent = dev; 1049 desc.bus_handle = i2c_handle; 1050 desc.num_aliases = 0; 1051 1052 ret = i2c_atr_add_adapter(priv->plat_data->atr, &desc); 1053 1054 fwnode_handle_put(i2c_handle); 1055 1056 if (ret) 1057 return ret; 1058 1059 return 0; 1060 } 1061 1062 static const struct regmap_config ub953_regmap_config = { 1063 .name = "ds90ub953", 1064 .reg_bits = 8, 1065 .val_bits = 8, 1066 .reg_format_endian = REGMAP_ENDIAN_DEFAULT, 1067 .val_format_endian = REGMAP_ENDIAN_DEFAULT, 1068 }; 1069 1070 static int ub953_parse_dt(struct ub953_data *priv) 1071 { 1072 struct device *dev = &priv->client->dev; 1073 struct v4l2_fwnode_endpoint vep = { 1074 .bus_type = V4L2_MBUS_CSI2_DPHY, 1075 }; 1076 struct fwnode_handle *ep_fwnode; 1077 unsigned char nlanes; 1078 int ret; 1079 1080 ep_fwnode = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 1081 UB953_PAD_SINK, 0, 0); 1082 if (!ep_fwnode) 1083 return dev_err_probe(dev, -ENOENT, "no endpoint found\n"); 1084 1085 ret = v4l2_fwnode_endpoint_parse(ep_fwnode, &vep); 1086 1087 fwnode_handle_put(ep_fwnode); 1088 1089 if (ret) 1090 return dev_err_probe(dev, ret, 1091 "failed to parse sink endpoint data\n"); 1092 1093 nlanes = vep.bus.mipi_csi2.num_data_lanes; 1094 if (nlanes != 1 && nlanes != 2 && nlanes != 4) 1095 return dev_err_probe(dev, -EINVAL, 1096 "bad number of data-lanes: %u\n", nlanes); 1097 1098 priv->num_data_lanes = nlanes; 1099 1100 priv->non_continous_clk = vep.bus.mipi_csi2.flags & 1101 V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK; 1102 1103 return 0; 1104 } 1105 1106 static int ub953_hw_init(struct ub953_data *priv) 1107 { 1108 struct device *dev = &priv->client->dev; 1109 bool mode_override; 1110 int ret; 1111 u8 v; 1112 1113 ret = ub953_read(priv, UB953_REG_MODE_SEL, &v, NULL); 1114 if (ret) 1115 return ret; 1116 1117 if (!(v & UB953_REG_MODE_SEL_MODE_DONE)) 1118 return dev_err_probe(dev, -EIO, "Mode value not stabilized\n"); 1119 1120 mode_override = v & UB953_REG_MODE_SEL_MODE_OVERRIDE; 1121 1122 switch (v & UB953_REG_MODE_SEL_MODE_MASK) { 1123 case 0: 1124 priv->mode = UB953_MODE_SYNC; 1125 break; 1126 case 2: 1127 priv->mode = UB953_MODE_NONSYNC_EXT; 1128 break; 1129 case 3: 1130 priv->mode = UB953_MODE_NONSYNC_INT; 1131 break; 1132 case 5: 1133 priv->mode = UB953_MODE_DVP; 1134 break; 1135 default: 1136 return dev_err_probe(dev, -EIO, 1137 "Invalid mode in mode register\n"); 1138 } 1139 1140 dev_dbg(dev, "mode from %s: %#x\n", mode_override ? "reg" : "strap", 1141 priv->mode); 1142 1143 if (priv->mode != UB953_MODE_SYNC && 1144 priv->mode != UB953_MODE_NONSYNC_EXT) 1145 return dev_err_probe(dev, -ENODEV, 1146 "Unsupported mode selected: %u\n", 1147 priv->mode); 1148 1149 if (priv->mode == UB953_MODE_NONSYNC_EXT && !priv->clkin) 1150 return dev_err_probe(dev, -EINVAL, 1151 "clkin required for non-sync ext mode\n"); 1152 1153 ret = ub953_read(priv, UB953_REG_REV_MASK_ID, &v, NULL); 1154 if (ret) 1155 return dev_err_probe(dev, ret, "Failed to read revision"); 1156 1157 dev_info(dev, "Found %s rev/mask %#04x\n", priv->hw_data->model, v); 1158 1159 ret = ub953_read(priv, UB953_REG_GENERAL_CFG, &v, NULL); 1160 if (ret) 1161 return ret; 1162 1163 dev_dbg(dev, "i2c strap setting %s V\n", 1164 (v & UB953_REG_GENERAL_CFG_I2C_STRAP_MODE) ? "1.8" : "3.3"); 1165 1166 ret = ub953_i2c_master_init(priv); 1167 if (ret) 1168 return dev_err_probe(dev, ret, "i2c init failed\n"); 1169 1170 v = 0; 1171 v |= priv->non_continous_clk ? 0 : UB953_REG_GENERAL_CFG_CONT_CLK; 1172 v |= (priv->num_data_lanes - 1) << 1173 UB953_REG_GENERAL_CFG_CSI_LANE_SEL_SHIFT; 1174 v |= UB953_REG_GENERAL_CFG_CRC_TX_GEN_ENABLE; 1175 1176 ret = ub953_write(priv, UB953_REG_GENERAL_CFG, v, NULL); 1177 if (ret) 1178 return ret; 1179 1180 v = 1U << UB953_REG_I2C_CONTROL2_SDA_OUTPUT_SETUP_SHIFT; 1181 v |= UB953_REG_I2C_CONTROL2_BUS_SPEEDUP; 1182 1183 ret = ub953_write(priv, UB953_REG_I2C_CONTROL2, v, NULL); 1184 1185 return ret; 1186 } 1187 1188 static int ub953_subdev_init(struct ub953_data *priv) 1189 { 1190 struct device *dev = &priv->client->dev; 1191 int ret; 1192 1193 v4l2_i2c_subdev_init(&priv->sd, priv->client, &ub953_subdev_ops); 1194 priv->sd.internal_ops = &ub953_internal_ops; 1195 1196 priv->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | 1197 V4L2_SUBDEV_FL_STREAMS; 1198 priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 1199 priv->sd.entity.ops = &ub953_entity_ops; 1200 1201 priv->pads[0].flags = MEDIA_PAD_FL_SINK; 1202 priv->pads[1].flags = MEDIA_PAD_FL_SOURCE; 1203 1204 ret = media_entity_pads_init(&priv->sd.entity, 2, priv->pads); 1205 if (ret) 1206 return dev_err_probe(dev, ret, "Failed to init pads\n"); 1207 1208 ret = v4l2_subdev_init_finalize(&priv->sd); 1209 if (ret) 1210 goto err_entity_cleanup; 1211 1212 ret = ub953_v4l2_notifier_register(priv); 1213 if (ret) { 1214 dev_err_probe(dev, ret, 1215 "v4l2 subdev notifier register failed\n"); 1216 goto err_free_state; 1217 } 1218 1219 ret = v4l2_async_register_subdev(&priv->sd); 1220 if (ret) { 1221 dev_err_probe(dev, ret, "v4l2_async_register_subdev error\n"); 1222 goto err_unreg_notif; 1223 } 1224 1225 return 0; 1226 1227 err_unreg_notif: 1228 ub953_v4l2_notifier_unregister(priv); 1229 err_free_state: 1230 v4l2_subdev_cleanup(&priv->sd); 1231 err_entity_cleanup: 1232 media_entity_cleanup(&priv->sd.entity); 1233 1234 return ret; 1235 } 1236 1237 static void ub953_subdev_uninit(struct ub953_data *priv) 1238 { 1239 v4l2_async_unregister_subdev(&priv->sd); 1240 ub953_v4l2_notifier_unregister(priv); 1241 v4l2_subdev_cleanup(&priv->sd); 1242 media_entity_cleanup(&priv->sd.entity); 1243 } 1244 1245 static int ub953_probe(struct i2c_client *client) 1246 { 1247 struct device *dev = &client->dev; 1248 struct ub953_data *priv; 1249 int ret; 1250 1251 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1252 if (!priv) 1253 return -ENOMEM; 1254 1255 priv->client = client; 1256 1257 priv->hw_data = device_get_match_data(dev); 1258 1259 priv->plat_data = dev_get_platdata(&client->dev); 1260 if (!priv->plat_data) 1261 return dev_err_probe(dev, -ENODEV, "Platform data missing\n"); 1262 1263 mutex_init(&priv->reg_lock); 1264 1265 /* 1266 * Initialize to invalid values so that the first reg writes will 1267 * configure the target. 1268 */ 1269 priv->current_indirect_target = 0xff; 1270 1271 priv->regmap = devm_regmap_init_i2c(client, &ub953_regmap_config); 1272 if (IS_ERR(priv->regmap)) { 1273 ret = PTR_ERR(priv->regmap); 1274 dev_err_probe(dev, ret, "Failed to init regmap\n"); 1275 goto err_mutex_destroy; 1276 } 1277 1278 priv->clkin = devm_clk_get_optional(dev, "clkin"); 1279 if (IS_ERR(priv->clkin)) { 1280 ret = PTR_ERR(priv->clkin); 1281 dev_err_probe(dev, ret, "failed to parse 'clkin'\n"); 1282 goto err_mutex_destroy; 1283 } 1284 1285 ret = ub953_parse_dt(priv); 1286 if (ret) 1287 goto err_mutex_destroy; 1288 1289 ret = ub953_hw_init(priv); 1290 if (ret) 1291 goto err_mutex_destroy; 1292 1293 ret = ub953_gpiochip_probe(priv); 1294 if (ret) { 1295 dev_err_probe(dev, ret, "Failed to init gpiochip\n"); 1296 goto err_mutex_destroy; 1297 } 1298 1299 ret = ub953_register_clkout(priv); 1300 if (ret) { 1301 dev_err_probe(dev, ret, "Failed to register clkout\n"); 1302 goto err_gpiochip_remove; 1303 } 1304 1305 ret = ub953_subdev_init(priv); 1306 if (ret) 1307 goto err_gpiochip_remove; 1308 1309 ret = ub953_add_i2c_adapter(priv); 1310 if (ret) { 1311 dev_err_probe(dev, ret, "failed to add remote i2c adapter\n"); 1312 goto err_subdev_uninit; 1313 } 1314 1315 return 0; 1316 1317 err_subdev_uninit: 1318 ub953_subdev_uninit(priv); 1319 err_gpiochip_remove: 1320 ub953_gpiochip_remove(priv); 1321 err_mutex_destroy: 1322 mutex_destroy(&priv->reg_lock); 1323 1324 return ret; 1325 } 1326 1327 static void ub953_remove(struct i2c_client *client) 1328 { 1329 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1330 struct ub953_data *priv = sd_to_ub953(sd); 1331 1332 i2c_atr_del_adapter(priv->plat_data->atr, priv->plat_data->port); 1333 1334 ub953_subdev_uninit(priv); 1335 1336 ub953_gpiochip_remove(priv); 1337 mutex_destroy(&priv->reg_lock); 1338 } 1339 1340 static const struct ub953_hw_data ds90ub953_hw = { 1341 .model = "ub953", 1342 }; 1343 1344 static const struct ub953_hw_data ds90ub971_hw = { 1345 .model = "ub971", 1346 .is_ub971 = true, 1347 }; 1348 1349 static const struct i2c_device_id ub953_id[] = { 1350 { "ds90ub953-q1", (kernel_ulong_t)&ds90ub953_hw }, 1351 { "ds90ub971-q1", (kernel_ulong_t)&ds90ub971_hw }, 1352 {} 1353 }; 1354 MODULE_DEVICE_TABLE(i2c, ub953_id); 1355 1356 static const struct of_device_id ub953_dt_ids[] = { 1357 { .compatible = "ti,ds90ub953-q1", .data = &ds90ub953_hw }, 1358 { .compatible = "ti,ds90ub971-q1", .data = &ds90ub971_hw }, 1359 {} 1360 }; 1361 MODULE_DEVICE_TABLE(of, ub953_dt_ids); 1362 1363 static struct i2c_driver ds90ub953_driver = { 1364 .probe = ub953_probe, 1365 .remove = ub953_remove, 1366 .id_table = ub953_id, 1367 .driver = { 1368 .name = "ds90ub953", 1369 .of_match_table = ub953_dt_ids, 1370 }, 1371 }; 1372 module_i2c_driver(ds90ub953_driver); 1373 1374 MODULE_LICENSE("GPL"); 1375 MODULE_DESCRIPTION("Texas Instruments FPD-Link III/IV CSI-2 Serializers Driver"); 1376 MODULE_AUTHOR("Luca Ceresoli <luca@lucaceresoli.net>"); 1377 MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>"); 1378 MODULE_IMPORT_NS("I2C_ATR"); 1379