1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the Texas Instruments DS90UB913 video serializer 4 * 5 * Based on a driver from Luca Ceresoli <luca@lucaceresoli.net> 6 * 7 * Copyright (c) 2019 Luca Ceresoli <luca@lucaceresoli.net> 8 * Copyright (c) 2023 Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/clk-provider.h> 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/gpio/driver.h> 16 #include <linux/i2c-atr.h> 17 #include <linux/i2c.h> 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/property.h> 21 #include <linux/regmap.h> 22 23 #include <media/i2c/ds90ub9xx.h> 24 #include <media/v4l2-fwnode.h> 25 #include <media/v4l2-mediabus.h> 26 #include <media/v4l2-subdev.h> 27 28 #define UB913_PAD_SINK 0 29 #define UB913_PAD_SOURCE 1 30 31 /* 32 * UB913 has 4 gpios, but gpios 3 and 4 are reserved for external oscillator 33 * mode. Thus we only support 2 gpios for now. 34 */ 35 #define UB913_NUM_GPIOS 2 36 37 #define UB913_REG_RESET_CTL 0x01 38 #define UB913_REG_RESET_CTL_DIGITAL_RESET_1 BIT(1) 39 #define UB913_REG_RESET_CTL_DIGITAL_RESET_0 BIT(0) 40 41 #define UB913_REG_GENERAL_CFG 0x03 42 #define UB913_REG_GENERAL_CFG_CRC_ERR_RESET BIT(5) 43 #define UB913_REG_GENERAL_CFG_PCLK_RISING BIT(0) 44 45 #define UB913_REG_MODE_SEL 0x05 46 #define UB913_REG_MODE_SEL_MODE_OVERRIDE BIT(5) 47 #define UB913_REG_MODE_SEL_MODE_UP_TO_DATE BIT(4) 48 #define UB913_REG_MODE_SEL_MODE_MASK GENMASK(3, 0) 49 50 #define UB913_REG_CRC_ERRORS_LSB 0x0a 51 #define UB913_REG_CRC_ERRORS_MSB 0x0b 52 53 #define UB913_REG_GENERAL_STATUS 0x0c 54 55 #define UB913_REG_GPIO_CFG(n) (0x0d + (n)) 56 #define UB913_REG_GPIO_CFG_ENABLE(n) BIT(0 + (n) * 4) 57 #define UB913_REG_GPIO_CFG_DIR_INPUT(n) BIT(1 + (n) * 4) 58 #define UB913_REG_GPIO_CFG_REMOTE_EN(n) BIT(2 + (n) * 4) 59 #define UB913_REG_GPIO_CFG_OUT_VAL(n) BIT(3 + (n) * 4) 60 #define UB913_REG_GPIO_CFG_MASK(n) (0xf << ((n) * 4)) 61 62 #define UB913_REG_SCL_HIGH_TIME 0x11 63 #define UB913_REG_SCL_LOW_TIME 0x12 64 65 #define UB913_REG_PLL_OVR 0x35 66 67 struct ub913_data { 68 struct i2c_client *client; 69 struct regmap *regmap; 70 struct clk *clkin; 71 72 struct gpio_chip gpio_chip; 73 74 struct v4l2_subdev sd; 75 struct media_pad pads[2]; 76 77 struct v4l2_async_notifier notifier; 78 79 struct v4l2_subdev *source_sd; 80 u16 source_sd_pad; 81 82 u64 enabled_source_streams; 83 84 struct clk_hw *clkout_clk_hw; 85 86 struct ds90ub9xx_platform_data *plat_data; 87 88 bool pclk_polarity_rising; 89 }; 90 91 static inline struct ub913_data *sd_to_ub913(struct v4l2_subdev *sd) 92 { 93 return container_of(sd, struct ub913_data, sd); 94 } 95 96 struct ub913_format_info { 97 u32 incode; 98 u32 outcode; 99 }; 100 101 static const struct ub913_format_info ub913_formats[] = { 102 /* Only RAW10 with 8-bit payload is supported at the moment */ 103 { .incode = MEDIA_BUS_FMT_YUYV8_2X8, .outcode = MEDIA_BUS_FMT_YUYV8_1X16 }, 104 { .incode = MEDIA_BUS_FMT_UYVY8_2X8, .outcode = MEDIA_BUS_FMT_UYVY8_1X16 }, 105 { .incode = MEDIA_BUS_FMT_VYUY8_2X8, .outcode = MEDIA_BUS_FMT_VYUY8_1X16 }, 106 { .incode = MEDIA_BUS_FMT_YVYU8_2X8, .outcode = MEDIA_BUS_FMT_YVYU8_1X16 }, 107 }; 108 109 static const struct ub913_format_info *ub913_find_format(u32 incode) 110 { 111 unsigned int i; 112 113 for (i = 0; i < ARRAY_SIZE(ub913_formats); i++) { 114 if (ub913_formats[i].incode == incode) 115 return &ub913_formats[i]; 116 } 117 118 return NULL; 119 } 120 121 static int ub913_read(const struct ub913_data *priv, u8 reg, u8 *val, 122 int *err) 123 { 124 unsigned int v; 125 int ret; 126 127 if (err && *err) 128 return *err; 129 130 ret = regmap_read(priv->regmap, reg, &v); 131 if (ret) { 132 dev_err(&priv->client->dev, 133 "Cannot read register 0x%02x: %d!\n", reg, ret); 134 goto out; 135 } 136 137 *val = v; 138 139 out: 140 if (ret && err) 141 *err = ret; 142 143 return ret; 144 } 145 146 static int ub913_write(const struct ub913_data *priv, u8 reg, u8 val, 147 int *err) 148 { 149 int ret; 150 151 if (err && *err) 152 return *err; 153 154 ret = regmap_write(priv->regmap, reg, val); 155 if (ret < 0) 156 dev_err(&priv->client->dev, 157 "Cannot write register 0x%02x: %d!\n", reg, ret); 158 159 if (ret && err) 160 *err = ret; 161 162 return ret; 163 } 164 165 static int ub913_update_bits(const struct ub913_data *priv, u8 reg, u8 mask, 166 u8 val, int *err) 167 { 168 int ret; 169 170 if (err && *err) 171 return *err; 172 173 ret = regmap_update_bits(priv->regmap, reg, mask, val); 174 if (ret < 0) 175 dev_err(&priv->client->dev, 176 "Cannot update register 0x%02x %d!\n", reg, ret); 177 178 if (ret && err) 179 *err = ret; 180 181 return ret; 182 } 183 184 /* 185 * GPIO chip 186 */ 187 static int ub913_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 188 { 189 return GPIO_LINE_DIRECTION_OUT; 190 } 191 192 static int ub913_gpio_direction_out(struct gpio_chip *gc, unsigned int offset, 193 int value) 194 { 195 struct ub913_data *priv = gpiochip_get_data(gc); 196 unsigned int reg_idx = offset / 2; 197 unsigned int field_idx = offset % 2; 198 199 return regmap_update_bits(priv->regmap, UB913_REG_GPIO_CFG(reg_idx), 200 UB913_REG_GPIO_CFG_MASK(field_idx), 201 UB913_REG_GPIO_CFG_ENABLE(field_idx) | 202 (value ? UB913_REG_GPIO_CFG_OUT_VAL(field_idx) : 203 0)); 204 } 205 206 static void ub913_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 207 { 208 ub913_gpio_direction_out(gc, offset, value); 209 } 210 211 static int ub913_gpio_of_xlate(struct gpio_chip *gc, 212 const struct of_phandle_args *gpiospec, 213 u32 *flags) 214 { 215 if (flags) 216 *flags = gpiospec->args[1]; 217 218 return gpiospec->args[0]; 219 } 220 221 static int ub913_gpiochip_probe(struct ub913_data *priv) 222 { 223 struct device *dev = &priv->client->dev; 224 struct gpio_chip *gc = &priv->gpio_chip; 225 int ret; 226 227 /* Initialize GPIOs 0 and 1 to local control, tri-state */ 228 ub913_write(priv, UB913_REG_GPIO_CFG(0), 0, NULL); 229 230 gc->label = dev_name(dev); 231 gc->parent = dev; 232 gc->owner = THIS_MODULE; 233 gc->base = -1; 234 gc->can_sleep = true; 235 gc->ngpio = UB913_NUM_GPIOS; 236 gc->get_direction = ub913_gpio_get_direction; 237 gc->direction_output = ub913_gpio_direction_out; 238 gc->set = ub913_gpio_set; 239 gc->of_xlate = ub913_gpio_of_xlate; 240 gc->of_gpio_n_cells = 2; 241 242 ret = gpiochip_add_data(gc, priv); 243 if (ret) { 244 dev_err(dev, "Failed to add GPIOs: %d\n", ret); 245 return ret; 246 } 247 248 return 0; 249 } 250 251 static void ub913_gpiochip_remove(struct ub913_data *priv) 252 { 253 gpiochip_remove(&priv->gpio_chip); 254 } 255 256 static const struct regmap_config ub913_regmap_config = { 257 .name = "ds90ub913", 258 .reg_bits = 8, 259 .val_bits = 8, 260 .reg_format_endian = REGMAP_ENDIAN_DEFAULT, 261 .val_format_endian = REGMAP_ENDIAN_DEFAULT, 262 }; 263 264 /* 265 * V4L2 266 */ 267 268 static int ub913_enable_streams(struct v4l2_subdev *sd, 269 struct v4l2_subdev_state *state, u32 pad, 270 u64 streams_mask) 271 { 272 struct ub913_data *priv = sd_to_ub913(sd); 273 u64 sink_streams; 274 int ret; 275 276 sink_streams = v4l2_subdev_state_xlate_streams(state, UB913_PAD_SOURCE, 277 UB913_PAD_SINK, 278 &streams_mask); 279 280 ret = v4l2_subdev_enable_streams(priv->source_sd, priv->source_sd_pad, 281 sink_streams); 282 if (ret) 283 return ret; 284 285 priv->enabled_source_streams |= streams_mask; 286 287 return 0; 288 } 289 290 static int ub913_disable_streams(struct v4l2_subdev *sd, 291 struct v4l2_subdev_state *state, u32 pad, 292 u64 streams_mask) 293 { 294 struct ub913_data *priv = sd_to_ub913(sd); 295 u64 sink_streams; 296 int ret; 297 298 sink_streams = v4l2_subdev_state_xlate_streams(state, UB913_PAD_SOURCE, 299 UB913_PAD_SINK, 300 &streams_mask); 301 302 ret = v4l2_subdev_disable_streams(priv->source_sd, priv->source_sd_pad, 303 sink_streams); 304 if (ret) 305 return ret; 306 307 priv->enabled_source_streams &= ~streams_mask; 308 309 return 0; 310 } 311 312 static int _ub913_set_routing(struct v4l2_subdev *sd, 313 struct v4l2_subdev_state *state, 314 struct v4l2_subdev_krouting *routing) 315 { 316 static const struct v4l2_mbus_framefmt in_format = { 317 .width = 640, 318 .height = 480, 319 .code = MEDIA_BUS_FMT_UYVY8_2X8, 320 .field = V4L2_FIELD_NONE, 321 .colorspace = V4L2_COLORSPACE_SRGB, 322 .ycbcr_enc = V4L2_YCBCR_ENC_601, 323 .quantization = V4L2_QUANTIZATION_LIM_RANGE, 324 .xfer_func = V4L2_XFER_FUNC_SRGB, 325 }; 326 static const struct v4l2_mbus_framefmt out_format = { 327 .width = 640, 328 .height = 480, 329 .code = MEDIA_BUS_FMT_UYVY8_1X16, 330 .field = V4L2_FIELD_NONE, 331 .colorspace = V4L2_COLORSPACE_SRGB, 332 .ycbcr_enc = V4L2_YCBCR_ENC_601, 333 .quantization = V4L2_QUANTIZATION_LIM_RANGE, 334 .xfer_func = V4L2_XFER_FUNC_SRGB, 335 }; 336 struct v4l2_subdev_stream_configs *stream_configs; 337 unsigned int i; 338 int ret; 339 340 /* 341 * Note: we can only support up to V4L2_FRAME_DESC_ENTRY_MAX, until 342 * frame desc is made dynamically allocated. 343 */ 344 345 if (routing->num_routes > V4L2_FRAME_DESC_ENTRY_MAX) 346 return -EINVAL; 347 348 ret = v4l2_subdev_routing_validate(sd, routing, 349 V4L2_SUBDEV_ROUTING_ONLY_1_TO_1); 350 if (ret) 351 return ret; 352 353 ret = v4l2_subdev_set_routing(sd, state, routing); 354 if (ret) 355 return ret; 356 357 stream_configs = &state->stream_configs; 358 359 for (i = 0; i < stream_configs->num_configs; i++) { 360 if (stream_configs->configs[i].pad == UB913_PAD_SINK) 361 stream_configs->configs[i].fmt = in_format; 362 else 363 stream_configs->configs[i].fmt = out_format; 364 } 365 366 return 0; 367 } 368 369 static int ub913_set_routing(struct v4l2_subdev *sd, 370 struct v4l2_subdev_state *state, 371 enum v4l2_subdev_format_whence which, 372 struct v4l2_subdev_krouting *routing) 373 { 374 struct ub913_data *priv = sd_to_ub913(sd); 375 376 if (which == V4L2_SUBDEV_FORMAT_ACTIVE && priv->enabled_source_streams) 377 return -EBUSY; 378 379 return _ub913_set_routing(sd, state, routing); 380 } 381 382 static int ub913_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad, 383 struct v4l2_mbus_frame_desc *fd) 384 { 385 struct ub913_data *priv = sd_to_ub913(sd); 386 const struct v4l2_subdev_krouting *routing; 387 struct v4l2_mbus_frame_desc source_fd; 388 struct v4l2_subdev_route *route; 389 struct v4l2_subdev_state *state; 390 int ret; 391 392 if (pad != UB913_PAD_SOURCE) 393 return -EINVAL; 394 395 ret = v4l2_subdev_call(priv->source_sd, pad, get_frame_desc, 396 priv->source_sd_pad, &source_fd); 397 if (ret) 398 return ret; 399 400 fd->type = V4L2_MBUS_FRAME_DESC_TYPE_PARALLEL; 401 402 state = v4l2_subdev_lock_and_get_active_state(sd); 403 404 routing = &state->routing; 405 406 for_each_active_route(routing, route) { 407 unsigned int i; 408 409 if (route->source_pad != pad) 410 continue; 411 412 for (i = 0; i < source_fd.num_entries; i++) { 413 if (source_fd.entry[i].stream == route->sink_stream) 414 break; 415 } 416 417 if (i == source_fd.num_entries) { 418 dev_err(&priv->client->dev, 419 "Failed to find stream from source frame desc\n"); 420 ret = -EPIPE; 421 goto out_unlock; 422 } 423 424 fd->entry[fd->num_entries].stream = route->source_stream; 425 fd->entry[fd->num_entries].flags = source_fd.entry[i].flags; 426 fd->entry[fd->num_entries].length = source_fd.entry[i].length; 427 fd->entry[fd->num_entries].pixelcode = 428 source_fd.entry[i].pixelcode; 429 430 fd->num_entries++; 431 } 432 433 out_unlock: 434 v4l2_subdev_unlock_state(state); 435 436 return ret; 437 } 438 439 static int ub913_set_fmt(struct v4l2_subdev *sd, 440 struct v4l2_subdev_state *state, 441 struct v4l2_subdev_format *format) 442 { 443 struct ub913_data *priv = sd_to_ub913(sd); 444 struct v4l2_mbus_framefmt *fmt; 445 const struct ub913_format_info *finfo; 446 447 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE && 448 priv->enabled_source_streams) 449 return -EBUSY; 450 451 /* Source format is fully defined by the sink format, so not settable */ 452 if (format->pad == UB913_PAD_SOURCE) 453 return v4l2_subdev_get_fmt(sd, state, format); 454 455 finfo = ub913_find_format(format->format.code); 456 if (!finfo) { 457 finfo = &ub913_formats[0]; 458 format->format.code = finfo->incode; 459 } 460 461 /* Set sink format */ 462 fmt = v4l2_subdev_state_get_format(state, format->pad, format->stream); 463 if (!fmt) 464 return -EINVAL; 465 466 *fmt = format->format; 467 468 /* Propagate to source format, and adjust the mbus code */ 469 fmt = v4l2_subdev_state_get_opposite_stream_format(state, format->pad, 470 format->stream); 471 if (!fmt) 472 return -EINVAL; 473 474 *fmt = format->format; 475 476 fmt->code = finfo->outcode; 477 478 return 0; 479 } 480 481 static int ub913_init_state(struct v4l2_subdev *sd, 482 struct v4l2_subdev_state *state) 483 { 484 struct v4l2_subdev_route routes[] = { 485 { 486 .sink_pad = UB913_PAD_SINK, 487 .sink_stream = 0, 488 .source_pad = UB913_PAD_SOURCE, 489 .source_stream = 0, 490 .flags = V4L2_SUBDEV_ROUTE_FL_ACTIVE, 491 }, 492 }; 493 494 struct v4l2_subdev_krouting routing = { 495 .num_routes = ARRAY_SIZE(routes), 496 .routes = routes, 497 }; 498 499 return _ub913_set_routing(sd, state, &routing); 500 } 501 502 static int ub913_log_status(struct v4l2_subdev *sd) 503 { 504 struct ub913_data *priv = sd_to_ub913(sd); 505 struct device *dev = &priv->client->dev; 506 u8 v, v1, v2; 507 int ret; 508 509 ret = ub913_read(priv, UB913_REG_MODE_SEL, &v, NULL); 510 if (ret) 511 return ret; 512 513 dev_info(dev, "MODE_SEL %#02x\n", v); 514 515 ub913_read(priv, UB913_REG_CRC_ERRORS_LSB, &v1, &ret); 516 ub913_read(priv, UB913_REG_CRC_ERRORS_MSB, &v2, &ret); 517 if (ret) 518 return ret; 519 520 dev_info(dev, "CRC errors %u\n", v1 | (v2 << 8)); 521 522 /* clear CRC errors */ 523 ub913_read(priv, UB913_REG_GENERAL_CFG, &v, &ret); 524 ub913_write(priv, UB913_REG_GENERAL_CFG, 525 v | UB913_REG_GENERAL_CFG_CRC_ERR_RESET, &ret); 526 ub913_write(priv, UB913_REG_GENERAL_CFG, v, &ret); 527 528 if (ret) 529 return ret; 530 531 ret = ub913_read(priv, UB913_REG_GENERAL_STATUS, &v, NULL); 532 if (ret) 533 return ret; 534 535 dev_info(dev, "GENERAL_STATUS %#02x\n", v); 536 537 ret = ub913_read(priv, UB913_REG_PLL_OVR, &v, NULL); 538 if (ret) 539 return ret; 540 541 dev_info(dev, "PLL_OVR %#02x\n", v); 542 543 return 0; 544 } 545 546 static const struct v4l2_subdev_core_ops ub913_subdev_core_ops = { 547 .log_status = ub913_log_status, 548 }; 549 550 static const struct v4l2_subdev_pad_ops ub913_pad_ops = { 551 .enable_streams = ub913_enable_streams, 552 .disable_streams = ub913_disable_streams, 553 .set_routing = ub913_set_routing, 554 .get_frame_desc = ub913_get_frame_desc, 555 .get_fmt = v4l2_subdev_get_fmt, 556 .set_fmt = ub913_set_fmt, 557 }; 558 559 static const struct v4l2_subdev_ops ub913_subdev_ops = { 560 .core = &ub913_subdev_core_ops, 561 .pad = &ub913_pad_ops, 562 }; 563 564 static const struct v4l2_subdev_internal_ops ub913_internal_ops = { 565 .init_state = ub913_init_state, 566 }; 567 568 static const struct media_entity_operations ub913_entity_ops = { 569 .link_validate = v4l2_subdev_link_validate, 570 }; 571 572 static int ub913_notify_bound(struct v4l2_async_notifier *notifier, 573 struct v4l2_subdev *source_subdev, 574 struct v4l2_async_connection *asd) 575 { 576 struct ub913_data *priv = sd_to_ub913(notifier->sd); 577 struct device *dev = &priv->client->dev; 578 int ret; 579 580 ret = media_entity_get_fwnode_pad(&source_subdev->entity, 581 source_subdev->fwnode, 582 MEDIA_PAD_FL_SOURCE); 583 if (ret < 0) { 584 dev_err(dev, "Failed to find pad for %s\n", 585 source_subdev->name); 586 return ret; 587 } 588 589 priv->source_sd = source_subdev; 590 priv->source_sd_pad = ret; 591 592 ret = media_create_pad_link(&source_subdev->entity, priv->source_sd_pad, 593 &priv->sd.entity, UB913_PAD_SINK, 594 MEDIA_LNK_FL_ENABLED | 595 MEDIA_LNK_FL_IMMUTABLE); 596 if (ret) { 597 dev_err(dev, "Unable to link %s:%u -> %s:0\n", 598 source_subdev->name, priv->source_sd_pad, 599 priv->sd.name); 600 return ret; 601 } 602 603 return 0; 604 } 605 606 static const struct v4l2_async_notifier_operations ub913_notify_ops = { 607 .bound = ub913_notify_bound, 608 }; 609 610 static int ub913_v4l2_notifier_register(struct ub913_data *priv) 611 { 612 struct device *dev = &priv->client->dev; 613 struct v4l2_async_connection *asd; 614 struct fwnode_handle *ep_fwnode; 615 int ret; 616 617 ep_fwnode = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 618 UB913_PAD_SINK, 0, 0); 619 if (!ep_fwnode) { 620 dev_err(dev, "No graph endpoint\n"); 621 return -ENODEV; 622 } 623 624 v4l2_async_subdev_nf_init(&priv->notifier, &priv->sd); 625 626 asd = v4l2_async_nf_add_fwnode_remote(&priv->notifier, ep_fwnode, 627 struct v4l2_async_connection); 628 629 fwnode_handle_put(ep_fwnode); 630 631 if (IS_ERR(asd)) { 632 dev_err(dev, "Failed to add subdev: %ld", PTR_ERR(asd)); 633 v4l2_async_nf_cleanup(&priv->notifier); 634 return PTR_ERR(asd); 635 } 636 637 priv->notifier.ops = &ub913_notify_ops; 638 639 ret = v4l2_async_nf_register(&priv->notifier); 640 if (ret) { 641 dev_err(dev, "Failed to register subdev_notifier"); 642 v4l2_async_nf_cleanup(&priv->notifier); 643 return ret; 644 } 645 646 return 0; 647 } 648 649 static void ub913_v4l2_nf_unregister(struct ub913_data *priv) 650 { 651 v4l2_async_nf_unregister(&priv->notifier); 652 v4l2_async_nf_cleanup(&priv->notifier); 653 } 654 655 static int ub913_register_clkout(struct ub913_data *priv) 656 { 657 struct device *dev = &priv->client->dev; 658 const char *name; 659 int ret; 660 661 name = kasprintf(GFP_KERNEL, "ds90ub913.%s.clk_out", dev_name(dev)); 662 if (!name) 663 return -ENOMEM; 664 665 priv->clkout_clk_hw = devm_clk_hw_register_fixed_factor(dev, name, 666 __clk_get_name(priv->clkin), 0, 1, 2); 667 668 kfree(name); 669 670 if (IS_ERR(priv->clkout_clk_hw)) 671 return dev_err_probe(dev, PTR_ERR(priv->clkout_clk_hw), 672 "Cannot register clkout hw\n"); 673 674 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 675 priv->clkout_clk_hw); 676 if (ret) 677 return dev_err_probe(dev, ret, 678 "Cannot add OF clock provider\n"); 679 680 return 0; 681 } 682 683 static int ub913_i2c_master_init(struct ub913_data *priv) 684 { 685 /* i2c fast mode */ 686 u32 scl_high = 600 + 300; /* high period + rise time, ns */ 687 u32 scl_low = 1300 + 300; /* low period + fall time, ns */ 688 unsigned long ref; 689 int ret; 690 691 ref = clk_get_rate(priv->clkin) / 2; 692 693 scl_high = div64_u64((u64)scl_high * ref, 1000000000); 694 scl_low = div64_u64((u64)scl_low * ref, 1000000000); 695 696 ret = ub913_write(priv, UB913_REG_SCL_HIGH_TIME, scl_high, NULL); 697 if (ret) 698 return ret; 699 700 ret = ub913_write(priv, UB913_REG_SCL_LOW_TIME, scl_low, NULL); 701 if (ret) 702 return ret; 703 704 return 0; 705 } 706 707 static int ub913_add_i2c_adapter(struct ub913_data *priv) 708 { 709 struct device *dev = &priv->client->dev; 710 struct i2c_atr_adap_desc desc = { }; 711 struct fwnode_handle *i2c_handle; 712 int ret; 713 714 i2c_handle = device_get_named_child_node(dev, "i2c"); 715 if (!i2c_handle) 716 return 0; 717 718 desc.chan_id = priv->plat_data->port; 719 desc.parent = dev; 720 desc.bus_handle = i2c_handle; 721 desc.num_aliases = 0; 722 723 ret = i2c_atr_add_adapter(priv->plat_data->atr, &desc); 724 725 fwnode_handle_put(i2c_handle); 726 727 if (ret) 728 return ret; 729 730 return 0; 731 } 732 733 static int ub913_parse_dt(struct ub913_data *priv) 734 { 735 struct device *dev = &priv->client->dev; 736 struct v4l2_fwnode_endpoint vep = { 737 .bus_type = V4L2_MBUS_PARALLEL, 738 }; 739 struct fwnode_handle *ep_fwnode; 740 int ret; 741 742 ep_fwnode = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 743 UB913_PAD_SINK, 0, 0); 744 if (!ep_fwnode) 745 return dev_err_probe(dev, -ENOENT, "No sink endpoint\n"); 746 747 ret = v4l2_fwnode_endpoint_parse(ep_fwnode, &vep); 748 749 fwnode_handle_put(ep_fwnode); 750 751 if (ret) 752 return dev_err_probe(dev, ret, 753 "failed to parse sink endpoint data\n"); 754 755 if (vep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING) 756 priv->pclk_polarity_rising = true; 757 else if (vep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) 758 priv->pclk_polarity_rising = false; 759 else 760 return dev_err_probe(dev, -EINVAL, 761 "bad value for 'pclk-sample'\n"); 762 763 return 0; 764 } 765 766 static int ub913_hw_init(struct ub913_data *priv) 767 { 768 struct device *dev = &priv->client->dev; 769 bool mode_override; 770 u8 mode; 771 int ret; 772 u8 v; 773 774 ret = ub913_read(priv, UB913_REG_MODE_SEL, &v, NULL); 775 if (ret) 776 return ret; 777 778 if (!(v & UB913_REG_MODE_SEL_MODE_UP_TO_DATE)) 779 return dev_err_probe(dev, -ENODEV, 780 "Mode value not stabilized\n"); 781 782 mode_override = v & UB913_REG_MODE_SEL_MODE_OVERRIDE; 783 mode = v & UB913_REG_MODE_SEL_MODE_MASK; 784 785 dev_dbg(dev, "mode from %s: %#x\n", 786 mode_override ? "reg" : "deserializer", mode); 787 788 ret = ub913_i2c_master_init(priv); 789 if (ret) 790 return dev_err_probe(dev, ret, "i2c master init failed\n"); 791 792 ret = ub913_update_bits(priv, UB913_REG_GENERAL_CFG, 793 UB913_REG_GENERAL_CFG_PCLK_RISING, 794 FIELD_PREP(UB913_REG_GENERAL_CFG_PCLK_RISING, 795 priv->pclk_polarity_rising), NULL); 796 797 if (ret) 798 return ret; 799 800 return 0; 801 } 802 803 static int ub913_subdev_init(struct ub913_data *priv) 804 { 805 struct device *dev = &priv->client->dev; 806 int ret; 807 808 v4l2_i2c_subdev_init(&priv->sd, priv->client, &ub913_subdev_ops); 809 priv->sd.internal_ops = &ub913_internal_ops; 810 priv->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_STREAMS; 811 priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 812 priv->sd.entity.ops = &ub913_entity_ops; 813 814 priv->pads[0].flags = MEDIA_PAD_FL_SINK; 815 priv->pads[1].flags = MEDIA_PAD_FL_SOURCE; 816 817 ret = media_entity_pads_init(&priv->sd.entity, 2, priv->pads); 818 if (ret) 819 return dev_err_probe(dev, ret, "Failed to init pads\n"); 820 821 ret = v4l2_subdev_init_finalize(&priv->sd); 822 if (ret) 823 goto err_entity_cleanup; 824 825 ret = ub913_v4l2_notifier_register(priv); 826 if (ret) { 827 dev_err_probe(dev, ret, 828 "v4l2 subdev notifier register failed\n"); 829 goto err_subdev_cleanup; 830 } 831 832 ret = v4l2_async_register_subdev(&priv->sd); 833 if (ret) { 834 dev_err_probe(dev, ret, "v4l2_async_register_subdev error\n"); 835 goto err_unreg_notif; 836 } 837 838 return 0; 839 840 err_unreg_notif: 841 ub913_v4l2_nf_unregister(priv); 842 err_subdev_cleanup: 843 v4l2_subdev_cleanup(&priv->sd); 844 err_entity_cleanup: 845 media_entity_cleanup(&priv->sd.entity); 846 847 return ret; 848 } 849 850 static void ub913_subdev_uninit(struct ub913_data *priv) 851 { 852 v4l2_async_unregister_subdev(&priv->sd); 853 ub913_v4l2_nf_unregister(priv); 854 v4l2_subdev_cleanup(&priv->sd); 855 media_entity_cleanup(&priv->sd.entity); 856 } 857 858 static int ub913_probe(struct i2c_client *client) 859 { 860 struct device *dev = &client->dev; 861 struct ub913_data *priv; 862 int ret; 863 864 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 865 if (!priv) 866 return -ENOMEM; 867 868 priv->client = client; 869 870 priv->plat_data = dev_get_platdata(&client->dev); 871 if (!priv->plat_data) 872 return dev_err_probe(dev, -ENODEV, "Platform data missing\n"); 873 874 priv->regmap = devm_regmap_init_i2c(client, &ub913_regmap_config); 875 if (IS_ERR(priv->regmap)) 876 return dev_err_probe(dev, PTR_ERR(priv->regmap), 877 "Failed to init regmap\n"); 878 879 /* 880 * ub913 can also work without ext clock, but that is not supported by 881 * the driver yet. 882 */ 883 priv->clkin = devm_clk_get(dev, "clkin"); 884 if (IS_ERR(priv->clkin)) 885 return dev_err_probe(dev, PTR_ERR(priv->clkin), 886 "Cannot get CLKIN\n"); 887 888 ret = ub913_parse_dt(priv); 889 if (ret) 890 return ret; 891 892 ret = ub913_hw_init(priv); 893 if (ret) 894 return ret; 895 896 ret = ub913_gpiochip_probe(priv); 897 if (ret) 898 return dev_err_probe(dev, ret, "Failed to init gpiochip\n"); 899 900 ret = ub913_register_clkout(priv); 901 if (ret) { 902 dev_err_probe(dev, ret, "Failed to register clkout\n"); 903 goto err_gpiochip_remove; 904 } 905 906 ret = ub913_subdev_init(priv); 907 if (ret) 908 goto err_gpiochip_remove; 909 910 ret = ub913_add_i2c_adapter(priv); 911 if (ret) { 912 dev_err_probe(dev, ret, "failed to add remote i2c adapter\n"); 913 goto err_subdev_uninit; 914 } 915 916 return 0; 917 918 err_subdev_uninit: 919 ub913_subdev_uninit(priv); 920 err_gpiochip_remove: 921 ub913_gpiochip_remove(priv); 922 923 return ret; 924 } 925 926 static void ub913_remove(struct i2c_client *client) 927 { 928 struct v4l2_subdev *sd = i2c_get_clientdata(client); 929 struct ub913_data *priv = sd_to_ub913(sd); 930 931 i2c_atr_del_adapter(priv->plat_data->atr, priv->plat_data->port); 932 933 ub913_subdev_uninit(priv); 934 935 ub913_gpiochip_remove(priv); 936 } 937 938 static const struct i2c_device_id ub913_id[] = { 939 { "ds90ub913a-q1" }, 940 {} 941 }; 942 MODULE_DEVICE_TABLE(i2c, ub913_id); 943 944 static const struct of_device_id ub913_dt_ids[] = { 945 { .compatible = "ti,ds90ub913a-q1" }, 946 {} 947 }; 948 MODULE_DEVICE_TABLE(of, ub913_dt_ids); 949 950 static struct i2c_driver ds90ub913_driver = { 951 .probe = ub913_probe, 952 .remove = ub913_remove, 953 .id_table = ub913_id, 954 .driver = { 955 .name = "ds90ub913a", 956 .of_match_table = ub913_dt_ids, 957 }, 958 }; 959 module_i2c_driver(ds90ub913_driver); 960 961 MODULE_LICENSE("GPL"); 962 MODULE_DESCRIPTION("Texas Instruments DS90UB913 FPD-Link III Serializer Driver"); 963 MODULE_AUTHOR("Luca Ceresoli <luca@lucaceresoli.net>"); 964 MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>"); 965 MODULE_IMPORT_NS("I2C_ATR"); 966