1 /* 2 * Aptina Sensor PLL Configuration 3 * 4 * Copyright (C) 2012 Laurent Pinchart <laurent.pinchart@ideasonboard.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * version 2 as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 */ 15 16 #include <linux/device.h> 17 #include <linux/gcd.h> 18 #include <linux/kernel.h> 19 #include <linux/lcm.h> 20 #include <linux/module.h> 21 22 #include "aptina-pll.h" 23 24 int aptina_pll_calculate(struct device *dev, 25 const struct aptina_pll_limits *limits, 26 struct aptina_pll *pll) 27 { 28 unsigned int mf_min; 29 unsigned int mf_max; 30 unsigned int p1_min; 31 unsigned int p1_max; 32 unsigned int p1; 33 unsigned int div; 34 35 dev_dbg(dev, "PLL: ext clock %u pix clock %u\n", 36 pll->ext_clock, pll->pix_clock); 37 38 if (pll->ext_clock < limits->ext_clock_min || 39 pll->ext_clock > limits->ext_clock_max) { 40 dev_err(dev, "pll: invalid external clock frequency.\n"); 41 return -EINVAL; 42 } 43 44 if (pll->pix_clock == 0 || pll->pix_clock > limits->pix_clock_max) { 45 dev_err(dev, "pll: invalid pixel clock frequency.\n"); 46 return -EINVAL; 47 } 48 49 /* Compute the multiplier M and combined N*P1 divisor. */ 50 div = gcd(pll->pix_clock, pll->ext_clock); 51 pll->m = pll->pix_clock / div; 52 div = pll->ext_clock / div; 53 54 /* We now have the smallest M and N*P1 values that will result in the 55 * desired pixel clock frequency, but they might be out of the valid 56 * range. Compute the factor by which we should multiply them given the 57 * following constraints: 58 * 59 * - minimum/maximum multiplier 60 * - minimum/maximum multiplier output clock frequency assuming the 61 * minimum/maximum N value 62 * - minimum/maximum combined N*P1 divisor 63 */ 64 mf_min = DIV_ROUND_UP(limits->m_min, pll->m); 65 mf_min = max(mf_min, limits->out_clock_min / 66 (pll->ext_clock / limits->n_min * pll->m)); 67 mf_min = max(mf_min, limits->n_min * limits->p1_min / div); 68 mf_max = limits->m_max / pll->m; 69 mf_max = min(mf_max, limits->out_clock_max / 70 (pll->ext_clock / limits->n_max * pll->m)); 71 mf_max = min(mf_max, DIV_ROUND_UP(limits->n_max * limits->p1_max, div)); 72 73 dev_dbg(dev, "pll: mf min %u max %u\n", mf_min, mf_max); 74 if (mf_min > mf_max) { 75 dev_err(dev, "pll: no valid combined N*P1 divisor.\n"); 76 return -EINVAL; 77 } 78 79 /* 80 * We're looking for the highest acceptable P1 value for which a 81 * multiplier factor MF exists that fulfills the following conditions: 82 * 83 * 1. p1 is in the [p1_min, p1_max] range given by the limits and is 84 * even 85 * 2. mf is in the [mf_min, mf_max] range computed above 86 * 3. div * mf is a multiple of p1, in order to compute 87 * n = div * mf / p1 88 * m = pll->m * mf 89 * 4. the internal clock frequency, given by ext_clock / n, is in the 90 * [int_clock_min, int_clock_max] range given by the limits 91 * 5. the output clock frequency, given by ext_clock / n * m, is in the 92 * [out_clock_min, out_clock_max] range given by the limits 93 * 94 * The first naive approach is to iterate over all p1 values acceptable 95 * according to (1) and all mf values acceptable according to (2), and 96 * stop at the first combination that fulfills (3), (4) and (5). This 97 * has a O(n^2) complexity. 98 * 99 * Instead of iterating over all mf values in the [mf_min, mf_max] range 100 * we can compute the mf increment between two acceptable values 101 * according to (3) with 102 * 103 * mf_inc = p1 / gcd(div, p1) (6) 104 * 105 * and round the minimum up to the nearest multiple of mf_inc. This will 106 * restrict the number of mf values to be checked. 107 * 108 * Furthermore, conditions (4) and (5) only restrict the range of 109 * acceptable p1 and mf values by modifying the minimum and maximum 110 * limits. (5) can be expressed as 111 * 112 * ext_clock / (div * mf / p1) * m * mf >= out_clock_min 113 * ext_clock / (div * mf / p1) * m * mf <= out_clock_max 114 * 115 * or 116 * 117 * p1 >= out_clock_min * div / (ext_clock * m) (7) 118 * p1 <= out_clock_max * div / (ext_clock * m) 119 * 120 * Similarly, (4) can be expressed as 121 * 122 * mf >= ext_clock * p1 / (int_clock_max * div) (8) 123 * mf <= ext_clock * p1 / (int_clock_min * div) 124 * 125 * We can thus iterate over the restricted p1 range defined by the 126 * combination of (1) and (7), and then compute the restricted mf range 127 * defined by the combination of (2), (6) and (8). If the resulting mf 128 * range is not empty, any value in the mf range is acceptable. We thus 129 * select the mf lwoer bound and the corresponding p1 value. 130 */ 131 if (limits->p1_min == 0) { 132 dev_err(dev, "pll: P1 minimum value must be >0.\n"); 133 return -EINVAL; 134 } 135 136 p1_min = max(limits->p1_min, DIV_ROUND_UP(limits->out_clock_min * div, 137 pll->ext_clock * pll->m)); 138 p1_max = min(limits->p1_max, limits->out_clock_max * div / 139 (pll->ext_clock * pll->m)); 140 141 for (p1 = p1_max & ~1; p1 >= p1_min; p1 -= 2) { 142 unsigned int mf_inc = p1 / gcd(div, p1); 143 unsigned int mf_high; 144 unsigned int mf_low; 145 146 mf_low = roundup(max(mf_min, DIV_ROUND_UP(pll->ext_clock * p1, 147 limits->int_clock_max * div)), mf_inc); 148 mf_high = min(mf_max, pll->ext_clock * p1 / 149 (limits->int_clock_min * div)); 150 151 if (mf_low > mf_high) 152 continue; 153 154 pll->n = div * mf_low / p1; 155 pll->m *= mf_low; 156 pll->p1 = p1; 157 dev_dbg(dev, "PLL: N %u M %u P1 %u\n", pll->n, pll->m, pll->p1); 158 return 0; 159 } 160 161 dev_err(dev, "pll: no valid N and P1 divisors found.\n"); 162 return -EINVAL; 163 } 164 EXPORT_SYMBOL_GPL(aptina_pll_calculate); 165 166 MODULE_DESCRIPTION("Aptina PLL Helpers"); 167 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>"); 168 MODULE_LICENSE("GPL v2"); 169