xref: /linux/drivers/media/i2c/alvium-csi2.h (revision 9e56ff53b4115875667760445b028357848b4748) 
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Allied Vision Technologies GmbH Alvium camera driver
4  *
5  * Copyright (C) 2023 Tommaso Merciai
6  * Copyright (C) 2023 Martin Hecht
7  * Copyright (C) 2023 Avnet EMG GmbH
8  */
9 
10 #ifndef ALVIUM_CSI2_H_
11 #define ALVIUM_CSI2_H_
12 
13 #include <linux/kernel.h>
14 #include <linux/regulator/consumer.h>
15 #include <media/v4l2-cci.h>
16 #include <media/v4l2-common.h>
17 #include <media/v4l2-ctrls.h>
18 #include <media/v4l2-fwnode.h>
19 #include <media/v4l2-subdev.h>
20 
21 #define REG_BCRM_V4L2					BIT(31)
22 
23 #define REG_BCRM_V4L2_8BIT(n)				(REG_BCRM_V4L2 | CCI_REG8(n))
24 #define REG_BCRM_V4L2_16BIT(n)				(REG_BCRM_V4L2 | CCI_REG16(n))
25 #define REG_BCRM_V4L2_32BIT(n)				(REG_BCRM_V4L2 | CCI_REG32(n))
26 #define REG_BCRM_V4L2_64BIT(n)				(REG_BCRM_V4L2 | CCI_REG64(n))
27 
28 /* Basic Control Register Map register offsets (BCRM) */
29 #define REG_BCRM_MINOR_VERSION_R			CCI_REG16(0x0000)
30 #define REG_BCRM_MAJOR_VERSION_R			CCI_REG16(0x0002)
31 #define REG_BCRM_REG_ADDR_R				CCI_REG16(0x0014)
32 
33 #define REG_BCRM_FEATURE_INQUIRY_R			REG_BCRM_V4L2_64BIT(0x0008)
34 #define REG_BCRM_DEVICE_FW_SPEC_VERSION_R		REG_BCRM_V4L2_8BIT(0x0010)
35 #define REG_BCRM_DEVICE_FW_MAJOR_VERSION_R		REG_BCRM_V4L2_8BIT(0x0011)
36 #define REG_BCRM_DEVICE_FW_MINOR_VERSION_R		REG_BCRM_V4L2_16BIT(0x0012)
37 #define REG_BCRM_DEVICE_FW_PATCH_VERSION_R		REG_BCRM_V4L2_32BIT(0x0014)
38 #define REG_BCRM_WRITE_HANDSHAKE_RW			REG_BCRM_V4L2_8BIT(0x0018)
39 
40 /* Streaming Control Registers */
41 #define REG_BCRM_SUPPORTED_CSI2_LANE_COUNTS_R		REG_BCRM_V4L2_8BIT(0x0040)
42 #define REG_BCRM_CSI2_LANE_COUNT_RW			REG_BCRM_V4L2_8BIT(0x0044)
43 #define REG_BCRM_CSI2_CLOCK_MIN_R			REG_BCRM_V4L2_32BIT(0x0048)
44 #define REG_BCRM_CSI2_CLOCK_MAX_R			REG_BCRM_V4L2_32BIT(0x004c)
45 #define REG_BCRM_CSI2_CLOCK_RW				REG_BCRM_V4L2_32BIT(0x0050)
46 #define REG_BCRM_BUFFER_SIZE_R				REG_BCRM_V4L2_32BIT(0x0054)
47 
48 #define REG_BCRM_IPU_X_MIN_W				REG_BCRM_V4L2_32BIT(0x0058)
49 #define REG_BCRM_IPU_X_MAX_W				REG_BCRM_V4L2_32BIT(0x005c)
50 #define REG_BCRM_IPU_X_INC_W				REG_BCRM_V4L2_32BIT(0x0060)
51 #define REG_BCRM_IPU_Y_MIN_W				REG_BCRM_V4L2_32BIT(0x0064)
52 #define REG_BCRM_IPU_Y_MAX_W				REG_BCRM_V4L2_32BIT(0x0068)
53 #define REG_BCRM_IPU_Y_INC_W				REG_BCRM_V4L2_32BIT(0x006c)
54 #define REG_BCRM_IPU_X_R				REG_BCRM_V4L2_32BIT(0x0070)
55 #define REG_BCRM_IPU_Y_R				REG_BCRM_V4L2_32BIT(0x0074)
56 
57 #define REG_BCRM_PHY_RESET_RW				REG_BCRM_V4L2_8BIT(0x0078)
58 #define REG_BCRM_LP2HS_DELAY_RW				REG_BCRM_V4L2_32BIT(0x007c)
59 
60 /* Acquisition Control Registers */
61 #define REG_BCRM_ACQUISITION_START_RW			REG_BCRM_V4L2_8BIT(0x0080)
62 #define REG_BCRM_ACQUISITION_STOP_RW			REG_BCRM_V4L2_8BIT(0x0084)
63 #define REG_BCRM_ACQUISITION_ABORT_RW			REG_BCRM_V4L2_8BIT(0x0088)
64 #define REG_BCRM_ACQUISITION_STATUS_R			REG_BCRM_V4L2_8BIT(0x008c)
65 #define REG_BCRM_ACQUISITION_FRAME_RATE_RW		REG_BCRM_V4L2_64BIT(0x0090)
66 #define REG_BCRM_ACQUISITION_FRAME_RATE_MIN_R		REG_BCRM_V4L2_64BIT(0x0098)
67 #define REG_BCRM_ACQUISITION_FRAME_RATE_MAX_R		REG_BCRM_V4L2_64BIT(0x00a0)
68 #define REG_BCRM_ACQUISITION_FRAME_RATE_INC_R		REG_BCRM_V4L2_64BIT(0x00a8)
69 #define REG_BCRM_ACQUISITION_FRAME_RATE_ENABLE_RW	REG_BCRM_V4L2_8BIT(0x00b0)
70 
71 #define REG_BCRM_FRAME_START_TRIGGER_MODE_RW		REG_BCRM_V4L2_8BIT(0x00b4)
72 #define REG_BCRM_FRAME_START_TRIGGER_SOURCE_RW		REG_BCRM_V4L2_8BIT(0x00b8)
73 #define REG_BCRM_FRAME_START_TRIGGER_ACTIVATION_RW	REG_BCRM_V4L2_8BIT(0x00bc)
74 #define REG_BCRM_FRAME_START_TRIGGER_SOFTWARE_W		REG_BCRM_V4L2_8BIT(0x00c0)
75 #define REG_BCRM_FRAME_START_TRIGGER_DELAY_RW		REG_BCRM_V4L2_32BIT(0x00c4)
76 #define REG_BCRM_EXPOSURE_ACTIVE_LINE_MODE_RW		REG_BCRM_V4L2_8BIT(0x00c8)
77 #define REG_BCRM_EXPOSURE_ACTIVE_LINE_SELECTOR_RW	REG_BCRM_V4L2_8BIT(0x00cc)
78 #define REG_BCRM_LINE_CONFIGURATION_RW			REG_BCRM_V4L2_32BIT(0x00d0)
79 
80 #define REG_BCRM_IMG_WIDTH_RW				REG_BCRM_V4L2_32BIT(0x0100)
81 #define REG_BCRM_IMG_WIDTH_MIN_R			REG_BCRM_V4L2_32BIT(0x0104)
82 #define REG_BCRM_IMG_WIDTH_MAX_R			REG_BCRM_V4L2_32BIT(0x0108)
83 #define REG_BCRM_IMG_WIDTH_INC_R			REG_BCRM_V4L2_32BIT(0x010c)
84 
85 #define REG_BCRM_IMG_HEIGHT_RW				REG_BCRM_V4L2_32BIT(0x0110)
86 #define REG_BCRM_IMG_HEIGHT_MIN_R			REG_BCRM_V4L2_32BIT(0x0114)
87 #define REG_BCRM_IMG_HEIGHT_MAX_R			REG_BCRM_V4L2_32BIT(0x0118)
88 #define REG_BCRM_IMG_HEIGHT_INC_R			REG_BCRM_V4L2_32BIT(0x011c)
89 
90 #define REG_BCRM_IMG_OFFSET_X_RW			REG_BCRM_V4L2_32BIT(0x0120)
91 #define REG_BCRM_IMG_OFFSET_X_MIN_R			REG_BCRM_V4L2_32BIT(0x0124)
92 #define REG_BCRM_IMG_OFFSET_X_MAX_R			REG_BCRM_V4L2_32BIT(0x0128)
93 #define REG_BCRM_IMG_OFFSET_X_INC_R			REG_BCRM_V4L2_32BIT(0x012c)
94 
95 #define REG_BCRM_IMG_OFFSET_Y_RW			REG_BCRM_V4L2_32BIT(0x0130)
96 #define REG_BCRM_IMG_OFFSET_Y_MIN_R			REG_BCRM_V4L2_32BIT(0x0134)
97 #define REG_BCRM_IMG_OFFSET_Y_MAX_R			REG_BCRM_V4L2_32BIT(0x0138)
98 #define REG_BCRM_IMG_OFFSET_Y_INC_R			REG_BCRM_V4L2_32BIT(0x013c)
99 
100 #define REG_BCRM_IMG_MIPI_DATA_FORMAT_RW		REG_BCRM_V4L2_32BIT(0x0140)
101 #define REG_BCRM_IMG_AVAILABLE_MIPI_DATA_FORMATS_R	REG_BCRM_V4L2_64BIT(0x0148)
102 #define REG_BCRM_IMG_BAYER_PATTERN_INQUIRY_R		REG_BCRM_V4L2_8BIT(0x0150)
103 #define REG_BCRM_IMG_BAYER_PATTERN_RW			REG_BCRM_V4L2_8BIT(0x0154)
104 #define REG_BCRM_IMG_REVERSE_X_RW			REG_BCRM_V4L2_8BIT(0x0158)
105 #define REG_BCRM_IMG_REVERSE_Y_RW			REG_BCRM_V4L2_8BIT(0x015c)
106 
107 #define REG_BCRM_SENSOR_WIDTH_R				REG_BCRM_V4L2_32BIT(0x0160)
108 #define REG_BCRM_SENSOR_HEIGHT_R			REG_BCRM_V4L2_32BIT(0x0164)
109 #define REG_BCRM_WIDTH_MAX_R				REG_BCRM_V4L2_32BIT(0x0168)
110 #define REG_BCRM_HEIGHT_MAX_R				REG_BCRM_V4L2_32BIT(0x016c)
111 
112 #define REG_BCRM_EXPOSURE_TIME_RW			REG_BCRM_V4L2_64BIT(0x0180)
113 #define REG_BCRM_EXPOSURE_TIME_MIN_R			REG_BCRM_V4L2_64BIT(0x0188)
114 #define REG_BCRM_EXPOSURE_TIME_MAX_R			REG_BCRM_V4L2_64BIT(0x0190)
115 #define REG_BCRM_EXPOSURE_TIME_INC_R			REG_BCRM_V4L2_64BIT(0x0198)
116 #define REG_BCRM_EXPOSURE_AUTO_RW			REG_BCRM_V4L2_8BIT(0x01a0)
117 
118 #define REG_BCRM_INTENSITY_AUTO_PRECEDENCE_RW		REG_BCRM_V4L2_8BIT(0x01a4)
119 #define REG_BCRM_INTENSITY_AUTO_PRECEDENCE_VALUE_RW	REG_BCRM_V4L2_32BIT(0x01a8)
120 #define REG_BCRM_INTENSITY_AUTO_PRECEDENCE_MIN_R	REG_BCRM_V4L2_32BIT(0x01ac)
121 #define REG_BCRM_INTENSITY_AUTO_PRECEDENCE_MAX_R	REG_BCRM_V4L2_32BIT(0x01b0)
122 #define REG_BCRM_INTENSITY_AUTO_PRECEDENCE_INC_R	REG_BCRM_V4L2_32BIT(0x01b4)
123 
124 #define REG_BCRM_BLACK_LEVEL_RW				REG_BCRM_V4L2_32BIT(0x01b8)
125 #define REG_BCRM_BLACK_LEVEL_MIN_R			REG_BCRM_V4L2_32BIT(0x01bc)
126 #define REG_BCRM_BLACK_LEVEL_MAX_R			REG_BCRM_V4L2_32BIT(0x01c0)
127 #define REG_BCRM_BLACK_LEVEL_INC_R			REG_BCRM_V4L2_32BIT(0x01c4)
128 
129 #define REG_BCRM_GAIN_RW				REG_BCRM_V4L2_64BIT(0x01c8)
130 #define REG_BCRM_GAIN_MIN_R				REG_BCRM_V4L2_64BIT(0x01d0)
131 #define REG_BCRM_GAIN_MAX_R				REG_BCRM_V4L2_64BIT(0x01d8)
132 #define REG_BCRM_GAIN_INC_R				REG_BCRM_V4L2_64BIT(0x01e0)
133 #define REG_BCRM_GAIN_AUTO_RW				REG_BCRM_V4L2_8BIT(0x01e8)
134 
135 #define REG_BCRM_GAMMA_RW				REG_BCRM_V4L2_64BIT(0x01f0)
136 #define REG_BCRM_GAMMA_MIN_R				REG_BCRM_V4L2_64BIT(0x01f8)
137 #define REG_BCRM_GAMMA_MAX_R				REG_BCRM_V4L2_64BIT(0x0200)
138 #define REG_BCRM_GAMMA_INC_R				REG_BCRM_V4L2_64BIT(0x0208)
139 
140 #define REG_BCRM_CONTRAST_VALUE_RW			REG_BCRM_V4L2_32BIT(0x0214)
141 #define REG_BCRM_CONTRAST_VALUE_MIN_R			REG_BCRM_V4L2_32BIT(0x0218)
142 #define REG_BCRM_CONTRAST_VALUE_MAX_R			REG_BCRM_V4L2_32BIT(0x021c)
143 #define REG_BCRM_CONTRAST_VALUE_INC_R			REG_BCRM_V4L2_32BIT(0x0220)
144 
145 #define REG_BCRM_SATURATION_RW				REG_BCRM_V4L2_32BIT(0x0240)
146 #define REG_BCRM_SATURATION_MIN_R			REG_BCRM_V4L2_32BIT(0x0244)
147 #define REG_BCRM_SATURATION_MAX_R			REG_BCRM_V4L2_32BIT(0x0248)
148 #define REG_BCRM_SATURATION_INC_R			REG_BCRM_V4L2_32BIT(0x024c)
149 
150 #define REG_BCRM_HUE_RW					REG_BCRM_V4L2_32BIT(0x0250)
151 #define REG_BCRM_HUE_MIN_R				REG_BCRM_V4L2_32BIT(0x0254)
152 #define REG_BCRM_HUE_MAX_R				REG_BCRM_V4L2_32BIT(0x0258)
153 #define REG_BCRM_HUE_INC_R				REG_BCRM_V4L2_32BIT(0x025c)
154 
155 #define REG_BCRM_ALL_BALANCE_RATIO_RW			REG_BCRM_V4L2_64BIT(0x0260)
156 #define REG_BCRM_ALL_BALANCE_RATIO_MIN_R		REG_BCRM_V4L2_64BIT(0x0268)
157 #define REG_BCRM_ALL_BALANCE_RATIO_MAX_R		REG_BCRM_V4L2_64BIT(0x0270)
158 #define REG_BCRM_ALL_BALANCE_RATIO_INC_R		REG_BCRM_V4L2_64BIT(0x0278)
159 
160 #define REG_BCRM_RED_BALANCE_RATIO_RW			REG_BCRM_V4L2_64BIT(0x0280)
161 #define REG_BCRM_RED_BALANCE_RATIO_MIN_R		REG_BCRM_V4L2_64BIT(0x0288)
162 #define REG_BCRM_RED_BALANCE_RATIO_MAX_R		REG_BCRM_V4L2_64BIT(0x0290)
163 #define REG_BCRM_RED_BALANCE_RATIO_INC_R		REG_BCRM_V4L2_64BIT(0x0298)
164 
165 #define REG_BCRM_GREEN_BALANCE_RATIO_RW			REG_BCRM_V4L2_64BIT(0x02a0)
166 #define REG_BCRM_GREEN_BALANCE_RATIO_MIN_R		REG_BCRM_V4L2_64BIT(0x02a8)
167 #define REG_BCRM_GREEN_BALANCE_RATIO_MAX_R		REG_BCRM_V4L2_64BIT(0x02b0)
168 #define REG_BCRM_GREEN_BALANCE_RATIO_INC_R		REG_BCRM_V4L2_64BIT(0x02b8)
169 
170 #define REG_BCRM_BLUE_BALANCE_RATIO_RW			REG_BCRM_V4L2_64BIT(0x02c0)
171 #define REG_BCRM_BLUE_BALANCE_RATIO_MIN_R		REG_BCRM_V4L2_64BIT(0x02c8)
172 #define REG_BCRM_BLUE_BALANCE_RATIO_MAX_R		REG_BCRM_V4L2_64BIT(0x02d0)
173 #define REG_BCRM_BLUE_BALANCE_RATIO_INC_R		REG_BCRM_V4L2_64BIT(0x02d8)
174 
175 #define REG_BCRM_WHITE_BALANCE_AUTO_RW			REG_BCRM_V4L2_8BIT(0x02e0)
176 #define REG_BCRM_SHARPNESS_RW				REG_BCRM_V4L2_32BIT(0x0300)
177 #define REG_BCRM_SHARPNESS_MIN_R			REG_BCRM_V4L2_32BIT(0x0304)
178 #define REG_BCRM_SHARPNESS_MAX_R			REG_BCRM_V4L2_32BIT(0x0308)
179 #define REG_BCRM_SHARPNESS_INC_R			REG_BCRM_V4L2_32BIT(0x030c)
180 
181 #define REG_BCRM_DEVICE_TEMPERATURE_R			REG_BCRM_V4L2_32BIT(0x0310)
182 #define REG_BCRM_EXPOSURE_AUTO_MIN_RW			REG_BCRM_V4L2_64BIT(0x0330)
183 #define REG_BCRM_EXPOSURE_AUTO_MAX_RW			REG_BCRM_V4L2_64BIT(0x0338)
184 #define REG_BCRM_GAIN_AUTO_MIN_RW			REG_BCRM_V4L2_64BIT(0x0340)
185 #define REG_BCRM_GAIN_AUTO_MAX_RW			REG_BCRM_V4L2_64BIT(0x0348)
186 
187 /* Heartbeat reg*/
188 #define REG_BCRM_HEARTBEAT_RW				CCI_REG8(0x021f)
189 
190 /* GenCP Registers */
191 #define REG_GENCP_CHANGEMODE_W				CCI_REG8(0x021c)
192 #define REG_GENCP_CURRENTMODE_R				CCI_REG8(0x021d)
193 #define REG_GENCP_IN_HANDSHAKE_RW			CCI_REG8(0x001c)
194 #define REG_GENCP_OUT_SIZE_W				CCI_REG16(0x0020)
195 #define REG_GENCP_IN_SIZE_R				CCI_REG16(0x0024)
196 
197 /* defines */
198 #define REG_BCRM_HANDSHAKE_STATUS_MASK			0x01
199 #define REG_BCRM_HANDSHAKE_AVAILABLE_MASK		0x80
200 
201 #define BCRM_HANDSHAKE_W_DONE_EN_BIT			BIT(0)
202 
203 #define ALVIUM_DEFAULT_FR_HZ				10
204 #define ALVIUM_DEFAULT_PIXEL_RATE_MHZ			148000000
205 
206 #define ALVIUM_LP2HS_DELAY_MS				100
207 
208 enum alvium_bcrm_mode {
209 	ALVIUM_BCM_MODE,
210 	ALVIUM_GENCP_MODE,
211 	ALVIUM_NUM_MODE
212 };
213 
214 enum alvium_mipi_fmt {
215 	ALVIUM_FMT_UYVY8_2X8 = 0,
216 	ALVIUM_FMT_UYVY8_1X16,
217 	ALVIUM_FMT_YUYV8_1X16,
218 	ALVIUM_FMT_YUYV8_2X8,
219 	ALVIUM_FMT_YUYV10_1X20,
220 	ALVIUM_FMT_RGB888_1X24,
221 	ALVIUM_FMT_RBG888_1X24,
222 	ALVIUM_FMT_BGR888_1X24,
223 	ALVIUM_FMT_RGB888_3X8,
224 	ALVIUM_FMT_Y8_1X8,
225 	ALVIUM_FMT_SGRBG8_1X8,
226 	ALVIUM_FMT_SRGGB8_1X8,
227 	ALVIUM_FMT_SGBRG8_1X8,
228 	ALVIUM_FMT_SBGGR8_1X8,
229 	ALVIUM_FMT_Y10_1X10,
230 	ALVIUM_FMT_SGRBG10_1X10,
231 	ALVIUM_FMT_SRGGB10_1X10,
232 	ALVIUM_FMT_SGBRG10_1X10,
233 	ALVIUM_FMT_SBGGR10_1X10,
234 	ALVIUM_FMT_Y12_1X12,
235 	ALVIUM_FMT_SGRBG12_1X12,
236 	ALVIUM_FMT_SRGGB12_1X12,
237 	ALVIUM_FMT_SGBRG12_1X12,
238 	ALVIUM_FMT_SBGGR12_1X12,
239 	ALVIUM_FMT_SBGGR14_1X14,
240 	ALVIUM_FMT_SGBRG14_1X14,
241 	ALVIUM_FMT_SRGGB14_1X14,
242 	ALVIUM_FMT_SGRBG14_1X14,
243 	ALVIUM_NUM_SUPP_MIPI_DATA_FMT
244 };
245 
246 enum alvium_av_bayer_bit {
247 	ALVIUM_BIT_BAY_NONE = -1,
248 	ALVIUM_BIT_BAY_MONO = 0,
249 	ALVIUM_BIT_BAY_GR,
250 	ALVIUM_BIT_BAY_RG,
251 	ALVIUM_BIT_BAY_GB,
252 	ALVIUM_BIT_BAY_BG,
253 	ALVIUM_NUM_BAY_AV_BIT
254 };
255 
256 enum alvium_av_mipi_bit {
257 	ALVIUM_BIT_YUV420_8_LEG = 0,
258 	ALVIUM_BIT_YUV420_8,
259 	ALVIUM_BIT_YUV420_10,
260 	ALVIUM_BIT_YUV420_8_CSPS,
261 	ALVIUM_BIT_YUV420_10_CSPS,
262 	ALVIUM_BIT_YUV422_8,
263 	ALVIUM_BIT_YUV422_10,
264 	ALVIUM_BIT_RGB888,
265 	ALVIUM_BIT_RGB666,
266 	ALVIUM_BIT_RGB565,
267 	ALVIUM_BIT_RGB555,
268 	ALVIUM_BIT_RGB444,
269 	ALVIUM_BIT_RAW6,
270 	ALVIUM_BIT_RAW7,
271 	ALVIUM_BIT_RAW8,
272 	ALVIUM_BIT_RAW10,
273 	ALVIUM_BIT_RAW12,
274 	ALVIUM_BIT_RAW14,
275 	ALVIUM_BIT_JPEG,
276 	ALVIUM_NUM_SUPP_MIPI_DATA_BIT
277 };
278 
279 struct alvium_avail_feat {
280 	u64 rev_x:1;
281 	u64 rev_y:1;
282 	u64 int_autop:1;
283 	u64 black_lvl:1;
284 	u64 gain:1;
285 	u64 gamma:1;
286 	u64 contrast:1;
287 	u64 sat:1;
288 	u64 hue:1;
289 	u64 whiteb:1;
290 	u64 sharp:1;
291 	u64 auto_exp:1;
292 	u64 auto_gain:1;
293 	u64 auto_whiteb:1;
294 	u64 dev_temp:1;
295 	u64 acq_abort:1;
296 	u64 acq_fr:1;
297 	u64 fr_trigger:1;
298 	u64 exp_acq_line:1;
299 	u64 reserved:45;
300 };
301 
302 struct alvium_avail_mipi_fmt {
303 	u64 yuv420_8_leg:1;
304 	u64 yuv420_8:1;
305 	u64 yuv420_10:1;
306 	u64 yuv420_8_csps:1;
307 	u64 yuv420_10_csps:1;
308 	u64 yuv422_8:1;
309 	u64 yuv422_10:1;
310 	u64 rgb888:1;
311 	u64 rgb666:1;
312 	u64 rgb565:1;
313 	u64 rgb555:1;
314 	u64 rgb444:1;
315 	u64 raw6:1;
316 	u64 raw7:1;
317 	u64 raw8:1;
318 	u64 raw10:1;
319 	u64 raw12:1;
320 	u64 raw14:1;
321 	u64 jpeg:1;
322 	u64 reserved:45;
323 };
324 
325 struct alvium_avail_bayer {
326 	u8 mono:1;
327 	u8 gr:1;
328 	u8 rg:1;
329 	u8 gb:1;
330 	u8 bg:1;
331 	u8 reserved:3;
332 };
333 
334 struct alvium_mode {
335 	struct v4l2_rect crop;
336 	struct v4l2_mbus_framefmt fmt;
337 	u32 width;
338 	u32 height;
339 };
340 
341 struct alvium_pixfmt {
342 	u32 code;
343 	u32 colorspace;
344 	u64 mipi_fmt_regval;
345 	u64 bay_fmt_regval;
346 	u8 id;
347 	u8 is_raw;
348 	u8 fmt_av_bit;
349 	u8 bay_av_bit;
350 };
351 
352 struct alvium_ctrls {
353 	struct v4l2_ctrl_handler handler;
354 	struct v4l2_ctrl *pixel_rate;
355 	struct v4l2_ctrl *link_freq;
356 	struct v4l2_ctrl *auto_exp;
357 	struct v4l2_ctrl *exposure;
358 	struct v4l2_ctrl *auto_wb;
359 	struct v4l2_ctrl *blue_balance;
360 	struct v4l2_ctrl *red_balance;
361 	struct v4l2_ctrl *auto_gain;
362 	struct v4l2_ctrl *gain;
363 	struct v4l2_ctrl *saturation;
364 	struct v4l2_ctrl *hue;
365 	struct v4l2_ctrl *contrast;
366 	struct v4l2_ctrl *gamma;
367 	struct v4l2_ctrl *sharpness;
368 	struct v4l2_ctrl *hflip;
369 	struct v4l2_ctrl *vflip;
370 };
371 
372 struct alvium_dev {
373 	struct i2c_client *i2c_client;
374 	struct v4l2_subdev sd;
375 	struct v4l2_fwnode_endpoint ep;
376 	struct media_pad pad;
377 	struct regmap *regmap;
378 
379 	struct regulator *reg_vcc;
380 
381 	u16 bcrm_addr;
382 
383 	struct alvium_avail_feat avail_ft;
384 	u8 is_mipi_fmt_avail[ALVIUM_NUM_SUPP_MIPI_DATA_BIT];
385 	u8 is_bay_avail[ALVIUM_NUM_BAY_AV_BIT];
386 
387 	u32 min_csi_clk;
388 	u32 max_csi_clk;
389 	u32 dft_img_width;
390 	u32 img_min_width;
391 	u32 img_max_width;
392 	u32 img_inc_width;
393 	u32 dft_img_height;
394 	u32 img_min_height;
395 	u32 img_max_height;
396 	u32 img_inc_height;
397 	u32 min_offx;
398 	u32 max_offx;
399 	u32 inc_offx;
400 	u32 min_offy;
401 	u32 max_offy;
402 	u32 inc_offy;
403 	u64 dft_gain;
404 	u64 min_gain;
405 	u64 max_gain;
406 	u64 inc_gain;
407 	u64 dft_exp;
408 	u64 min_exp;
409 	u64 max_exp;
410 	u64 inc_exp;
411 	u64 dft_rbalance;
412 	u64 min_rbalance;
413 	u64 max_rbalance;
414 	u64 inc_rbalance;
415 	u64 dft_bbalance;
416 	u64 min_bbalance;
417 	u64 max_bbalance;
418 	u64 inc_bbalance;
419 	s32 dft_hue;
420 	s32 min_hue;
421 	s32 max_hue;
422 	s32 inc_hue;
423 	u32 dft_contrast;
424 	u32 min_contrast;
425 	u32 max_contrast;
426 	u32 inc_contrast;
427 	u32 dft_sat;
428 	u32 min_sat;
429 	u32 max_sat;
430 	u32 inc_sat;
431 	s32 dft_black_lvl;
432 	s32 min_black_lvl;
433 	s32 max_black_lvl;
434 	s32 inc_black_lvl;
435 	u64 dft_gamma;
436 	u64 min_gamma;
437 	u64 max_gamma;
438 	u64 inc_gamma;
439 	s32 dft_sharp;
440 	s32 min_sharp;
441 	s32 max_sharp;
442 	s32 inc_sharp;
443 
444 	struct alvium_mode mode;
445 	struct v4l2_fract frame_interval;
446 	u64 dft_fr;
447 	u64 min_fr;
448 	u64 max_fr;
449 	u64 fr;
450 
451 	u8 h_sup_csi_lanes;
452 	u64 link_freq;
453 
454 	struct alvium_ctrls ctrls;
455 
456 	u8 bcrm_mode;
457 
458 	struct alvium_pixfmt *alvium_csi2_fmt;
459 	u8 alvium_csi2_fmt_n;
460 
461 	u8 streaming;
462 	u8 apply_fiv;
463 };
464 
465 static inline struct alvium_dev *sd_to_alvium(struct v4l2_subdev *sd)
466 {
467 	return container_of_const(sd, struct alvium_dev, sd);
468 }
469 
470 static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl)
471 {
472 	return &container_of_const(ctrl->handler, struct alvium_dev,
473 					  ctrls.handler)->sd;
474 }
475 #endif /* ALVIUM_CSI2_H_ */
476