1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * adv7842 - Analog Devices ADV7842 video decoder driver 4 * 5 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved. 6 */ 7 8 /* 9 * References (c = chapter, p = page): 10 * REF_01 - Analog devices, ADV7842, 11 * Register Settings Recommendations, Rev. 1.9, April 2011 12 * REF_02 - Analog devices, Software User Guide, UG-206, 13 * ADV7842 I2C Register Maps, Rev. 0, November 2010 14 * REF_03 - Analog devices, Hardware User Guide, UG-214, 15 * ADV7842 Fast Switching 2:1 HDMI 1.4 Receiver with 3D-Comb 16 * Decoder and Digitizer , Rev. 0, January 2011 17 */ 18 19 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/slab.h> 23 #include <linux/i2c.h> 24 #include <linux/delay.h> 25 #include <linux/videodev2.h> 26 #include <linux/workqueue.h> 27 #include <linux/v4l2-dv-timings.h> 28 #include <linux/hdmi.h> 29 #include <media/cec.h> 30 #include <media/v4l2-device.h> 31 #include <media/v4l2-event.h> 32 #include <media/v4l2-ctrls.h> 33 #include <media/v4l2-dv-timings.h> 34 #include <media/i2c/adv7842.h> 35 36 static int debug; 37 module_param(debug, int, 0644); 38 MODULE_PARM_DESC(debug, "debug level (0-2)"); 39 40 MODULE_DESCRIPTION("Analog Devices ADV7842 video decoder driver"); 41 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>"); 42 MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>"); 43 MODULE_LICENSE("GPL"); 44 45 /* ADV7842 system clock frequency */ 46 #define ADV7842_fsc (28636360) 47 48 #define ADV7842_RGB_OUT (1 << 1) 49 50 #define ADV7842_OP_FORMAT_SEL_8BIT (0 << 0) 51 #define ADV7842_OP_FORMAT_SEL_10BIT (1 << 0) 52 #define ADV7842_OP_FORMAT_SEL_12BIT (2 << 0) 53 54 #define ADV7842_OP_MODE_SEL_SDR_422 (0 << 5) 55 #define ADV7842_OP_MODE_SEL_DDR_422 (1 << 5) 56 #define ADV7842_OP_MODE_SEL_SDR_444 (2 << 5) 57 #define ADV7842_OP_MODE_SEL_DDR_444 (3 << 5) 58 #define ADV7842_OP_MODE_SEL_SDR_422_2X (4 << 5) 59 #define ADV7842_OP_MODE_SEL_ADI_CM (5 << 5) 60 61 #define ADV7842_OP_CH_SEL_GBR (0 << 5) 62 #define ADV7842_OP_CH_SEL_GRB (1 << 5) 63 #define ADV7842_OP_CH_SEL_BGR (2 << 5) 64 #define ADV7842_OP_CH_SEL_RGB (3 << 5) 65 #define ADV7842_OP_CH_SEL_BRG (4 << 5) 66 #define ADV7842_OP_CH_SEL_RBG (5 << 5) 67 68 #define ADV7842_OP_SWAP_CB_CR (1 << 0) 69 70 #define ADV7842_MAX_ADDRS (3) 71 72 /* 73 ********************************************************************** 74 * 75 * Arrays with configuration parameters for the ADV7842 76 * 77 ********************************************************************** 78 */ 79 80 struct adv7842_format_info { 81 u32 code; 82 u8 op_ch_sel; 83 bool rgb_out; 84 bool swap_cb_cr; 85 u8 op_format_sel; 86 }; 87 88 struct adv7842_state { 89 struct adv7842_platform_data pdata; 90 struct v4l2_subdev sd; 91 struct media_pad pads[ADV7842_PAD_SOURCE + 1]; 92 struct v4l2_ctrl_handler hdl; 93 enum adv7842_mode mode; 94 struct v4l2_dv_timings timings; 95 enum adv7842_vid_std_select vid_std_select; 96 97 const struct adv7842_format_info *format; 98 99 v4l2_std_id norm; 100 struct { 101 u8 edid[512]; 102 u32 blocks; 103 u32 present; 104 } hdmi_edid; 105 struct { 106 u8 edid[128]; 107 u32 blocks; 108 u32 present; 109 } vga_edid; 110 struct v4l2_fract aspect_ratio; 111 u32 rgb_quantization_range; 112 bool is_cea_format; 113 struct delayed_work delayed_work_enable_hotplug; 114 bool restart_stdi_once; 115 bool hdmi_port_a; 116 117 struct dentry *debugfs_dir; 118 struct v4l2_debugfs_if *infoframes; 119 120 /* i2c clients */ 121 struct i2c_client *i2c_sdp_io; 122 struct i2c_client *i2c_sdp; 123 struct i2c_client *i2c_cp; 124 struct i2c_client *i2c_vdp; 125 struct i2c_client *i2c_afe; 126 struct i2c_client *i2c_hdmi; 127 struct i2c_client *i2c_repeater; 128 struct i2c_client *i2c_edid; 129 struct i2c_client *i2c_infoframe; 130 struct i2c_client *i2c_cec; 131 struct i2c_client *i2c_avlink; 132 133 /* controls */ 134 struct v4l2_ctrl *detect_tx_5v_ctrl; 135 struct v4l2_ctrl *analog_sampling_phase_ctrl; 136 struct v4l2_ctrl *free_run_color_ctrl_manual; 137 struct v4l2_ctrl *free_run_color_ctrl; 138 struct v4l2_ctrl *rgb_quantization_range_ctrl; 139 140 struct cec_adapter *cec_adap; 141 u8 cec_addr[ADV7842_MAX_ADDRS]; 142 u8 cec_valid_addrs; 143 bool cec_enabled_adap; 144 }; 145 146 /* Unsupported timings. This device cannot support 720p30. */ 147 static const struct v4l2_dv_timings adv7842_timings_exceptions[] = { 148 V4L2_DV_BT_CEA_1280X720P30, 149 { } 150 }; 151 152 static bool adv7842_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl) 153 { 154 int i; 155 156 for (i = 0; adv7842_timings_exceptions[i].bt.width; i++) 157 if (v4l2_match_dv_timings(t, adv7842_timings_exceptions + i, 0, false)) 158 return false; 159 return true; 160 } 161 162 struct adv7842_video_standards { 163 struct v4l2_dv_timings timings; 164 u8 vid_std; 165 u8 v_freq; 166 }; 167 168 /* sorted by number of lines */ 169 static const struct adv7842_video_standards adv7842_prim_mode_comp[] = { 170 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */ 171 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 172 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 }, 173 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 }, 174 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 175 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 176 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 177 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 178 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 179 /* TODO add 1920x1080P60_RB (CVT timing) */ 180 { }, 181 }; 182 183 /* sorted by number of lines */ 184 static const struct adv7842_video_standards adv7842_prim_mode_gr[] = { 185 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 186 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 187 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 188 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 189 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 190 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 191 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 192 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 193 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 194 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 195 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 196 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 197 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 198 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 199 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 200 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 }, 201 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 }, 202 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 }, 203 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 }, 204 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */ 205 /* TODO add 1600X1200P60_RB (not a DMT timing) */ 206 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 }, 207 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */ 208 { }, 209 }; 210 211 /* sorted by number of lines */ 212 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_comp[] = { 213 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, 214 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 215 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 }, 216 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 }, 217 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 218 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 219 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 220 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 221 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 222 { }, 223 }; 224 225 /* sorted by number of lines */ 226 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_gr[] = { 227 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 228 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 229 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 230 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 231 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 232 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 233 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 234 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 235 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 236 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 237 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 238 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 239 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 240 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 241 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 242 { }, 243 }; 244 245 static const struct v4l2_event adv7842_ev_fmt = { 246 .type = V4L2_EVENT_SOURCE_CHANGE, 247 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, 248 }; 249 250 /* ----------------------------------------------------------------------- */ 251 252 static inline struct adv7842_state *to_state(struct v4l2_subdev *sd) 253 { 254 return container_of(sd, struct adv7842_state, sd); 255 } 256 257 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) 258 { 259 return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd; 260 } 261 262 static inline unsigned htotal(const struct v4l2_bt_timings *t) 263 { 264 return V4L2_DV_BT_FRAME_WIDTH(t); 265 } 266 267 static inline unsigned vtotal(const struct v4l2_bt_timings *t) 268 { 269 return V4L2_DV_BT_FRAME_HEIGHT(t); 270 } 271 272 273 /* ----------------------------------------------------------------------- */ 274 275 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client, 276 u8 command, bool check) 277 { 278 union i2c_smbus_data data; 279 280 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags, 281 I2C_SMBUS_READ, command, 282 I2C_SMBUS_BYTE_DATA, &data)) 283 return data.byte; 284 if (check) 285 v4l_err(client, "error reading %02x, %02x\n", 286 client->addr, command); 287 return -EIO; 288 } 289 290 static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command) 291 { 292 int i; 293 294 for (i = 0; i < 3; i++) { 295 int ret = adv_smbus_read_byte_data_check(client, command, true); 296 297 if (ret >= 0) { 298 if (i) 299 v4l_err(client, "read ok after %d retries\n", i); 300 return ret; 301 } 302 } 303 v4l_err(client, "read failed\n"); 304 return -EIO; 305 } 306 307 static s32 adv_smbus_write_byte_data(struct i2c_client *client, 308 u8 command, u8 value) 309 { 310 union i2c_smbus_data data; 311 int err; 312 int i; 313 314 data.byte = value; 315 for (i = 0; i < 3; i++) { 316 err = i2c_smbus_xfer(client->adapter, client->addr, 317 client->flags, 318 I2C_SMBUS_WRITE, command, 319 I2C_SMBUS_BYTE_DATA, &data); 320 if (!err) 321 break; 322 } 323 if (err < 0) 324 v4l_err(client, "error writing %02x, %02x, %02x\n", 325 client->addr, command, value); 326 return err; 327 } 328 329 static void adv_smbus_write_byte_no_check(struct i2c_client *client, 330 u8 command, u8 value) 331 { 332 union i2c_smbus_data data; 333 data.byte = value; 334 335 i2c_smbus_xfer(client->adapter, client->addr, 336 client->flags, 337 I2C_SMBUS_WRITE, command, 338 I2C_SMBUS_BYTE_DATA, &data); 339 } 340 341 /* ----------------------------------------------------------------------- */ 342 343 static inline int io_read(struct v4l2_subdev *sd, u8 reg) 344 { 345 struct i2c_client *client = v4l2_get_subdevdata(sd); 346 347 return adv_smbus_read_byte_data(client, reg); 348 } 349 350 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) 351 { 352 struct i2c_client *client = v4l2_get_subdevdata(sd); 353 354 return adv_smbus_write_byte_data(client, reg, val); 355 } 356 357 static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 358 { 359 return io_write(sd, reg, (io_read(sd, reg) & mask) | val); 360 } 361 362 static inline int io_write_clr_set(struct v4l2_subdev *sd, 363 u8 reg, u8 mask, u8 val) 364 { 365 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val); 366 } 367 368 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg) 369 { 370 struct adv7842_state *state = to_state(sd); 371 372 return adv_smbus_read_byte_data(state->i2c_avlink, reg); 373 } 374 375 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) 376 { 377 struct adv7842_state *state = to_state(sd); 378 379 return adv_smbus_write_byte_data(state->i2c_avlink, reg, val); 380 } 381 382 static inline int cec_read(struct v4l2_subdev *sd, u8 reg) 383 { 384 struct adv7842_state *state = to_state(sd); 385 386 return adv_smbus_read_byte_data(state->i2c_cec, reg); 387 } 388 389 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) 390 { 391 struct adv7842_state *state = to_state(sd); 392 393 return adv_smbus_write_byte_data(state->i2c_cec, reg, val); 394 } 395 396 static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 397 { 398 return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val); 399 } 400 401 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg) 402 { 403 struct adv7842_state *state = to_state(sd); 404 405 return adv_smbus_read_byte_data(state->i2c_infoframe, reg); 406 } 407 408 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 409 { 410 struct adv7842_state *state = to_state(sd); 411 412 return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val); 413 } 414 415 static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg) 416 { 417 struct adv7842_state *state = to_state(sd); 418 419 return adv_smbus_read_byte_data(state->i2c_sdp_io, reg); 420 } 421 422 static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val) 423 { 424 struct adv7842_state *state = to_state(sd); 425 426 return adv_smbus_write_byte_data(state->i2c_sdp_io, reg, val); 427 } 428 429 static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 430 { 431 return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val); 432 } 433 434 static inline int sdp_read(struct v4l2_subdev *sd, u8 reg) 435 { 436 struct adv7842_state *state = to_state(sd); 437 438 return adv_smbus_read_byte_data(state->i2c_sdp, reg); 439 } 440 441 static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 442 { 443 struct adv7842_state *state = to_state(sd); 444 445 return adv_smbus_write_byte_data(state->i2c_sdp, reg, val); 446 } 447 448 static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 449 { 450 return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val); 451 } 452 453 static inline int afe_read(struct v4l2_subdev *sd, u8 reg) 454 { 455 struct adv7842_state *state = to_state(sd); 456 457 return adv_smbus_read_byte_data(state->i2c_afe, reg); 458 } 459 460 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 461 { 462 struct adv7842_state *state = to_state(sd); 463 464 return adv_smbus_write_byte_data(state->i2c_afe, reg, val); 465 } 466 467 static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 468 { 469 return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val); 470 } 471 472 static inline int rep_read(struct v4l2_subdev *sd, u8 reg) 473 { 474 struct adv7842_state *state = to_state(sd); 475 476 return adv_smbus_read_byte_data(state->i2c_repeater, reg); 477 } 478 479 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) 480 { 481 struct adv7842_state *state = to_state(sd); 482 483 return adv_smbus_write_byte_data(state->i2c_repeater, reg, val); 484 } 485 486 static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 487 { 488 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val); 489 } 490 491 static inline int edid_read(struct v4l2_subdev *sd, u8 reg) 492 { 493 struct adv7842_state *state = to_state(sd); 494 495 return adv_smbus_read_byte_data(state->i2c_edid, reg); 496 } 497 498 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) 499 { 500 struct adv7842_state *state = to_state(sd); 501 502 return adv_smbus_write_byte_data(state->i2c_edid, reg, val); 503 } 504 505 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) 506 { 507 struct adv7842_state *state = to_state(sd); 508 509 return adv_smbus_read_byte_data(state->i2c_hdmi, reg); 510 } 511 512 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) 513 { 514 struct adv7842_state *state = to_state(sd); 515 516 return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val); 517 } 518 519 static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 520 { 521 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val); 522 } 523 524 static inline int cp_read(struct v4l2_subdev *sd, u8 reg) 525 { 526 struct adv7842_state *state = to_state(sd); 527 528 return adv_smbus_read_byte_data(state->i2c_cp, reg); 529 } 530 531 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 532 { 533 struct adv7842_state *state = to_state(sd); 534 535 return adv_smbus_write_byte_data(state->i2c_cp, reg, val); 536 } 537 538 static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 539 { 540 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val); 541 } 542 543 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg) 544 { 545 struct adv7842_state *state = to_state(sd); 546 547 return adv_smbus_read_byte_data(state->i2c_vdp, reg); 548 } 549 550 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 551 { 552 struct adv7842_state *state = to_state(sd); 553 554 return adv_smbus_write_byte_data(state->i2c_vdp, reg, val); 555 } 556 557 static void main_reset(struct v4l2_subdev *sd) 558 { 559 struct i2c_client *client = v4l2_get_subdevdata(sd); 560 561 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 562 563 adv_smbus_write_byte_no_check(client, 0xff, 0x80); 564 565 mdelay(5); 566 } 567 568 /* ----------------------------------------------------------------------------- 569 * Format helpers 570 */ 571 572 static const struct adv7842_format_info adv7842_formats[] = { 573 { MEDIA_BUS_FMT_RGB888_1X24, ADV7842_OP_CH_SEL_RGB, true, false, 574 ADV7842_OP_MODE_SEL_SDR_444 | ADV7842_OP_FORMAT_SEL_8BIT }, 575 { MEDIA_BUS_FMT_YUYV8_2X8, ADV7842_OP_CH_SEL_RGB, false, false, 576 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_8BIT }, 577 { MEDIA_BUS_FMT_YVYU8_2X8, ADV7842_OP_CH_SEL_RGB, false, true, 578 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_8BIT }, 579 { MEDIA_BUS_FMT_YUYV10_2X10, ADV7842_OP_CH_SEL_RGB, false, false, 580 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_10BIT }, 581 { MEDIA_BUS_FMT_YVYU10_2X10, ADV7842_OP_CH_SEL_RGB, false, true, 582 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_10BIT }, 583 { MEDIA_BUS_FMT_YUYV12_2X12, ADV7842_OP_CH_SEL_RGB, false, false, 584 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_12BIT }, 585 { MEDIA_BUS_FMT_YVYU12_2X12, ADV7842_OP_CH_SEL_RGB, false, true, 586 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_12BIT }, 587 { MEDIA_BUS_FMT_UYVY8_1X16, ADV7842_OP_CH_SEL_RBG, false, false, 588 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT }, 589 { MEDIA_BUS_FMT_VYUY8_1X16, ADV7842_OP_CH_SEL_RBG, false, true, 590 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT }, 591 { MEDIA_BUS_FMT_YUYV8_1X16, ADV7842_OP_CH_SEL_RGB, false, false, 592 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT }, 593 { MEDIA_BUS_FMT_YVYU8_1X16, ADV7842_OP_CH_SEL_RGB, false, true, 594 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT }, 595 { MEDIA_BUS_FMT_UYVY10_1X20, ADV7842_OP_CH_SEL_RBG, false, false, 596 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT }, 597 { MEDIA_BUS_FMT_VYUY10_1X20, ADV7842_OP_CH_SEL_RBG, false, true, 598 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT }, 599 { MEDIA_BUS_FMT_YUYV10_1X20, ADV7842_OP_CH_SEL_RGB, false, false, 600 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT }, 601 { MEDIA_BUS_FMT_YVYU10_1X20, ADV7842_OP_CH_SEL_RGB, false, true, 602 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT }, 603 { MEDIA_BUS_FMT_UYVY12_1X24, ADV7842_OP_CH_SEL_RBG, false, false, 604 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT }, 605 { MEDIA_BUS_FMT_VYUY12_1X24, ADV7842_OP_CH_SEL_RBG, false, true, 606 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT }, 607 { MEDIA_BUS_FMT_YUYV12_1X24, ADV7842_OP_CH_SEL_RGB, false, false, 608 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT }, 609 { MEDIA_BUS_FMT_YVYU12_1X24, ADV7842_OP_CH_SEL_RGB, false, true, 610 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT }, 611 }; 612 613 static const struct adv7842_format_info * 614 adv7842_format_info(struct adv7842_state *state, u32 code) 615 { 616 unsigned int i; 617 618 for (i = 0; i < ARRAY_SIZE(adv7842_formats); ++i) { 619 if (adv7842_formats[i].code == code) 620 return &adv7842_formats[i]; 621 } 622 623 return NULL; 624 } 625 626 /* ----------------------------------------------------------------------- */ 627 628 static inline bool is_analog_input(struct v4l2_subdev *sd) 629 { 630 struct adv7842_state *state = to_state(sd); 631 632 return ((state->mode == ADV7842_MODE_RGB) || 633 (state->mode == ADV7842_MODE_COMP)); 634 } 635 636 static inline bool is_digital_input(struct v4l2_subdev *sd) 637 { 638 struct adv7842_state *state = to_state(sd); 639 640 return state->mode == ADV7842_MODE_HDMI; 641 } 642 643 static const struct v4l2_dv_timings_cap adv7842_timings_cap_analog = { 644 .type = V4L2_DV_BT_656_1120, 645 /* keep this initialization for compatibility with GCC < 4.4.6 */ 646 .reserved = { 0 }, 647 V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 170000000, 648 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 649 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, 650 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING | 651 V4L2_DV_BT_CAP_CUSTOM) 652 }; 653 654 static const struct v4l2_dv_timings_cap adv7842_timings_cap_digital = { 655 .type = V4L2_DV_BT_656_1120, 656 /* keep this initialization for compatibility with GCC < 4.4.6 */ 657 .reserved = { 0 }, 658 V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 225000000, 659 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 660 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, 661 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING | 662 V4L2_DV_BT_CAP_CUSTOM) 663 }; 664 665 static inline const struct v4l2_dv_timings_cap * 666 adv7842_get_dv_timings_cap(struct v4l2_subdev *sd) 667 { 668 return is_digital_input(sd) ? &adv7842_timings_cap_digital : 669 &adv7842_timings_cap_analog; 670 } 671 672 /* ----------------------------------------------------------------------- */ 673 674 static u16 adv7842_read_cable_det(struct v4l2_subdev *sd) 675 { 676 u8 reg = io_read(sd, 0x6f); 677 u16 val = 0; 678 679 if (reg & 0x02) 680 val |= 1; /* port A */ 681 if (reg & 0x01) 682 val |= 2; /* port B */ 683 return val; 684 } 685 686 static void adv7842_delayed_work_enable_hotplug(struct work_struct *work) 687 { 688 struct delayed_work *dwork = to_delayed_work(work); 689 struct adv7842_state *state = container_of(dwork, 690 struct adv7842_state, delayed_work_enable_hotplug); 691 struct v4l2_subdev *sd = &state->sd; 692 int present = state->hdmi_edid.present; 693 u8 mask = 0; 694 695 v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n", 696 __func__, present); 697 698 if (present & (0x04 << ADV7842_EDID_PORT_A)) 699 mask |= 0x20; 700 if (present & (0x04 << ADV7842_EDID_PORT_B)) 701 mask |= 0x10; 702 io_write_and_or(sd, 0x20, 0xcf, mask); 703 } 704 705 static int edid_write_vga_segment(struct v4l2_subdev *sd) 706 { 707 struct i2c_client *client = v4l2_get_subdevdata(sd); 708 struct adv7842_state *state = to_state(sd); 709 const u8 *edid = state->vga_edid.edid; 710 u32 blocks = state->vga_edid.blocks; 711 int err = 0; 712 int i; 713 714 v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n", __func__); 715 716 if (!state->vga_edid.present) 717 return 0; 718 719 /* HPA disable on port A and B */ 720 io_write_and_or(sd, 0x20, 0xcf, 0x00); 721 722 /* Disable I2C access to internal EDID ram from VGA DDC port */ 723 rep_write_and_or(sd, 0x7f, 0x7f, 0x00); 724 725 /* edid segment pointer '1' for VGA port */ 726 rep_write_and_or(sd, 0x77, 0xef, 0x10); 727 728 for (i = 0; !err && i < blocks * 128; i += I2C_SMBUS_BLOCK_MAX) 729 err = i2c_smbus_write_i2c_block_data(state->i2c_edid, i, 730 I2C_SMBUS_BLOCK_MAX, 731 edid + i); 732 if (err) 733 return err; 734 735 /* Calculates the checksums and enables I2C access 736 * to internal EDID ram from VGA DDC port. 737 */ 738 rep_write_and_or(sd, 0x7f, 0x7f, 0x80); 739 740 for (i = 0; i < 1000; i++) { 741 if (rep_read(sd, 0x79) & 0x20) 742 break; 743 mdelay(1); 744 } 745 if (i == 1000) { 746 v4l_err(client, "error enabling edid on VGA port\n"); 747 return -EIO; 748 } 749 750 /* enable hotplug after 200 ms */ 751 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 5); 752 753 return 0; 754 } 755 756 static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port) 757 { 758 struct i2c_client *client = v4l2_get_subdevdata(sd); 759 struct adv7842_state *state = to_state(sd); 760 const u8 *edid = state->hdmi_edid.edid; 761 u32 blocks = state->hdmi_edid.blocks; 762 unsigned int spa_loc; 763 u16 pa, parent_pa; 764 int err = 0; 765 int i; 766 767 v4l2_dbg(2, debug, sd, "%s: write EDID on port %c\n", 768 __func__, (port == ADV7842_EDID_PORT_A) ? 'A' : 'B'); 769 770 /* HPA disable on port A and B */ 771 io_write_and_or(sd, 0x20, 0xcf, 0x00); 772 773 /* Disable I2C access to internal EDID ram from HDMI DDC ports */ 774 rep_write_and_or(sd, 0x77, 0xf3, 0x00); 775 776 if (!state->hdmi_edid.present) { 777 cec_phys_addr_invalidate(state->cec_adap); 778 return 0; 779 } 780 781 pa = v4l2_get_edid_phys_addr(edid, blocks * 128, &spa_loc); 782 err = v4l2_phys_addr_validate(pa, &parent_pa, NULL); 783 if (err) 784 return err; 785 786 if (!spa_loc) { 787 /* 788 * There is no SPA, so just set spa_loc to 128 and pa to whatever 789 * data is there. 790 */ 791 spa_loc = 128; 792 pa = (edid[spa_loc] << 8) | edid[spa_loc + 1]; 793 } 794 795 796 for (i = 0; !err && i < blocks * 128; i += I2C_SMBUS_BLOCK_MAX) { 797 /* set edid segment pointer for HDMI ports */ 798 if (i % 256 == 0) 799 rep_write_and_or(sd, 0x77, 0xef, i >= 256 ? 0x10 : 0x00); 800 err = i2c_smbus_write_i2c_block_data(state->i2c_edid, i, 801 I2C_SMBUS_BLOCK_MAX, edid + i); 802 } 803 if (err) 804 return err; 805 806 if (port == ADV7842_EDID_PORT_A) { 807 rep_write(sd, 0x72, pa >> 8); 808 rep_write(sd, 0x73, pa & 0xff); 809 } else { 810 rep_write(sd, 0x74, pa >> 8); 811 rep_write(sd, 0x75, pa & 0xff); 812 } 813 rep_write(sd, 0x76, spa_loc & 0xff); 814 rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40); 815 816 /* Calculates the checksums and enables I2C access to internal 817 * EDID ram from HDMI DDC ports 818 */ 819 rep_write_and_or(sd, 0x77, 0xf3, state->hdmi_edid.present); 820 821 for (i = 0; i < 1000; i++) { 822 if (rep_read(sd, 0x7d) & state->hdmi_edid.present) 823 break; 824 mdelay(1); 825 } 826 if (i == 1000) { 827 v4l_err(client, "error enabling edid on port %c\n", 828 (port == ADV7842_EDID_PORT_A) ? 'A' : 'B'); 829 return -EIO; 830 } 831 cec_s_phys_addr(state->cec_adap, parent_pa, false); 832 833 /* enable hotplug after 200 ms */ 834 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 5); 835 836 return 0; 837 } 838 839 /* ----------------------------------------------------------------------- */ 840 841 #ifdef CONFIG_VIDEO_ADV_DEBUG 842 static void adv7842_inv_register(struct v4l2_subdev *sd) 843 { 844 v4l2_info(sd, "0x000-0x0ff: IO Map\n"); 845 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n"); 846 v4l2_info(sd, "0x200-0x2ff: CEC Map\n"); 847 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n"); 848 v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n"); 849 v4l2_info(sd, "0x500-0x5ff: SDP Map\n"); 850 v4l2_info(sd, "0x600-0x6ff: AFE Map\n"); 851 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n"); 852 v4l2_info(sd, "0x800-0x8ff: EDID Map\n"); 853 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n"); 854 v4l2_info(sd, "0xa00-0xaff: CP Map\n"); 855 v4l2_info(sd, "0xb00-0xbff: VDP Map\n"); 856 } 857 858 static int adv7842_g_register(struct v4l2_subdev *sd, 859 struct v4l2_dbg_register *reg) 860 { 861 reg->size = 1; 862 switch (reg->reg >> 8) { 863 case 0: 864 reg->val = io_read(sd, reg->reg & 0xff); 865 break; 866 case 1: 867 reg->val = avlink_read(sd, reg->reg & 0xff); 868 break; 869 case 2: 870 reg->val = cec_read(sd, reg->reg & 0xff); 871 break; 872 case 3: 873 reg->val = infoframe_read(sd, reg->reg & 0xff); 874 break; 875 case 4: 876 reg->val = sdp_io_read(sd, reg->reg & 0xff); 877 break; 878 case 5: 879 reg->val = sdp_read(sd, reg->reg & 0xff); 880 break; 881 case 6: 882 reg->val = afe_read(sd, reg->reg & 0xff); 883 break; 884 case 7: 885 reg->val = rep_read(sd, reg->reg & 0xff); 886 break; 887 case 8: 888 reg->val = edid_read(sd, reg->reg & 0xff); 889 break; 890 case 9: 891 reg->val = hdmi_read(sd, reg->reg & 0xff); 892 break; 893 case 0xa: 894 reg->val = cp_read(sd, reg->reg & 0xff); 895 break; 896 case 0xb: 897 reg->val = vdp_read(sd, reg->reg & 0xff); 898 break; 899 default: 900 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 901 adv7842_inv_register(sd); 902 break; 903 } 904 return 0; 905 } 906 907 static int adv7842_s_register(struct v4l2_subdev *sd, 908 const struct v4l2_dbg_register *reg) 909 { 910 u8 val = reg->val & 0xff; 911 912 switch (reg->reg >> 8) { 913 case 0: 914 io_write(sd, reg->reg & 0xff, val); 915 break; 916 case 1: 917 avlink_write(sd, reg->reg & 0xff, val); 918 break; 919 case 2: 920 cec_write(sd, reg->reg & 0xff, val); 921 break; 922 case 3: 923 infoframe_write(sd, reg->reg & 0xff, val); 924 break; 925 case 4: 926 sdp_io_write(sd, reg->reg & 0xff, val); 927 break; 928 case 5: 929 sdp_write(sd, reg->reg & 0xff, val); 930 break; 931 case 6: 932 afe_write(sd, reg->reg & 0xff, val); 933 break; 934 case 7: 935 rep_write(sd, reg->reg & 0xff, val); 936 break; 937 case 8: 938 edid_write(sd, reg->reg & 0xff, val); 939 break; 940 case 9: 941 hdmi_write(sd, reg->reg & 0xff, val); 942 break; 943 case 0xa: 944 cp_write(sd, reg->reg & 0xff, val); 945 break; 946 case 0xb: 947 vdp_write(sd, reg->reg & 0xff, val); 948 break; 949 default: 950 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 951 adv7842_inv_register(sd); 952 break; 953 } 954 return 0; 955 } 956 #endif 957 958 static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd) 959 { 960 struct adv7842_state *state = to_state(sd); 961 u16 cable_det = adv7842_read_cable_det(sd); 962 963 v4l2_dbg(1, debug, sd, "%s: 0x%x\n", __func__, cable_det); 964 965 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, cable_det); 966 } 967 968 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd, 969 u8 prim_mode, 970 const struct adv7842_video_standards *predef_vid_timings, 971 const struct v4l2_dv_timings *timings) 972 { 973 int i; 974 975 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) { 976 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings, 977 is_digital_input(sd) ? 250000 : 1000000, false)) 978 continue; 979 /* video std */ 980 io_write(sd, 0x00, predef_vid_timings[i].vid_std); 981 /* v_freq and prim mode */ 982 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode); 983 return 0; 984 } 985 986 return -1; 987 } 988 989 static int configure_predefined_video_timings(struct v4l2_subdev *sd, 990 struct v4l2_dv_timings *timings) 991 { 992 struct adv7842_state *state = to_state(sd); 993 int err; 994 995 v4l2_dbg(1, debug, sd, "%s\n", __func__); 996 997 /* reset to default values */ 998 io_write(sd, 0x16, 0x43); 999 io_write(sd, 0x17, 0x5a); 1000 /* disable embedded syncs for auto graphics mode */ 1001 cp_write_and_or(sd, 0x81, 0xef, 0x00); 1002 cp_write(sd, 0x26, 0x00); 1003 cp_write(sd, 0x27, 0x00); 1004 cp_write(sd, 0x28, 0x00); 1005 cp_write(sd, 0x29, 0x00); 1006 cp_write(sd, 0x8f, 0x40); 1007 cp_write(sd, 0x90, 0x00); 1008 cp_write(sd, 0xa5, 0x00); 1009 cp_write(sd, 0xa6, 0x00); 1010 cp_write(sd, 0xa7, 0x00); 1011 cp_write(sd, 0xab, 0x00); 1012 cp_write(sd, 0xac, 0x00); 1013 1014 switch (state->mode) { 1015 case ADV7842_MODE_COMP: 1016 case ADV7842_MODE_RGB: 1017 err = find_and_set_predefined_video_timings(sd, 1018 0x01, adv7842_prim_mode_comp, timings); 1019 if (err) 1020 err = find_and_set_predefined_video_timings(sd, 1021 0x02, adv7842_prim_mode_gr, timings); 1022 break; 1023 case ADV7842_MODE_HDMI: 1024 err = find_and_set_predefined_video_timings(sd, 1025 0x05, adv7842_prim_mode_hdmi_comp, timings); 1026 if (err) 1027 err = find_and_set_predefined_video_timings(sd, 1028 0x06, adv7842_prim_mode_hdmi_gr, timings); 1029 break; 1030 default: 1031 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", 1032 __func__, state->mode); 1033 err = -1; 1034 break; 1035 } 1036 1037 1038 return err; 1039 } 1040 1041 static void configure_custom_video_timings(struct v4l2_subdev *sd, 1042 const struct v4l2_bt_timings *bt) 1043 { 1044 struct adv7842_state *state = to_state(sd); 1045 struct i2c_client *client = v4l2_get_subdevdata(sd); 1046 u32 width = htotal(bt); 1047 u32 height = vtotal(bt); 1048 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4; 1049 u16 cp_start_eav = width - bt->hfrontporch; 1050 u16 cp_start_vbi = height - bt->vfrontporch + 1; 1051 u16 cp_end_vbi = bt->vsync + bt->vbackporch + 1; 1052 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ? 1053 ((width * (ADV7842_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0; 1054 const u8 pll[2] = { 1055 0xc0 | ((width >> 8) & 0x1f), 1056 width & 0xff 1057 }; 1058 1059 v4l2_dbg(2, debug, sd, "%s\n", __func__); 1060 1061 switch (state->mode) { 1062 case ADV7842_MODE_COMP: 1063 case ADV7842_MODE_RGB: 1064 /* auto graphics */ 1065 io_write(sd, 0x00, 0x07); /* video std */ 1066 io_write(sd, 0x01, 0x02); /* prim mode */ 1067 /* enable embedded syncs for auto graphics mode */ 1068 cp_write_and_or(sd, 0x81, 0xef, 0x10); 1069 1070 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */ 1071 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */ 1072 /* IO-map reg. 0x16 and 0x17 should be written in sequence */ 1073 if (i2c_smbus_write_i2c_block_data(client, 0x16, 2, pll)) { 1074 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n"); 1075 break; 1076 } 1077 1078 /* active video - horizontal timing */ 1079 cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf); 1080 cp_write(sd, 0x27, (cp_start_sav & 0xff)); 1081 cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf); 1082 cp_write(sd, 0x29, (cp_start_eav & 0xff)); 1083 1084 /* active video - vertical timing */ 1085 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff); 1086 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) | 1087 ((cp_end_vbi >> 8) & 0xf)); 1088 cp_write(sd, 0xa7, cp_end_vbi & 0xff); 1089 break; 1090 case ADV7842_MODE_HDMI: 1091 /* set default prim_mode/vid_std for HDMI 1092 according to [REF_03, c. 4.2] */ 1093 io_write(sd, 0x00, 0x02); /* video std */ 1094 io_write(sd, 0x01, 0x06); /* prim mode */ 1095 break; 1096 default: 1097 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", 1098 __func__, state->mode); 1099 break; 1100 } 1101 1102 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7); 1103 cp_write(sd, 0x90, ch1_fr_ll & 0xff); 1104 cp_write(sd, 0xab, (height >> 4) & 0xff); 1105 cp_write(sd, 0xac, (height & 0x0f) << 4); 1106 } 1107 1108 static void adv7842_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c) 1109 { 1110 struct adv7842_state *state = to_state(sd); 1111 u8 offset_buf[4]; 1112 1113 if (auto_offset) { 1114 offset_a = 0x3ff; 1115 offset_b = 0x3ff; 1116 offset_c = 0x3ff; 1117 } 1118 1119 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n", 1120 __func__, auto_offset ? "Auto" : "Manual", 1121 offset_a, offset_b, offset_c); 1122 1123 offset_buf[0]= (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4); 1124 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6); 1125 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8); 1126 offset_buf[3] = offset_c & 0x0ff; 1127 1128 /* Registers must be written in this order with no i2c access in between */ 1129 if (i2c_smbus_write_i2c_block_data(state->i2c_cp, 0x77, 4, offset_buf)) 1130 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__); 1131 } 1132 1133 static void adv7842_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c) 1134 { 1135 struct adv7842_state *state = to_state(sd); 1136 u8 gain_buf[4]; 1137 u8 gain_man = 1; 1138 u8 agc_mode_man = 1; 1139 1140 if (auto_gain) { 1141 gain_man = 0; 1142 agc_mode_man = 0; 1143 gain_a = 0x100; 1144 gain_b = 0x100; 1145 gain_c = 0x100; 1146 } 1147 1148 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n", 1149 __func__, auto_gain ? "Auto" : "Manual", 1150 gain_a, gain_b, gain_c); 1151 1152 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4)); 1153 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6)); 1154 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8)); 1155 gain_buf[3] = ((gain_c & 0x0ff)); 1156 1157 /* Registers must be written in this order with no i2c access in between */ 1158 if (i2c_smbus_write_i2c_block_data(state->i2c_cp, 0x73, 4, gain_buf)) 1159 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__); 1160 } 1161 1162 static void set_rgb_quantization_range(struct v4l2_subdev *sd) 1163 { 1164 struct adv7842_state *state = to_state(sd); 1165 bool rgb_output = io_read(sd, 0x02) & 0x02; 1166 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; 1167 u8 y = HDMI_COLORSPACE_RGB; 1168 1169 if (hdmi_signal && (io_read(sd, 0x60) & 1)) 1170 y = infoframe_read(sd, 0x01) >> 5; 1171 1172 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n", 1173 __func__, state->rgb_quantization_range, 1174 rgb_output, hdmi_signal); 1175 1176 adv7842_set_gain(sd, true, 0x0, 0x0, 0x0); 1177 adv7842_set_offset(sd, true, 0x0, 0x0, 0x0); 1178 io_write_clr_set(sd, 0x02, 0x04, rgb_output ? 0 : 4); 1179 1180 switch (state->rgb_quantization_range) { 1181 case V4L2_DV_RGB_RANGE_AUTO: 1182 if (state->mode == ADV7842_MODE_RGB) { 1183 /* Receiving analog RGB signal 1184 * Set RGB full range (0-255) */ 1185 io_write_and_or(sd, 0x02, 0x0f, 0x10); 1186 break; 1187 } 1188 1189 if (state->mode == ADV7842_MODE_COMP) { 1190 /* Receiving analog YPbPr signal 1191 * Set automode */ 1192 io_write_and_or(sd, 0x02, 0x0f, 0xf0); 1193 break; 1194 } 1195 1196 if (hdmi_signal) { 1197 /* Receiving HDMI signal 1198 * Set automode */ 1199 io_write_and_or(sd, 0x02, 0x0f, 0xf0); 1200 break; 1201 } 1202 1203 /* Receiving DVI-D signal 1204 * ADV7842 selects RGB limited range regardless of 1205 * input format (CE/IT) in automatic mode */ 1206 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) { 1207 /* RGB limited range (16-235) */ 1208 io_write_and_or(sd, 0x02, 0x0f, 0x00); 1209 } else { 1210 /* RGB full range (0-255) */ 1211 io_write_and_or(sd, 0x02, 0x0f, 0x10); 1212 1213 if (is_digital_input(sd) && rgb_output) { 1214 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40); 1215 } else { 1216 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 1217 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70); 1218 } 1219 } 1220 break; 1221 case V4L2_DV_RGB_RANGE_LIMITED: 1222 if (state->mode == ADV7842_MODE_COMP) { 1223 /* YCrCb limited range (16-235) */ 1224 io_write_and_or(sd, 0x02, 0x0f, 0x20); 1225 break; 1226 } 1227 1228 if (y != HDMI_COLORSPACE_RGB) 1229 break; 1230 1231 /* RGB limited range (16-235) */ 1232 io_write_and_or(sd, 0x02, 0x0f, 0x00); 1233 1234 break; 1235 case V4L2_DV_RGB_RANGE_FULL: 1236 if (state->mode == ADV7842_MODE_COMP) { 1237 /* YCrCb full range (0-255) */ 1238 io_write_and_or(sd, 0x02, 0x0f, 0x60); 1239 break; 1240 } 1241 1242 if (y != HDMI_COLORSPACE_RGB) 1243 break; 1244 1245 /* RGB full range (0-255) */ 1246 io_write_and_or(sd, 0x02, 0x0f, 0x10); 1247 1248 if (is_analog_input(sd) || hdmi_signal) 1249 break; 1250 1251 /* Adjust gain/offset for DVI-D signals only */ 1252 if (rgb_output) { 1253 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40); 1254 } else { 1255 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 1256 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70); 1257 } 1258 break; 1259 } 1260 } 1261 1262 static int adv7842_s_ctrl(struct v4l2_ctrl *ctrl) 1263 { 1264 struct v4l2_subdev *sd = to_sd(ctrl); 1265 struct adv7842_state *state = to_state(sd); 1266 1267 /* TODO SDP ctrls 1268 contrast/brightness/hue/free run is acting a bit strange, 1269 not sure if sdp csc is correct. 1270 */ 1271 switch (ctrl->id) { 1272 /* standard ctrls */ 1273 case V4L2_CID_BRIGHTNESS: 1274 cp_write(sd, 0x3c, ctrl->val); 1275 sdp_write(sd, 0x14, ctrl->val); 1276 /* ignore lsb sdp 0x17[3:2] */ 1277 return 0; 1278 case V4L2_CID_CONTRAST: 1279 cp_write(sd, 0x3a, ctrl->val); 1280 sdp_write(sd, 0x13, ctrl->val); 1281 /* ignore lsb sdp 0x17[1:0] */ 1282 return 0; 1283 case V4L2_CID_SATURATION: 1284 cp_write(sd, 0x3b, ctrl->val); 1285 sdp_write(sd, 0x15, ctrl->val); 1286 /* ignore lsb sdp 0x17[5:4] */ 1287 return 0; 1288 case V4L2_CID_HUE: 1289 cp_write(sd, 0x3d, ctrl->val); 1290 sdp_write(sd, 0x16, ctrl->val); 1291 /* ignore lsb sdp 0x17[7:6] */ 1292 return 0; 1293 /* custom ctrls */ 1294 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE: 1295 afe_write(sd, 0xc8, ctrl->val); 1296 return 0; 1297 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL: 1298 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2)); 1299 sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2)); 1300 return 0; 1301 case V4L2_CID_ADV_RX_FREE_RUN_COLOR: { 1302 u8 R = (ctrl->val & 0xff0000) >> 16; 1303 u8 G = (ctrl->val & 0x00ff00) >> 8; 1304 u8 B = (ctrl->val & 0x0000ff); 1305 /* RGB -> YUV, numerical approximation */ 1306 int Y = 66 * R + 129 * G + 25 * B; 1307 int U = -38 * R - 74 * G + 112 * B; 1308 int V = 112 * R - 94 * G - 18 * B; 1309 1310 /* Scale down to 8 bits with rounding */ 1311 Y = (Y + 128) >> 8; 1312 U = (U + 128) >> 8; 1313 V = (V + 128) >> 8; 1314 /* make U,V positive */ 1315 Y += 16; 1316 U += 128; 1317 V += 128; 1318 1319 v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n", R, G, B); 1320 v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n", Y, U, V); 1321 1322 /* CP */ 1323 cp_write(sd, 0xc1, R); 1324 cp_write(sd, 0xc0, G); 1325 cp_write(sd, 0xc2, B); 1326 /* SDP */ 1327 sdp_write(sd, 0xde, Y); 1328 sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f)); 1329 return 0; 1330 } 1331 case V4L2_CID_DV_RX_RGB_RANGE: 1332 state->rgb_quantization_range = ctrl->val; 1333 set_rgb_quantization_range(sd); 1334 return 0; 1335 } 1336 return -EINVAL; 1337 } 1338 1339 static int adv7842_g_volatile_ctrl(struct v4l2_ctrl *ctrl) 1340 { 1341 struct v4l2_subdev *sd = to_sd(ctrl); 1342 1343 if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) { 1344 ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC; 1345 if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80)) 1346 ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3; 1347 return 0; 1348 } 1349 return -EINVAL; 1350 } 1351 1352 static inline bool no_power(struct v4l2_subdev *sd) 1353 { 1354 return io_read(sd, 0x0c) & 0x24; 1355 } 1356 1357 static inline bool no_cp_signal(struct v4l2_subdev *sd) 1358 { 1359 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80); 1360 } 1361 1362 static inline bool is_hdmi(struct v4l2_subdev *sd) 1363 { 1364 return hdmi_read(sd, 0x05) & 0x80; 1365 } 1366 1367 static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status) 1368 { 1369 struct adv7842_state *state = to_state(sd); 1370 1371 *status = 0; 1372 1373 if (io_read(sd, 0x0c) & 0x24) 1374 *status |= V4L2_IN_ST_NO_POWER; 1375 1376 if (state->mode == ADV7842_MODE_SDP) { 1377 /* status from SDP block */ 1378 if (!(sdp_read(sd, 0x5A) & 0x01)) 1379 *status |= V4L2_IN_ST_NO_SIGNAL; 1380 1381 v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n", 1382 __func__, *status); 1383 return 0; 1384 } 1385 /* status from CP block */ 1386 if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 || 1387 !(cp_read(sd, 0xb1) & 0x80)) 1388 /* TODO channel 2 */ 1389 *status |= V4L2_IN_ST_NO_SIGNAL; 1390 1391 if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03)) 1392 *status |= V4L2_IN_ST_NO_SIGNAL; 1393 1394 v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n", 1395 __func__, *status); 1396 1397 return 0; 1398 } 1399 1400 struct stdi_readback { 1401 u16 bl, lcf, lcvs; 1402 u8 hs_pol, vs_pol; 1403 bool interlaced; 1404 }; 1405 1406 static int stdi2dv_timings(struct v4l2_subdev *sd, 1407 struct stdi_readback *stdi, 1408 struct v4l2_dv_timings *timings) 1409 { 1410 struct adv7842_state *state = to_state(sd); 1411 u32 hfreq = (ADV7842_fsc * 8) / stdi->bl; 1412 u32 pix_clk; 1413 int i; 1414 1415 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) { 1416 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt; 1417 1418 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i], 1419 adv7842_get_dv_timings_cap(sd), 1420 adv7842_check_dv_timings, NULL)) 1421 continue; 1422 if (vtotal(bt) != stdi->lcf + 1) 1423 continue; 1424 if (bt->vsync != stdi->lcvs) 1425 continue; 1426 1427 pix_clk = hfreq * htotal(bt); 1428 1429 if ((pix_clk < bt->pixelclock + 1000000) && 1430 (pix_clk > bt->pixelclock - 1000000)) { 1431 *timings = v4l2_dv_timings_presets[i]; 1432 return 0; 1433 } 1434 } 1435 1436 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0, 1437 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 1438 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 1439 false, timings)) 1440 return 0; 1441 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs, 1442 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 1443 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 1444 false, state->aspect_ratio, timings)) 1445 return 0; 1446 1447 v4l2_dbg(2, debug, sd, 1448 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n", 1449 __func__, stdi->lcvs, stdi->lcf, stdi->bl, 1450 stdi->hs_pol, stdi->vs_pol); 1451 return -1; 1452 } 1453 1454 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi) 1455 { 1456 u32 status; 1457 1458 adv7842_g_input_status(sd, &status); 1459 if (status & V4L2_IN_ST_NO_SIGNAL) { 1460 v4l2_dbg(2, debug, sd, "%s: no signal\n", __func__); 1461 return -ENOLINK; 1462 } 1463 1464 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2); 1465 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4); 1466 stdi->lcvs = cp_read(sd, 0xb3) >> 3; 1467 1468 if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) { 1469 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ? 1470 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x'); 1471 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ? 1472 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x'); 1473 } else { 1474 stdi->hs_pol = 'x'; 1475 stdi->vs_pol = 'x'; 1476 } 1477 stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false; 1478 1479 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) { 1480 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__); 1481 return -ENOLINK; 1482 } 1483 1484 v4l2_dbg(2, debug, sd, 1485 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n", 1486 __func__, stdi->lcf, stdi->bl, stdi->lcvs, 1487 stdi->hs_pol, stdi->vs_pol, 1488 stdi->interlaced ? "interlaced" : "progressive"); 1489 1490 return 0; 1491 } 1492 1493 static int adv7842_enum_dv_timings(struct v4l2_subdev *sd, 1494 struct v4l2_enum_dv_timings *timings) 1495 { 1496 if (timings->pad != 0) 1497 return -EINVAL; 1498 1499 return v4l2_enum_dv_timings_cap(timings, 1500 adv7842_get_dv_timings_cap(sd), adv7842_check_dv_timings, NULL); 1501 } 1502 1503 static int adv7842_dv_timings_cap(struct v4l2_subdev *sd, 1504 struct v4l2_dv_timings_cap *cap) 1505 { 1506 if (cap->pad != 0) 1507 return -EINVAL; 1508 1509 *cap = *adv7842_get_dv_timings_cap(sd); 1510 return 0; 1511 } 1512 1513 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings 1514 if the format is listed in adv7842_timings[] */ 1515 static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd, 1516 struct v4l2_dv_timings *timings) 1517 { 1518 v4l2_find_dv_timings_cap(timings, adv7842_get_dv_timings_cap(sd), 1519 is_digital_input(sd) ? 250000 : 1000000, 1520 adv7842_check_dv_timings, NULL); 1521 timings->bt.flags |= V4L2_DV_FL_CAN_DETECT_REDUCED_FPS; 1522 } 1523 1524 static int adv7842_query_dv_timings(struct v4l2_subdev *sd, unsigned int pad, 1525 struct v4l2_dv_timings *timings) 1526 { 1527 struct adv7842_state *state = to_state(sd); 1528 struct v4l2_bt_timings *bt = &timings->bt; 1529 struct stdi_readback stdi = { 0 }; 1530 1531 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 1532 1533 if (pad != 0) 1534 return -EINVAL; 1535 1536 memset(timings, 0, sizeof(struct v4l2_dv_timings)); 1537 1538 /* SDP block */ 1539 if (state->mode == ADV7842_MODE_SDP) 1540 return -ENODATA; 1541 1542 /* read STDI */ 1543 if (read_stdi(sd, &stdi)) { 1544 state->restart_stdi_once = true; 1545 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); 1546 return -ENOLINK; 1547 } 1548 bt->interlaced = stdi.interlaced ? 1549 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; 1550 bt->standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 1551 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT; 1552 1553 if (is_digital_input(sd)) { 1554 u32 freq; 1555 1556 timings->type = V4L2_DV_BT_656_1120; 1557 1558 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08); 1559 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a); 1560 freq = ((hdmi_read(sd, 0x51) << 1) + (hdmi_read(sd, 0x52) >> 7)) * 1000000; 1561 freq += ((hdmi_read(sd, 0x52) & 0x7f) * 7813); 1562 if (is_hdmi(sd)) { 1563 /* adjust for deep color mode */ 1564 freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 6) * 2 + 8); 1565 } 1566 bt->pixelclock = freq; 1567 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 + 1568 hdmi_read(sd, 0x21); 1569 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 + 1570 hdmi_read(sd, 0x23); 1571 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 + 1572 hdmi_read(sd, 0x25); 1573 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 + 1574 hdmi_read(sd, 0x2b)) / 2; 1575 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 + 1576 hdmi_read(sd, 0x2f)) / 2; 1577 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 + 1578 hdmi_read(sd, 0x33)) / 2; 1579 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | 1580 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0); 1581 if (bt->interlaced == V4L2_DV_INTERLACED) { 1582 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 + 1583 hdmi_read(sd, 0x0c); 1584 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 + 1585 hdmi_read(sd, 0x2d)) / 2; 1586 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 + 1587 hdmi_read(sd, 0x31)) / 2; 1588 bt->il_vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 + 1589 hdmi_read(sd, 0x35)) / 2; 1590 } else { 1591 bt->il_vfrontporch = 0; 1592 bt->il_vsync = 0; 1593 bt->il_vbackporch = 0; 1594 } 1595 adv7842_fill_optional_dv_timings_fields(sd, timings); 1596 if ((timings->bt.flags & V4L2_DV_FL_CAN_REDUCE_FPS) && 1597 freq < bt->pixelclock) { 1598 u32 reduced_freq = ((u32)bt->pixelclock / 1001) * 1000; 1599 u32 delta_freq = abs(freq - reduced_freq); 1600 1601 if (delta_freq < ((u32)bt->pixelclock - reduced_freq) / 2) 1602 timings->bt.flags |= V4L2_DV_FL_REDUCED_FPS; 1603 } 1604 } else { 1605 /* find format 1606 * Since LCVS values are inaccurate [REF_03, p. 339-340], 1607 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails. 1608 */ 1609 if (!stdi2dv_timings(sd, &stdi, timings)) 1610 goto found; 1611 stdi.lcvs += 1; 1612 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs); 1613 if (!stdi2dv_timings(sd, &stdi, timings)) 1614 goto found; 1615 stdi.lcvs -= 2; 1616 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs); 1617 if (stdi2dv_timings(sd, &stdi, timings)) { 1618 /* 1619 * The STDI block may measure wrong values, especially 1620 * for lcvs and lcf. If the driver can not find any 1621 * valid timing, the STDI block is restarted to measure 1622 * the video timings again. The function will return an 1623 * error, but the restart of STDI will generate a new 1624 * STDI interrupt and the format detection process will 1625 * restart. 1626 */ 1627 if (state->restart_stdi_once) { 1628 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__); 1629 /* TODO restart STDI for Sync Channel 2 */ 1630 /* enter one-shot mode */ 1631 cp_write_and_or(sd, 0x86, 0xf9, 0x00); 1632 /* trigger STDI restart */ 1633 cp_write_and_or(sd, 0x86, 0xf9, 0x04); 1634 /* reset to continuous mode */ 1635 cp_write_and_or(sd, 0x86, 0xf9, 0x02); 1636 state->restart_stdi_once = false; 1637 return -ENOLINK; 1638 } 1639 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__); 1640 return -ERANGE; 1641 } 1642 state->restart_stdi_once = true; 1643 } 1644 found: 1645 1646 if (debug > 1) 1647 v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings:", 1648 timings, true); 1649 return 0; 1650 } 1651 1652 static int adv7842_s_dv_timings(struct v4l2_subdev *sd, unsigned int pad, 1653 struct v4l2_dv_timings *timings) 1654 { 1655 struct adv7842_state *state = to_state(sd); 1656 struct v4l2_bt_timings *bt; 1657 int err; 1658 1659 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 1660 1661 if (pad != 0) 1662 return -EINVAL; 1663 1664 if (state->mode == ADV7842_MODE_SDP) 1665 return -ENODATA; 1666 1667 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) { 1668 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__); 1669 return 0; 1670 } 1671 1672 bt = &timings->bt; 1673 1674 if (!v4l2_valid_dv_timings(timings, adv7842_get_dv_timings_cap(sd), 1675 adv7842_check_dv_timings, NULL)) 1676 return -ERANGE; 1677 1678 adv7842_fill_optional_dv_timings_fields(sd, timings); 1679 1680 state->timings = *timings; 1681 1682 cp_write(sd, 0x91, bt->interlaced ? 0x40 : 0x00); 1683 1684 /* Use prim_mode and vid_std when available */ 1685 err = configure_predefined_video_timings(sd, timings); 1686 if (err) { 1687 /* custom settings when the video format 1688 does not have prim_mode/vid_std */ 1689 configure_custom_video_timings(sd, bt); 1690 } 1691 1692 set_rgb_quantization_range(sd); 1693 1694 1695 if (debug > 1) 1696 v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ", 1697 timings, true); 1698 return 0; 1699 } 1700 1701 static int adv7842_g_dv_timings(struct v4l2_subdev *sd, unsigned int pad, 1702 struct v4l2_dv_timings *timings) 1703 { 1704 struct adv7842_state *state = to_state(sd); 1705 1706 if (pad != 0) 1707 return -EINVAL; 1708 1709 if (state->mode == ADV7842_MODE_SDP) 1710 return -ENODATA; 1711 *timings = state->timings; 1712 return 0; 1713 } 1714 1715 static void enable_input(struct v4l2_subdev *sd) 1716 { 1717 struct adv7842_state *state = to_state(sd); 1718 1719 set_rgb_quantization_range(sd); 1720 switch (state->mode) { 1721 case ADV7842_MODE_SDP: 1722 case ADV7842_MODE_COMP: 1723 case ADV7842_MODE_RGB: 1724 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */ 1725 break; 1726 case ADV7842_MODE_HDMI: 1727 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */ 1728 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */ 1729 hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */ 1730 break; 1731 default: 1732 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", 1733 __func__, state->mode); 1734 break; 1735 } 1736 } 1737 1738 static void disable_input(struct v4l2_subdev *sd) 1739 { 1740 hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio [REF_01, c. 2.2.2] */ 1741 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 8.29] */ 1742 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */ 1743 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */ 1744 } 1745 1746 static void sdp_csc_coeff(struct v4l2_subdev *sd, 1747 const struct adv7842_sdp_csc_coeff *c) 1748 { 1749 /* csc auto/manual */ 1750 sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40); 1751 1752 if (!c->manual) 1753 return; 1754 1755 /* csc scaling */ 1756 sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00); 1757 1758 /* A coeff */ 1759 sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8); 1760 sdp_io_write(sd, 0xe1, c->A1); 1761 sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8); 1762 sdp_io_write(sd, 0xe3, c->A2); 1763 sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8); 1764 sdp_io_write(sd, 0xe5, c->A3); 1765 1766 /* A scale */ 1767 sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8); 1768 sdp_io_write(sd, 0xe7, c->A4); 1769 1770 /* B coeff */ 1771 sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8); 1772 sdp_io_write(sd, 0xe9, c->B1); 1773 sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8); 1774 sdp_io_write(sd, 0xeb, c->B2); 1775 sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8); 1776 sdp_io_write(sd, 0xed, c->B3); 1777 1778 /* B scale */ 1779 sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8); 1780 sdp_io_write(sd, 0xef, c->B4); 1781 1782 /* C coeff */ 1783 sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8); 1784 sdp_io_write(sd, 0xf1, c->C1); 1785 sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8); 1786 sdp_io_write(sd, 0xf3, c->C2); 1787 sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8); 1788 sdp_io_write(sd, 0xf5, c->C3); 1789 1790 /* C scale */ 1791 sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8); 1792 sdp_io_write(sd, 0xf7, c->C4); 1793 } 1794 1795 static void select_input(struct v4l2_subdev *sd, 1796 enum adv7842_vid_std_select vid_std_select) 1797 { 1798 struct adv7842_state *state = to_state(sd); 1799 1800 switch (state->mode) { 1801 case ADV7842_MODE_SDP: 1802 io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */ 1803 io_write(sd, 0x01, 0); /* prim mode */ 1804 /* enable embedded syncs for auto graphics mode */ 1805 cp_write_and_or(sd, 0x81, 0xef, 0x10); 1806 1807 afe_write(sd, 0x00, 0x00); /* power up ADC */ 1808 afe_write(sd, 0xc8, 0x00); /* phase control */ 1809 1810 io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */ 1811 /* script says register 0xde, which don't exist in manual */ 1812 1813 /* Manual analog input muxing mode, CVBS (6.4)*/ 1814 afe_write_and_or(sd, 0x02, 0x7f, 0x80); 1815 if (vid_std_select == ADV7842_SDP_VID_STD_CVBS_SD_4x1) { 1816 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/ 1817 afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/ 1818 } else { 1819 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/ 1820 afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/ 1821 } 1822 afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */ 1823 afe_write(sd, 0x12, 0x63); /* ADI recommend write */ 1824 1825 sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */ 1826 sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */ 1827 1828 /* SDP recommended settings */ 1829 sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */ 1830 sdp_write(sd, 0x01, 0x00); /* Pedestal Off */ 1831 1832 sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */ 1833 sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */ 1834 sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */ 1835 sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */ 1836 sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */ 1837 sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */ 1838 sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */ 1839 1840 /* deinterlacer enabled and 3D comb */ 1841 sdp_write_and_or(sd, 0x12, 0xf6, 0x09); 1842 1843 break; 1844 1845 case ADV7842_MODE_COMP: 1846 case ADV7842_MODE_RGB: 1847 /* Automatic analog input muxing mode */ 1848 afe_write_and_or(sd, 0x02, 0x7f, 0x00); 1849 /* set mode and select free run resolution */ 1850 io_write(sd, 0x00, vid_std_select); /* video std */ 1851 io_write(sd, 0x01, 0x02); /* prim mode */ 1852 cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs 1853 for auto graphics mode */ 1854 1855 afe_write(sd, 0x00, 0x00); /* power up ADC */ 1856 afe_write(sd, 0xc8, 0x00); /* phase control */ 1857 if (state->mode == ADV7842_MODE_COMP) { 1858 /* force to YCrCb */ 1859 io_write_and_or(sd, 0x02, 0x0f, 0x60); 1860 } else { 1861 /* force to RGB */ 1862 io_write_and_or(sd, 0x02, 0x0f, 0x10); 1863 } 1864 1865 /* set ADI recommended settings for digitizer */ 1866 /* "ADV7842 Register Settings Recommendations 1867 * (rev. 1.8, November 2010)" p. 9. */ 1868 afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */ 1869 afe_write(sd, 0x12, 0x63); /* ADC Range improvement */ 1870 1871 /* set to default gain for RGB */ 1872 cp_write(sd, 0x73, 0x10); 1873 cp_write(sd, 0x74, 0x04); 1874 cp_write(sd, 0x75, 0x01); 1875 cp_write(sd, 0x76, 0x00); 1876 1877 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */ 1878 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */ 1879 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */ 1880 break; 1881 1882 case ADV7842_MODE_HDMI: 1883 /* Automatic analog input muxing mode */ 1884 afe_write_and_or(sd, 0x02, 0x7f, 0x00); 1885 /* set mode and select free run resolution */ 1886 if (state->hdmi_port_a) 1887 hdmi_write(sd, 0x00, 0x02); /* select port A */ 1888 else 1889 hdmi_write(sd, 0x00, 0x03); /* select port B */ 1890 io_write(sd, 0x00, vid_std_select); /* video std */ 1891 io_write(sd, 0x01, 5); /* prim mode */ 1892 cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs 1893 for auto graphics mode */ 1894 1895 /* set ADI recommended settings for HDMI: */ 1896 /* "ADV7842 Register Settings Recommendations 1897 * (rev. 1.8, November 2010)" p. 3. */ 1898 hdmi_write(sd, 0xc0, 0x00); 1899 hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */ 1900 hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */ 1901 hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */ 1902 hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */ 1903 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */ 1904 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */ 1905 hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */ 1906 hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */ 1907 hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit, 1908 Improve robustness */ 1909 hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */ 1910 hdmi_write(sd, 0x85, 0x1f); /* equaliser */ 1911 hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */ 1912 hdmi_write(sd, 0x89, 0x04); /* equaliser */ 1913 hdmi_write(sd, 0x8a, 0x1e); /* equaliser */ 1914 hdmi_write(sd, 0x93, 0x04); /* equaliser */ 1915 hdmi_write(sd, 0x94, 0x1e); /* equaliser */ 1916 hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */ 1917 hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */ 1918 hdmi_write(sd, 0x9d, 0x02); /* equaliser */ 1919 1920 afe_write(sd, 0x00, 0xff); /* power down ADC */ 1921 afe_write(sd, 0xc8, 0x40); /* phase control */ 1922 1923 /* set to default gain for HDMI */ 1924 cp_write(sd, 0x73, 0x10); 1925 cp_write(sd, 0x74, 0x04); 1926 cp_write(sd, 0x75, 0x01); 1927 cp_write(sd, 0x76, 0x00); 1928 1929 /* reset ADI recommended settings for digitizer */ 1930 /* "ADV7842 Register Settings Recommendations 1931 * (rev. 2.5, June 2010)" p. 17. */ 1932 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */ 1933 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */ 1934 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */ 1935 1936 /* CP coast control */ 1937 cp_write(sd, 0xc3, 0x33); /* Component mode */ 1938 1939 /* color space conversion, autodetect color space */ 1940 io_write_and_or(sd, 0x02, 0x0f, 0xf0); 1941 break; 1942 1943 default: 1944 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", 1945 __func__, state->mode); 1946 break; 1947 } 1948 } 1949 1950 static int adv7842_s_routing(struct v4l2_subdev *sd, 1951 u32 input, u32 output, u32 config) 1952 { 1953 struct adv7842_state *state = to_state(sd); 1954 1955 v4l2_dbg(2, debug, sd, "%s: input %d\n", __func__, input); 1956 1957 switch (input) { 1958 case ADV7842_SELECT_HDMI_PORT_A: 1959 state->mode = ADV7842_MODE_HDMI; 1960 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P; 1961 state->hdmi_port_a = true; 1962 break; 1963 case ADV7842_SELECT_HDMI_PORT_B: 1964 state->mode = ADV7842_MODE_HDMI; 1965 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P; 1966 state->hdmi_port_a = false; 1967 break; 1968 case ADV7842_SELECT_VGA_COMP: 1969 state->mode = ADV7842_MODE_COMP; 1970 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE; 1971 break; 1972 case ADV7842_SELECT_VGA_RGB: 1973 state->mode = ADV7842_MODE_RGB; 1974 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE; 1975 break; 1976 case ADV7842_SELECT_SDP_CVBS: 1977 state->mode = ADV7842_MODE_SDP; 1978 state->vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1; 1979 break; 1980 case ADV7842_SELECT_SDP_YC: 1981 state->mode = ADV7842_MODE_SDP; 1982 state->vid_std_select = ADV7842_SDP_VID_STD_YC_SD4_x1; 1983 break; 1984 default: 1985 return -EINVAL; 1986 } 1987 1988 disable_input(sd); 1989 select_input(sd, state->vid_std_select); 1990 enable_input(sd); 1991 1992 v4l2_subdev_notify_event(sd, &adv7842_ev_fmt); 1993 1994 return 0; 1995 } 1996 1997 static int adv7842_enum_mbus_code(struct v4l2_subdev *sd, 1998 struct v4l2_subdev_state *sd_state, 1999 struct v4l2_subdev_mbus_code_enum *code) 2000 { 2001 if (code->index >= ARRAY_SIZE(adv7842_formats)) 2002 return -EINVAL; 2003 code->code = adv7842_formats[code->index].code; 2004 return 0; 2005 } 2006 2007 static void adv7842_fill_format(struct adv7842_state *state, 2008 struct v4l2_mbus_framefmt *format) 2009 { 2010 memset(format, 0, sizeof(*format)); 2011 2012 format->width = state->timings.bt.width; 2013 format->height = state->timings.bt.height; 2014 format->field = V4L2_FIELD_NONE; 2015 format->colorspace = V4L2_COLORSPACE_SRGB; 2016 2017 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) 2018 format->colorspace = (state->timings.bt.height <= 576) ? 2019 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709; 2020 } 2021 2022 /* 2023 * Compute the op_ch_sel value required to obtain on the bus the component order 2024 * corresponding to the selected format taking into account bus reordering 2025 * applied by the board at the output of the device. 2026 * 2027 * The following table gives the op_ch_value from the format component order 2028 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as 2029 * adv7842_bus_order value in row). 2030 * 2031 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5) 2032 * ----------+------------------------------------------------- 2033 * RGB (NOP) | GBR GRB BGR RGB BRG RBG 2034 * GRB (1-2) | BGR RGB GBR GRB RBG BRG 2035 * RBG (2-3) | GRB GBR BRG RBG BGR RGB 2036 * BGR (1-3) | RBG BRG RGB BGR GRB GBR 2037 * BRG (ROR) | BRG RBG GRB GBR RGB BGR 2038 * GBR (ROL) | RGB BGR RBG BRG GBR GRB 2039 */ 2040 static unsigned int adv7842_op_ch_sel(struct adv7842_state *state) 2041 { 2042 #define _SEL(a, b, c, d, e, f) { \ 2043 ADV7842_OP_CH_SEL_##a, ADV7842_OP_CH_SEL_##b, ADV7842_OP_CH_SEL_##c, \ 2044 ADV7842_OP_CH_SEL_##d, ADV7842_OP_CH_SEL_##e, ADV7842_OP_CH_SEL_##f } 2045 #define _BUS(x) [ADV7842_BUS_ORDER_##x] 2046 2047 static const unsigned int op_ch_sel[6][6] = { 2048 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG), 2049 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG), 2050 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB), 2051 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR), 2052 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR), 2053 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB), 2054 }; 2055 2056 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5]; 2057 } 2058 2059 static void adv7842_setup_format(struct adv7842_state *state) 2060 { 2061 struct v4l2_subdev *sd = &state->sd; 2062 2063 io_write_clr_set(sd, 0x02, 0x02, 2064 state->format->rgb_out ? ADV7842_RGB_OUT : 0); 2065 io_write(sd, 0x03, state->format->op_format_sel | 2066 state->pdata.op_format_mode_sel); 2067 io_write_clr_set(sd, 0x04, 0xe0, adv7842_op_ch_sel(state)); 2068 io_write_clr_set(sd, 0x05, 0x01, 2069 state->format->swap_cb_cr ? ADV7842_OP_SWAP_CB_CR : 0); 2070 set_rgb_quantization_range(sd); 2071 } 2072 2073 static int adv7842_get_format(struct v4l2_subdev *sd, 2074 struct v4l2_subdev_state *sd_state, 2075 struct v4l2_subdev_format *format) 2076 { 2077 struct adv7842_state *state = to_state(sd); 2078 2079 if (format->pad != ADV7842_PAD_SOURCE) 2080 return -EINVAL; 2081 2082 if (state->mode == ADV7842_MODE_SDP) { 2083 /* SPD block */ 2084 if (!(sdp_read(sd, 0x5a) & 0x01)) 2085 return -EINVAL; 2086 format->format.code = MEDIA_BUS_FMT_YUYV8_2X8; 2087 format->format.width = 720; 2088 /* valid signal */ 2089 if (state->norm & V4L2_STD_525_60) 2090 format->format.height = 480; 2091 else 2092 format->format.height = 576; 2093 format->format.colorspace = V4L2_COLORSPACE_SMPTE170M; 2094 return 0; 2095 } 2096 2097 adv7842_fill_format(state, &format->format); 2098 2099 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 2100 struct v4l2_mbus_framefmt *fmt; 2101 2102 fmt = v4l2_subdev_state_get_format(sd_state, format->pad); 2103 format->format.code = fmt->code; 2104 } else { 2105 format->format.code = state->format->code; 2106 } 2107 2108 return 0; 2109 } 2110 2111 static int adv7842_set_format(struct v4l2_subdev *sd, 2112 struct v4l2_subdev_state *sd_state, 2113 struct v4l2_subdev_format *format) 2114 { 2115 struct adv7842_state *state = to_state(sd); 2116 const struct adv7842_format_info *info; 2117 2118 if (format->pad != ADV7842_PAD_SOURCE) 2119 return -EINVAL; 2120 2121 if (state->mode == ADV7842_MODE_SDP) 2122 return adv7842_get_format(sd, sd_state, format); 2123 2124 info = adv7842_format_info(state, format->format.code); 2125 if (info == NULL) 2126 info = adv7842_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); 2127 2128 adv7842_fill_format(state, &format->format); 2129 format->format.code = info->code; 2130 2131 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 2132 struct v4l2_mbus_framefmt *fmt; 2133 2134 fmt = v4l2_subdev_state_get_format(sd_state, format->pad); 2135 fmt->code = format->format.code; 2136 } else { 2137 state->format = info; 2138 adv7842_setup_format(state); 2139 } 2140 2141 return 0; 2142 } 2143 2144 static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable) 2145 { 2146 if (enable) { 2147 /* Enable SSPD, STDI and CP locked/unlocked interrupts */ 2148 io_write(sd, 0x46, 0x9c); 2149 /* ESDP_50HZ_DET interrupt */ 2150 io_write(sd, 0x5a, 0x10); 2151 /* Enable CABLE_DET_A/B_ST (+5v) interrupt */ 2152 io_write(sd, 0x73, 0x03); 2153 /* Enable V_LOCKED and DE_REGEN_LCK interrupts */ 2154 io_write(sd, 0x78, 0x03); 2155 /* Enable SDP Standard Detection Change and SDP Video Detected */ 2156 io_write(sd, 0xa0, 0x09); 2157 /* Enable HDMI_MODE interrupt */ 2158 io_write(sd, 0x69, 0x08); 2159 } else { 2160 io_write(sd, 0x46, 0x0); 2161 io_write(sd, 0x5a, 0x0); 2162 io_write(sd, 0x73, 0x0); 2163 io_write(sd, 0x78, 0x0); 2164 io_write(sd, 0xa0, 0x0); 2165 io_write(sd, 0x69, 0x0); 2166 } 2167 } 2168 2169 #if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC) 2170 static void adv7842_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status) 2171 { 2172 struct adv7842_state *state = to_state(sd); 2173 2174 if ((cec_read(sd, 0x11) & 0x01) == 0) { 2175 v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n", __func__); 2176 return; 2177 } 2178 2179 if (tx_raw_status & 0x02) { 2180 v4l2_dbg(1, debug, sd, "%s: tx raw: arbitration lost\n", 2181 __func__); 2182 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_ARB_LOST, 2183 1, 0, 0, 0); 2184 return; 2185 } 2186 if (tx_raw_status & 0x04) { 2187 u8 status; 2188 u8 nack_cnt; 2189 u8 low_drive_cnt; 2190 2191 v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n", __func__); 2192 /* 2193 * We set this status bit since this hardware performs 2194 * retransmissions. 2195 */ 2196 status = CEC_TX_STATUS_MAX_RETRIES; 2197 nack_cnt = cec_read(sd, 0x14) & 0xf; 2198 if (nack_cnt) 2199 status |= CEC_TX_STATUS_NACK; 2200 low_drive_cnt = cec_read(sd, 0x14) >> 4; 2201 if (low_drive_cnt) 2202 status |= CEC_TX_STATUS_LOW_DRIVE; 2203 cec_transmit_done(state->cec_adap, status, 2204 0, nack_cnt, low_drive_cnt, 0); 2205 return; 2206 } 2207 if (tx_raw_status & 0x01) { 2208 v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n", __func__); 2209 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0); 2210 return; 2211 } 2212 } 2213 2214 static void adv7842_cec_isr(struct v4l2_subdev *sd, bool *handled) 2215 { 2216 u8 cec_irq; 2217 2218 /* cec controller */ 2219 cec_irq = io_read(sd, 0x93) & 0x0f; 2220 if (!cec_irq) 2221 return; 2222 2223 v4l2_dbg(1, debug, sd, "%s: cec: irq 0x%x\n", __func__, cec_irq); 2224 adv7842_cec_tx_raw_status(sd, cec_irq); 2225 if (cec_irq & 0x08) { 2226 struct adv7842_state *state = to_state(sd); 2227 struct cec_msg msg; 2228 2229 msg.len = cec_read(sd, 0x25) & 0x1f; 2230 if (msg.len > CEC_MAX_MSG_SIZE) 2231 msg.len = CEC_MAX_MSG_SIZE; 2232 2233 if (msg.len) { 2234 u8 i; 2235 2236 for (i = 0; i < msg.len; i++) 2237 msg.msg[i] = cec_read(sd, i + 0x15); 2238 cec_write(sd, 0x26, 0x01); /* re-enable rx */ 2239 cec_received_msg(state->cec_adap, &msg); 2240 } 2241 } 2242 2243 io_write(sd, 0x94, cec_irq); 2244 2245 if (handled) 2246 *handled = true; 2247 } 2248 2249 static int adv7842_cec_adap_enable(struct cec_adapter *adap, bool enable) 2250 { 2251 struct adv7842_state *state = cec_get_drvdata(adap); 2252 struct v4l2_subdev *sd = &state->sd; 2253 2254 if (!state->cec_enabled_adap && enable) { 2255 cec_write_clr_set(sd, 0x2a, 0x01, 0x01); /* power up cec */ 2256 cec_write(sd, 0x2c, 0x01); /* cec soft reset */ 2257 cec_write_clr_set(sd, 0x11, 0x01, 0); /* initially disable tx */ 2258 /* enabled irqs: */ 2259 /* tx: ready */ 2260 /* tx: arbitration lost */ 2261 /* tx: retry timeout */ 2262 /* rx: ready */ 2263 io_write_clr_set(sd, 0x96, 0x0f, 0x0f); 2264 cec_write(sd, 0x26, 0x01); /* enable rx */ 2265 } else if (state->cec_enabled_adap && !enable) { 2266 /* disable cec interrupts */ 2267 io_write_clr_set(sd, 0x96, 0x0f, 0x00); 2268 /* disable address mask 1-3 */ 2269 cec_write_clr_set(sd, 0x27, 0x70, 0x00); 2270 /* power down cec section */ 2271 cec_write_clr_set(sd, 0x2a, 0x01, 0x00); 2272 state->cec_valid_addrs = 0; 2273 } 2274 state->cec_enabled_adap = enable; 2275 return 0; 2276 } 2277 2278 static int adv7842_cec_adap_log_addr(struct cec_adapter *adap, u8 addr) 2279 { 2280 struct adv7842_state *state = cec_get_drvdata(adap); 2281 struct v4l2_subdev *sd = &state->sd; 2282 unsigned int i, free_idx = ADV7842_MAX_ADDRS; 2283 2284 if (!state->cec_enabled_adap) 2285 return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO; 2286 2287 if (addr == CEC_LOG_ADDR_INVALID) { 2288 cec_write_clr_set(sd, 0x27, 0x70, 0); 2289 state->cec_valid_addrs = 0; 2290 return 0; 2291 } 2292 2293 for (i = 0; i < ADV7842_MAX_ADDRS; i++) { 2294 bool is_valid = state->cec_valid_addrs & (1 << i); 2295 2296 if (free_idx == ADV7842_MAX_ADDRS && !is_valid) 2297 free_idx = i; 2298 if (is_valid && state->cec_addr[i] == addr) 2299 return 0; 2300 } 2301 if (i == ADV7842_MAX_ADDRS) { 2302 i = free_idx; 2303 if (i == ADV7842_MAX_ADDRS) 2304 return -ENXIO; 2305 } 2306 state->cec_addr[i] = addr; 2307 state->cec_valid_addrs |= 1 << i; 2308 2309 switch (i) { 2310 case 0: 2311 /* enable address mask 0 */ 2312 cec_write_clr_set(sd, 0x27, 0x10, 0x10); 2313 /* set address for mask 0 */ 2314 cec_write_clr_set(sd, 0x28, 0x0f, addr); 2315 break; 2316 case 1: 2317 /* enable address mask 1 */ 2318 cec_write_clr_set(sd, 0x27, 0x20, 0x20); 2319 /* set address for mask 1 */ 2320 cec_write_clr_set(sd, 0x28, 0xf0, addr << 4); 2321 break; 2322 case 2: 2323 /* enable address mask 2 */ 2324 cec_write_clr_set(sd, 0x27, 0x40, 0x40); 2325 /* set address for mask 1 */ 2326 cec_write_clr_set(sd, 0x29, 0x0f, addr); 2327 break; 2328 } 2329 return 0; 2330 } 2331 2332 static int adv7842_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 2333 u32 signal_free_time, struct cec_msg *msg) 2334 { 2335 struct adv7842_state *state = cec_get_drvdata(adap); 2336 struct v4l2_subdev *sd = &state->sd; 2337 u8 len = msg->len; 2338 unsigned int i; 2339 2340 /* 2341 * The number of retries is the number of attempts - 1, but retry 2342 * at least once. It's not clear if a value of 0 is allowed, so 2343 * let's do at least one retry. 2344 */ 2345 cec_write_clr_set(sd, 0x12, 0x70, max(1, attempts - 1) << 4); 2346 2347 if (len > 16) { 2348 v4l2_err(sd, "%s: len exceeded 16 (%d)\n", __func__, len); 2349 return -EINVAL; 2350 } 2351 2352 /* write data */ 2353 for (i = 0; i < len; i++) 2354 cec_write(sd, i, msg->msg[i]); 2355 2356 /* set length (data + header) */ 2357 cec_write(sd, 0x10, len); 2358 /* start transmit, enable tx */ 2359 cec_write(sd, 0x11, 0x01); 2360 return 0; 2361 } 2362 2363 static const struct cec_adap_ops adv7842_cec_adap_ops = { 2364 .adap_enable = adv7842_cec_adap_enable, 2365 .adap_log_addr = adv7842_cec_adap_log_addr, 2366 .adap_transmit = adv7842_cec_adap_transmit, 2367 }; 2368 #endif 2369 2370 static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled) 2371 { 2372 struct adv7842_state *state = to_state(sd); 2373 u8 fmt_change_cp, fmt_change_digital, fmt_change_sdp; 2374 u8 irq_status[6]; 2375 2376 adv7842_irq_enable(sd, false); 2377 2378 /* read status */ 2379 irq_status[0] = io_read(sd, 0x43); 2380 irq_status[1] = io_read(sd, 0x57); 2381 irq_status[2] = io_read(sd, 0x70); 2382 irq_status[3] = io_read(sd, 0x75); 2383 irq_status[4] = io_read(sd, 0x9d); 2384 irq_status[5] = io_read(sd, 0x66); 2385 2386 /* and clear */ 2387 if (irq_status[0]) 2388 io_write(sd, 0x44, irq_status[0]); 2389 if (irq_status[1]) 2390 io_write(sd, 0x58, irq_status[1]); 2391 if (irq_status[2]) 2392 io_write(sd, 0x71, irq_status[2]); 2393 if (irq_status[3]) 2394 io_write(sd, 0x76, irq_status[3]); 2395 if (irq_status[4]) 2396 io_write(sd, 0x9e, irq_status[4]); 2397 if (irq_status[5]) 2398 io_write(sd, 0x67, irq_status[5]); 2399 2400 adv7842_irq_enable(sd, true); 2401 2402 v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x, %x\n", __func__, 2403 irq_status[0], irq_status[1], irq_status[2], 2404 irq_status[3], irq_status[4], irq_status[5]); 2405 2406 /* format change CP */ 2407 fmt_change_cp = irq_status[0] & 0x9c; 2408 2409 /* format change SDP */ 2410 if (state->mode == ADV7842_MODE_SDP) 2411 fmt_change_sdp = (irq_status[1] & 0x30) | (irq_status[4] & 0x09); 2412 else 2413 fmt_change_sdp = 0; 2414 2415 /* digital format CP */ 2416 if (is_digital_input(sd)) 2417 fmt_change_digital = irq_status[3] & 0x03; 2418 else 2419 fmt_change_digital = 0; 2420 2421 /* format change */ 2422 if (fmt_change_cp || fmt_change_digital || fmt_change_sdp) { 2423 v4l2_dbg(1, debug, sd, 2424 "%s: fmt_change_cp = 0x%x, fmt_change_digital = 0x%x, fmt_change_sdp = 0x%x\n", 2425 __func__, fmt_change_cp, fmt_change_digital, 2426 fmt_change_sdp); 2427 v4l2_subdev_notify_event(sd, &adv7842_ev_fmt); 2428 if (handled) 2429 *handled = true; 2430 } 2431 2432 /* HDMI/DVI mode */ 2433 if (irq_status[5] & 0x08) { 2434 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__, 2435 (io_read(sd, 0x65) & 0x08) ? "HDMI" : "DVI"); 2436 set_rgb_quantization_range(sd); 2437 if (handled) 2438 *handled = true; 2439 } 2440 2441 #if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC) 2442 /* cec */ 2443 adv7842_cec_isr(sd, handled); 2444 #endif 2445 2446 /* tx 5v detect */ 2447 if (irq_status[2] & 0x3) { 2448 v4l2_dbg(1, debug, sd, "%s: irq tx_5v\n", __func__); 2449 adv7842_s_detect_tx_5v_ctrl(sd); 2450 if (handled) 2451 *handled = true; 2452 } 2453 return 0; 2454 } 2455 2456 static int adv7842_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 2457 { 2458 struct adv7842_state *state = to_state(sd); 2459 u32 blocks = 0; 2460 u8 *data = NULL; 2461 2462 memset(edid->reserved, 0, sizeof(edid->reserved)); 2463 2464 switch (edid->pad) { 2465 case ADV7842_EDID_PORT_A: 2466 case ADV7842_EDID_PORT_B: 2467 if (state->hdmi_edid.present & (0x04 << edid->pad)) { 2468 data = state->hdmi_edid.edid; 2469 blocks = state->hdmi_edid.blocks; 2470 } 2471 break; 2472 case ADV7842_EDID_PORT_VGA: 2473 if (state->vga_edid.present) { 2474 data = state->vga_edid.edid; 2475 blocks = state->vga_edid.blocks; 2476 } 2477 break; 2478 default: 2479 return -EINVAL; 2480 } 2481 2482 if (edid->start_block == 0 && edid->blocks == 0) { 2483 edid->blocks = blocks; 2484 return 0; 2485 } 2486 2487 if (!data) 2488 return -ENODATA; 2489 2490 if (edid->start_block >= blocks) 2491 return -EINVAL; 2492 2493 if (edid->start_block + edid->blocks > blocks) 2494 edid->blocks = blocks - edid->start_block; 2495 2496 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128); 2497 2498 return 0; 2499 } 2500 2501 /* 2502 * If the VGA_EDID_ENABLE bit is set (Repeater Map 0x7f, bit 7), then 2503 * the first two blocks of the EDID are for the HDMI, and the first block 2504 * of segment 1 (i.e. the third block of the EDID) is for VGA. 2505 * So if a VGA EDID is installed, then the maximum size of the HDMI EDID 2506 * is 2 blocks. 2507 */ 2508 static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *e) 2509 { 2510 struct adv7842_state *state = to_state(sd); 2511 unsigned int max_blocks = e->pad == ADV7842_EDID_PORT_VGA ? 1 : 4; 2512 int err = 0; 2513 2514 memset(e->reserved, 0, sizeof(e->reserved)); 2515 2516 if (e->pad > ADV7842_EDID_PORT_VGA) 2517 return -EINVAL; 2518 if (e->start_block != 0) 2519 return -EINVAL; 2520 if (e->pad < ADV7842_EDID_PORT_VGA && state->vga_edid.blocks) 2521 max_blocks = 2; 2522 if (e->pad == ADV7842_EDID_PORT_VGA && state->hdmi_edid.blocks > 2) 2523 return -EBUSY; 2524 if (e->blocks > max_blocks) { 2525 e->blocks = max_blocks; 2526 return -E2BIG; 2527 } 2528 2529 /* todo, per edid */ 2530 if (e->blocks) 2531 state->aspect_ratio = v4l2_calc_aspect_ratio(e->edid[0x15], 2532 e->edid[0x16]); 2533 2534 switch (e->pad) { 2535 case ADV7842_EDID_PORT_VGA: 2536 memset(state->vga_edid.edid, 0, sizeof(state->vga_edid.edid)); 2537 state->vga_edid.blocks = e->blocks; 2538 state->vga_edid.present = e->blocks ? 0x1 : 0x0; 2539 if (e->blocks) 2540 memcpy(state->vga_edid.edid, e->edid, 128); 2541 err = edid_write_vga_segment(sd); 2542 break; 2543 case ADV7842_EDID_PORT_A: 2544 case ADV7842_EDID_PORT_B: 2545 memset(state->hdmi_edid.edid, 0, sizeof(state->hdmi_edid.edid)); 2546 state->hdmi_edid.blocks = e->blocks; 2547 if (e->blocks) { 2548 state->hdmi_edid.present |= 0x04 << e->pad; 2549 memcpy(state->hdmi_edid.edid, e->edid, 128 * e->blocks); 2550 } else { 2551 state->hdmi_edid.present &= ~(0x04 << e->pad); 2552 adv7842_s_detect_tx_5v_ctrl(sd); 2553 } 2554 err = edid_write_hdmi_segment(sd, e->pad); 2555 break; 2556 default: 2557 return -EINVAL; 2558 } 2559 if (err < 0) 2560 v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad); 2561 return err; 2562 } 2563 2564 struct adv7842_cfg_read_infoframe { 2565 const char *desc; 2566 u8 present_mask; 2567 u8 head_addr; 2568 u8 payload_addr; 2569 }; 2570 2571 static const struct adv7842_cfg_read_infoframe adv7842_cri[] = { 2572 { "AVI", 0x01, 0xe0, 0x00 }, 2573 { "Audio", 0x02, 0xe3, 0x1c }, 2574 { "SDP", 0x04, 0xe6, 0x2a }, 2575 { "Vendor", 0x10, 0xec, 0x54 } 2576 }; 2577 2578 static int adv7842_read_infoframe_buf(struct v4l2_subdev *sd, int index, 2579 u8 buf[V4L2_DEBUGFS_IF_MAX_LEN]) 2580 { 2581 const struct adv7842_cfg_read_infoframe *cri = &adv7842_cri[index]; 2582 int len, i; 2583 2584 if (!(io_read(sd, 0x60) & cri->present_mask)) { 2585 v4l2_dbg(1, debug, sd, 2586 "%s infoframe not received\n", cri->desc); 2587 return -ENOENT; 2588 } 2589 2590 for (i = 0; i < 3; i++) 2591 buf[i] = infoframe_read(sd, cri->head_addr + i); 2592 2593 len = buf[2] + 1; 2594 2595 if (len + 3 > V4L2_DEBUGFS_IF_MAX_LEN) { 2596 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", 2597 __func__, cri->desc, len); 2598 return -ENOENT; 2599 } 2600 2601 for (i = 0; i < len; i++) 2602 buf[i + 3] = infoframe_read(sd, cri->payload_addr + i); 2603 return len + 3; 2604 } 2605 2606 static void adv7842_log_infoframes(struct v4l2_subdev *sd) 2607 { 2608 struct i2c_client *client = v4l2_get_subdevdata(sd); 2609 struct device *dev = &client->dev; 2610 union hdmi_infoframe frame; 2611 u8 buffer[V4L2_DEBUGFS_IF_MAX_LEN] = {}; 2612 int len, i; 2613 2614 if (!(hdmi_read(sd, 0x05) & 0x80)) { 2615 v4l2_info(sd, "receive DVI-D signal, no infoframes\n"); 2616 return; 2617 } 2618 2619 for (i = 0; i < ARRAY_SIZE(adv7842_cri); i++) { 2620 len = adv7842_read_infoframe_buf(sd, i, buffer); 2621 if (len < 0) 2622 continue; 2623 2624 if (hdmi_infoframe_unpack(&frame, buffer, len) < 0) 2625 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", 2626 __func__, adv7842_cri[i].desc); 2627 else 2628 hdmi_infoframe_log(KERN_INFO, dev, &frame); 2629 } 2630 } 2631 2632 #if 0 2633 /* Let's keep it here for now, as it could be useful for debug */ 2634 static const char * const prim_mode_txt[] = { 2635 "SDP", 2636 "Component", 2637 "Graphics", 2638 "Reserved", 2639 "CVBS & HDMI AUDIO", 2640 "HDMI-Comp", 2641 "HDMI-GR", 2642 "Reserved", 2643 "Reserved", 2644 "Reserved", 2645 "Reserved", 2646 "Reserved", 2647 "Reserved", 2648 "Reserved", 2649 "Reserved", 2650 "Reserved", 2651 }; 2652 #endif 2653 2654 static int adv7842_sdp_log_status(struct v4l2_subdev *sd) 2655 { 2656 /* SDP (Standard definition processor) block */ 2657 u8 sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01; 2658 2659 v4l2_info(sd, "Chip powered %s\n", no_power(sd) ? "off" : "on"); 2660 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n", 2661 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f); 2662 2663 v4l2_info(sd, "SDP: free run: %s\n", 2664 (sdp_read(sd, 0x56) & 0x01) ? "on" : "off"); 2665 v4l2_info(sd, "SDP: %s\n", sdp_signal_detected ? 2666 "valid SD/PR signal detected" : "invalid/no signal"); 2667 if (sdp_signal_detected) { 2668 static const char * const sdp_std_txt[] = { 2669 "NTSC-M/J", 2670 "1?", 2671 "NTSC-443", 2672 "60HzSECAM", 2673 "PAL-M", 2674 "5?", 2675 "PAL-60", 2676 "7?", "8?", "9?", "a?", "b?", 2677 "PAL-CombN", 2678 "d?", 2679 "PAL-BGHID", 2680 "SECAM" 2681 }; 2682 v4l2_info(sd, "SDP: standard %s\n", 2683 sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]); 2684 v4l2_info(sd, "SDP: %s\n", 2685 (sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz"); 2686 v4l2_info(sd, "SDP: %s\n", 2687 (sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive"); 2688 v4l2_info(sd, "SDP: deinterlacer %s\n", 2689 (sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled"); 2690 v4l2_info(sd, "SDP: csc %s mode\n", 2691 (sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual"); 2692 } 2693 return 0; 2694 } 2695 2696 static int adv7842_cp_log_status(struct v4l2_subdev *sd) 2697 { 2698 /* CP block */ 2699 struct adv7842_state *state = to_state(sd); 2700 struct v4l2_dv_timings timings; 2701 u8 reg_io_0x02 = io_read(sd, 0x02); 2702 u8 reg_io_0x21 = io_read(sd, 0x21); 2703 u8 reg_rep_0x77 = rep_read(sd, 0x77); 2704 u8 reg_rep_0x7d = rep_read(sd, 0x7d); 2705 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01; 2706 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01; 2707 bool audio_mute = io_read(sd, 0x65) & 0x40; 2708 2709 static const char * const csc_coeff_sel_rb[16] = { 2710 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB", 2711 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709", 2712 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709", 2713 "reserved", "reserved", "reserved", "reserved", "manual" 2714 }; 2715 static const char * const input_color_space_txt[16] = { 2716 "RGB limited range (16-235)", "RGB full range (0-255)", 2717 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", 2718 "xvYCC Bt.601", "xvYCC Bt.709", 2719 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", 2720 "invalid", "invalid", "invalid", "invalid", "invalid", 2721 "invalid", "invalid", "automatic" 2722 }; 2723 static const char * const rgb_quantization_range_txt[] = { 2724 "Automatic", 2725 "RGB limited range (16-235)", 2726 "RGB full range (0-255)", 2727 }; 2728 static const char * const deep_color_mode_txt[4] = { 2729 "8-bits per channel", 2730 "10-bits per channel", 2731 "12-bits per channel", 2732 "16-bits per channel (not supported)" 2733 }; 2734 2735 v4l2_info(sd, "-----Chip status-----\n"); 2736 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on"); 2737 v4l2_info(sd, "HDMI/DVI-D port selected: %s\n", 2738 state->hdmi_port_a ? "A" : "B"); 2739 v4l2_info(sd, "EDID A %s, B %s\n", 2740 ((reg_rep_0x7d & 0x04) && (reg_rep_0x77 & 0x04)) ? 2741 "enabled" : "disabled", 2742 ((reg_rep_0x7d & 0x08) && (reg_rep_0x77 & 0x08)) ? 2743 "enabled" : "disabled"); 2744 v4l2_info(sd, "HPD A %s, B %s\n", 2745 reg_io_0x21 & 0x02 ? "enabled" : "disabled", 2746 reg_io_0x21 & 0x01 ? "enabled" : "disabled"); 2747 v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ? 2748 "enabled" : "disabled"); 2749 if (state->cec_enabled_adap) { 2750 int i; 2751 2752 for (i = 0; i < ADV7842_MAX_ADDRS; i++) { 2753 bool is_valid = state->cec_valid_addrs & (1 << i); 2754 2755 if (is_valid) 2756 v4l2_info(sd, "CEC Logical Address: 0x%x\n", 2757 state->cec_addr[i]); 2758 } 2759 } 2760 2761 v4l2_info(sd, "-----Signal status-----\n"); 2762 if (state->hdmi_port_a) { 2763 v4l2_info(sd, "Cable detected (+5V power): %s\n", 2764 io_read(sd, 0x6f) & 0x02 ? "true" : "false"); 2765 v4l2_info(sd, "TMDS signal detected: %s\n", 2766 (io_read(sd, 0x6a) & 0x02) ? "true" : "false"); 2767 v4l2_info(sd, "TMDS signal locked: %s\n", 2768 (io_read(sd, 0x6a) & 0x20) ? "true" : "false"); 2769 } else { 2770 v4l2_info(sd, "Cable detected (+5V power):%s\n", 2771 io_read(sd, 0x6f) & 0x01 ? "true" : "false"); 2772 v4l2_info(sd, "TMDS signal detected: %s\n", 2773 (io_read(sd, 0x6a) & 0x01) ? "true" : "false"); 2774 v4l2_info(sd, "TMDS signal locked: %s\n", 2775 (io_read(sd, 0x6a) & 0x10) ? "true" : "false"); 2776 } 2777 v4l2_info(sd, "CP free run: %s\n", 2778 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off")); 2779 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n", 2780 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f, 2781 (io_read(sd, 0x01) & 0x70) >> 4); 2782 2783 v4l2_info(sd, "-----Video Timings-----\n"); 2784 if (no_cp_signal(sd)) { 2785 v4l2_info(sd, "STDI: not locked\n"); 2786 } else { 2787 u32 bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2); 2788 u32 lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4); 2789 u32 lcvs = cp_read(sd, 0xb3) >> 3; 2790 u32 fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9); 2791 char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ? 2792 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x'); 2793 char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ? 2794 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x'); 2795 v4l2_info(sd, 2796 "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, fcl = %d, %s, %chsync, %cvsync\n", 2797 lcf, bl, lcvs, fcl, 2798 (cp_read(sd, 0xb1) & 0x40) ? 2799 "interlaced" : "progressive", 2800 hs_pol, vs_pol); 2801 } 2802 if (adv7842_query_dv_timings(sd, 0, &timings)) 2803 v4l2_info(sd, "No video detected\n"); 2804 else 2805 v4l2_print_dv_timings(sd->name, "Detected format: ", 2806 &timings, true); 2807 v4l2_print_dv_timings(sd->name, "Configured format: ", 2808 &state->timings, true); 2809 2810 if (no_cp_signal(sd)) 2811 return 0; 2812 2813 v4l2_info(sd, "-----Color space-----\n"); 2814 v4l2_info(sd, "RGB quantization range ctrl: %s\n", 2815 rgb_quantization_range_txt[state->rgb_quantization_range]); 2816 v4l2_info(sd, "Input color space: %s\n", 2817 input_color_space_txt[reg_io_0x02 >> 4]); 2818 v4l2_info(sd, "Output color space: %s %s, alt-gamma %s\n", 2819 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr", 2820 (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ? 2821 "(16-235)" : "(0-255)", 2822 (reg_io_0x02 & 0x08) ? "enabled" : "disabled"); 2823 v4l2_info(sd, "Color space conversion: %s\n", 2824 csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]); 2825 2826 if (!is_digital_input(sd)) 2827 return 0; 2828 2829 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); 2830 v4l2_info(sd, "HDCP encrypted content: %s\n", 2831 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false"); 2832 v4l2_info(sd, "HDCP keys read: %s%s\n", 2833 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no", 2834 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : ""); 2835 if (!is_hdmi(sd)) 2836 return 0; 2837 2838 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n", 2839 audio_pll_locked ? "locked" : "not locked", 2840 audio_sample_packet_detect ? "detected" : "not detected", 2841 audio_mute ? "muted" : "enabled"); 2842 if (audio_pll_locked && audio_sample_packet_detect) { 2843 v4l2_info(sd, "Audio format: %s\n", 2844 (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo"); 2845 } 2846 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) + 2847 (hdmi_read(sd, 0x5c) << 8) + 2848 (hdmi_read(sd, 0x5d) & 0xf0)); 2849 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) + 2850 (hdmi_read(sd, 0x5e) << 8) + 2851 hdmi_read(sd, 0x5f)); 2852 v4l2_info(sd, "AV Mute: %s\n", 2853 (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off"); 2854 v4l2_info(sd, "Deep color mode: %s\n", 2855 deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]); 2856 2857 adv7842_log_infoframes(sd); 2858 2859 return 0; 2860 } 2861 2862 static int adv7842_log_status(struct v4l2_subdev *sd) 2863 { 2864 struct adv7842_state *state = to_state(sd); 2865 2866 if (state->mode == ADV7842_MODE_SDP) 2867 return adv7842_sdp_log_status(sd); 2868 return adv7842_cp_log_status(sd); 2869 } 2870 2871 static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std) 2872 { 2873 struct adv7842_state *state = to_state(sd); 2874 2875 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 2876 2877 if (state->mode != ADV7842_MODE_SDP) 2878 return -ENODATA; 2879 2880 if (!(sdp_read(sd, 0x5A) & 0x01)) { 2881 *std = 0; 2882 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); 2883 return 0; 2884 } 2885 2886 switch (sdp_read(sd, 0x52) & 0x0f) { 2887 case 0: 2888 /* NTSC-M/J */ 2889 *std &= V4L2_STD_NTSC; 2890 break; 2891 case 2: 2892 /* NTSC-443 */ 2893 *std &= V4L2_STD_NTSC_443; 2894 break; 2895 case 3: 2896 /* 60HzSECAM */ 2897 *std &= V4L2_STD_SECAM; 2898 break; 2899 case 4: 2900 /* PAL-M */ 2901 *std &= V4L2_STD_PAL_M; 2902 break; 2903 case 6: 2904 /* PAL-60 */ 2905 *std &= V4L2_STD_PAL_60; 2906 break; 2907 case 0xc: 2908 /* PAL-CombN */ 2909 *std &= V4L2_STD_PAL_Nc; 2910 break; 2911 case 0xe: 2912 /* PAL-BGHID */ 2913 *std &= V4L2_STD_PAL; 2914 break; 2915 case 0xf: 2916 /* SECAM */ 2917 *std &= V4L2_STD_SECAM; 2918 break; 2919 default: 2920 *std &= V4L2_STD_ALL; 2921 break; 2922 } 2923 return 0; 2924 } 2925 2926 static void adv7842_s_sdp_io(struct v4l2_subdev *sd, struct adv7842_sdp_io_sync_adjustment *s) 2927 { 2928 if (s && s->adjust) { 2929 sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf); 2930 sdp_io_write(sd, 0x95, s->hs_beg & 0xff); 2931 sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf); 2932 sdp_io_write(sd, 0x97, s->hs_width & 0xff); 2933 sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf); 2934 sdp_io_write(sd, 0x99, s->de_beg & 0xff); 2935 sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf); 2936 sdp_io_write(sd, 0x9b, s->de_end & 0xff); 2937 sdp_io_write(sd, 0xa8, s->vs_beg_o); 2938 sdp_io_write(sd, 0xa9, s->vs_beg_e); 2939 sdp_io_write(sd, 0xaa, s->vs_end_o); 2940 sdp_io_write(sd, 0xab, s->vs_end_e); 2941 sdp_io_write(sd, 0xac, s->de_v_beg_o); 2942 sdp_io_write(sd, 0xad, s->de_v_beg_e); 2943 sdp_io_write(sd, 0xae, s->de_v_end_o); 2944 sdp_io_write(sd, 0xaf, s->de_v_end_e); 2945 } else { 2946 /* set to default */ 2947 sdp_io_write(sd, 0x94, 0x00); 2948 sdp_io_write(sd, 0x95, 0x00); 2949 sdp_io_write(sd, 0x96, 0x00); 2950 sdp_io_write(sd, 0x97, 0x20); 2951 sdp_io_write(sd, 0x98, 0x00); 2952 sdp_io_write(sd, 0x99, 0x00); 2953 sdp_io_write(sd, 0x9a, 0x00); 2954 sdp_io_write(sd, 0x9b, 0x00); 2955 sdp_io_write(sd, 0xa8, 0x04); 2956 sdp_io_write(sd, 0xa9, 0x04); 2957 sdp_io_write(sd, 0xaa, 0x04); 2958 sdp_io_write(sd, 0xab, 0x04); 2959 sdp_io_write(sd, 0xac, 0x04); 2960 sdp_io_write(sd, 0xad, 0x04); 2961 sdp_io_write(sd, 0xae, 0x04); 2962 sdp_io_write(sd, 0xaf, 0x04); 2963 } 2964 } 2965 2966 static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm) 2967 { 2968 struct adv7842_state *state = to_state(sd); 2969 struct adv7842_platform_data *pdata = &state->pdata; 2970 2971 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 2972 2973 if (state->mode != ADV7842_MODE_SDP) 2974 return -ENODATA; 2975 2976 if (norm & V4L2_STD_625_50) 2977 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_625); 2978 else if (norm & V4L2_STD_525_60) 2979 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_525); 2980 else 2981 adv7842_s_sdp_io(sd, NULL); 2982 2983 if (norm & V4L2_STD_ALL) { 2984 state->norm = norm; 2985 return 0; 2986 } 2987 return -EINVAL; 2988 } 2989 2990 static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm) 2991 { 2992 struct adv7842_state *state = to_state(sd); 2993 2994 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 2995 2996 if (state->mode != ADV7842_MODE_SDP) 2997 return -ENODATA; 2998 2999 *norm = state->norm; 3000 return 0; 3001 } 3002 3003 /* ----------------------------------------------------------------------- */ 3004 3005 static int adv7842_core_init(struct v4l2_subdev *sd) 3006 { 3007 struct adv7842_state *state = to_state(sd); 3008 struct adv7842_platform_data *pdata = &state->pdata; 3009 hdmi_write(sd, 0x48, 3010 (pdata->disable_pwrdnb ? 0x80 : 0) | 3011 (pdata->disable_cable_det_rst ? 0x40 : 0)); 3012 3013 disable_input(sd); 3014 3015 /* 3016 * Disable I2C access to internal EDID ram from HDMI DDC ports 3017 * Disable auto edid enable when leaving powerdown mode 3018 */ 3019 rep_write_and_or(sd, 0x77, 0xd3, 0x20); 3020 3021 /* power */ 3022 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */ 3023 io_write(sd, 0x15, 0x80); /* Power up pads */ 3024 3025 /* video format */ 3026 io_write(sd, 0x02, 0xf0 | pdata->alt_gamma << 3); 3027 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 | 3028 pdata->insert_av_codes << 2 | 3029 pdata->replicate_av_codes << 1); 3030 adv7842_setup_format(state); 3031 3032 /* HDMI audio */ 3033 hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */ 3034 3035 /* Drive strength */ 3036 io_write_and_or(sd, 0x14, 0xc0, 3037 pdata->dr_str_data << 4 | 3038 pdata->dr_str_clk << 2 | 3039 pdata->dr_str_sync); 3040 3041 /* HDMI free run */ 3042 cp_write_and_or(sd, 0xba, 0xfc, pdata->hdmi_free_run_enable | 3043 (pdata->hdmi_free_run_mode << 1)); 3044 3045 /* SPD free run */ 3046 sdp_write_and_or(sd, 0xdd, 0xf0, pdata->sdp_free_run_force | 3047 (pdata->sdp_free_run_cbar_en << 1) | 3048 (pdata->sdp_free_run_man_col_en << 2) | 3049 (pdata->sdp_free_run_auto << 3)); 3050 3051 /* TODO from platform data */ 3052 cp_write(sd, 0x69, 0x14); /* Enable CP CSC */ 3053 io_write(sd, 0x06, 0xa6); /* positive VS and HS and DE */ 3054 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */ 3055 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ 3056 3057 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ 3058 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4); 3059 3060 sdp_csc_coeff(sd, &pdata->sdp_csc_coeff); 3061 3062 /* todo, improve settings for sdram */ 3063 if (pdata->sd_ram_size >= 128) { 3064 sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */ 3065 if (pdata->sd_ram_ddr) { 3066 /* SDP setup for the AD eval board */ 3067 sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */ 3068 sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */ 3069 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */ 3070 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */ 3071 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */ 3072 } else { 3073 sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/ 3074 sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */ 3075 sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3, 3076 depends on memory */ 3077 sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */ 3078 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */ 3079 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */ 3080 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */ 3081 } 3082 } else { 3083 /* 3084 * Manual UG-214, rev 0 is bit confusing on this bit 3085 * but a '1' disables any signal if the Ram is active. 3086 */ 3087 sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */ 3088 } 3089 3090 select_input(sd, pdata->vid_std_select); 3091 3092 enable_input(sd); 3093 3094 if (pdata->hpa_auto) { 3095 /* HPA auto, HPA 0.5s after Edid set and Cable detect */ 3096 hdmi_write(sd, 0x69, 0x5c); 3097 } else { 3098 /* HPA manual */ 3099 hdmi_write(sd, 0x69, 0xa3); 3100 /* HPA disable on port A and B */ 3101 io_write_and_or(sd, 0x20, 0xcf, 0x00); 3102 } 3103 3104 /* LLC */ 3105 io_write(sd, 0x19, 0x80 | pdata->llc_dll_phase); 3106 io_write(sd, 0x33, 0x40); 3107 3108 /* interrupts */ 3109 io_write(sd, 0x40, 0xf2); /* Configure INT1 */ 3110 3111 adv7842_irq_enable(sd, true); 3112 3113 return v4l2_ctrl_handler_setup(sd->ctrl_handler); 3114 } 3115 3116 /* ----------------------------------------------------------------------- */ 3117 3118 static int adv7842_ddr_ram_test(struct v4l2_subdev *sd) 3119 { 3120 /* 3121 * From ADV784x external Memory test.pdf 3122 * 3123 * Reset must just been performed before running test. 3124 * Recommended to reset after test. 3125 */ 3126 int i; 3127 int pass = 0; 3128 int fail = 0; 3129 int complete = 0; 3130 3131 io_write(sd, 0x00, 0x01); /* Program SDP 4x1 */ 3132 io_write(sd, 0x01, 0x00); /* Program SDP mode */ 3133 afe_write(sd, 0x80, 0x92); /* SDP Recommended Write */ 3134 afe_write(sd, 0x9B, 0x01); /* SDP Recommended Write ADV7844ES1 */ 3135 afe_write(sd, 0x9C, 0x60); /* SDP Recommended Write ADV7844ES1 */ 3136 afe_write(sd, 0x9E, 0x02); /* SDP Recommended Write ADV7844ES1 */ 3137 afe_write(sd, 0xA0, 0x0B); /* SDP Recommended Write ADV7844ES1 */ 3138 afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */ 3139 io_write(sd, 0x0C, 0x40); /* Power up ADV7844 */ 3140 io_write(sd, 0x15, 0xBA); /* Enable outputs */ 3141 sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */ 3142 io_write(sd, 0xFF, 0x04); /* Reset memory controller */ 3143 3144 usleep_range(5000, 6000); 3145 3146 sdp_write(sd, 0x12, 0x00); /* Disable 3D Comb, Frame TBC & 3DNR */ 3147 sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */ 3148 sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */ 3149 sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */ 3150 sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */ 3151 sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */ 3152 sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */ 3153 sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */ 3154 sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */ 3155 sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */ 3156 sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */ 3157 3158 usleep_range(5000, 6000); 3159 3160 sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */ 3161 sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */ 3162 3163 msleep(20); 3164 3165 for (i = 0; i < 10; i++) { 3166 u8 result = sdp_io_read(sd, 0xdb); 3167 if (result & 0x10) { 3168 complete++; 3169 if (result & 0x20) 3170 fail++; 3171 else 3172 pass++; 3173 } 3174 msleep(20); 3175 } 3176 3177 v4l2_dbg(1, debug, sd, 3178 "Ram Test: completed %d of %d: pass %d, fail %d\n", 3179 complete, i, pass, fail); 3180 3181 if (!complete || fail) 3182 return -EIO; 3183 return 0; 3184 } 3185 3186 static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd, 3187 struct adv7842_platform_data *pdata) 3188 { 3189 io_write(sd, 0xf1, pdata->i2c_sdp << 1); 3190 io_write(sd, 0xf2, pdata->i2c_sdp_io << 1); 3191 io_write(sd, 0xf3, pdata->i2c_avlink << 1); 3192 io_write(sd, 0xf4, pdata->i2c_cec << 1); 3193 io_write(sd, 0xf5, pdata->i2c_infoframe << 1); 3194 3195 io_write(sd, 0xf8, pdata->i2c_afe << 1); 3196 io_write(sd, 0xf9, pdata->i2c_repeater << 1); 3197 io_write(sd, 0xfa, pdata->i2c_edid << 1); 3198 io_write(sd, 0xfb, pdata->i2c_hdmi << 1); 3199 3200 io_write(sd, 0xfd, pdata->i2c_cp << 1); 3201 io_write(sd, 0xfe, pdata->i2c_vdp << 1); 3202 } 3203 3204 static int adv7842_command_ram_test(struct v4l2_subdev *sd) 3205 { 3206 struct i2c_client *client = v4l2_get_subdevdata(sd); 3207 struct adv7842_state *state = to_state(sd); 3208 struct adv7842_platform_data *pdata = client->dev.platform_data; 3209 struct v4l2_dv_timings timings; 3210 int ret = 0; 3211 3212 if (!pdata) 3213 return -ENODEV; 3214 3215 if (!pdata->sd_ram_size || !pdata->sd_ram_ddr) { 3216 v4l2_info(sd, "no sdram or no ddr sdram\n"); 3217 return -EINVAL; 3218 } 3219 3220 main_reset(sd); 3221 3222 adv7842_rewrite_i2c_addresses(sd, pdata); 3223 3224 /* run ram test */ 3225 ret = adv7842_ddr_ram_test(sd); 3226 3227 main_reset(sd); 3228 3229 adv7842_rewrite_i2c_addresses(sd, pdata); 3230 3231 /* and re-init chip and state */ 3232 adv7842_core_init(sd); 3233 3234 disable_input(sd); 3235 3236 select_input(sd, state->vid_std_select); 3237 3238 enable_input(sd); 3239 3240 edid_write_vga_segment(sd); 3241 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_A); 3242 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_B); 3243 3244 timings = state->timings; 3245 3246 memset(&state->timings, 0, sizeof(struct v4l2_dv_timings)); 3247 3248 adv7842_s_dv_timings(sd, 0, &timings); 3249 3250 return ret; 3251 } 3252 3253 static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) 3254 { 3255 switch (cmd) { 3256 case ADV7842_CMD_RAM_TEST: 3257 return adv7842_command_ram_test(sd); 3258 } 3259 return -ENOTTY; 3260 } 3261 3262 static int adv7842_subscribe_event(struct v4l2_subdev *sd, 3263 struct v4l2_fh *fh, 3264 struct v4l2_event_subscription *sub) 3265 { 3266 switch (sub->type) { 3267 case V4L2_EVENT_SOURCE_CHANGE: 3268 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub); 3269 case V4L2_EVENT_CTRL: 3270 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub); 3271 default: 3272 return -EINVAL; 3273 } 3274 } 3275 3276 static ssize_t 3277 adv7842_debugfs_if_read(u32 type, void *priv, struct file *filp, 3278 char __user *ubuf, size_t count, loff_t *ppos) 3279 { 3280 u8 buf[V4L2_DEBUGFS_IF_MAX_LEN] = {}; 3281 struct v4l2_subdev *sd = priv; 3282 int index; 3283 int len; 3284 3285 if (!is_hdmi(sd)) 3286 return 0; 3287 3288 switch (type) { 3289 case V4L2_DEBUGFS_IF_AVI: 3290 index = 0; 3291 break; 3292 case V4L2_DEBUGFS_IF_AUDIO: 3293 index = 1; 3294 break; 3295 case V4L2_DEBUGFS_IF_SPD: 3296 index = 2; 3297 break; 3298 case V4L2_DEBUGFS_IF_HDMI: 3299 index = 3; 3300 break; 3301 default: 3302 return 0; 3303 } 3304 3305 len = adv7842_read_infoframe_buf(sd, index, buf); 3306 if (len > 0) 3307 len = simple_read_from_buffer(ubuf, count, ppos, buf, len); 3308 return len < 0 ? 0 : len; 3309 } 3310 3311 static int adv7842_registered(struct v4l2_subdev *sd) 3312 { 3313 struct adv7842_state *state = to_state(sd); 3314 struct i2c_client *client = v4l2_get_subdevdata(sd); 3315 int err; 3316 3317 err = cec_register_adapter(state->cec_adap, &client->dev); 3318 if (err) { 3319 cec_delete_adapter(state->cec_adap); 3320 } else { 3321 state->debugfs_dir = debugfs_create_dir(sd->name, v4l2_debugfs_root()); 3322 state->infoframes = v4l2_debugfs_if_alloc(state->debugfs_dir, 3323 V4L2_DEBUGFS_IF_AVI | V4L2_DEBUGFS_IF_AUDIO | 3324 V4L2_DEBUGFS_IF_SPD | V4L2_DEBUGFS_IF_HDMI, sd, 3325 adv7842_debugfs_if_read); 3326 } 3327 return err; 3328 } 3329 3330 static void adv7842_unregistered(struct v4l2_subdev *sd) 3331 { 3332 struct adv7842_state *state = to_state(sd); 3333 3334 cec_unregister_adapter(state->cec_adap); 3335 v4l2_debugfs_if_free(state->infoframes); 3336 state->infoframes = NULL; 3337 debugfs_remove_recursive(state->debugfs_dir); 3338 state->debugfs_dir = NULL; 3339 } 3340 3341 /* ----------------------------------------------------------------------- */ 3342 3343 static const struct v4l2_ctrl_ops adv7842_ctrl_ops = { 3344 .s_ctrl = adv7842_s_ctrl, 3345 .g_volatile_ctrl = adv7842_g_volatile_ctrl, 3346 }; 3347 3348 static const struct v4l2_subdev_core_ops adv7842_core_ops = { 3349 .log_status = adv7842_log_status, 3350 .ioctl = adv7842_ioctl, 3351 .interrupt_service_routine = adv7842_isr, 3352 .subscribe_event = adv7842_subscribe_event, 3353 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 3354 #ifdef CONFIG_VIDEO_ADV_DEBUG 3355 .g_register = adv7842_g_register, 3356 .s_register = adv7842_s_register, 3357 #endif 3358 }; 3359 3360 static const struct v4l2_subdev_video_ops adv7842_video_ops = { 3361 .g_std = adv7842_g_std, 3362 .s_std = adv7842_s_std, 3363 .s_routing = adv7842_s_routing, 3364 .querystd = adv7842_querystd, 3365 .g_input_status = adv7842_g_input_status, 3366 }; 3367 3368 static const struct v4l2_subdev_pad_ops adv7842_pad_ops = { 3369 .enum_mbus_code = adv7842_enum_mbus_code, 3370 .get_fmt = adv7842_get_format, 3371 .set_fmt = adv7842_set_format, 3372 .get_edid = adv7842_get_edid, 3373 .set_edid = adv7842_set_edid, 3374 .s_dv_timings = adv7842_s_dv_timings, 3375 .g_dv_timings = adv7842_g_dv_timings, 3376 .query_dv_timings = adv7842_query_dv_timings, 3377 .enum_dv_timings = adv7842_enum_dv_timings, 3378 .dv_timings_cap = adv7842_dv_timings_cap, 3379 }; 3380 3381 static const struct v4l2_subdev_ops adv7842_ops = { 3382 .core = &adv7842_core_ops, 3383 .video = &adv7842_video_ops, 3384 .pad = &adv7842_pad_ops, 3385 }; 3386 3387 static const struct v4l2_subdev_internal_ops adv7842_int_ops = { 3388 .registered = adv7842_registered, 3389 .unregistered = adv7842_unregistered, 3390 }; 3391 3392 /* -------------------------- custom ctrls ---------------------------------- */ 3393 3394 static const struct v4l2_ctrl_config adv7842_ctrl_analog_sampling_phase = { 3395 .ops = &adv7842_ctrl_ops, 3396 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE, 3397 .name = "Analog Sampling Phase", 3398 .type = V4L2_CTRL_TYPE_INTEGER, 3399 .min = 0, 3400 .max = 0x1f, 3401 .step = 1, 3402 .def = 0, 3403 }; 3404 3405 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color_manual = { 3406 .ops = &adv7842_ctrl_ops, 3407 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL, 3408 .name = "Free Running Color, Manual", 3409 .type = V4L2_CTRL_TYPE_BOOLEAN, 3410 .max = 1, 3411 .step = 1, 3412 .def = 1, 3413 }; 3414 3415 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color = { 3416 .ops = &adv7842_ctrl_ops, 3417 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR, 3418 .name = "Free Running Color", 3419 .type = V4L2_CTRL_TYPE_INTEGER, 3420 .max = 0xffffff, 3421 .step = 0x1, 3422 }; 3423 3424 3425 static void adv7842_unregister_clients(struct v4l2_subdev *sd) 3426 { 3427 struct adv7842_state *state = to_state(sd); 3428 i2c_unregister_device(state->i2c_avlink); 3429 i2c_unregister_device(state->i2c_cec); 3430 i2c_unregister_device(state->i2c_infoframe); 3431 i2c_unregister_device(state->i2c_sdp_io); 3432 i2c_unregister_device(state->i2c_sdp); 3433 i2c_unregister_device(state->i2c_afe); 3434 i2c_unregister_device(state->i2c_repeater); 3435 i2c_unregister_device(state->i2c_edid); 3436 i2c_unregister_device(state->i2c_hdmi); 3437 i2c_unregister_device(state->i2c_cp); 3438 i2c_unregister_device(state->i2c_vdp); 3439 3440 state->i2c_avlink = NULL; 3441 state->i2c_cec = NULL; 3442 state->i2c_infoframe = NULL; 3443 state->i2c_sdp_io = NULL; 3444 state->i2c_sdp = NULL; 3445 state->i2c_afe = NULL; 3446 state->i2c_repeater = NULL; 3447 state->i2c_edid = NULL; 3448 state->i2c_hdmi = NULL; 3449 state->i2c_cp = NULL; 3450 state->i2c_vdp = NULL; 3451 } 3452 3453 static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd, const char *desc, 3454 u8 addr, u8 io_reg) 3455 { 3456 struct i2c_client *client = v4l2_get_subdevdata(sd); 3457 struct i2c_client *cp; 3458 3459 io_write(sd, io_reg, addr << 1); 3460 3461 if (addr == 0) { 3462 v4l2_err(sd, "no %s i2c addr configured\n", desc); 3463 return NULL; 3464 } 3465 3466 cp = i2c_new_dummy_device(client->adapter, io_read(sd, io_reg) >> 1); 3467 if (IS_ERR(cp)) { 3468 v4l2_err(sd, "register %s on i2c addr 0x%x failed with %ld\n", 3469 desc, addr, PTR_ERR(cp)); 3470 cp = NULL; 3471 } 3472 3473 return cp; 3474 } 3475 3476 static int adv7842_register_clients(struct v4l2_subdev *sd) 3477 { 3478 struct adv7842_state *state = to_state(sd); 3479 struct adv7842_platform_data *pdata = &state->pdata; 3480 3481 state->i2c_avlink = adv7842_dummy_client(sd, "avlink", pdata->i2c_avlink, 0xf3); 3482 state->i2c_cec = adv7842_dummy_client(sd, "cec", pdata->i2c_cec, 0xf4); 3483 state->i2c_infoframe = adv7842_dummy_client(sd, "infoframe", pdata->i2c_infoframe, 0xf5); 3484 state->i2c_sdp_io = adv7842_dummy_client(sd, "sdp_io", pdata->i2c_sdp_io, 0xf2); 3485 state->i2c_sdp = adv7842_dummy_client(sd, "sdp", pdata->i2c_sdp, 0xf1); 3486 state->i2c_afe = adv7842_dummy_client(sd, "afe", pdata->i2c_afe, 0xf8); 3487 state->i2c_repeater = adv7842_dummy_client(sd, "repeater", pdata->i2c_repeater, 0xf9); 3488 state->i2c_edid = adv7842_dummy_client(sd, "edid", pdata->i2c_edid, 0xfa); 3489 state->i2c_hdmi = adv7842_dummy_client(sd, "hdmi", pdata->i2c_hdmi, 0xfb); 3490 state->i2c_cp = adv7842_dummy_client(sd, "cp", pdata->i2c_cp, 0xfd); 3491 state->i2c_vdp = adv7842_dummy_client(sd, "vdp", pdata->i2c_vdp, 0xfe); 3492 3493 if (!state->i2c_avlink || 3494 !state->i2c_cec || 3495 !state->i2c_infoframe || 3496 !state->i2c_sdp_io || 3497 !state->i2c_sdp || 3498 !state->i2c_afe || 3499 !state->i2c_repeater || 3500 !state->i2c_edid || 3501 !state->i2c_hdmi || 3502 !state->i2c_cp || 3503 !state->i2c_vdp) 3504 return -1; 3505 3506 return 0; 3507 } 3508 3509 static int adv7842_probe(struct i2c_client *client) 3510 { 3511 struct adv7842_state *state; 3512 static const struct v4l2_dv_timings cea640x480 = 3513 V4L2_DV_BT_CEA_640X480P59_94; 3514 struct adv7842_platform_data *pdata = client->dev.platform_data; 3515 struct v4l2_ctrl_handler *hdl; 3516 struct v4l2_ctrl *ctrl; 3517 struct v4l2_subdev *sd; 3518 unsigned int i; 3519 u16 rev; 3520 int err; 3521 3522 /* Check if the adapter supports the needed features */ 3523 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 3524 return -EIO; 3525 3526 v4l_dbg(1, debug, client, "detecting adv7842 client on address 0x%x\n", 3527 client->addr << 1); 3528 3529 if (!pdata) { 3530 v4l_err(client, "No platform data!\n"); 3531 return -ENODEV; 3532 } 3533 3534 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); 3535 if (!state) 3536 return -ENOMEM; 3537 3538 /* platform data */ 3539 state->pdata = *pdata; 3540 state->timings = cea640x480; 3541 state->format = adv7842_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); 3542 3543 sd = &state->sd; 3544 v4l2_i2c_subdev_init(sd, client, &adv7842_ops); 3545 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; 3546 sd->internal_ops = &adv7842_int_ops; 3547 state->mode = pdata->mode; 3548 3549 state->hdmi_port_a = pdata->input == ADV7842_SELECT_HDMI_PORT_A; 3550 state->restart_stdi_once = true; 3551 3552 /* i2c access to adv7842? */ 3553 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 | 3554 adv_smbus_read_byte_data_check(client, 0xeb, false); 3555 if (rev != 0x2012) { 3556 v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev); 3557 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 | 3558 adv_smbus_read_byte_data_check(client, 0xeb, false); 3559 } 3560 if (rev != 0x2012) { 3561 v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n", 3562 client->addr << 1, rev); 3563 return -ENODEV; 3564 } 3565 3566 if (pdata->chip_reset) 3567 main_reset(sd); 3568 3569 /* control handlers */ 3570 hdl = &state->hdl; 3571 v4l2_ctrl_handler_init(hdl, 6); 3572 3573 /* add in ascending ID order */ 3574 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops, 3575 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0); 3576 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops, 3577 V4L2_CID_CONTRAST, 0, 255, 1, 128); 3578 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops, 3579 V4L2_CID_SATURATION, 0, 255, 1, 128); 3580 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops, 3581 V4L2_CID_HUE, 0, 128, 1, 0); 3582 ctrl = v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops, 3583 V4L2_CID_DV_RX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC, 3584 0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC); 3585 if (ctrl) 3586 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE; 3587 3588 /* custom controls */ 3589 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, 3590 V4L2_CID_DV_RX_POWER_PRESENT, 0, 3, 0, 0); 3591 state->analog_sampling_phase_ctrl = v4l2_ctrl_new_custom(hdl, 3592 &adv7842_ctrl_analog_sampling_phase, NULL); 3593 state->free_run_color_ctrl_manual = v4l2_ctrl_new_custom(hdl, 3594 &adv7842_ctrl_free_run_color_manual, NULL); 3595 state->free_run_color_ctrl = v4l2_ctrl_new_custom(hdl, 3596 &adv7842_ctrl_free_run_color, NULL); 3597 state->rgb_quantization_range_ctrl = 3598 v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops, 3599 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL, 3600 0, V4L2_DV_RGB_RANGE_AUTO); 3601 sd->ctrl_handler = hdl; 3602 if (hdl->error) { 3603 err = hdl->error; 3604 goto err_hdl; 3605 } 3606 if (adv7842_s_detect_tx_5v_ctrl(sd)) { 3607 err = -ENODEV; 3608 goto err_hdl; 3609 } 3610 3611 if (adv7842_register_clients(sd) < 0) { 3612 err = -ENOMEM; 3613 v4l2_err(sd, "failed to create all i2c clients\n"); 3614 goto err_i2c; 3615 } 3616 3617 3618 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, 3619 adv7842_delayed_work_enable_hotplug); 3620 3621 sd->entity.function = MEDIA_ENT_F_DV_DECODER; 3622 for (i = 0; i < ADV7842_PAD_SOURCE; ++i) 3623 state->pads[i].flags = MEDIA_PAD_FL_SINK; 3624 state->pads[ADV7842_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; 3625 err = media_entity_pads_init(&sd->entity, ADV7842_PAD_SOURCE + 1, 3626 state->pads); 3627 if (err) 3628 goto err_work_queues; 3629 3630 err = adv7842_core_init(sd); 3631 if (err) 3632 goto err_entity; 3633 3634 #if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC) 3635 state->cec_adap = cec_allocate_adapter(&adv7842_cec_adap_ops, 3636 state, dev_name(&client->dev), 3637 CEC_CAP_DEFAULTS, ADV7842_MAX_ADDRS); 3638 err = PTR_ERR_OR_ZERO(state->cec_adap); 3639 if (err) 3640 goto err_entity; 3641 #endif 3642 3643 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, 3644 client->addr << 1, client->adapter->name); 3645 return 0; 3646 3647 err_entity: 3648 media_entity_cleanup(&sd->entity); 3649 err_work_queues: 3650 cancel_delayed_work(&state->delayed_work_enable_hotplug); 3651 err_i2c: 3652 adv7842_unregister_clients(sd); 3653 err_hdl: 3654 v4l2_ctrl_handler_free(hdl); 3655 return err; 3656 } 3657 3658 /* ----------------------------------------------------------------------- */ 3659 3660 static void adv7842_remove(struct i2c_client *client) 3661 { 3662 struct v4l2_subdev *sd = i2c_get_clientdata(client); 3663 struct adv7842_state *state = to_state(sd); 3664 3665 adv7842_irq_enable(sd, false); 3666 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); 3667 v4l2_device_unregister_subdev(sd); 3668 media_entity_cleanup(&sd->entity); 3669 adv7842_unregister_clients(sd); 3670 v4l2_ctrl_handler_free(sd->ctrl_handler); 3671 } 3672 3673 /* ----------------------------------------------------------------------- */ 3674 3675 static const struct i2c_device_id adv7842_id[] = { 3676 { "adv7842" }, 3677 { } 3678 }; 3679 MODULE_DEVICE_TABLE(i2c, adv7842_id); 3680 3681 /* ----------------------------------------------------------------------- */ 3682 3683 static struct i2c_driver adv7842_driver = { 3684 .driver = { 3685 .name = "adv7842", 3686 }, 3687 .probe = adv7842_probe, 3688 .remove = adv7842_remove, 3689 .id_table = adv7842_id, 3690 }; 3691 3692 module_i2c_driver(adv7842_driver); 3693