1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * adv7604 - Analog Devices ADV7604 video decoder driver 4 * 5 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved. 6 * 7 */ 8 9 /* 10 * References (c = chapter, p = page): 11 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations, 12 * Revision 2.5, June 2010 13 * REF_02 - Analog devices, Register map documentation, Documentation of 14 * the register maps, Software manual, Rev. F, June 2010 15 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010 16 */ 17 18 #include <linux/delay.h> 19 #include <linux/gpio/consumer.h> 20 #include <linux/hdmi.h> 21 #include <linux/i2c.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/of_graph.h> 25 #include <linux/slab.h> 26 #include <linux/v4l2-dv-timings.h> 27 #include <linux/videodev2.h> 28 #include <linux/workqueue.h> 29 #include <linux/regmap.h> 30 #include <linux/interrupt.h> 31 32 #include <media/i2c/adv7604.h> 33 #include <media/cec.h> 34 #include <media/v4l2-ctrls.h> 35 #include <media/v4l2-device.h> 36 #include <media/v4l2-event.h> 37 #include <media/v4l2-dv-timings.h> 38 #include <media/v4l2-fwnode.h> 39 40 static int debug; 41 module_param(debug, int, 0644); 42 MODULE_PARM_DESC(debug, "debug level (0-2)"); 43 44 MODULE_DESCRIPTION("Analog Devices ADV7604/10/11/12 video decoder driver"); 45 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>"); 46 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>"); 47 MODULE_LICENSE("GPL"); 48 49 /* ADV7604 system clock frequency */ 50 #define ADV76XX_FSC (28636360) 51 52 #define ADV76XX_RGB_OUT (1 << 1) 53 54 #define ADV76XX_OP_FORMAT_SEL_8BIT (0 << 0) 55 #define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0) 56 #define ADV76XX_OP_FORMAT_SEL_12BIT (2 << 0) 57 58 #define ADV76XX_OP_MODE_SEL_SDR_422 (0 << 5) 59 #define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5) 60 #define ADV76XX_OP_MODE_SEL_SDR_444 (2 << 5) 61 #define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5) 62 #define ADV76XX_OP_MODE_SEL_SDR_422_2X (4 << 5) 63 #define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5) 64 65 #define ADV76XX_OP_CH_SEL_GBR (0 << 5) 66 #define ADV76XX_OP_CH_SEL_GRB (1 << 5) 67 #define ADV76XX_OP_CH_SEL_BGR (2 << 5) 68 #define ADV76XX_OP_CH_SEL_RGB (3 << 5) 69 #define ADV76XX_OP_CH_SEL_BRG (4 << 5) 70 #define ADV76XX_OP_CH_SEL_RBG (5 << 5) 71 72 #define ADV76XX_OP_SWAP_CB_CR (1 << 0) 73 74 #define ADV76XX_MAX_ADDRS (3) 75 76 #define ADV76XX_MAX_EDID_BLOCKS 4 77 78 enum adv76xx_type { 79 ADV7604, 80 ADV7611, // including ADV7610 81 ADV7612, 82 }; 83 84 struct adv76xx_reg_seq { 85 unsigned int reg; 86 u8 val; 87 }; 88 89 struct adv76xx_format_info { 90 u32 code; 91 u8 op_ch_sel; 92 bool rgb_out; 93 bool swap_cb_cr; 94 u8 op_format_sel; 95 }; 96 97 struct adv76xx_cfg_read_infoframe { 98 const char *desc; 99 u8 present_mask; 100 u8 head_addr; 101 u8 payload_addr; 102 }; 103 104 struct adv76xx_chip_info { 105 enum adv76xx_type type; 106 107 bool has_afe; 108 unsigned int max_port; 109 unsigned int num_dv_ports; 110 111 unsigned int edid_enable_reg; 112 unsigned int edid_status_reg; 113 unsigned int edid_segment_reg; 114 unsigned int edid_segment_mask; 115 unsigned int edid_spa_loc_reg; 116 unsigned int edid_spa_loc_msb_mask; 117 unsigned int edid_spa_port_b_reg; 118 unsigned int lcf_reg; 119 120 unsigned int cable_det_mask; 121 unsigned int tdms_lock_mask; 122 unsigned int fmt_change_digital_mask; 123 unsigned int cp_csc; 124 125 unsigned int cec_irq_status; 126 unsigned int cec_rx_enable; 127 unsigned int cec_rx_enable_mask; 128 bool cec_irq_swap; 129 130 const struct adv76xx_format_info *formats; 131 unsigned int nformats; 132 133 void (*set_termination)(struct v4l2_subdev *sd, bool enable); 134 void (*setup_irqs)(struct v4l2_subdev *sd); 135 unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd); 136 unsigned int (*read_cable_det)(struct v4l2_subdev *sd); 137 138 /* 0 = AFE, 1 = HDMI */ 139 const struct adv76xx_reg_seq *recommended_settings[2]; 140 unsigned int num_recommended_settings[2]; 141 142 unsigned long page_mask; 143 144 /* Masks for timings */ 145 unsigned int linewidth_mask; 146 unsigned int field0_height_mask; 147 unsigned int field1_height_mask; 148 unsigned int hfrontporch_mask; 149 unsigned int hsync_mask; 150 unsigned int hbackporch_mask; 151 unsigned int field0_vfrontporch_mask; 152 unsigned int field1_vfrontporch_mask; 153 unsigned int field0_vsync_mask; 154 unsigned int field1_vsync_mask; 155 unsigned int field0_vbackporch_mask; 156 unsigned int field1_vbackporch_mask; 157 }; 158 159 /* 160 ********************************************************************** 161 * 162 * Arrays with configuration parameters for the ADV7604 163 * 164 ********************************************************************** 165 */ 166 167 struct adv76xx_state { 168 const struct adv76xx_chip_info *info; 169 struct adv76xx_platform_data pdata; 170 171 struct gpio_desc *hpd_gpio[4]; 172 struct gpio_desc *reset_gpio; 173 174 struct v4l2_subdev sd; 175 struct media_pad pads[ADV76XX_PAD_MAX]; 176 unsigned int source_pad; 177 178 struct v4l2_ctrl_handler hdl; 179 180 enum adv76xx_pad selected_input; 181 182 struct v4l2_dv_timings timings; 183 const struct adv76xx_format_info *format; 184 185 struct { 186 u8 edid[ADV76XX_MAX_EDID_BLOCKS * 128]; 187 u32 present; 188 unsigned blocks; 189 } edid; 190 u16 spa_port_a[2]; 191 struct v4l2_fract aspect_ratio; 192 u32 rgb_quantization_range; 193 struct delayed_work delayed_work_enable_hotplug; 194 bool restart_stdi_once; 195 196 struct dentry *debugfs_dir; 197 struct v4l2_debugfs_if *infoframes; 198 199 /* CEC */ 200 struct cec_adapter *cec_adap; 201 u8 cec_addr[ADV76XX_MAX_ADDRS]; 202 u8 cec_valid_addrs; 203 bool cec_enabled_adap; 204 205 /* i2c clients */ 206 struct i2c_client *i2c_clients[ADV76XX_PAGE_MAX]; 207 208 /* Regmaps */ 209 struct regmap *regmap[ADV76XX_PAGE_MAX]; 210 211 /* controls */ 212 struct v4l2_ctrl *detect_tx_5v_ctrl; 213 struct v4l2_ctrl *analog_sampling_phase_ctrl; 214 struct v4l2_ctrl *free_run_color_manual_ctrl; 215 struct v4l2_ctrl *free_run_color_ctrl; 216 struct v4l2_ctrl *rgb_quantization_range_ctrl; 217 }; 218 219 static bool adv76xx_has_afe(struct adv76xx_state *state) 220 { 221 return state->info->has_afe; 222 } 223 224 /* Unsupported timings. This device cannot support 720p30. */ 225 static const struct v4l2_dv_timings adv76xx_timings_exceptions[] = { 226 V4L2_DV_BT_CEA_1280X720P30, 227 { } 228 }; 229 230 static bool adv76xx_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl) 231 { 232 int i; 233 234 for (i = 0; adv76xx_timings_exceptions[i].bt.width; i++) 235 if (v4l2_match_dv_timings(t, adv76xx_timings_exceptions + i, 0, false)) 236 return false; 237 return true; 238 } 239 240 struct adv76xx_video_standards { 241 struct v4l2_dv_timings timings; 242 u8 vid_std; 243 u8 v_freq; 244 }; 245 246 /* sorted by number of lines */ 247 static const struct adv76xx_video_standards adv7604_prim_mode_comp[] = { 248 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */ 249 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 250 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 }, 251 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 }, 252 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 253 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 254 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 255 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 256 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 257 /* TODO add 1920x1080P60_RB (CVT timing) */ 258 { }, 259 }; 260 261 /* sorted by number of lines */ 262 static const struct adv76xx_video_standards adv7604_prim_mode_gr[] = { 263 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 264 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 265 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 266 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 267 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 268 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 269 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 270 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 271 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 272 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 273 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 274 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 275 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 276 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 277 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 278 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 }, 279 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 }, 280 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 }, 281 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 }, 282 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */ 283 /* TODO add 1600X1200P60_RB (not a DMT timing) */ 284 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 }, 285 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */ 286 { }, 287 }; 288 289 /* sorted by number of lines */ 290 static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_comp[] = { 291 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, 292 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 293 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 }, 294 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 }, 295 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 296 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 297 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 298 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 299 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 300 { }, 301 }; 302 303 /* sorted by number of lines */ 304 static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_gr[] = { 305 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 306 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 307 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 308 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 309 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 310 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 311 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 312 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 313 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 314 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 315 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 316 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 317 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 318 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 319 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 320 { }, 321 }; 322 323 static const struct v4l2_event adv76xx_ev_fmt = { 324 .type = V4L2_EVENT_SOURCE_CHANGE, 325 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, 326 }; 327 328 /* ----------------------------------------------------------------------- */ 329 330 static inline struct adv76xx_state *to_state(struct v4l2_subdev *sd) 331 { 332 return container_of(sd, struct adv76xx_state, sd); 333 } 334 335 static inline unsigned htotal(const struct v4l2_bt_timings *t) 336 { 337 return V4L2_DV_BT_FRAME_WIDTH(t); 338 } 339 340 static inline unsigned vtotal(const struct v4l2_bt_timings *t) 341 { 342 return V4L2_DV_BT_FRAME_HEIGHT(t); 343 } 344 345 /* ----------------------------------------------------------------------- */ 346 347 static int adv76xx_read_check(struct adv76xx_state *state, 348 int client_page, u8 reg) 349 { 350 struct i2c_client *client = state->i2c_clients[client_page]; 351 int err; 352 unsigned int val; 353 354 err = regmap_read(state->regmap[client_page], reg, &val); 355 356 if (err) { 357 v4l_err(client, "error reading %02x, %02x\n", 358 client->addr, reg); 359 return err; 360 } 361 return val; 362 } 363 364 /* adv76xx_write_block(): Write raw data with a maximum of I2C_SMBUS_BLOCK_MAX 365 * size to one or more registers. 366 * 367 * A value of zero will be returned on success, a negative errno will 368 * be returned in error cases. 369 */ 370 static int adv76xx_write_block(struct adv76xx_state *state, int client_page, 371 unsigned int init_reg, const void *val, 372 size_t val_len) 373 { 374 struct regmap *regmap = state->regmap[client_page]; 375 376 if (val_len > I2C_SMBUS_BLOCK_MAX) 377 val_len = I2C_SMBUS_BLOCK_MAX; 378 379 return regmap_raw_write(regmap, init_reg, val, val_len); 380 } 381 382 /* ----------------------------------------------------------------------- */ 383 384 static inline int io_read(struct v4l2_subdev *sd, u8 reg) 385 { 386 struct adv76xx_state *state = to_state(sd); 387 388 return adv76xx_read_check(state, ADV76XX_PAGE_IO, reg); 389 } 390 391 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) 392 { 393 struct adv76xx_state *state = to_state(sd); 394 395 return regmap_write(state->regmap[ADV76XX_PAGE_IO], reg, val); 396 } 397 398 static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, 399 u8 val) 400 { 401 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val); 402 } 403 404 static inline int __always_unused avlink_read(struct v4l2_subdev *sd, u8 reg) 405 { 406 struct adv76xx_state *state = to_state(sd); 407 408 return adv76xx_read_check(state, ADV7604_PAGE_AVLINK, reg); 409 } 410 411 static inline int __always_unused avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) 412 { 413 struct adv76xx_state *state = to_state(sd); 414 415 return regmap_write(state->regmap[ADV7604_PAGE_AVLINK], reg, val); 416 } 417 418 static inline int cec_read(struct v4l2_subdev *sd, u8 reg) 419 { 420 struct adv76xx_state *state = to_state(sd); 421 422 return adv76xx_read_check(state, ADV76XX_PAGE_CEC, reg); 423 } 424 425 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) 426 { 427 struct adv76xx_state *state = to_state(sd); 428 429 return regmap_write(state->regmap[ADV76XX_PAGE_CEC], reg, val); 430 } 431 432 static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, 433 u8 val) 434 { 435 return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val); 436 } 437 438 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg) 439 { 440 struct adv76xx_state *state = to_state(sd); 441 442 return adv76xx_read_check(state, ADV76XX_PAGE_INFOFRAME, reg); 443 } 444 445 static inline int __always_unused infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 446 { 447 struct adv76xx_state *state = to_state(sd); 448 449 return regmap_write(state->regmap[ADV76XX_PAGE_INFOFRAME], reg, val); 450 } 451 452 static inline int __always_unused afe_read(struct v4l2_subdev *sd, u8 reg) 453 { 454 struct adv76xx_state *state = to_state(sd); 455 456 return adv76xx_read_check(state, ADV76XX_PAGE_AFE, reg); 457 } 458 459 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 460 { 461 struct adv76xx_state *state = to_state(sd); 462 463 return regmap_write(state->regmap[ADV76XX_PAGE_AFE], reg, val); 464 } 465 466 static inline int rep_read(struct v4l2_subdev *sd, u8 reg) 467 { 468 struct adv76xx_state *state = to_state(sd); 469 470 return adv76xx_read_check(state, ADV76XX_PAGE_REP, reg); 471 } 472 473 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) 474 { 475 struct adv76xx_state *state = to_state(sd); 476 477 return regmap_write(state->regmap[ADV76XX_PAGE_REP], reg, val); 478 } 479 480 static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 481 { 482 return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val); 483 } 484 485 static inline int __always_unused edid_read(struct v4l2_subdev *sd, u8 reg) 486 { 487 struct adv76xx_state *state = to_state(sd); 488 489 return adv76xx_read_check(state, ADV76XX_PAGE_EDID, reg); 490 } 491 492 static inline int __always_unused edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) 493 { 494 struct adv76xx_state *state = to_state(sd); 495 496 return regmap_write(state->regmap[ADV76XX_PAGE_EDID], reg, val); 497 } 498 499 static inline int edid_write_block(struct v4l2_subdev *sd, 500 unsigned int total_len, const u8 *val) 501 { 502 struct adv76xx_state *state = to_state(sd); 503 int err = 0; 504 int i = 0; 505 int len = 0; 506 507 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", 508 __func__, total_len); 509 510 while (!err && i < total_len) { 511 len = (total_len - i) > I2C_SMBUS_BLOCK_MAX ? 512 I2C_SMBUS_BLOCK_MAX : 513 (total_len - i); 514 515 err = adv76xx_write_block(state, ADV76XX_PAGE_EDID, 516 i, val + i, len); 517 i += len; 518 } 519 520 return err; 521 } 522 523 static void adv76xx_set_hpd(struct adv76xx_state *state, unsigned int hpd) 524 { 525 const struct adv76xx_chip_info *info = state->info; 526 unsigned int i; 527 528 if (info->type == ADV7604) { 529 for (i = 0; i < state->info->num_dv_ports; ++i) 530 gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i)); 531 } else { 532 for (i = 0; i < state->info->num_dv_ports; ++i) 533 io_write_clr_set(&state->sd, 0x20, 0x80 >> i, 534 (!!(hpd & BIT(i))) << (7 - i)); 535 } 536 537 v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd); 538 } 539 540 static void adv76xx_delayed_work_enable_hotplug(struct work_struct *work) 541 { 542 struct delayed_work *dwork = to_delayed_work(work); 543 struct adv76xx_state *state = container_of(dwork, struct adv76xx_state, 544 delayed_work_enable_hotplug); 545 struct v4l2_subdev *sd = &state->sd; 546 547 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__); 548 549 adv76xx_set_hpd(state, state->edid.present); 550 } 551 552 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) 553 { 554 struct adv76xx_state *state = to_state(sd); 555 556 return adv76xx_read_check(state, ADV76XX_PAGE_HDMI, reg); 557 } 558 559 static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) 560 { 561 return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask; 562 } 563 564 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) 565 { 566 struct adv76xx_state *state = to_state(sd); 567 568 return regmap_write(state->regmap[ADV76XX_PAGE_HDMI], reg, val); 569 } 570 571 static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 572 { 573 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val); 574 } 575 576 static inline int __always_unused test_write(struct v4l2_subdev *sd, u8 reg, u8 val) 577 { 578 struct adv76xx_state *state = to_state(sd); 579 580 return regmap_write(state->regmap[ADV76XX_PAGE_TEST], reg, val); 581 } 582 583 static inline int cp_read(struct v4l2_subdev *sd, u8 reg) 584 { 585 struct adv76xx_state *state = to_state(sd); 586 587 return adv76xx_read_check(state, ADV76XX_PAGE_CP, reg); 588 } 589 590 static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) 591 { 592 return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask; 593 } 594 595 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 596 { 597 struct adv76xx_state *state = to_state(sd); 598 599 return regmap_write(state->regmap[ADV76XX_PAGE_CP], reg, val); 600 } 601 602 static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 603 { 604 return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val); 605 } 606 607 static inline int __always_unused vdp_read(struct v4l2_subdev *sd, u8 reg) 608 { 609 struct adv76xx_state *state = to_state(sd); 610 611 return adv76xx_read_check(state, ADV7604_PAGE_VDP, reg); 612 } 613 614 static inline int __always_unused vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 615 { 616 struct adv76xx_state *state = to_state(sd); 617 618 return regmap_write(state->regmap[ADV7604_PAGE_VDP], reg, val); 619 } 620 621 #define ADV76XX_REG(page, offset) (((page) << 8) | (offset)) 622 #define ADV76XX_REG_SEQ_TERM 0xffff 623 624 #ifdef CONFIG_VIDEO_ADV_DEBUG 625 static int adv76xx_read_reg(struct v4l2_subdev *sd, unsigned int reg) 626 { 627 struct adv76xx_state *state = to_state(sd); 628 unsigned int page = reg >> 8; 629 unsigned int val; 630 int err; 631 632 if (page >= ADV76XX_PAGE_MAX || !(BIT(page) & state->info->page_mask)) 633 return -EINVAL; 634 635 reg &= 0xff; 636 err = regmap_read(state->regmap[page], reg, &val); 637 638 return err ? err : val; 639 } 640 #endif 641 642 static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val) 643 { 644 struct adv76xx_state *state = to_state(sd); 645 unsigned int page = reg >> 8; 646 647 if (page >= ADV76XX_PAGE_MAX || !(BIT(page) & state->info->page_mask)) 648 return -EINVAL; 649 650 reg &= 0xff; 651 652 return regmap_write(state->regmap[page], reg, val); 653 } 654 655 static void adv76xx_write_reg_seq(struct v4l2_subdev *sd, 656 const struct adv76xx_reg_seq *reg_seq) 657 { 658 unsigned int i; 659 660 for (i = 0; reg_seq[i].reg != ADV76XX_REG_SEQ_TERM; i++) 661 adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val); 662 } 663 664 /* ----------------------------------------------------------------------------- 665 * Format helpers 666 */ 667 668 static const struct adv76xx_format_info adv7604_formats[] = { 669 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false, 670 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT }, 671 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false, 672 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 673 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true, 674 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 675 { MEDIA_BUS_FMT_YUYV10_2X10, ADV76XX_OP_CH_SEL_RGB, false, false, 676 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, 677 { MEDIA_BUS_FMT_YVYU10_2X10, ADV76XX_OP_CH_SEL_RGB, false, true, 678 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, 679 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false, 680 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, 681 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true, 682 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, 683 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false, 684 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 685 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true, 686 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 687 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false, 688 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 689 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true, 690 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 691 { MEDIA_BUS_FMT_UYVY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, false, 692 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 693 { MEDIA_BUS_FMT_VYUY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, true, 694 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 695 { MEDIA_BUS_FMT_YUYV10_1X20, ADV76XX_OP_CH_SEL_RGB, false, false, 696 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 697 { MEDIA_BUS_FMT_YVYU10_1X20, ADV76XX_OP_CH_SEL_RGB, false, true, 698 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 699 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false, 700 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 701 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true, 702 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 703 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false, 704 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 705 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true, 706 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 707 }; 708 709 static const struct adv76xx_format_info adv7611_formats[] = { 710 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false, 711 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT }, 712 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false, 713 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 714 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true, 715 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 716 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false, 717 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, 718 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true, 719 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, 720 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false, 721 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 722 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true, 723 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 724 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false, 725 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 726 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true, 727 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 728 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false, 729 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 730 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true, 731 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 732 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false, 733 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 734 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true, 735 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 736 }; 737 738 static const struct adv76xx_format_info adv7612_formats[] = { 739 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false, 740 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT }, 741 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false, 742 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 743 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true, 744 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 745 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false, 746 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 747 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true, 748 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 749 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false, 750 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 751 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true, 752 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 753 }; 754 755 static const struct adv76xx_format_info * 756 adv76xx_format_info(struct adv76xx_state *state, u32 code) 757 { 758 unsigned int i; 759 760 for (i = 0; i < state->info->nformats; ++i) { 761 if (state->info->formats[i].code == code) 762 return &state->info->formats[i]; 763 } 764 765 return NULL; 766 } 767 768 /* ----------------------------------------------------------------------- */ 769 770 static inline bool is_analog_input(struct v4l2_subdev *sd) 771 { 772 struct adv76xx_state *state = to_state(sd); 773 774 return state->selected_input == ADV7604_PAD_VGA_RGB || 775 state->selected_input == ADV7604_PAD_VGA_COMP; 776 } 777 778 static inline bool is_digital_input(struct v4l2_subdev *sd) 779 { 780 struct adv76xx_state *state = to_state(sd); 781 782 return state->selected_input == ADV76XX_PAD_HDMI_PORT_A || 783 state->selected_input == ADV7604_PAD_HDMI_PORT_B || 784 state->selected_input == ADV7604_PAD_HDMI_PORT_C || 785 state->selected_input == ADV7604_PAD_HDMI_PORT_D; 786 } 787 788 static const struct v4l2_dv_timings_cap adv7604_timings_cap_analog = { 789 .type = V4L2_DV_BT_656_1120, 790 /* keep this initialization for compatibility with GCC < 4.4.6 */ 791 .reserved = { 0 }, 792 V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 170000000, 793 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 794 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, 795 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING | 796 V4L2_DV_BT_CAP_CUSTOM) 797 }; 798 799 static const struct v4l2_dv_timings_cap adv76xx_timings_cap_digital = { 800 .type = V4L2_DV_BT_656_1120, 801 /* keep this initialization for compatibility with GCC < 4.4.6 */ 802 .reserved = { 0 }, 803 V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 225000000, 804 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 805 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, 806 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING | 807 V4L2_DV_BT_CAP_CUSTOM) 808 }; 809 810 /* 811 * Return the DV timings capabilities for the requested sink pad. As a special 812 * case, pad value -1 returns the capabilities for the currently selected input. 813 */ 814 static const struct v4l2_dv_timings_cap * 815 adv76xx_get_dv_timings_cap(struct v4l2_subdev *sd, int pad) 816 { 817 if (pad == -1) { 818 struct adv76xx_state *state = to_state(sd); 819 820 pad = state->selected_input; 821 } 822 823 switch (pad) { 824 case ADV76XX_PAD_HDMI_PORT_A: 825 case ADV7604_PAD_HDMI_PORT_B: 826 case ADV7604_PAD_HDMI_PORT_C: 827 case ADV7604_PAD_HDMI_PORT_D: 828 return &adv76xx_timings_cap_digital; 829 830 case ADV7604_PAD_VGA_RGB: 831 case ADV7604_PAD_VGA_COMP: 832 default: 833 return &adv7604_timings_cap_analog; 834 } 835 } 836 837 838 /* ----------------------------------------------------------------------- */ 839 840 #ifdef CONFIG_VIDEO_ADV_DEBUG 841 static void adv76xx_inv_register(struct v4l2_subdev *sd) 842 { 843 v4l2_info(sd, "0x000-0x0ff: IO Map\n"); 844 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n"); 845 v4l2_info(sd, "0x200-0x2ff: CEC Map\n"); 846 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n"); 847 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n"); 848 v4l2_info(sd, "0x500-0x5ff: DPP Map\n"); 849 v4l2_info(sd, "0x600-0x6ff: AFE Map\n"); 850 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n"); 851 v4l2_info(sd, "0x800-0x8ff: EDID Map\n"); 852 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n"); 853 v4l2_info(sd, "0xa00-0xaff: Test Map\n"); 854 v4l2_info(sd, "0xb00-0xbff: CP Map\n"); 855 v4l2_info(sd, "0xc00-0xcff: VDP Map\n"); 856 } 857 858 static int adv76xx_g_register(struct v4l2_subdev *sd, 859 struct v4l2_dbg_register *reg) 860 { 861 int ret; 862 863 ret = adv76xx_read_reg(sd, reg->reg); 864 if (ret < 0) { 865 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 866 adv76xx_inv_register(sd); 867 return ret; 868 } 869 870 reg->size = 1; 871 reg->val = ret; 872 873 return 0; 874 } 875 876 static int adv76xx_s_register(struct v4l2_subdev *sd, 877 const struct v4l2_dbg_register *reg) 878 { 879 int ret; 880 881 ret = adv76xx_write_reg(sd, reg->reg, reg->val); 882 if (ret < 0) { 883 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 884 adv76xx_inv_register(sd); 885 return ret; 886 } 887 888 return 0; 889 } 890 #endif 891 892 static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd) 893 { 894 u8 value = io_read(sd, 0x6f); 895 896 return ((value & 0x10) >> 4) 897 | ((value & 0x08) >> 2) 898 | ((value & 0x04) << 0) 899 | ((value & 0x02) << 2); 900 } 901 902 static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd) 903 { 904 u8 value = io_read(sd, 0x6f); 905 906 return value & 1; 907 } 908 909 static unsigned int adv7612_read_cable_det(struct v4l2_subdev *sd) 910 { 911 /* Reads CABLE_DET_A_RAW. For input B support, need to 912 * account for bit 7 [MSB] of 0x6a (ie. CABLE_DET_B_RAW) 913 */ 914 u8 value = io_read(sd, 0x6f); 915 916 return value & 1; 917 } 918 919 static int adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd) 920 { 921 struct adv76xx_state *state = to_state(sd); 922 const struct adv76xx_chip_info *info = state->info; 923 u16 cable_det = info->read_cable_det(sd); 924 925 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, cable_det); 926 } 927 928 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd, 929 u8 prim_mode, 930 const struct adv76xx_video_standards *predef_vid_timings, 931 const struct v4l2_dv_timings *timings) 932 { 933 int i; 934 935 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) { 936 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings, 937 is_digital_input(sd) ? 250000 : 1000000, false)) 938 continue; 939 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */ 940 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + 941 prim_mode); /* v_freq and prim mode */ 942 return 0; 943 } 944 945 return -1; 946 } 947 948 static int configure_predefined_video_timings(struct v4l2_subdev *sd, 949 struct v4l2_dv_timings *timings) 950 { 951 struct adv76xx_state *state = to_state(sd); 952 int err; 953 954 v4l2_dbg(1, debug, sd, "%s", __func__); 955 956 if (adv76xx_has_afe(state)) { 957 /* reset to default values */ 958 io_write(sd, 0x16, 0x43); 959 io_write(sd, 0x17, 0x5a); 960 } 961 /* disable embedded syncs for auto graphics mode */ 962 cp_write_clr_set(sd, 0x81, 0x10, 0x00); 963 cp_write(sd, 0x8f, 0x00); 964 cp_write(sd, 0x90, 0x00); 965 cp_write(sd, 0xa2, 0x00); 966 cp_write(sd, 0xa3, 0x00); 967 cp_write(sd, 0xa4, 0x00); 968 cp_write(sd, 0xa5, 0x00); 969 cp_write(sd, 0xa6, 0x00); 970 cp_write(sd, 0xa7, 0x00); 971 cp_write(sd, 0xab, 0x00); 972 cp_write(sd, 0xac, 0x00); 973 974 if (is_analog_input(sd)) { 975 err = find_and_set_predefined_video_timings(sd, 976 0x01, adv7604_prim_mode_comp, timings); 977 if (err) 978 err = find_and_set_predefined_video_timings(sd, 979 0x02, adv7604_prim_mode_gr, timings); 980 } else if (is_digital_input(sd)) { 981 err = find_and_set_predefined_video_timings(sd, 982 0x05, adv76xx_prim_mode_hdmi_comp, timings); 983 if (err) 984 err = find_and_set_predefined_video_timings(sd, 985 0x06, adv76xx_prim_mode_hdmi_gr, timings); 986 } else { 987 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 988 __func__, state->selected_input); 989 err = -1; 990 } 991 992 993 return err; 994 } 995 996 static void configure_custom_video_timings(struct v4l2_subdev *sd, 997 const struct v4l2_bt_timings *bt) 998 { 999 struct adv76xx_state *state = to_state(sd); 1000 u32 width = htotal(bt); 1001 u32 height = vtotal(bt); 1002 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4; 1003 u16 cp_start_eav = width - bt->hfrontporch; 1004 u16 cp_start_vbi = height - bt->vfrontporch; 1005 u16 cp_end_vbi = bt->vsync + bt->vbackporch; 1006 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ? 1007 ((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0; 1008 const u8 pll[2] = { 1009 0xc0 | ((width >> 8) & 0x1f), 1010 width & 0xff 1011 }; 1012 1013 v4l2_dbg(2, debug, sd, "%s\n", __func__); 1014 1015 if (is_analog_input(sd)) { 1016 /* auto graphics */ 1017 io_write(sd, 0x00, 0x07); /* video std */ 1018 io_write(sd, 0x01, 0x02); /* prim mode */ 1019 /* enable embedded syncs for auto graphics mode */ 1020 cp_write_clr_set(sd, 0x81, 0x10, 0x10); 1021 1022 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */ 1023 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */ 1024 /* IO-map reg. 0x16 and 0x17 should be written in sequence */ 1025 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_IO], 1026 0x16, pll, 2)) 1027 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n"); 1028 1029 /* active video - horizontal timing */ 1030 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff); 1031 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) | 1032 ((cp_start_eav >> 8) & 0x0f)); 1033 cp_write(sd, 0xa4, cp_start_eav & 0xff); 1034 1035 /* active video - vertical timing */ 1036 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff); 1037 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) | 1038 ((cp_end_vbi >> 8) & 0xf)); 1039 cp_write(sd, 0xa7, cp_end_vbi & 0xff); 1040 } else if (is_digital_input(sd)) { 1041 /* set default prim_mode/vid_std for HDMI 1042 according to [REF_03, c. 4.2] */ 1043 io_write(sd, 0x00, 0x02); /* video std */ 1044 io_write(sd, 0x01, 0x06); /* prim mode */ 1045 } else { 1046 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 1047 __func__, state->selected_input); 1048 } 1049 1050 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7); 1051 cp_write(sd, 0x90, ch1_fr_ll & 0xff); 1052 cp_write(sd, 0xab, (height >> 4) & 0xff); 1053 cp_write(sd, 0xac, (height & 0x0f) << 4); 1054 } 1055 1056 static void adv76xx_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c) 1057 { 1058 struct adv76xx_state *state = to_state(sd); 1059 u8 offset_buf[4]; 1060 1061 if (auto_offset) { 1062 offset_a = 0x3ff; 1063 offset_b = 0x3ff; 1064 offset_c = 0x3ff; 1065 } 1066 1067 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n", 1068 __func__, auto_offset ? "Auto" : "Manual", 1069 offset_a, offset_b, offset_c); 1070 1071 offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4); 1072 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6); 1073 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8); 1074 offset_buf[3] = offset_c & 0x0ff; 1075 1076 /* Registers must be written in this order with no i2c access in between */ 1077 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP], 1078 0x77, offset_buf, 4)) 1079 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__); 1080 } 1081 1082 static void adv76xx_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c) 1083 { 1084 struct adv76xx_state *state = to_state(sd); 1085 u8 gain_buf[4]; 1086 u8 gain_man = 1; 1087 u8 agc_mode_man = 1; 1088 1089 if (auto_gain) { 1090 gain_man = 0; 1091 agc_mode_man = 0; 1092 gain_a = 0x100; 1093 gain_b = 0x100; 1094 gain_c = 0x100; 1095 } 1096 1097 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n", 1098 __func__, auto_gain ? "Auto" : "Manual", 1099 gain_a, gain_b, gain_c); 1100 1101 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4)); 1102 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6)); 1103 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8)); 1104 gain_buf[3] = ((gain_c & 0x0ff)); 1105 1106 /* Registers must be written in this order with no i2c access in between */ 1107 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP], 1108 0x73, gain_buf, 4)) 1109 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__); 1110 } 1111 1112 static void set_rgb_quantization_range(struct v4l2_subdev *sd) 1113 { 1114 struct adv76xx_state *state = to_state(sd); 1115 bool rgb_output = io_read(sd, 0x02) & 0x02; 1116 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; 1117 u8 y = HDMI_COLORSPACE_RGB; 1118 1119 if (hdmi_signal && (io_read(sd, 0x60) & 1)) 1120 y = infoframe_read(sd, 0x01) >> 5; 1121 1122 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n", 1123 __func__, state->rgb_quantization_range, 1124 rgb_output, hdmi_signal); 1125 1126 adv76xx_set_gain(sd, true, 0x0, 0x0, 0x0); 1127 adv76xx_set_offset(sd, true, 0x0, 0x0, 0x0); 1128 io_write_clr_set(sd, 0x02, 0x04, rgb_output ? 0 : 4); 1129 1130 switch (state->rgb_quantization_range) { 1131 case V4L2_DV_RGB_RANGE_AUTO: 1132 if (state->selected_input == ADV7604_PAD_VGA_RGB) { 1133 /* Receiving analog RGB signal 1134 * Set RGB full range (0-255) */ 1135 io_write_clr_set(sd, 0x02, 0xf0, 0x10); 1136 break; 1137 } 1138 1139 if (state->selected_input == ADV7604_PAD_VGA_COMP) { 1140 /* Receiving analog YPbPr signal 1141 * Set automode */ 1142 io_write_clr_set(sd, 0x02, 0xf0, 0xf0); 1143 break; 1144 } 1145 1146 if (hdmi_signal) { 1147 /* Receiving HDMI signal 1148 * Set automode */ 1149 io_write_clr_set(sd, 0x02, 0xf0, 0xf0); 1150 break; 1151 } 1152 1153 /* Receiving DVI-D signal 1154 * ADV7604 selects RGB limited range regardless of 1155 * input format (CE/IT) in automatic mode */ 1156 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) { 1157 /* RGB limited range (16-235) */ 1158 io_write_clr_set(sd, 0x02, 0xf0, 0x00); 1159 } else { 1160 /* RGB full range (0-255) */ 1161 io_write_clr_set(sd, 0x02, 0xf0, 0x10); 1162 1163 if (is_digital_input(sd) && rgb_output) { 1164 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40); 1165 } else { 1166 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 1167 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70); 1168 } 1169 } 1170 break; 1171 case V4L2_DV_RGB_RANGE_LIMITED: 1172 if (state->selected_input == ADV7604_PAD_VGA_COMP) { 1173 /* YCrCb limited range (16-235) */ 1174 io_write_clr_set(sd, 0x02, 0xf0, 0x20); 1175 break; 1176 } 1177 1178 if (y != HDMI_COLORSPACE_RGB) 1179 break; 1180 1181 /* RGB limited range (16-235) */ 1182 io_write_clr_set(sd, 0x02, 0xf0, 0x00); 1183 1184 break; 1185 case V4L2_DV_RGB_RANGE_FULL: 1186 if (state->selected_input == ADV7604_PAD_VGA_COMP) { 1187 /* YCrCb full range (0-255) */ 1188 io_write_clr_set(sd, 0x02, 0xf0, 0x60); 1189 break; 1190 } 1191 1192 if (y != HDMI_COLORSPACE_RGB) 1193 break; 1194 1195 /* RGB full range (0-255) */ 1196 io_write_clr_set(sd, 0x02, 0xf0, 0x10); 1197 1198 if (is_analog_input(sd) || hdmi_signal) 1199 break; 1200 1201 /* Adjust gain/offset for DVI-D signals only */ 1202 if (rgb_output) { 1203 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40); 1204 } else { 1205 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 1206 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70); 1207 } 1208 break; 1209 } 1210 } 1211 1212 static int adv76xx_s_ctrl(struct v4l2_ctrl *ctrl) 1213 { 1214 struct v4l2_subdev *sd = 1215 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd; 1216 1217 struct adv76xx_state *state = to_state(sd); 1218 1219 switch (ctrl->id) { 1220 case V4L2_CID_BRIGHTNESS: 1221 cp_write(sd, 0x3c, ctrl->val); 1222 return 0; 1223 case V4L2_CID_CONTRAST: 1224 cp_write(sd, 0x3a, ctrl->val); 1225 return 0; 1226 case V4L2_CID_SATURATION: 1227 cp_write(sd, 0x3b, ctrl->val); 1228 return 0; 1229 case V4L2_CID_HUE: 1230 cp_write(sd, 0x3d, ctrl->val); 1231 return 0; 1232 case V4L2_CID_DV_RX_RGB_RANGE: 1233 state->rgb_quantization_range = ctrl->val; 1234 set_rgb_quantization_range(sd); 1235 return 0; 1236 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE: 1237 if (!adv76xx_has_afe(state)) 1238 return -EINVAL; 1239 /* Set the analog sampling phase. This is needed to find the 1240 best sampling phase for analog video: an application or 1241 driver has to try a number of phases and analyze the picture 1242 quality before settling on the best performing phase. */ 1243 afe_write(sd, 0xc8, ctrl->val); 1244 return 0; 1245 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL: 1246 /* Use the default blue color for free running mode, 1247 or supply your own. */ 1248 cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2); 1249 return 0; 1250 case V4L2_CID_ADV_RX_FREE_RUN_COLOR: 1251 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16); 1252 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8); 1253 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff)); 1254 return 0; 1255 } 1256 return -EINVAL; 1257 } 1258 1259 static int adv76xx_g_volatile_ctrl(struct v4l2_ctrl *ctrl) 1260 { 1261 struct v4l2_subdev *sd = 1262 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd; 1263 1264 if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) { 1265 ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC; 1266 if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80)) 1267 ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3; 1268 return 0; 1269 } 1270 return -EINVAL; 1271 } 1272 1273 /* ----------------------------------------------------------------------- */ 1274 1275 static inline bool no_power(struct v4l2_subdev *sd) 1276 { 1277 /* Entire chip or CP powered off */ 1278 return io_read(sd, 0x0c) & 0x24; 1279 } 1280 1281 static inline bool no_signal_tmds(struct v4l2_subdev *sd) 1282 { 1283 struct adv76xx_state *state = to_state(sd); 1284 1285 return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input)); 1286 } 1287 1288 static inline bool no_lock_tmds(struct v4l2_subdev *sd) 1289 { 1290 struct adv76xx_state *state = to_state(sd); 1291 const struct adv76xx_chip_info *info = state->info; 1292 1293 return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask; 1294 } 1295 1296 static inline bool is_hdmi(struct v4l2_subdev *sd) 1297 { 1298 return hdmi_read(sd, 0x05) & 0x80; 1299 } 1300 1301 static inline bool no_lock_sspd(struct v4l2_subdev *sd) 1302 { 1303 struct adv76xx_state *state = to_state(sd); 1304 1305 /* 1306 * Chips without a AFE don't expose registers for the SSPD, so just assume 1307 * that we have a lock. 1308 */ 1309 if (adv76xx_has_afe(state)) 1310 return false; 1311 1312 /* TODO channel 2 */ 1313 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0); 1314 } 1315 1316 static inline bool no_lock_stdi(struct v4l2_subdev *sd) 1317 { 1318 /* TODO channel 2 */ 1319 return !(cp_read(sd, 0xb1) & 0x80); 1320 } 1321 1322 static inline bool no_signal(struct v4l2_subdev *sd) 1323 { 1324 bool ret; 1325 1326 ret = no_power(sd); 1327 1328 ret |= no_lock_stdi(sd); 1329 ret |= no_lock_sspd(sd); 1330 1331 if (is_digital_input(sd)) { 1332 ret |= no_lock_tmds(sd); 1333 ret |= no_signal_tmds(sd); 1334 } 1335 1336 return ret; 1337 } 1338 1339 static inline bool no_lock_cp(struct v4l2_subdev *sd) 1340 { 1341 struct adv76xx_state *state = to_state(sd); 1342 1343 if (!adv76xx_has_afe(state)) 1344 return false; 1345 1346 /* CP has detected a non standard number of lines on the incoming 1347 video compared to what it is configured to receive by s_dv_timings */ 1348 return io_read(sd, 0x12) & 0x01; 1349 } 1350 1351 static inline bool in_free_run(struct v4l2_subdev *sd) 1352 { 1353 return cp_read(sd, 0xff) & 0x10; 1354 } 1355 1356 static int adv76xx_g_input_status(struct v4l2_subdev *sd, u32 *status) 1357 { 1358 *status = 0; 1359 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0; 1360 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0; 1361 if (!in_free_run(sd) && no_lock_cp(sd)) 1362 *status |= is_digital_input(sd) ? 1363 V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK; 1364 1365 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status); 1366 1367 return 0; 1368 } 1369 1370 /* ----------------------------------------------------------------------- */ 1371 1372 struct stdi_readback { 1373 u16 bl, lcf, lcvs; 1374 u8 hs_pol, vs_pol; 1375 bool interlaced; 1376 }; 1377 1378 static int stdi2dv_timings(struct v4l2_subdev *sd, 1379 struct stdi_readback *stdi, 1380 struct v4l2_dv_timings *timings) 1381 { 1382 struct adv76xx_state *state = to_state(sd); 1383 u32 hfreq = (ADV76XX_FSC * 8) / stdi->bl; 1384 u32 pix_clk; 1385 int i; 1386 1387 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) { 1388 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt; 1389 1390 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i], 1391 adv76xx_get_dv_timings_cap(sd, -1), 1392 adv76xx_check_dv_timings, NULL)) 1393 continue; 1394 if (vtotal(bt) != stdi->lcf + 1) 1395 continue; 1396 if (bt->vsync != stdi->lcvs) 1397 continue; 1398 1399 pix_clk = hfreq * htotal(bt); 1400 1401 if ((pix_clk < bt->pixelclock + 1000000) && 1402 (pix_clk > bt->pixelclock - 1000000)) { 1403 *timings = v4l2_dv_timings_presets[i]; 1404 return 0; 1405 } 1406 } 1407 1408 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0, 1409 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 1410 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 1411 false, timings)) 1412 return 0; 1413 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs, 1414 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 1415 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 1416 false, state->aspect_ratio, timings)) 1417 return 0; 1418 1419 v4l2_dbg(2, debug, sd, 1420 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n", 1421 __func__, stdi->lcvs, stdi->lcf, stdi->bl, 1422 stdi->hs_pol, stdi->vs_pol); 1423 return -1; 1424 } 1425 1426 1427 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi) 1428 { 1429 struct adv76xx_state *state = to_state(sd); 1430 const struct adv76xx_chip_info *info = state->info; 1431 u8 polarity; 1432 1433 if (no_lock_stdi(sd) || no_lock_sspd(sd)) { 1434 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__); 1435 return -1; 1436 } 1437 1438 /* read STDI */ 1439 stdi->bl = cp_read16(sd, 0xb1, 0x3fff); 1440 stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff); 1441 stdi->lcvs = cp_read(sd, 0xb3) >> 3; 1442 stdi->interlaced = io_read(sd, 0x12) & 0x10; 1443 1444 if (adv76xx_has_afe(state)) { 1445 /* read SSPD */ 1446 polarity = cp_read(sd, 0xb5); 1447 if ((polarity & 0x03) == 0x01) { 1448 stdi->hs_pol = polarity & 0x10 1449 ? (polarity & 0x08 ? '+' : '-') : 'x'; 1450 stdi->vs_pol = polarity & 0x40 1451 ? (polarity & 0x20 ? '+' : '-') : 'x'; 1452 } else { 1453 stdi->hs_pol = 'x'; 1454 stdi->vs_pol = 'x'; 1455 } 1456 } else { 1457 polarity = hdmi_read(sd, 0x05); 1458 stdi->hs_pol = polarity & 0x20 ? '+' : '-'; 1459 stdi->vs_pol = polarity & 0x10 ? '+' : '-'; 1460 } 1461 1462 if (no_lock_stdi(sd) || no_lock_sspd(sd)) { 1463 v4l2_dbg(2, debug, sd, 1464 "%s: signal lost during readout of STDI/SSPD\n", __func__); 1465 return -1; 1466 } 1467 1468 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) { 1469 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__); 1470 memset(stdi, 0, sizeof(struct stdi_readback)); 1471 return -1; 1472 } 1473 1474 v4l2_dbg(2, debug, sd, 1475 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n", 1476 __func__, stdi->lcf, stdi->bl, stdi->lcvs, 1477 stdi->hs_pol, stdi->vs_pol, 1478 stdi->interlaced ? "interlaced" : "progressive"); 1479 1480 return 0; 1481 } 1482 1483 static int adv76xx_enum_dv_timings(struct v4l2_subdev *sd, 1484 struct v4l2_enum_dv_timings *timings) 1485 { 1486 struct adv76xx_state *state = to_state(sd); 1487 1488 if (timings->pad >= state->source_pad) 1489 return -EINVAL; 1490 1491 return v4l2_enum_dv_timings_cap(timings, 1492 adv76xx_get_dv_timings_cap(sd, timings->pad), 1493 adv76xx_check_dv_timings, NULL); 1494 } 1495 1496 static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd, 1497 struct v4l2_dv_timings_cap *cap) 1498 { 1499 struct adv76xx_state *state = to_state(sd); 1500 unsigned int pad = cap->pad; 1501 1502 if (cap->pad >= state->source_pad) 1503 return -EINVAL; 1504 1505 *cap = *adv76xx_get_dv_timings_cap(sd, pad); 1506 cap->pad = pad; 1507 1508 return 0; 1509 } 1510 1511 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings 1512 if the format is listed in adv76xx_timings[] */ 1513 static void adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev *sd, 1514 struct v4l2_dv_timings *timings) 1515 { 1516 v4l2_find_dv_timings_cap(timings, adv76xx_get_dv_timings_cap(sd, -1), 1517 is_digital_input(sd) ? 250000 : 1000000, 1518 adv76xx_check_dv_timings, NULL); 1519 } 1520 1521 static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd) 1522 { 1523 int a, b; 1524 1525 a = hdmi_read(sd, 0x06); 1526 b = hdmi_read(sd, 0x3b); 1527 if (a < 0 || b < 0) 1528 return 0; 1529 1530 return a * 1000000 + ((b & 0x30) >> 4) * 250000; 1531 } 1532 1533 static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd) 1534 { 1535 int a, b; 1536 1537 a = hdmi_read(sd, 0x51); 1538 b = hdmi_read(sd, 0x52); 1539 if (a < 0 || b < 0) 1540 return 0; 1541 1542 return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128; 1543 } 1544 1545 static unsigned int adv76xx_read_hdmi_pixelclock(struct v4l2_subdev *sd) 1546 { 1547 struct adv76xx_state *state = to_state(sd); 1548 const struct adv76xx_chip_info *info = state->info; 1549 unsigned int freq, bits_per_channel, pixelrepetition; 1550 1551 freq = info->read_hdmi_pixelclock(sd); 1552 if (is_hdmi(sd)) { 1553 /* adjust for deep color mode and pixel repetition */ 1554 bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8; 1555 pixelrepetition = (hdmi_read(sd, 0x05) & 0x0f) + 1; 1556 1557 freq = freq * 8 / bits_per_channel / pixelrepetition; 1558 } 1559 1560 return freq; 1561 } 1562 1563 static int adv76xx_query_dv_timings(struct v4l2_subdev *sd, unsigned int pad, 1564 struct v4l2_dv_timings *timings) 1565 { 1566 struct adv76xx_state *state = to_state(sd); 1567 const struct adv76xx_chip_info *info = state->info; 1568 struct v4l2_bt_timings *bt = &timings->bt; 1569 struct stdi_readback stdi; 1570 1571 if (!timings) 1572 return -EINVAL; 1573 1574 memset(timings, 0, sizeof(struct v4l2_dv_timings)); 1575 1576 if (no_signal(sd)) { 1577 state->restart_stdi_once = true; 1578 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); 1579 return -ENOLINK; 1580 } 1581 1582 /* read STDI */ 1583 if (read_stdi(sd, &stdi)) { 1584 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__); 1585 return -ENOLINK; 1586 } 1587 bt->interlaced = stdi.interlaced ? 1588 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; 1589 1590 if (is_digital_input(sd)) { 1591 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; 1592 u8 vic = 0; 1593 u32 w, h; 1594 1595 w = hdmi_read16(sd, 0x07, info->linewidth_mask); 1596 h = hdmi_read16(sd, 0x09, info->field0_height_mask); 1597 1598 if (hdmi_signal && (io_read(sd, 0x60) & 1)) 1599 vic = infoframe_read(sd, 0x04); 1600 1601 if (vic && v4l2_find_dv_timings_cea861_vic(timings, vic) && 1602 bt->width == w && bt->height == h) 1603 goto found; 1604 1605 timings->type = V4L2_DV_BT_656_1120; 1606 1607 bt->width = w; 1608 bt->height = h; 1609 bt->pixelclock = adv76xx_read_hdmi_pixelclock(sd); 1610 bt->hfrontporch = hdmi_read16(sd, 0x20, info->hfrontporch_mask); 1611 bt->hsync = hdmi_read16(sd, 0x22, info->hsync_mask); 1612 bt->hbackporch = hdmi_read16(sd, 0x24, info->hbackporch_mask); 1613 bt->vfrontporch = hdmi_read16(sd, 0x2a, 1614 info->field0_vfrontporch_mask) / 2; 1615 bt->vsync = hdmi_read16(sd, 0x2e, info->field0_vsync_mask) / 2; 1616 bt->vbackporch = hdmi_read16(sd, 0x32, 1617 info->field0_vbackporch_mask) / 2; 1618 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | 1619 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0); 1620 if (bt->interlaced == V4L2_DV_INTERLACED) { 1621 bt->height += hdmi_read16(sd, 0x0b, 1622 info->field1_height_mask); 1623 bt->il_vfrontporch = hdmi_read16(sd, 0x2c, 1624 info->field1_vfrontporch_mask) / 2; 1625 bt->il_vsync = hdmi_read16(sd, 0x30, 1626 info->field1_vsync_mask) / 2; 1627 bt->il_vbackporch = hdmi_read16(sd, 0x34, 1628 info->field1_vbackporch_mask) / 2; 1629 } 1630 adv76xx_fill_optional_dv_timings_fields(sd, timings); 1631 } else { 1632 /* find format 1633 * Since LCVS values are inaccurate [REF_03, p. 275-276], 1634 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails. 1635 */ 1636 if (!stdi2dv_timings(sd, &stdi, timings)) 1637 goto found; 1638 stdi.lcvs += 1; 1639 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs); 1640 if (!stdi2dv_timings(sd, &stdi, timings)) 1641 goto found; 1642 stdi.lcvs -= 2; 1643 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs); 1644 if (stdi2dv_timings(sd, &stdi, timings)) { 1645 /* 1646 * The STDI block may measure wrong values, especially 1647 * for lcvs and lcf. If the driver can not find any 1648 * valid timing, the STDI block is restarted to measure 1649 * the video timings again. The function will return an 1650 * error, but the restart of STDI will generate a new 1651 * STDI interrupt and the format detection process will 1652 * restart. 1653 */ 1654 if (state->restart_stdi_once) { 1655 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__); 1656 /* TODO restart STDI for Sync Channel 2 */ 1657 /* enter one-shot mode */ 1658 cp_write_clr_set(sd, 0x86, 0x06, 0x00); 1659 /* trigger STDI restart */ 1660 cp_write_clr_set(sd, 0x86, 0x06, 0x04); 1661 /* reset to continuous mode */ 1662 cp_write_clr_set(sd, 0x86, 0x06, 0x02); 1663 state->restart_stdi_once = false; 1664 return -ENOLINK; 1665 } 1666 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__); 1667 return -ERANGE; 1668 } 1669 state->restart_stdi_once = true; 1670 } 1671 found: 1672 1673 if (no_signal(sd)) { 1674 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__); 1675 memset(timings, 0, sizeof(struct v4l2_dv_timings)); 1676 return -ENOLINK; 1677 } 1678 1679 if ((is_analog_input(sd) && bt->pixelclock > 170000000) || 1680 (is_digital_input(sd) && bt->pixelclock > 225000000)) { 1681 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n", 1682 __func__, (u32)bt->pixelclock); 1683 return -ERANGE; 1684 } 1685 1686 if (debug > 1) 1687 v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ", 1688 timings, true); 1689 1690 return 0; 1691 } 1692 1693 static int adv76xx_s_dv_timings(struct v4l2_subdev *sd, unsigned int pad, 1694 struct v4l2_dv_timings *timings) 1695 { 1696 struct adv76xx_state *state = to_state(sd); 1697 struct v4l2_bt_timings *bt; 1698 int err; 1699 1700 if (!timings) 1701 return -EINVAL; 1702 1703 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) { 1704 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__); 1705 return 0; 1706 } 1707 1708 bt = &timings->bt; 1709 1710 if (!v4l2_valid_dv_timings(timings, adv76xx_get_dv_timings_cap(sd, -1), 1711 adv76xx_check_dv_timings, NULL)) 1712 return -ERANGE; 1713 1714 adv76xx_fill_optional_dv_timings_fields(sd, timings); 1715 1716 state->timings = *timings; 1717 1718 cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00); 1719 1720 /* Use prim_mode and vid_std when available */ 1721 err = configure_predefined_video_timings(sd, timings); 1722 if (err) { 1723 /* custom settings when the video format 1724 does not have prim_mode/vid_std */ 1725 configure_custom_video_timings(sd, bt); 1726 } 1727 1728 set_rgb_quantization_range(sd); 1729 1730 if (debug > 1) 1731 v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ", 1732 timings, true); 1733 return 0; 1734 } 1735 1736 static int adv76xx_g_dv_timings(struct v4l2_subdev *sd, unsigned int pad, 1737 struct v4l2_dv_timings *timings) 1738 { 1739 struct adv76xx_state *state = to_state(sd); 1740 1741 *timings = state->timings; 1742 return 0; 1743 } 1744 1745 static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable) 1746 { 1747 hdmi_write(sd, 0x01, enable ? 0x00 : 0x78); 1748 } 1749 1750 static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable) 1751 { 1752 hdmi_write(sd, 0x83, enable ? 0xfe : 0xff); 1753 } 1754 1755 static void enable_input(struct v4l2_subdev *sd) 1756 { 1757 struct adv76xx_state *state = to_state(sd); 1758 1759 if (is_analog_input(sd)) { 1760 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */ 1761 } else if (is_digital_input(sd)) { 1762 hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input); 1763 state->info->set_termination(sd, true); 1764 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */ 1765 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */ 1766 } else { 1767 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 1768 __func__, state->selected_input); 1769 } 1770 } 1771 1772 static void disable_input(struct v4l2_subdev *sd) 1773 { 1774 struct adv76xx_state *state = to_state(sd); 1775 1776 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */ 1777 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */ 1778 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */ 1779 state->info->set_termination(sd, false); 1780 } 1781 1782 static void select_input(struct v4l2_subdev *sd) 1783 { 1784 struct adv76xx_state *state = to_state(sd); 1785 const struct adv76xx_chip_info *info = state->info; 1786 1787 if (is_analog_input(sd)) { 1788 adv76xx_write_reg_seq(sd, info->recommended_settings[0]); 1789 1790 afe_write(sd, 0x00, 0x08); /* power up ADC */ 1791 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */ 1792 afe_write(sd, 0xc8, 0x00); /* phase control */ 1793 } else if (is_digital_input(sd)) { 1794 hdmi_write(sd, 0x00, state->selected_input & 0x03); 1795 1796 adv76xx_write_reg_seq(sd, info->recommended_settings[1]); 1797 1798 if (adv76xx_has_afe(state)) { 1799 afe_write(sd, 0x00, 0xff); /* power down ADC */ 1800 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */ 1801 afe_write(sd, 0xc8, 0x40); /* phase control */ 1802 } 1803 1804 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */ 1805 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */ 1806 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */ 1807 } else { 1808 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 1809 __func__, state->selected_input); 1810 } 1811 1812 /* Enable video adjustment (contrast, saturation, brightness and hue) */ 1813 cp_write_clr_set(sd, 0x3e, 0x80, 0x80); 1814 } 1815 1816 static int adv76xx_s_routing(struct v4l2_subdev *sd, 1817 u32 input, u32 output, u32 config) 1818 { 1819 struct adv76xx_state *state = to_state(sd); 1820 1821 v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d", 1822 __func__, input, state->selected_input); 1823 1824 if (input == state->selected_input) 1825 return 0; 1826 1827 if (input > state->info->max_port) 1828 return -EINVAL; 1829 1830 state->selected_input = input; 1831 1832 disable_input(sd); 1833 select_input(sd); 1834 enable_input(sd); 1835 1836 v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt); 1837 1838 return 0; 1839 } 1840 1841 static int adv76xx_enum_mbus_code(struct v4l2_subdev *sd, 1842 struct v4l2_subdev_state *sd_state, 1843 struct v4l2_subdev_mbus_code_enum *code) 1844 { 1845 struct adv76xx_state *state = to_state(sd); 1846 1847 if (code->index >= state->info->nformats) 1848 return -EINVAL; 1849 1850 code->code = state->info->formats[code->index].code; 1851 1852 return 0; 1853 } 1854 1855 static void adv76xx_fill_format(struct adv76xx_state *state, 1856 struct v4l2_mbus_framefmt *format) 1857 { 1858 memset(format, 0, sizeof(*format)); 1859 1860 format->width = state->timings.bt.width; 1861 format->height = state->timings.bt.height; 1862 format->field = V4L2_FIELD_NONE; 1863 format->colorspace = V4L2_COLORSPACE_SRGB; 1864 1865 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) 1866 format->colorspace = (state->timings.bt.height <= 576) ? 1867 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709; 1868 } 1869 1870 /* 1871 * Compute the op_ch_sel value required to obtain on the bus the component order 1872 * corresponding to the selected format taking into account bus reordering 1873 * applied by the board at the output of the device. 1874 * 1875 * The following table gives the op_ch_value from the format component order 1876 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as 1877 * adv76xx_bus_order value in row). 1878 * 1879 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5) 1880 * ----------+------------------------------------------------- 1881 * RGB (NOP) | GBR GRB BGR RGB BRG RBG 1882 * GRB (1-2) | BGR RGB GBR GRB RBG BRG 1883 * RBG (2-3) | GRB GBR BRG RBG BGR RGB 1884 * BGR (1-3) | RBG BRG RGB BGR GRB GBR 1885 * BRG (ROR) | BRG RBG GRB GBR RGB BGR 1886 * GBR (ROL) | RGB BGR RBG BRG GBR GRB 1887 */ 1888 static unsigned int adv76xx_op_ch_sel(struct adv76xx_state *state) 1889 { 1890 #define _SEL(a,b,c,d,e,f) { \ 1891 ADV76XX_OP_CH_SEL_##a, ADV76XX_OP_CH_SEL_##b, ADV76XX_OP_CH_SEL_##c, \ 1892 ADV76XX_OP_CH_SEL_##d, ADV76XX_OP_CH_SEL_##e, ADV76XX_OP_CH_SEL_##f } 1893 #define _BUS(x) [ADV7604_BUS_ORDER_##x] 1894 1895 static const unsigned int op_ch_sel[6][6] = { 1896 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG), 1897 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG), 1898 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB), 1899 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR), 1900 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR), 1901 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB), 1902 }; 1903 1904 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5]; 1905 } 1906 1907 static void adv76xx_setup_format(struct adv76xx_state *state) 1908 { 1909 struct v4l2_subdev *sd = &state->sd; 1910 1911 io_write_clr_set(sd, 0x02, 0x02, 1912 state->format->rgb_out ? ADV76XX_RGB_OUT : 0); 1913 io_write(sd, 0x03, state->format->op_format_sel | 1914 state->pdata.op_format_mode_sel); 1915 io_write_clr_set(sd, 0x04, 0xe0, adv76xx_op_ch_sel(state)); 1916 io_write_clr_set(sd, 0x05, 0x01, 1917 state->format->swap_cb_cr ? ADV76XX_OP_SWAP_CB_CR : 0); 1918 set_rgb_quantization_range(sd); 1919 } 1920 1921 static int adv76xx_get_format(struct v4l2_subdev *sd, 1922 struct v4l2_subdev_state *sd_state, 1923 struct v4l2_subdev_format *format) 1924 { 1925 struct adv76xx_state *state = to_state(sd); 1926 1927 if (format->pad != state->source_pad) 1928 return -EINVAL; 1929 1930 adv76xx_fill_format(state, &format->format); 1931 1932 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1933 struct v4l2_mbus_framefmt *fmt; 1934 1935 fmt = v4l2_subdev_state_get_format(sd_state, format->pad); 1936 format->format.code = fmt->code; 1937 } else { 1938 format->format.code = state->format->code; 1939 } 1940 1941 return 0; 1942 } 1943 1944 static int adv76xx_get_selection(struct v4l2_subdev *sd, 1945 struct v4l2_subdev_state *sd_state, 1946 struct v4l2_subdev_selection *sel) 1947 { 1948 struct adv76xx_state *state = to_state(sd); 1949 1950 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE) 1951 return -EINVAL; 1952 /* Only CROP, CROP_DEFAULT and CROP_BOUNDS are supported */ 1953 if (sel->target > V4L2_SEL_TGT_CROP_BOUNDS) 1954 return -EINVAL; 1955 1956 sel->r.left = 0; 1957 sel->r.top = 0; 1958 sel->r.width = state->timings.bt.width; 1959 sel->r.height = state->timings.bt.height; 1960 1961 return 0; 1962 } 1963 1964 static int adv76xx_set_format(struct v4l2_subdev *sd, 1965 struct v4l2_subdev_state *sd_state, 1966 struct v4l2_subdev_format *format) 1967 { 1968 struct adv76xx_state *state = to_state(sd); 1969 const struct adv76xx_format_info *info; 1970 1971 if (format->pad != state->source_pad) 1972 return -EINVAL; 1973 1974 info = adv76xx_format_info(state, format->format.code); 1975 if (!info) 1976 info = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); 1977 1978 adv76xx_fill_format(state, &format->format); 1979 format->format.code = info->code; 1980 1981 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1982 struct v4l2_mbus_framefmt *fmt; 1983 1984 fmt = v4l2_subdev_state_get_format(sd_state, format->pad); 1985 fmt->code = format->format.code; 1986 } else { 1987 state->format = info; 1988 adv76xx_setup_format(state); 1989 } 1990 1991 return 0; 1992 } 1993 1994 #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC) 1995 static void adv76xx_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status) 1996 { 1997 struct adv76xx_state *state = to_state(sd); 1998 1999 if ((cec_read(sd, 0x11) & 0x01) == 0) { 2000 v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n", __func__); 2001 return; 2002 } 2003 2004 if (tx_raw_status & 0x02) { 2005 v4l2_dbg(1, debug, sd, "%s: tx raw: arbitration lost\n", 2006 __func__); 2007 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_ARB_LOST, 2008 1, 0, 0, 0); 2009 return; 2010 } 2011 if (tx_raw_status & 0x04) { 2012 u8 status; 2013 u8 nack_cnt; 2014 u8 low_drive_cnt; 2015 2016 v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n", __func__); 2017 /* 2018 * We set this status bit since this hardware performs 2019 * retransmissions. 2020 */ 2021 status = CEC_TX_STATUS_MAX_RETRIES; 2022 nack_cnt = cec_read(sd, 0x14) & 0xf; 2023 if (nack_cnt) 2024 status |= CEC_TX_STATUS_NACK; 2025 low_drive_cnt = cec_read(sd, 0x14) >> 4; 2026 if (low_drive_cnt) 2027 status |= CEC_TX_STATUS_LOW_DRIVE; 2028 cec_transmit_done(state->cec_adap, status, 2029 0, nack_cnt, low_drive_cnt, 0); 2030 return; 2031 } 2032 if (tx_raw_status & 0x01) { 2033 v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n", __func__); 2034 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0); 2035 return; 2036 } 2037 } 2038 2039 static void adv76xx_cec_isr(struct v4l2_subdev *sd, bool *handled) 2040 { 2041 struct adv76xx_state *state = to_state(sd); 2042 const struct adv76xx_chip_info *info = state->info; 2043 u8 cec_irq; 2044 2045 /* cec controller */ 2046 cec_irq = io_read(sd, info->cec_irq_status) & 0x0f; 2047 if (!cec_irq) 2048 return; 2049 2050 v4l2_dbg(1, debug, sd, "%s: cec: irq 0x%x\n", __func__, cec_irq); 2051 adv76xx_cec_tx_raw_status(sd, cec_irq); 2052 if (cec_irq & 0x08) { 2053 struct cec_msg msg; 2054 2055 msg.len = cec_read(sd, 0x25) & 0x1f; 2056 if (msg.len > CEC_MAX_MSG_SIZE) 2057 msg.len = CEC_MAX_MSG_SIZE; 2058 2059 if (msg.len) { 2060 u8 i; 2061 2062 for (i = 0; i < msg.len; i++) 2063 msg.msg[i] = cec_read(sd, i + 0x15); 2064 cec_write(sd, info->cec_rx_enable, 2065 info->cec_rx_enable_mask); /* re-enable rx */ 2066 cec_received_msg(state->cec_adap, &msg); 2067 } 2068 } 2069 2070 if (info->cec_irq_swap) { 2071 /* 2072 * Note: the bit order is swapped between 0x4d and 0x4e 2073 * on adv7604 2074 */ 2075 cec_irq = ((cec_irq & 0x08) >> 3) | ((cec_irq & 0x04) >> 1) | 2076 ((cec_irq & 0x02) << 1) | ((cec_irq & 0x01) << 3); 2077 } 2078 io_write(sd, info->cec_irq_status + 1, cec_irq); 2079 2080 if (handled) 2081 *handled = true; 2082 } 2083 2084 static int adv76xx_cec_adap_enable(struct cec_adapter *adap, bool enable) 2085 { 2086 struct adv76xx_state *state = cec_get_drvdata(adap); 2087 const struct adv76xx_chip_info *info = state->info; 2088 struct v4l2_subdev *sd = &state->sd; 2089 2090 if (!state->cec_enabled_adap && enable) { 2091 cec_write_clr_set(sd, 0x2a, 0x01, 0x01); /* power up cec */ 2092 cec_write(sd, 0x2c, 0x01); /* cec soft reset */ 2093 cec_write_clr_set(sd, 0x11, 0x01, 0); /* initially disable tx */ 2094 /* enabled irqs: */ 2095 /* tx: ready */ 2096 /* tx: arbitration lost */ 2097 /* tx: retry timeout */ 2098 /* rx: ready */ 2099 io_write_clr_set(sd, info->cec_irq_status + 3, 0x0f, 0x0f); 2100 cec_write(sd, info->cec_rx_enable, info->cec_rx_enable_mask); 2101 } else if (state->cec_enabled_adap && !enable) { 2102 /* disable cec interrupts */ 2103 io_write_clr_set(sd, info->cec_irq_status + 3, 0x0f, 0x00); 2104 /* disable address mask 1-3 */ 2105 cec_write_clr_set(sd, 0x27, 0x70, 0x00); 2106 /* power down cec section */ 2107 cec_write_clr_set(sd, 0x2a, 0x01, 0x00); 2108 state->cec_valid_addrs = 0; 2109 } 2110 state->cec_enabled_adap = enable; 2111 adv76xx_s_detect_tx_5v_ctrl(sd); 2112 return 0; 2113 } 2114 2115 static int adv76xx_cec_adap_log_addr(struct cec_adapter *adap, u8 addr) 2116 { 2117 struct adv76xx_state *state = cec_get_drvdata(adap); 2118 struct v4l2_subdev *sd = &state->sd; 2119 unsigned int i, free_idx = ADV76XX_MAX_ADDRS; 2120 2121 if (!state->cec_enabled_adap) 2122 return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO; 2123 2124 if (addr == CEC_LOG_ADDR_INVALID) { 2125 cec_write_clr_set(sd, 0x27, 0x70, 0); 2126 state->cec_valid_addrs = 0; 2127 return 0; 2128 } 2129 2130 for (i = 0; i < ADV76XX_MAX_ADDRS; i++) { 2131 bool is_valid = state->cec_valid_addrs & (1 << i); 2132 2133 if (free_idx == ADV76XX_MAX_ADDRS && !is_valid) 2134 free_idx = i; 2135 if (is_valid && state->cec_addr[i] == addr) 2136 return 0; 2137 } 2138 if (i == ADV76XX_MAX_ADDRS) { 2139 i = free_idx; 2140 if (i == ADV76XX_MAX_ADDRS) 2141 return -ENXIO; 2142 } 2143 state->cec_addr[i] = addr; 2144 state->cec_valid_addrs |= 1 << i; 2145 2146 switch (i) { 2147 case 0: 2148 /* enable address mask 0 */ 2149 cec_write_clr_set(sd, 0x27, 0x10, 0x10); 2150 /* set address for mask 0 */ 2151 cec_write_clr_set(sd, 0x28, 0x0f, addr); 2152 break; 2153 case 1: 2154 /* enable address mask 1 */ 2155 cec_write_clr_set(sd, 0x27, 0x20, 0x20); 2156 /* set address for mask 1 */ 2157 cec_write_clr_set(sd, 0x28, 0xf0, addr << 4); 2158 break; 2159 case 2: 2160 /* enable address mask 2 */ 2161 cec_write_clr_set(sd, 0x27, 0x40, 0x40); 2162 /* set address for mask 1 */ 2163 cec_write_clr_set(sd, 0x29, 0x0f, addr); 2164 break; 2165 } 2166 return 0; 2167 } 2168 2169 static int adv76xx_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 2170 u32 signal_free_time, struct cec_msg *msg) 2171 { 2172 struct adv76xx_state *state = cec_get_drvdata(adap); 2173 struct v4l2_subdev *sd = &state->sd; 2174 u8 len = msg->len; 2175 unsigned int i; 2176 2177 /* 2178 * The number of retries is the number of attempts - 1, but retry 2179 * at least once. It's not clear if a value of 0 is allowed, so 2180 * let's do at least one retry. 2181 */ 2182 cec_write_clr_set(sd, 0x12, 0x70, max(1, attempts - 1) << 4); 2183 2184 if (len > 16) { 2185 v4l2_err(sd, "%s: len exceeded 16 (%d)\n", __func__, len); 2186 return -EINVAL; 2187 } 2188 2189 /* write data */ 2190 for (i = 0; i < len; i++) 2191 cec_write(sd, i, msg->msg[i]); 2192 2193 /* set length (data + header) */ 2194 cec_write(sd, 0x10, len); 2195 /* start transmit, enable tx */ 2196 cec_write(sd, 0x11, 0x01); 2197 return 0; 2198 } 2199 2200 static const struct cec_adap_ops adv76xx_cec_adap_ops = { 2201 .adap_enable = adv76xx_cec_adap_enable, 2202 .adap_log_addr = adv76xx_cec_adap_log_addr, 2203 .adap_transmit = adv76xx_cec_adap_transmit, 2204 }; 2205 #endif 2206 2207 static int adv76xx_isr(struct v4l2_subdev *sd, u32 status, bool *handled) 2208 { 2209 struct adv76xx_state *state = to_state(sd); 2210 const struct adv76xx_chip_info *info = state->info; 2211 const u8 irq_reg_0x43 = io_read(sd, 0x43); 2212 const u8 irq_reg_0x6b = io_read(sd, 0x6b); 2213 const u8 irq_reg_0x70 = io_read(sd, 0x70); 2214 u8 fmt_change_digital; 2215 u8 fmt_change; 2216 u8 tx_5v; 2217 2218 if (irq_reg_0x43) 2219 io_write(sd, 0x44, irq_reg_0x43); 2220 if (irq_reg_0x70) 2221 io_write(sd, 0x71, irq_reg_0x70); 2222 if (irq_reg_0x6b) 2223 io_write(sd, 0x6c, irq_reg_0x6b); 2224 2225 v4l2_dbg(2, debug, sd, "%s: ", __func__); 2226 2227 /* format change */ 2228 fmt_change = irq_reg_0x43 & 0x98; 2229 fmt_change_digital = is_digital_input(sd) 2230 ? irq_reg_0x6b & info->fmt_change_digital_mask 2231 : 0; 2232 2233 if (fmt_change || fmt_change_digital) { 2234 v4l2_dbg(1, debug, sd, 2235 "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n", 2236 __func__, fmt_change, fmt_change_digital); 2237 2238 v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt); 2239 2240 if (handled) 2241 *handled = true; 2242 } 2243 /* HDMI/DVI mode */ 2244 if (irq_reg_0x6b & 0x01) { 2245 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__, 2246 (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI"); 2247 set_rgb_quantization_range(sd); 2248 if (handled) 2249 *handled = true; 2250 } 2251 2252 #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC) 2253 /* cec */ 2254 adv76xx_cec_isr(sd, handled); 2255 #endif 2256 2257 /* tx 5v detect */ 2258 tx_5v = irq_reg_0x70 & info->cable_det_mask; 2259 if (tx_5v) { 2260 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v); 2261 adv76xx_s_detect_tx_5v_ctrl(sd); 2262 if (handled) 2263 *handled = true; 2264 } 2265 return 0; 2266 } 2267 2268 static irqreturn_t adv76xx_irq_handler(int irq, void *dev_id) 2269 { 2270 struct adv76xx_state *state = dev_id; 2271 bool handled = false; 2272 2273 adv76xx_isr(&state->sd, 0, &handled); 2274 2275 return handled ? IRQ_HANDLED : IRQ_NONE; 2276 } 2277 2278 static int adv76xx_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 2279 { 2280 struct adv76xx_state *state = to_state(sd); 2281 u8 *data = NULL; 2282 2283 memset(edid->reserved, 0, sizeof(edid->reserved)); 2284 2285 switch (edid->pad) { 2286 case ADV76XX_PAD_HDMI_PORT_A: 2287 case ADV7604_PAD_HDMI_PORT_B: 2288 case ADV7604_PAD_HDMI_PORT_C: 2289 case ADV7604_PAD_HDMI_PORT_D: 2290 if (state->edid.present & (1 << edid->pad)) 2291 data = state->edid.edid; 2292 break; 2293 default: 2294 return -EINVAL; 2295 } 2296 2297 if (edid->start_block == 0 && edid->blocks == 0) { 2298 edid->blocks = data ? state->edid.blocks : 0; 2299 return 0; 2300 } 2301 2302 if (!data) 2303 return -ENODATA; 2304 2305 if (edid->start_block >= state->edid.blocks) 2306 return -EINVAL; 2307 2308 if (edid->start_block + edid->blocks > state->edid.blocks) 2309 edid->blocks = state->edid.blocks - edid->start_block; 2310 2311 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128); 2312 2313 return 0; 2314 } 2315 2316 static int adv76xx_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 2317 { 2318 struct adv76xx_state *state = to_state(sd); 2319 const struct adv76xx_chip_info *info = state->info; 2320 unsigned int spa_loc; 2321 u16 pa, parent_pa; 2322 int err; 2323 int i; 2324 2325 memset(edid->reserved, 0, sizeof(edid->reserved)); 2326 2327 if (edid->pad > ADV7604_PAD_HDMI_PORT_D) 2328 return -EINVAL; 2329 if (edid->start_block != 0) 2330 return -EINVAL; 2331 if (edid->blocks == 0) { 2332 /* Disable hotplug and I2C access to EDID RAM from DDC port */ 2333 state->edid.present &= ~(1 << edid->pad); 2334 adv76xx_set_hpd(state, state->edid.present); 2335 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); 2336 2337 /* Fall back to a 16:9 aspect ratio */ 2338 state->aspect_ratio.numerator = 16; 2339 state->aspect_ratio.denominator = 9; 2340 2341 if (!state->edid.present) { 2342 state->edid.blocks = 0; 2343 cec_phys_addr_invalidate(state->cec_adap); 2344 } 2345 2346 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n", 2347 __func__, edid->pad, state->edid.present); 2348 return 0; 2349 } 2350 if (edid->blocks > ADV76XX_MAX_EDID_BLOCKS) { 2351 edid->blocks = ADV76XX_MAX_EDID_BLOCKS; 2352 return -E2BIG; 2353 } 2354 2355 pa = v4l2_get_edid_phys_addr(edid->edid, edid->blocks * 128, &spa_loc); 2356 err = v4l2_phys_addr_validate(pa, &parent_pa, NULL); 2357 if (err) 2358 return err; 2359 2360 if (!spa_loc) { 2361 /* 2362 * There is no SPA, so just set spa_loc to 128 and pa to whatever 2363 * data is there. 2364 */ 2365 spa_loc = 128; 2366 pa = (edid->edid[spa_loc] << 8) | edid->edid[spa_loc + 1]; 2367 } 2368 2369 v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n", 2370 __func__, edid->pad, state->edid.present); 2371 2372 /* Disable hotplug and I2C access to EDID RAM from DDC port */ 2373 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); 2374 adv76xx_set_hpd(state, 0); 2375 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00); 2376 2377 switch (edid->pad) { 2378 case ADV76XX_PAD_HDMI_PORT_A: 2379 state->spa_port_a[0] = pa >> 8; 2380 state->spa_port_a[1] = pa & 0xff; 2381 break; 2382 case ADV7604_PAD_HDMI_PORT_B: 2383 rep_write(sd, info->edid_spa_port_b_reg, pa >> 8); 2384 rep_write(sd, info->edid_spa_port_b_reg + 1, pa & 0xff); 2385 break; 2386 case ADV7604_PAD_HDMI_PORT_C: 2387 rep_write(sd, info->edid_spa_port_b_reg + 2, pa >> 8); 2388 rep_write(sd, info->edid_spa_port_b_reg + 3, pa & 0xff); 2389 break; 2390 case ADV7604_PAD_HDMI_PORT_D: 2391 rep_write(sd, info->edid_spa_port_b_reg + 4, pa >> 8); 2392 rep_write(sd, info->edid_spa_port_b_reg + 5, pa & 0xff); 2393 break; 2394 default: 2395 return -EINVAL; 2396 } 2397 2398 if (info->edid_spa_loc_reg) { 2399 u8 mask = info->edid_spa_loc_msb_mask; 2400 2401 rep_write(sd, info->edid_spa_loc_reg, spa_loc & 0xff); 2402 rep_write_clr_set(sd, info->edid_spa_loc_reg + 1, 2403 mask, (spa_loc & 0x100) ? mask : 0); 2404 } 2405 2406 edid->edid[spa_loc] = state->spa_port_a[0]; 2407 edid->edid[spa_loc + 1] = state->spa_port_a[1]; 2408 2409 memcpy(state->edid.edid, edid->edid, 128 * edid->blocks); 2410 state->edid.blocks = edid->blocks; 2411 state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15], 2412 edid->edid[0x16]); 2413 state->edid.present |= 1 << edid->pad; 2414 2415 rep_write_clr_set(sd, info->edid_segment_reg, 2416 info->edid_segment_mask, 0); 2417 err = edid_write_block(sd, 128 * min(edid->blocks, 2U), state->edid.edid); 2418 if (err < 0) { 2419 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad); 2420 return err; 2421 } 2422 if (edid->blocks > 2) { 2423 rep_write_clr_set(sd, info->edid_segment_reg, 2424 info->edid_segment_mask, 2425 info->edid_segment_mask); 2426 err = edid_write_block(sd, 128 * (edid->blocks - 2), 2427 state->edid.edid + 256); 2428 if (err < 0) { 2429 v4l2_err(sd, "error %d writing edid pad %d\n", 2430 err, edid->pad); 2431 return err; 2432 } 2433 } 2434 2435 /* adv76xx calculates the checksums and enables I2C access to internal 2436 EDID RAM from DDC port. */ 2437 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); 2438 2439 for (i = 0; i < 1000; i++) { 2440 if (rep_read(sd, info->edid_status_reg) & state->edid.present) 2441 break; 2442 mdelay(1); 2443 } 2444 if (i == 1000) { 2445 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present); 2446 return -EIO; 2447 } 2448 cec_s_phys_addr(state->cec_adap, parent_pa, false); 2449 2450 /* enable hotplug after 100 ms */ 2451 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 10); 2452 return 0; 2453 } 2454 2455 /*********** avi info frame CEA-861-E **************/ 2456 2457 static const struct adv76xx_cfg_read_infoframe adv76xx_cri[] = { 2458 { "AVI", 0x01, 0xe0, 0x00 }, 2459 { "Audio", 0x02, 0xe3, 0x1c }, 2460 { "SDP", 0x04, 0xe6, 0x2a }, 2461 { "Vendor", 0x10, 0xec, 0x54 } 2462 }; 2463 2464 static int adv76xx_read_infoframe_buf(struct v4l2_subdev *sd, int index, 2465 u8 buf[V4L2_DEBUGFS_IF_MAX_LEN]) 2466 { 2467 u8 len; 2468 int i; 2469 2470 if (!(io_read(sd, 0x60) & adv76xx_cri[index].present_mask)) { 2471 v4l2_info(sd, "%s infoframe not received\n", 2472 adv76xx_cri[index].desc); 2473 return -ENOENT; 2474 } 2475 2476 for (i = 0; i < 3; i++) 2477 buf[i] = infoframe_read(sd, adv76xx_cri[index].head_addr + i); 2478 2479 len = buf[2] + 1; 2480 2481 if (len + 3 > V4L2_DEBUGFS_IF_MAX_LEN) { 2482 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, 2483 adv76xx_cri[index].desc, len); 2484 return -ENOENT; 2485 } 2486 2487 for (i = 0; i < len; i++) 2488 buf[i + 3] = infoframe_read(sd, 2489 adv76xx_cri[index].payload_addr + i); 2490 return len + 3; 2491 } 2492 2493 static void adv76xx_log_infoframes(struct v4l2_subdev *sd) 2494 { 2495 int i; 2496 2497 if (!is_hdmi(sd)) { 2498 v4l2_info(sd, "receive DVI-D signal, no infoframes\n"); 2499 return; 2500 } 2501 2502 for (i = 0; i < ARRAY_SIZE(adv76xx_cri); i++) { 2503 struct i2c_client *client = v4l2_get_subdevdata(sd); 2504 u8 buffer[V4L2_DEBUGFS_IF_MAX_LEN] = {}; 2505 union hdmi_infoframe frame; 2506 int len; 2507 2508 len = adv76xx_read_infoframe_buf(sd, i, buffer); 2509 if (len < 0) 2510 continue; 2511 2512 if (hdmi_infoframe_unpack(&frame, buffer, len) < 0) 2513 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", 2514 __func__, adv76xx_cri[i].desc); 2515 else 2516 hdmi_infoframe_log(KERN_INFO, &client->dev, &frame); 2517 } 2518 } 2519 2520 static int adv76xx_log_status(struct v4l2_subdev *sd) 2521 { 2522 struct adv76xx_state *state = to_state(sd); 2523 const struct adv76xx_chip_info *info = state->info; 2524 struct v4l2_dv_timings timings; 2525 struct stdi_readback stdi; 2526 u8 reg_io_0x02 = io_read(sd, 0x02); 2527 u8 edid_enabled; 2528 u8 cable_det; 2529 2530 static const char * const csc_coeff_sel_rb[16] = { 2531 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB", 2532 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709", 2533 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709", 2534 "reserved", "reserved", "reserved", "reserved", "manual" 2535 }; 2536 static const char * const input_color_space_txt[16] = { 2537 "RGB limited range (16-235)", "RGB full range (0-255)", 2538 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", 2539 "xvYCC Bt.601", "xvYCC Bt.709", 2540 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", 2541 "invalid", "invalid", "invalid", "invalid", "invalid", 2542 "invalid", "invalid", "automatic" 2543 }; 2544 static const char * const hdmi_color_space_txt[16] = { 2545 "RGB limited range (16-235)", "RGB full range (0-255)", 2546 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", 2547 "xvYCC Bt.601", "xvYCC Bt.709", 2548 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", 2549 "sYCC", "opYCC 601", "opRGB", "invalid", "invalid", 2550 "invalid", "invalid", "invalid" 2551 }; 2552 static const char * const rgb_quantization_range_txt[] = { 2553 "Automatic", 2554 "RGB limited range (16-235)", 2555 "RGB full range (0-255)", 2556 }; 2557 static const char * const deep_color_mode_txt[4] = { 2558 "8-bits per channel", 2559 "10-bits per channel", 2560 "12-bits per channel", 2561 "16-bits per channel (not supported)" 2562 }; 2563 2564 v4l2_info(sd, "-----Chip status-----\n"); 2565 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on"); 2566 edid_enabled = rep_read(sd, info->edid_status_reg); 2567 v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n", 2568 ((edid_enabled & 0x01) ? "Yes" : "No"), 2569 ((edid_enabled & 0x02) ? "Yes" : "No"), 2570 ((edid_enabled & 0x04) ? "Yes" : "No"), 2571 ((edid_enabled & 0x08) ? "Yes" : "No")); 2572 v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ? 2573 "enabled" : "disabled"); 2574 if (state->cec_enabled_adap) { 2575 int i; 2576 2577 for (i = 0; i < ADV76XX_MAX_ADDRS; i++) { 2578 bool is_valid = state->cec_valid_addrs & (1 << i); 2579 2580 if (is_valid) 2581 v4l2_info(sd, "CEC Logical Address: 0x%x\n", 2582 state->cec_addr[i]); 2583 } 2584 } 2585 2586 v4l2_info(sd, "-----Signal status-----\n"); 2587 cable_det = info->read_cable_det(sd); 2588 v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n", 2589 ((cable_det & 0x01) ? "Yes" : "No"), 2590 ((cable_det & 0x02) ? "Yes" : "No"), 2591 ((cable_det & 0x04) ? "Yes" : "No"), 2592 ((cable_det & 0x08) ? "Yes" : "No")); 2593 v4l2_info(sd, "TMDS signal detected: %s\n", 2594 no_signal_tmds(sd) ? "false" : "true"); 2595 v4l2_info(sd, "TMDS signal locked: %s\n", 2596 no_lock_tmds(sd) ? "false" : "true"); 2597 v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true"); 2598 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true"); 2599 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true"); 2600 v4l2_info(sd, "CP free run: %s\n", 2601 (in_free_run(sd)) ? "on" : "off"); 2602 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n", 2603 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f, 2604 (io_read(sd, 0x01) & 0x70) >> 4); 2605 2606 v4l2_info(sd, "-----Video Timings-----\n"); 2607 if (read_stdi(sd, &stdi)) 2608 v4l2_info(sd, "STDI: not locked\n"); 2609 else 2610 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n", 2611 stdi.lcf, stdi.bl, stdi.lcvs, 2612 stdi.interlaced ? "interlaced" : "progressive", 2613 stdi.hs_pol, stdi.vs_pol); 2614 if (adv76xx_query_dv_timings(sd, 0, &timings)) 2615 v4l2_info(sd, "No video detected\n"); 2616 else 2617 v4l2_print_dv_timings(sd->name, "Detected format: ", 2618 &timings, true); 2619 v4l2_print_dv_timings(sd->name, "Configured format: ", 2620 &state->timings, true); 2621 2622 if (no_signal(sd)) 2623 return 0; 2624 2625 v4l2_info(sd, "-----Color space-----\n"); 2626 v4l2_info(sd, "RGB quantization range ctrl: %s\n", 2627 rgb_quantization_range_txt[state->rgb_quantization_range]); 2628 v4l2_info(sd, "Input color space: %s\n", 2629 input_color_space_txt[reg_io_0x02 >> 4]); 2630 v4l2_info(sd, "Output color space: %s %s, alt-gamma %s\n", 2631 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr", 2632 (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ? 2633 "(16-235)" : "(0-255)", 2634 (reg_io_0x02 & 0x08) ? "enabled" : "disabled"); 2635 v4l2_info(sd, "Color space conversion: %s\n", 2636 csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]); 2637 2638 if (!is_digital_input(sd)) 2639 return 0; 2640 2641 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); 2642 v4l2_info(sd, "Digital video port selected: %c\n", 2643 (hdmi_read(sd, 0x00) & 0x03) + 'A'); 2644 v4l2_info(sd, "HDCP encrypted content: %s\n", 2645 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false"); 2646 v4l2_info(sd, "HDCP keys read: %s%s\n", 2647 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no", 2648 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : ""); 2649 if (is_hdmi(sd)) { 2650 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01; 2651 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01; 2652 bool audio_mute = io_read(sd, 0x65) & 0x40; 2653 2654 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n", 2655 audio_pll_locked ? "locked" : "not locked", 2656 audio_sample_packet_detect ? "detected" : "not detected", 2657 audio_mute ? "muted" : "enabled"); 2658 if (audio_pll_locked && audio_sample_packet_detect) { 2659 v4l2_info(sd, "Audio format: %s\n", 2660 (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo"); 2661 } 2662 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) + 2663 (hdmi_read(sd, 0x5c) << 8) + 2664 (hdmi_read(sd, 0x5d) & 0xf0)); 2665 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) + 2666 (hdmi_read(sd, 0x5e) << 8) + 2667 hdmi_read(sd, 0x5f)); 2668 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off"); 2669 2670 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]); 2671 v4l2_info(sd, "HDMI colorspace: %s\n", hdmi_color_space_txt[hdmi_read(sd, 0x53) & 0xf]); 2672 2673 adv76xx_log_infoframes(sd); 2674 } 2675 2676 return 0; 2677 } 2678 2679 static int adv76xx_subscribe_event(struct v4l2_subdev *sd, 2680 struct v4l2_fh *fh, 2681 struct v4l2_event_subscription *sub) 2682 { 2683 switch (sub->type) { 2684 case V4L2_EVENT_SOURCE_CHANGE: 2685 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub); 2686 case V4L2_EVENT_CTRL: 2687 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub); 2688 default: 2689 return -EINVAL; 2690 } 2691 } 2692 2693 static ssize_t 2694 adv76xx_debugfs_if_read(u32 type, void *priv, struct file *filp, 2695 char __user *ubuf, size_t count, loff_t *ppos) 2696 { 2697 u8 buf[V4L2_DEBUGFS_IF_MAX_LEN] = {}; 2698 struct v4l2_subdev *sd = priv; 2699 int index; 2700 int len; 2701 2702 if (!is_hdmi(sd)) 2703 return 0; 2704 2705 switch (type) { 2706 case V4L2_DEBUGFS_IF_AVI: 2707 index = 0; 2708 break; 2709 case V4L2_DEBUGFS_IF_AUDIO: 2710 index = 1; 2711 break; 2712 case V4L2_DEBUGFS_IF_SPD: 2713 index = 2; 2714 break; 2715 case V4L2_DEBUGFS_IF_HDMI: 2716 index = 3; 2717 break; 2718 default: 2719 return 0; 2720 } 2721 2722 len = adv76xx_read_infoframe_buf(sd, index, buf); 2723 if (len > 0) 2724 len = simple_read_from_buffer(ubuf, count, ppos, buf, len); 2725 return len < 0 ? 0 : len; 2726 } 2727 2728 static int adv76xx_registered(struct v4l2_subdev *sd) 2729 { 2730 struct adv76xx_state *state = to_state(sd); 2731 struct i2c_client *client = v4l2_get_subdevdata(sd); 2732 int err; 2733 2734 err = cec_register_adapter(state->cec_adap, &client->dev); 2735 if (err) { 2736 cec_delete_adapter(state->cec_adap); 2737 return err; 2738 } 2739 state->debugfs_dir = debugfs_create_dir(sd->name, v4l2_debugfs_root()); 2740 state->infoframes = v4l2_debugfs_if_alloc(state->debugfs_dir, 2741 V4L2_DEBUGFS_IF_AVI | V4L2_DEBUGFS_IF_AUDIO | 2742 V4L2_DEBUGFS_IF_SPD | V4L2_DEBUGFS_IF_HDMI, sd, 2743 adv76xx_debugfs_if_read); 2744 return 0; 2745 } 2746 2747 static void adv76xx_unregistered(struct v4l2_subdev *sd) 2748 { 2749 struct adv76xx_state *state = to_state(sd); 2750 2751 cec_unregister_adapter(state->cec_adap); 2752 v4l2_debugfs_if_free(state->infoframes); 2753 state->infoframes = NULL; 2754 debugfs_remove_recursive(state->debugfs_dir); 2755 state->debugfs_dir = NULL; 2756 } 2757 2758 /* ----------------------------------------------------------------------- */ 2759 2760 static const struct v4l2_ctrl_ops adv76xx_ctrl_ops = { 2761 .s_ctrl = adv76xx_s_ctrl, 2762 .g_volatile_ctrl = adv76xx_g_volatile_ctrl, 2763 }; 2764 2765 static const struct v4l2_subdev_core_ops adv76xx_core_ops = { 2766 .log_status = adv76xx_log_status, 2767 .interrupt_service_routine = adv76xx_isr, 2768 .subscribe_event = adv76xx_subscribe_event, 2769 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 2770 #ifdef CONFIG_VIDEO_ADV_DEBUG 2771 .g_register = adv76xx_g_register, 2772 .s_register = adv76xx_s_register, 2773 #endif 2774 }; 2775 2776 static const struct v4l2_subdev_video_ops adv76xx_video_ops = { 2777 .s_routing = adv76xx_s_routing, 2778 .g_input_status = adv76xx_g_input_status, 2779 }; 2780 2781 static const struct v4l2_subdev_pad_ops adv76xx_pad_ops = { 2782 .enum_mbus_code = adv76xx_enum_mbus_code, 2783 .get_selection = adv76xx_get_selection, 2784 .get_fmt = adv76xx_get_format, 2785 .set_fmt = adv76xx_set_format, 2786 .get_edid = adv76xx_get_edid, 2787 .set_edid = adv76xx_set_edid, 2788 .s_dv_timings = adv76xx_s_dv_timings, 2789 .g_dv_timings = adv76xx_g_dv_timings, 2790 .query_dv_timings = adv76xx_query_dv_timings, 2791 .dv_timings_cap = adv76xx_dv_timings_cap, 2792 .enum_dv_timings = adv76xx_enum_dv_timings, 2793 }; 2794 2795 static const struct v4l2_subdev_ops adv76xx_ops = { 2796 .core = &adv76xx_core_ops, 2797 .video = &adv76xx_video_ops, 2798 .pad = &adv76xx_pad_ops, 2799 }; 2800 2801 static const struct v4l2_subdev_internal_ops adv76xx_int_ops = { 2802 .registered = adv76xx_registered, 2803 .unregistered = adv76xx_unregistered, 2804 }; 2805 2806 /* -------------------------- custom ctrls ---------------------------------- */ 2807 2808 static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = { 2809 .ops = &adv76xx_ctrl_ops, 2810 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE, 2811 .name = "Analog Sampling Phase", 2812 .type = V4L2_CTRL_TYPE_INTEGER, 2813 .min = 0, 2814 .max = 0x1f, 2815 .step = 1, 2816 .def = 0, 2817 }; 2818 2819 static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color_manual = { 2820 .ops = &adv76xx_ctrl_ops, 2821 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL, 2822 .name = "Free Running Color, Manual", 2823 .type = V4L2_CTRL_TYPE_BOOLEAN, 2824 .min = false, 2825 .max = true, 2826 .step = 1, 2827 .def = false, 2828 }; 2829 2830 static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color = { 2831 .ops = &adv76xx_ctrl_ops, 2832 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR, 2833 .name = "Free Running Color", 2834 .type = V4L2_CTRL_TYPE_INTEGER, 2835 .min = 0x0, 2836 .max = 0xffffff, 2837 .step = 0x1, 2838 .def = 0x0, 2839 }; 2840 2841 /* ----------------------------------------------------------------------- */ 2842 2843 struct adv76xx_register_map { 2844 const char *name; 2845 u8 default_addr; 2846 }; 2847 2848 static const struct adv76xx_register_map adv76xx_default_addresses[] = { 2849 [ADV76XX_PAGE_IO] = { "main", 0x4c }, 2850 [ADV7604_PAGE_AVLINK] = { "avlink", 0x42 }, 2851 [ADV76XX_PAGE_CEC] = { "cec", 0x40 }, 2852 [ADV76XX_PAGE_INFOFRAME] = { "infoframe", 0x3e }, 2853 [ADV7604_PAGE_ESDP] = { "esdp", 0x38 }, 2854 [ADV7604_PAGE_DPP] = { "dpp", 0x3c }, 2855 [ADV76XX_PAGE_AFE] = { "afe", 0x26 }, 2856 [ADV76XX_PAGE_REP] = { "rep", 0x32 }, 2857 [ADV76XX_PAGE_EDID] = { "edid", 0x36 }, 2858 [ADV76XX_PAGE_HDMI] = { "hdmi", 0x34 }, 2859 [ADV76XX_PAGE_TEST] = { "test", 0x30 }, 2860 [ADV76XX_PAGE_CP] = { "cp", 0x22 }, 2861 [ADV7604_PAGE_VDP] = { "vdp", 0x24 }, 2862 }; 2863 2864 static int adv76xx_core_init(struct v4l2_subdev *sd) 2865 { 2866 struct adv76xx_state *state = to_state(sd); 2867 const struct adv76xx_chip_info *info = state->info; 2868 struct adv76xx_platform_data *pdata = &state->pdata; 2869 2870 hdmi_write(sd, 0x48, 2871 (pdata->disable_pwrdnb ? 0x80 : 0) | 2872 (pdata->disable_cable_det_rst ? 0x40 : 0)); 2873 2874 disable_input(sd); 2875 2876 if (pdata->default_input >= 0 && 2877 pdata->default_input < state->source_pad) { 2878 state->selected_input = pdata->default_input; 2879 select_input(sd); 2880 enable_input(sd); 2881 } 2882 2883 /* power */ 2884 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */ 2885 io_write(sd, 0x0b, 0x44); /* Power down ESDP block */ 2886 cp_write(sd, 0xcf, 0x01); /* Power down macrovision */ 2887 2888 /* HPD */ 2889 if (info->type != ADV7604) { 2890 /* Set manual HPD values to 0 */ 2891 io_write_clr_set(sd, 0x20, 0xc0, 0); 2892 /* 2893 * Set HPA_DELAY to 200 ms and set automatic HPD control 2894 * to: internal EDID is active AND a cable is detected 2895 * AND the manual HPD control is set to 1. 2896 */ 2897 hdmi_write_clr_set(sd, 0x6c, 0xf6, 0x26); 2898 } 2899 2900 /* video format */ 2901 io_write_clr_set(sd, 0x02, 0x0f, pdata->alt_gamma << 3); 2902 io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 | 2903 pdata->insert_av_codes << 2 | 2904 pdata->replicate_av_codes << 1); 2905 adv76xx_setup_format(state); 2906 2907 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */ 2908 2909 /* VS, HS polarities */ 2910 io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 | 2911 pdata->inv_hs_pol << 1 | pdata->inv_llc_pol); 2912 2913 /* Adjust drive strength */ 2914 io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 | 2915 pdata->dr_str_clk << 2 | 2916 pdata->dr_str_sync); 2917 2918 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */ 2919 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */ 2920 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold - 2921 ADI recommended setting [REF_01, c. 2.3.3] */ 2922 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold - 2923 ADI recommended setting [REF_01, c. 2.3.3] */ 2924 cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution 2925 for digital formats */ 2926 2927 /* HDMI audio */ 2928 hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */ 2929 hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */ 2930 hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */ 2931 2932 /* TODO from platform data */ 2933 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ 2934 2935 if (adv76xx_has_afe(state)) { 2936 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ 2937 io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4); 2938 } 2939 2940 /* interrupts */ 2941 io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */ 2942 io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */ 2943 io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */ 2944 io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */ 2945 info->setup_irqs(sd); 2946 2947 return v4l2_ctrl_handler_setup(sd->ctrl_handler); 2948 } 2949 2950 static void adv7604_setup_irqs(struct v4l2_subdev *sd) 2951 { 2952 io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */ 2953 } 2954 2955 static void adv7611_setup_irqs(struct v4l2_subdev *sd) 2956 { 2957 io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */ 2958 } 2959 2960 static void adv7612_setup_irqs(struct v4l2_subdev *sd) 2961 { 2962 io_write(sd, 0x41, 0xd0); /* disable INT2 */ 2963 } 2964 2965 static void adv76xx_unregister_clients(struct adv76xx_state *state) 2966 { 2967 unsigned int i; 2968 2969 for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) 2970 i2c_unregister_device(state->i2c_clients[i]); 2971 } 2972 2973 static struct i2c_client *adv76xx_dummy_client(struct v4l2_subdev *sd, 2974 unsigned int page) 2975 { 2976 struct i2c_client *client = v4l2_get_subdevdata(sd); 2977 struct adv76xx_state *state = to_state(sd); 2978 struct adv76xx_platform_data *pdata = &state->pdata; 2979 unsigned int io_reg = 0xf2 + page; 2980 struct i2c_client *new_client; 2981 2982 if (pdata && pdata->i2c_addresses[page]) 2983 new_client = i2c_new_dummy_device(client->adapter, 2984 pdata->i2c_addresses[page]); 2985 else 2986 new_client = i2c_new_ancillary_device(client, 2987 adv76xx_default_addresses[page].name, 2988 adv76xx_default_addresses[page].default_addr); 2989 2990 if (!IS_ERR(new_client)) 2991 io_write(sd, io_reg, new_client->addr << 1); 2992 2993 return new_client; 2994 } 2995 2996 static const struct adv76xx_reg_seq adv7604_recommended_settings_afe[] = { 2997 /* reset ADI recommended settings for HDMI: */ 2998 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ 2999 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */ 3000 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */ 3001 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */ 3002 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */ 3003 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */ 3004 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */ 3005 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */ 3006 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */ 3007 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */ 3008 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */ 3009 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */ 3010 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */ 3011 3012 /* set ADI recommended settings for digitizer */ 3013 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ 3014 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */ 3015 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */ 3016 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */ 3017 { ADV76XX_REG(ADV76XX_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */ 3018 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */ 3019 3020 { ADV76XX_REG_SEQ_TERM, 0 }, 3021 }; 3022 3023 static const struct adv76xx_reg_seq adv7604_recommended_settings_hdmi[] = { 3024 /* set ADI recommended settings for HDMI: */ 3025 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ 3026 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */ 3027 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */ 3028 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */ 3029 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */ 3030 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */ 3031 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */ 3032 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */ 3033 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */ 3034 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */ 3035 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */ 3036 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */ 3037 3038 /* reset ADI recommended settings for digitizer */ 3039 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ 3040 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */ 3041 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */ 3042 3043 { ADV76XX_REG_SEQ_TERM, 0 }, 3044 }; 3045 3046 static const struct adv76xx_reg_seq adv7611_recommended_settings_hdmi[] = { 3047 /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */ 3048 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 }, 3049 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 }, 3050 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 }, 3051 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f }, 3052 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 }, 3053 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda }, 3054 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 }, 3055 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 }, 3056 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 }, 3057 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x04 }, 3058 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x1e }, 3059 3060 { ADV76XX_REG_SEQ_TERM, 0 }, 3061 }; 3062 3063 static const struct adv76xx_reg_seq adv7612_recommended_settings_hdmi[] = { 3064 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 }, 3065 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 }, 3066 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 }, 3067 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f }, 3068 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 }, 3069 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda }, 3070 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 }, 3071 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 }, 3072 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 }, 3073 { ADV76XX_REG_SEQ_TERM, 0 }, 3074 }; 3075 3076 static const struct adv76xx_chip_info adv76xx_chip_info[] = { 3077 [ADV7604] = { 3078 .type = ADV7604, 3079 .has_afe = true, 3080 .max_port = ADV7604_PAD_VGA_COMP, 3081 .num_dv_ports = 4, 3082 .edid_enable_reg = 0x77, 3083 .edid_status_reg = 0x7d, 3084 .edid_segment_reg = 0x77, 3085 .edid_segment_mask = 0x10, 3086 .edid_spa_loc_reg = 0x76, 3087 .edid_spa_loc_msb_mask = 0x40, 3088 .edid_spa_port_b_reg = 0x70, 3089 .lcf_reg = 0xb3, 3090 .tdms_lock_mask = 0xe0, 3091 .cable_det_mask = 0x1e, 3092 .fmt_change_digital_mask = 0xc1, 3093 .cp_csc = 0xfc, 3094 .cec_irq_status = 0x4d, 3095 .cec_rx_enable = 0x26, 3096 .cec_rx_enable_mask = 0x01, 3097 .cec_irq_swap = true, 3098 .formats = adv7604_formats, 3099 .nformats = ARRAY_SIZE(adv7604_formats), 3100 .set_termination = adv7604_set_termination, 3101 .setup_irqs = adv7604_setup_irqs, 3102 .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock, 3103 .read_cable_det = adv7604_read_cable_det, 3104 .recommended_settings = { 3105 [0] = adv7604_recommended_settings_afe, 3106 [1] = adv7604_recommended_settings_hdmi, 3107 }, 3108 .num_recommended_settings = { 3109 [0] = ARRAY_SIZE(adv7604_recommended_settings_afe), 3110 [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi), 3111 }, 3112 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) | 3113 BIT(ADV76XX_PAGE_CEC) | BIT(ADV76XX_PAGE_INFOFRAME) | 3114 BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) | 3115 BIT(ADV76XX_PAGE_AFE) | BIT(ADV76XX_PAGE_REP) | 3116 BIT(ADV76XX_PAGE_EDID) | BIT(ADV76XX_PAGE_HDMI) | 3117 BIT(ADV76XX_PAGE_TEST) | BIT(ADV76XX_PAGE_CP) | 3118 BIT(ADV7604_PAGE_VDP), 3119 .linewidth_mask = 0xfff, 3120 .field0_height_mask = 0xfff, 3121 .field1_height_mask = 0xfff, 3122 .hfrontporch_mask = 0x3ff, 3123 .hsync_mask = 0x3ff, 3124 .hbackporch_mask = 0x3ff, 3125 .field0_vfrontporch_mask = 0x1fff, 3126 .field0_vsync_mask = 0x1fff, 3127 .field0_vbackporch_mask = 0x1fff, 3128 .field1_vfrontporch_mask = 0x1fff, 3129 .field1_vsync_mask = 0x1fff, 3130 .field1_vbackporch_mask = 0x1fff, 3131 }, 3132 [ADV7611] = { 3133 .type = ADV7611, 3134 .has_afe = false, 3135 .max_port = ADV76XX_PAD_HDMI_PORT_A, 3136 .num_dv_ports = 1, 3137 .edid_enable_reg = 0x74, 3138 .edid_status_reg = 0x76, 3139 .edid_segment_reg = 0x7a, 3140 .edid_segment_mask = 0x01, 3141 .lcf_reg = 0xa3, 3142 .tdms_lock_mask = 0x43, 3143 .cable_det_mask = 0x01, 3144 .fmt_change_digital_mask = 0x03, 3145 .cp_csc = 0xf4, 3146 .cec_irq_status = 0x93, 3147 .cec_rx_enable = 0x2c, 3148 .cec_rx_enable_mask = 0x02, 3149 .formats = adv7611_formats, 3150 .nformats = ARRAY_SIZE(adv7611_formats), 3151 .set_termination = adv7611_set_termination, 3152 .setup_irqs = adv7611_setup_irqs, 3153 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock, 3154 .read_cable_det = adv7611_read_cable_det, 3155 .recommended_settings = { 3156 [1] = adv7611_recommended_settings_hdmi, 3157 }, 3158 .num_recommended_settings = { 3159 [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi), 3160 }, 3161 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) | 3162 BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) | 3163 BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) | 3164 BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP), 3165 .linewidth_mask = 0x1fff, 3166 .field0_height_mask = 0x1fff, 3167 .field1_height_mask = 0x1fff, 3168 .hfrontporch_mask = 0x1fff, 3169 .hsync_mask = 0x1fff, 3170 .hbackporch_mask = 0x1fff, 3171 .field0_vfrontporch_mask = 0x3fff, 3172 .field0_vsync_mask = 0x3fff, 3173 .field0_vbackporch_mask = 0x3fff, 3174 .field1_vfrontporch_mask = 0x3fff, 3175 .field1_vsync_mask = 0x3fff, 3176 .field1_vbackporch_mask = 0x3fff, 3177 }, 3178 [ADV7612] = { 3179 .type = ADV7612, 3180 .has_afe = false, 3181 .max_port = ADV76XX_PAD_HDMI_PORT_A, /* B not supported */ 3182 .num_dv_ports = 1, /* normally 2 */ 3183 .edid_enable_reg = 0x74, 3184 .edid_status_reg = 0x76, 3185 .edid_segment_reg = 0x7a, 3186 .edid_segment_mask = 0x01, 3187 .edid_spa_loc_reg = 0x70, 3188 .edid_spa_loc_msb_mask = 0x01, 3189 .edid_spa_port_b_reg = 0x52, 3190 .lcf_reg = 0xa3, 3191 .tdms_lock_mask = 0x43, 3192 .cable_det_mask = 0x01, 3193 .fmt_change_digital_mask = 0x03, 3194 .cp_csc = 0xf4, 3195 .cec_irq_status = 0x93, 3196 .cec_rx_enable = 0x2c, 3197 .cec_rx_enable_mask = 0x02, 3198 .formats = adv7612_formats, 3199 .nformats = ARRAY_SIZE(adv7612_formats), 3200 .set_termination = adv7611_set_termination, 3201 .setup_irqs = adv7612_setup_irqs, 3202 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock, 3203 .read_cable_det = adv7612_read_cable_det, 3204 .recommended_settings = { 3205 [1] = adv7612_recommended_settings_hdmi, 3206 }, 3207 .num_recommended_settings = { 3208 [1] = ARRAY_SIZE(adv7612_recommended_settings_hdmi), 3209 }, 3210 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) | 3211 BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) | 3212 BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) | 3213 BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP), 3214 .linewidth_mask = 0x1fff, 3215 .field0_height_mask = 0x1fff, 3216 .field1_height_mask = 0x1fff, 3217 .hfrontporch_mask = 0x1fff, 3218 .hsync_mask = 0x1fff, 3219 .hbackporch_mask = 0x1fff, 3220 .field0_vfrontporch_mask = 0x3fff, 3221 .field0_vsync_mask = 0x3fff, 3222 .field0_vbackporch_mask = 0x3fff, 3223 .field1_vfrontporch_mask = 0x3fff, 3224 .field1_vsync_mask = 0x3fff, 3225 .field1_vbackporch_mask = 0x3fff, 3226 }, 3227 }; 3228 3229 static const struct i2c_device_id adv76xx_i2c_id[] = { 3230 { "adv7604", (kernel_ulong_t)&adv76xx_chip_info[ADV7604] }, 3231 { "adv7610", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] }, 3232 { "adv7611", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] }, 3233 { "adv7612", (kernel_ulong_t)&adv76xx_chip_info[ADV7612] }, 3234 { } 3235 }; 3236 MODULE_DEVICE_TABLE(i2c, adv76xx_i2c_id); 3237 3238 static const struct of_device_id adv76xx_of_id[] __maybe_unused = { 3239 { .compatible = "adi,adv7610", .data = &adv76xx_chip_info[ADV7611] }, 3240 { .compatible = "adi,adv7611", .data = &adv76xx_chip_info[ADV7611] }, 3241 { .compatible = "adi,adv7612", .data = &adv76xx_chip_info[ADV7612] }, 3242 { } 3243 }; 3244 MODULE_DEVICE_TABLE(of, adv76xx_of_id); 3245 3246 static int adv76xx_parse_dt(struct adv76xx_state *state) 3247 { 3248 struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 }; 3249 struct device_node *endpoint; 3250 struct device_node *np; 3251 unsigned int flags; 3252 int ret; 3253 u32 v; 3254 3255 np = state->i2c_clients[ADV76XX_PAGE_IO]->dev.of_node; 3256 3257 /* FIXME: Parse the endpoint. */ 3258 endpoint = of_graph_get_endpoint_by_regs(np, -1, -1); 3259 if (!endpoint) 3260 return -EINVAL; 3261 3262 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint), &bus_cfg); 3263 of_node_put(endpoint); 3264 if (ret) 3265 return ret; 3266 3267 if (!of_property_read_u32(np, "default-input", &v)) 3268 state->pdata.default_input = v; 3269 else 3270 state->pdata.default_input = -1; 3271 3272 flags = bus_cfg.bus.parallel.flags; 3273 3274 if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) 3275 state->pdata.inv_hs_pol = 1; 3276 3277 if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) 3278 state->pdata.inv_vs_pol = 1; 3279 3280 if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING) 3281 state->pdata.inv_llc_pol = 1; 3282 3283 if (bus_cfg.bus_type == V4L2_MBUS_BT656) 3284 state->pdata.insert_av_codes = 1; 3285 3286 /* Disable the interrupt for now as no DT-based board uses it. */ 3287 state->pdata.int1_config = ADV76XX_INT1_CONFIG_ACTIVE_HIGH; 3288 3289 /* Hardcode the remaining platform data fields. */ 3290 state->pdata.disable_pwrdnb = 0; 3291 state->pdata.disable_cable_det_rst = 0; 3292 state->pdata.blank_data = 1; 3293 state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0; 3294 state->pdata.bus_order = ADV7604_BUS_ORDER_RGB; 3295 state->pdata.dr_str_data = ADV76XX_DR_STR_MEDIUM_HIGH; 3296 state->pdata.dr_str_clk = ADV76XX_DR_STR_MEDIUM_HIGH; 3297 state->pdata.dr_str_sync = ADV76XX_DR_STR_MEDIUM_HIGH; 3298 3299 return 0; 3300 } 3301 3302 static const struct regmap_config adv76xx_regmap_cnf[] = { 3303 { 3304 .name = "io", 3305 .reg_bits = 8, 3306 .val_bits = 8, 3307 3308 .max_register = 0xff, 3309 .cache_type = REGCACHE_NONE, 3310 }, 3311 { 3312 .name = "avlink", 3313 .reg_bits = 8, 3314 .val_bits = 8, 3315 3316 .max_register = 0xff, 3317 .cache_type = REGCACHE_NONE, 3318 }, 3319 { 3320 .name = "cec", 3321 .reg_bits = 8, 3322 .val_bits = 8, 3323 3324 .max_register = 0xff, 3325 .cache_type = REGCACHE_NONE, 3326 }, 3327 { 3328 .name = "infoframe", 3329 .reg_bits = 8, 3330 .val_bits = 8, 3331 3332 .max_register = 0xff, 3333 .cache_type = REGCACHE_NONE, 3334 }, 3335 { 3336 .name = "esdp", 3337 .reg_bits = 8, 3338 .val_bits = 8, 3339 3340 .max_register = 0xff, 3341 .cache_type = REGCACHE_NONE, 3342 }, 3343 { 3344 .name = "epp", 3345 .reg_bits = 8, 3346 .val_bits = 8, 3347 3348 .max_register = 0xff, 3349 .cache_type = REGCACHE_NONE, 3350 }, 3351 { 3352 .name = "afe", 3353 .reg_bits = 8, 3354 .val_bits = 8, 3355 3356 .max_register = 0xff, 3357 .cache_type = REGCACHE_NONE, 3358 }, 3359 { 3360 .name = "rep", 3361 .reg_bits = 8, 3362 .val_bits = 8, 3363 3364 .max_register = 0xff, 3365 .cache_type = REGCACHE_NONE, 3366 }, 3367 { 3368 .name = "edid", 3369 .reg_bits = 8, 3370 .val_bits = 8, 3371 3372 .max_register = 0xff, 3373 .cache_type = REGCACHE_NONE, 3374 }, 3375 3376 { 3377 .name = "hdmi", 3378 .reg_bits = 8, 3379 .val_bits = 8, 3380 3381 .max_register = 0xff, 3382 .cache_type = REGCACHE_NONE, 3383 }, 3384 { 3385 .name = "test", 3386 .reg_bits = 8, 3387 .val_bits = 8, 3388 3389 .max_register = 0xff, 3390 .cache_type = REGCACHE_NONE, 3391 }, 3392 { 3393 .name = "cp", 3394 .reg_bits = 8, 3395 .val_bits = 8, 3396 3397 .max_register = 0xff, 3398 .cache_type = REGCACHE_NONE, 3399 }, 3400 { 3401 .name = "vdp", 3402 .reg_bits = 8, 3403 .val_bits = 8, 3404 3405 .max_register = 0xff, 3406 .cache_type = REGCACHE_NONE, 3407 }, 3408 }; 3409 3410 static int configure_regmap(struct adv76xx_state *state, int region) 3411 { 3412 int err; 3413 3414 if (!state->i2c_clients[region]) 3415 return -ENODEV; 3416 3417 state->regmap[region] = 3418 devm_regmap_init_i2c(state->i2c_clients[region], 3419 &adv76xx_regmap_cnf[region]); 3420 3421 if (IS_ERR(state->regmap[region])) { 3422 err = PTR_ERR(state->regmap[region]); 3423 v4l_err(state->i2c_clients[region], 3424 "Error initializing regmap %d with error %d\n", 3425 region, err); 3426 return -EINVAL; 3427 } 3428 3429 return 0; 3430 } 3431 3432 static int configure_regmaps(struct adv76xx_state *state) 3433 { 3434 int i, err; 3435 3436 for (i = ADV7604_PAGE_AVLINK ; i < ADV76XX_PAGE_MAX; i++) { 3437 err = configure_regmap(state, i); 3438 if (err && (err != -ENODEV)) 3439 return err; 3440 } 3441 return 0; 3442 } 3443 3444 static void adv76xx_reset(struct adv76xx_state *state) 3445 { 3446 if (state->reset_gpio) { 3447 /* ADV76XX can be reset by a low reset pulse of minimum 5 ms. */ 3448 gpiod_set_value_cansleep(state->reset_gpio, 0); 3449 usleep_range(5000, 10000); 3450 gpiod_set_value_cansleep(state->reset_gpio, 1); 3451 /* It is recommended to wait 5 ms after the low pulse before */ 3452 /* an I2C write is performed to the ADV76XX. */ 3453 usleep_range(5000, 10000); 3454 } 3455 } 3456 3457 static int adv76xx_probe(struct i2c_client *client) 3458 { 3459 const struct i2c_device_id *id = i2c_client_get_device_id(client); 3460 static const struct v4l2_dv_timings cea640x480 = 3461 V4L2_DV_BT_CEA_640X480P59_94; 3462 struct adv76xx_state *state; 3463 struct v4l2_ctrl_handler *hdl; 3464 struct v4l2_ctrl *ctrl; 3465 struct v4l2_subdev *sd; 3466 unsigned int i; 3467 unsigned int val, val2; 3468 int err; 3469 3470 /* Check if the adapter supports the needed features */ 3471 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 3472 return -EIO; 3473 v4l_dbg(1, debug, client, "detecting adv76xx client on address 0x%x\n", 3474 client->addr << 1); 3475 3476 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); 3477 if (!state) 3478 return -ENOMEM; 3479 3480 state->i2c_clients[ADV76XX_PAGE_IO] = client; 3481 3482 /* initialize variables */ 3483 state->restart_stdi_once = true; 3484 state->selected_input = ~0; 3485 3486 if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) { 3487 const struct of_device_id *oid; 3488 3489 oid = of_match_node(adv76xx_of_id, client->dev.of_node); 3490 state->info = oid->data; 3491 3492 err = adv76xx_parse_dt(state); 3493 if (err < 0) { 3494 v4l_err(client, "DT parsing error\n"); 3495 return err; 3496 } 3497 } else if (client->dev.platform_data) { 3498 struct adv76xx_platform_data *pdata = client->dev.platform_data; 3499 3500 state->info = (const struct adv76xx_chip_info *)id->driver_data; 3501 state->pdata = *pdata; 3502 } else { 3503 v4l_err(client, "No platform data!\n"); 3504 return -ENODEV; 3505 } 3506 3507 /* Request GPIOs. */ 3508 for (i = 0; i < state->info->num_dv_ports; ++i) { 3509 state->hpd_gpio[i] = 3510 devm_gpiod_get_index_optional(&client->dev, "hpd", i, 3511 GPIOD_OUT_LOW); 3512 if (IS_ERR(state->hpd_gpio[i])) 3513 return PTR_ERR(state->hpd_gpio[i]); 3514 3515 if (state->hpd_gpio[i]) 3516 v4l_info(client, "Handling HPD %u GPIO\n", i); 3517 } 3518 state->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", 3519 GPIOD_OUT_HIGH); 3520 if (IS_ERR(state->reset_gpio)) 3521 return PTR_ERR(state->reset_gpio); 3522 3523 adv76xx_reset(state); 3524 3525 state->timings = cea640x480; 3526 state->format = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); 3527 3528 sd = &state->sd; 3529 v4l2_i2c_subdev_init(sd, client, &adv76xx_ops); 3530 snprintf(sd->name, sizeof(sd->name), "%s %d-%04x", 3531 id->name, i2c_adapter_id(client->adapter), 3532 client->addr); 3533 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; 3534 sd->internal_ops = &adv76xx_int_ops; 3535 3536 /* Configure IO Regmap region */ 3537 err = configure_regmap(state, ADV76XX_PAGE_IO); 3538 3539 if (err) { 3540 v4l2_err(sd, "Error configuring IO regmap region\n"); 3541 return -ENODEV; 3542 } 3543 3544 /* 3545 * Verify that the chip is present. On ADV7604 the RD_INFO register only 3546 * identifies the revision, while on ADV7611 it identifies the model as 3547 * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611. 3548 */ 3549 switch (state->info->type) { 3550 case ADV7604: 3551 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 0xfb, &val); 3552 if (err) { 3553 v4l2_err(sd, "Error %d reading IO Regmap\n", err); 3554 return -ENODEV; 3555 } 3556 if (val != 0x68) { 3557 v4l2_err(sd, "not an ADV7604 on address 0x%x\n", 3558 client->addr << 1); 3559 return -ENODEV; 3560 } 3561 break; 3562 case ADV7611: 3563 case ADV7612: 3564 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 3565 0xea, 3566 &val); 3567 if (err) { 3568 v4l2_err(sd, "Error %d reading IO Regmap\n", err); 3569 return -ENODEV; 3570 } 3571 val2 = val << 8; 3572 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 3573 0xeb, 3574 &val); 3575 if (err) { 3576 v4l2_err(sd, "Error %d reading IO Regmap\n", err); 3577 return -ENODEV; 3578 } 3579 val |= val2; 3580 if ((state->info->type == ADV7611 && val != 0x2051) || 3581 (state->info->type == ADV7612 && val != 0x2041)) { 3582 v4l2_err(sd, "not an %s on address 0x%x\n", 3583 state->info->type == ADV7611 ? "ADV7610/11" : "ADV7612", 3584 client->addr << 1); 3585 return -ENODEV; 3586 } 3587 break; 3588 } 3589 3590 /* control handlers */ 3591 hdl = &state->hdl; 3592 v4l2_ctrl_handler_init(hdl, adv76xx_has_afe(state) ? 9 : 8); 3593 3594 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, 3595 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0); 3596 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, 3597 V4L2_CID_CONTRAST, 0, 255, 1, 128); 3598 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, 3599 V4L2_CID_SATURATION, 0, 255, 1, 128); 3600 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, 3601 V4L2_CID_HUE, 0, 255, 1, 0); 3602 ctrl = v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops, 3603 V4L2_CID_DV_RX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC, 3604 0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC); 3605 if (ctrl) 3606 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE; 3607 3608 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, 3609 V4L2_CID_DV_RX_POWER_PRESENT, 0, 3610 (1 << state->info->num_dv_ports) - 1, 0, 0); 3611 state->rgb_quantization_range_ctrl = 3612 v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops, 3613 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL, 3614 0, V4L2_DV_RGB_RANGE_AUTO); 3615 3616 /* custom controls */ 3617 if (adv76xx_has_afe(state)) 3618 state->analog_sampling_phase_ctrl = 3619 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL); 3620 state->free_run_color_manual_ctrl = 3621 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color_manual, NULL); 3622 state->free_run_color_ctrl = 3623 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color, NULL); 3624 3625 sd->ctrl_handler = hdl; 3626 if (hdl->error) { 3627 err = hdl->error; 3628 goto err_hdl; 3629 } 3630 if (adv76xx_s_detect_tx_5v_ctrl(sd)) { 3631 err = -ENODEV; 3632 goto err_hdl; 3633 } 3634 3635 for (i = 1; i < ADV76XX_PAGE_MAX; ++i) { 3636 struct i2c_client *dummy_client; 3637 3638 if (!(BIT(i) & state->info->page_mask)) 3639 continue; 3640 3641 dummy_client = adv76xx_dummy_client(sd, i); 3642 if (IS_ERR(dummy_client)) { 3643 err = PTR_ERR(dummy_client); 3644 v4l2_err(sd, "failed to create i2c client %u\n", i); 3645 goto err_i2c; 3646 } 3647 3648 state->i2c_clients[i] = dummy_client; 3649 } 3650 3651 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, 3652 adv76xx_delayed_work_enable_hotplug); 3653 3654 state->source_pad = state->info->num_dv_ports 3655 + (state->info->has_afe ? 2 : 0); 3656 for (i = 0; i < state->source_pad; ++i) 3657 state->pads[i].flags = MEDIA_PAD_FL_SINK; 3658 state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE; 3659 sd->entity.function = MEDIA_ENT_F_DV_DECODER; 3660 3661 err = media_entity_pads_init(&sd->entity, state->source_pad + 1, 3662 state->pads); 3663 if (err) 3664 goto err_work_queues; 3665 3666 /* Configure regmaps */ 3667 err = configure_regmaps(state); 3668 if (err) 3669 goto err_entity; 3670 3671 err = adv76xx_core_init(sd); 3672 if (err) 3673 goto err_entity; 3674 3675 if (client->irq) { 3676 err = devm_request_threaded_irq(&client->dev, 3677 client->irq, 3678 NULL, adv76xx_irq_handler, 3679 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 3680 client->name, state); 3681 if (err) 3682 goto err_entity; 3683 } 3684 3685 #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC) 3686 state->cec_adap = cec_allocate_adapter(&adv76xx_cec_adap_ops, 3687 state, dev_name(&client->dev), 3688 CEC_CAP_DEFAULTS, ADV76XX_MAX_ADDRS); 3689 err = PTR_ERR_OR_ZERO(state->cec_adap); 3690 if (err) 3691 goto err_entity; 3692 #endif 3693 3694 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, 3695 client->addr << 1, client->adapter->name); 3696 3697 err = v4l2_async_register_subdev(sd); 3698 if (err) 3699 goto err_entity; 3700 3701 return 0; 3702 3703 err_entity: 3704 media_entity_cleanup(&sd->entity); 3705 err_work_queues: 3706 cancel_delayed_work(&state->delayed_work_enable_hotplug); 3707 err_i2c: 3708 adv76xx_unregister_clients(state); 3709 err_hdl: 3710 v4l2_ctrl_handler_free(hdl); 3711 return err; 3712 } 3713 3714 /* ----------------------------------------------------------------------- */ 3715 3716 static void adv76xx_remove(struct i2c_client *client) 3717 { 3718 struct v4l2_subdev *sd = i2c_get_clientdata(client); 3719 struct adv76xx_state *state = to_state(sd); 3720 3721 /* disable interrupts */ 3722 io_write(sd, 0x40, 0); 3723 io_write(sd, 0x41, 0); 3724 io_write(sd, 0x46, 0); 3725 io_write(sd, 0x6e, 0); 3726 io_write(sd, 0x73, 0); 3727 3728 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); 3729 v4l2_async_unregister_subdev(sd); 3730 media_entity_cleanup(&sd->entity); 3731 adv76xx_unregister_clients(to_state(sd)); 3732 v4l2_ctrl_handler_free(sd->ctrl_handler); 3733 } 3734 3735 /* ----------------------------------------------------------------------- */ 3736 3737 static struct i2c_driver adv76xx_driver = { 3738 .driver = { 3739 .name = "adv7604", 3740 .of_match_table = of_match_ptr(adv76xx_of_id), 3741 }, 3742 .probe = adv76xx_probe, 3743 .remove = adv76xx_remove, 3744 .id_table = adv76xx_i2c_id, 3745 }; 3746 3747 module_i2c_driver(adv76xx_driver); 3748