1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Driver for Analog Devices ADV748X video decoder and HDMI receiver 4 * 5 * Copyright (C) 2017 Renesas Electronics Corp. 6 * 7 * Authors: 8 * Koji Matsuoka <koji.matsuoka.xm@renesas.com> 9 * Niklas Söderlund <niklas.soderlund@ragnatech.se> 10 * Kieran Bingham <kieran.bingham@ideasonboard.com> 11 * 12 * The ADV748x range of receivers have the following configurations: 13 * 14 * Analog HDMI MHL 4-Lane 1-Lane 15 * In In CSI CSI 16 * ADV7480 X X X 17 * ADV7481 X X X X X 18 * ADV7482 X X X X 19 */ 20 21 #include <linux/i2c.h> 22 23 #ifndef _ADV748X_H_ 24 #define _ADV748X_H_ 25 26 enum adv748x_page { 27 ADV748X_PAGE_IO, 28 ADV748X_PAGE_DPLL, 29 ADV748X_PAGE_CP, 30 ADV748X_PAGE_HDMI, 31 ADV748X_PAGE_EDID, 32 ADV748X_PAGE_REPEATER, 33 ADV748X_PAGE_INFOFRAME, 34 ADV748X_PAGE_CBUS, 35 ADV748X_PAGE_CEC, 36 ADV748X_PAGE_SDP, 37 ADV748X_PAGE_TXB, 38 ADV748X_PAGE_TXA, 39 ADV748X_PAGE_MAX, 40 41 /* Fake pages for register sequences */ 42 ADV748X_PAGE_EOR, /* End Mark */ 43 }; 44 45 /* 46 * Device tree port number definitions 47 * 48 * The ADV748X ports define the mapping between subdevices 49 * and the device tree specification 50 */ 51 enum adv748x_ports { 52 ADV748X_PORT_AIN0 = 0, 53 ADV748X_PORT_AIN1 = 1, 54 ADV748X_PORT_AIN2 = 2, 55 ADV748X_PORT_AIN3 = 3, 56 ADV748X_PORT_AIN4 = 4, 57 ADV748X_PORT_AIN5 = 5, 58 ADV748X_PORT_AIN6 = 6, 59 ADV748X_PORT_AIN7 = 7, 60 ADV748X_PORT_HDMI = 8, 61 ADV748X_PORT_TTL = 9, 62 ADV748X_PORT_TXA = 10, 63 ADV748X_PORT_TXB = 11, 64 ADV748X_PORT_MAX = 12, 65 }; 66 67 enum adv748x_csi2_pads { 68 ADV748X_CSI2_SINK, 69 ADV748X_CSI2_SOURCE, 70 ADV748X_CSI2_NR_PADS, 71 }; 72 73 /* CSI2 transmitters can have 2 internal connections, HDMI/AFE */ 74 #define ADV748X_CSI2_MAX_SUBDEVS 2 75 76 struct adv748x_csi2 { 77 struct adv748x_state *state; 78 struct v4l2_mbus_framefmt format; 79 unsigned int page; 80 unsigned int port; 81 unsigned int num_lanes; 82 unsigned int active_lanes; 83 84 struct media_pad pads[ADV748X_CSI2_NR_PADS]; 85 struct v4l2_ctrl_handler ctrl_hdl; 86 struct v4l2_ctrl *pixel_rate; 87 struct v4l2_subdev *src; 88 struct v4l2_subdev sd; 89 }; 90 91 #define notifier_to_csi2(n) container_of(n, struct adv748x_csi2, notifier) 92 #define adv748x_sd_to_csi2(sd) container_of(sd, struct adv748x_csi2, sd) 93 94 #define is_tx_enabled(_tx) ((_tx)->state->endpoints[(_tx)->port] != NULL) 95 #define is_txa(_tx) ((_tx) == &(_tx)->state->txa) 96 #define is_txb(_tx) ((_tx) == &(_tx)->state->txb) 97 #define is_tx(_tx) (is_txa(_tx) || is_txb(_tx)) 98 99 #define is_afe_enabled(_state) \ 100 ((_state)->endpoints[ADV748X_PORT_AIN0] != NULL || \ 101 (_state)->endpoints[ADV748X_PORT_AIN1] != NULL || \ 102 (_state)->endpoints[ADV748X_PORT_AIN2] != NULL || \ 103 (_state)->endpoints[ADV748X_PORT_AIN3] != NULL || \ 104 (_state)->endpoints[ADV748X_PORT_AIN4] != NULL || \ 105 (_state)->endpoints[ADV748X_PORT_AIN5] != NULL || \ 106 (_state)->endpoints[ADV748X_PORT_AIN6] != NULL || \ 107 (_state)->endpoints[ADV748X_PORT_AIN7] != NULL) 108 #define is_hdmi_enabled(_state) ((_state)->endpoints[ADV748X_PORT_HDMI] != NULL) 109 110 enum adv748x_hdmi_pads { 111 ADV748X_HDMI_SINK, 112 ADV748X_HDMI_SOURCE, 113 ADV748X_HDMI_NR_PADS, 114 }; 115 116 struct adv748x_hdmi { 117 struct media_pad pads[ADV748X_HDMI_NR_PADS]; 118 struct v4l2_ctrl_handler ctrl_hdl; 119 struct v4l2_subdev sd; 120 struct v4l2_mbus_framefmt format; 121 122 struct v4l2_dv_timings timings; 123 struct v4l2_fract aspect_ratio; 124 125 struct adv748x_csi2 *tx; 126 127 struct { 128 u8 edid[512]; 129 u32 present; 130 unsigned int blocks; 131 } edid; 132 }; 133 134 #define adv748x_ctrl_to_hdmi(ctrl) \ 135 container_of(ctrl->handler, struct adv748x_hdmi, ctrl_hdl) 136 #define adv748x_sd_to_hdmi(sd) container_of(sd, struct adv748x_hdmi, sd) 137 138 enum adv748x_afe_pads { 139 ADV748X_AFE_SINK_AIN0, 140 ADV748X_AFE_SINK_AIN1, 141 ADV748X_AFE_SINK_AIN2, 142 ADV748X_AFE_SINK_AIN3, 143 ADV748X_AFE_SINK_AIN4, 144 ADV748X_AFE_SINK_AIN5, 145 ADV748X_AFE_SINK_AIN6, 146 ADV748X_AFE_SINK_AIN7, 147 ADV748X_AFE_SOURCE, 148 ADV748X_AFE_NR_PADS, 149 }; 150 151 struct adv748x_afe { 152 struct media_pad pads[ADV748X_AFE_NR_PADS]; 153 struct v4l2_ctrl_handler ctrl_hdl; 154 struct v4l2_subdev sd; 155 struct v4l2_mbus_framefmt format; 156 157 struct adv748x_csi2 *tx; 158 159 bool streaming; 160 v4l2_std_id curr_norm; 161 unsigned int input; 162 }; 163 164 #define adv748x_ctrl_to_afe(ctrl) \ 165 container_of(ctrl->handler, struct adv748x_afe, ctrl_hdl) 166 #define adv748x_sd_to_afe(sd) container_of(sd, struct adv748x_afe, sd) 167 168 /** 169 * struct adv748x_state - State of ADV748X 170 * @dev: (OF) device 171 * @client: I2C client 172 * @mutex: protect global state 173 * 174 * @endpoints: parsed device node endpoints for each port 175 * 176 * @i2c_addresses: I2C Page addresses 177 * @i2c_clients: I2C clients for the page accesses 178 * @regmap: regmap configuration pages. 179 * 180 * @hdmi: state of HDMI receiver context 181 * @afe: state of AFE receiver context 182 * @txa: state of TXA transmitter context 183 * @txb: state of TXB transmitter context 184 */ 185 struct adv748x_state { 186 struct device *dev; 187 struct i2c_client *client; 188 struct mutex mutex; 189 190 struct device_node *endpoints[ADV748X_PORT_MAX]; 191 192 struct i2c_client *i2c_clients[ADV748X_PAGE_MAX]; 193 struct regmap *regmap[ADV748X_PAGE_MAX]; 194 195 struct adv748x_hdmi hdmi; 196 struct adv748x_afe afe; 197 struct adv748x_csi2 txa; 198 struct adv748x_csi2 txb; 199 }; 200 201 #define adv748x_hdmi_to_state(h) container_of(h, struct adv748x_state, hdmi) 202 #define adv748x_afe_to_state(a) container_of(a, struct adv748x_state, afe) 203 204 #define adv_err(a, fmt, arg...) dev_err(a->dev, fmt, ##arg) 205 #define adv_info(a, fmt, arg...) dev_info(a->dev, fmt, ##arg) 206 #define adv_dbg(a, fmt, arg...) dev_dbg(a->dev, fmt, ##arg) 207 208 /* Register Mappings */ 209 210 /* IO Map */ 211 #define ADV748X_IO_PD 0x00 /* power down controls */ 212 #define ADV748X_IO_PD_RX_EN BIT(6) 213 214 #define ADV748X_IO_REG_01 0x01 /* pwrdn{2}b, prog_xtal_freq */ 215 #define ADV748X_IO_REG_01_PWRDN_MASK (BIT(7) | BIT(6)) 216 #define ADV748X_IO_REG_01_PWRDN2B BIT(7) /* CEC Wakeup Support */ 217 #define ADV748X_IO_REG_01_PWRDNB BIT(6) /* CEC Wakeup Support */ 218 219 #define ADV748X_IO_REG_04 0x04 220 #define ADV748X_IO_REG_04_FORCE_FR BIT(0) /* Force CP free-run */ 221 222 #define ADV748X_IO_DATAPATH 0x03 /* datapath cntrl */ 223 #define ADV748X_IO_DATAPATH_VFREQ_M 0x70 224 #define ADV748X_IO_DATAPATH_VFREQ_SHIFT 4 225 226 #define ADV748X_IO_VID_STD 0x05 227 228 #define ADV748X_IO_10 0x10 /* io_reg_10 */ 229 #define ADV748X_IO_10_CSI4_EN BIT(7) 230 #define ADV748X_IO_10_CSI1_EN BIT(6) 231 #define ADV748X_IO_10_PIX_OUT_EN BIT(5) 232 #define ADV748X_IO_10_CSI4_IN_SEL_AFE BIT(3) 233 234 #define ADV748X_IO_CHIP_REV_ID_1 0xdf 235 #define ADV748X_IO_CHIP_REV_ID_2 0xe0 236 237 #define ADV748X_IO_REG_F2 0xf2 238 #define ADV748X_IO_REG_F2_READ_AUTO_INC BIT(0) 239 240 /* For PAGE slave address offsets */ 241 #define ADV748X_IO_SLAVE_ADDR_BASE 0xf2 242 243 /* 244 * The ADV748x_Recommended_Settings_PrA_2014-08-20.pdf details both 0x80 and 245 * 0xff as examples for performing a software reset. 246 */ 247 #define ADV748X_IO_REG_FF 0xff 248 #define ADV748X_IO_REG_FF_MAIN_RESET 0xff 249 250 /* HDMI RX Map */ 251 #define ADV748X_HDMI_LW1 0x07 /* line width_1 */ 252 #define ADV748X_HDMI_LW1_VERT_FILTER BIT(7) 253 #define ADV748X_HDMI_LW1_DE_REGEN BIT(5) 254 #define ADV748X_HDMI_LW1_WIDTH_MASK 0x1fff 255 256 #define ADV748X_HDMI_F0H1 0x09 /* field0 height_1 */ 257 #define ADV748X_HDMI_F0H1_HEIGHT_MASK 0x1fff 258 259 #define ADV748X_HDMI_F1H1 0x0b /* field1 height_1 */ 260 #define ADV748X_HDMI_F1H1_INTERLACED BIT(5) 261 262 #define ADV748X_HDMI_HFRONT_PORCH 0x20 /* hsync_front_porch_1 */ 263 #define ADV748X_HDMI_HFRONT_PORCH_MASK 0x1fff 264 265 #define ADV748X_HDMI_HSYNC_WIDTH 0x22 /* hsync_pulse_width_1 */ 266 #define ADV748X_HDMI_HSYNC_WIDTH_MASK 0x1fff 267 268 #define ADV748X_HDMI_HBACK_PORCH 0x24 /* hsync_back_porch_1 */ 269 #define ADV748X_HDMI_HBACK_PORCH_MASK 0x1fff 270 271 #define ADV748X_HDMI_VFRONT_PORCH 0x2a /* field0_vs_front_porch_1 */ 272 #define ADV748X_HDMI_VFRONT_PORCH_MASK 0x3fff 273 274 #define ADV748X_HDMI_VSYNC_WIDTH 0x2e /* field0_vs_pulse_width_1 */ 275 #define ADV748X_HDMI_VSYNC_WIDTH_MASK 0x3fff 276 277 #define ADV748X_HDMI_VBACK_PORCH 0x32 /* field0_vs_back_porch_1 */ 278 #define ADV748X_HDMI_VBACK_PORCH_MASK 0x3fff 279 280 #define ADV748X_HDMI_TMDS_1 0x51 /* hdmi_reg_51 */ 281 #define ADV748X_HDMI_TMDS_2 0x52 /* hdmi_reg_52 */ 282 283 /* HDMI RX Repeater Map */ 284 #define ADV748X_REPEATER_EDID_SZ 0x70 /* primary_edid_size */ 285 #define ADV748X_REPEATER_EDID_SZ_SHIFT 4 286 287 #define ADV748X_REPEATER_EDID_CTL 0x74 /* hdcp edid controls */ 288 #define ADV748X_REPEATER_EDID_CTL_EN BIT(0) /* man_edid_a_enable */ 289 290 /* SDP Main Map */ 291 #define ADV748X_SDP_INSEL 0x00 /* user_map_rw_reg_00 */ 292 293 #define ADV748X_SDP_VID_SEL 0x02 /* user_map_rw_reg_02 */ 294 #define ADV748X_SDP_VID_SEL_MASK 0xf0 295 #define ADV748X_SDP_VID_SEL_SHIFT 4 296 297 /* Contrast - Unsigned*/ 298 #define ADV748X_SDP_CON 0x08 /* user_map_rw_reg_08 */ 299 #define ADV748X_SDP_CON_MIN 0 300 #define ADV748X_SDP_CON_DEF 128 301 #define ADV748X_SDP_CON_MAX 255 302 303 /* Brightness - Signed */ 304 #define ADV748X_SDP_BRI 0x0a /* user_map_rw_reg_0a */ 305 #define ADV748X_SDP_BRI_MIN -128 306 #define ADV748X_SDP_BRI_DEF 0 307 #define ADV748X_SDP_BRI_MAX 127 308 309 /* Hue - Signed, inverted*/ 310 #define ADV748X_SDP_HUE 0x0b /* user_map_rw_reg_0b */ 311 #define ADV748X_SDP_HUE_MIN -127 312 #define ADV748X_SDP_HUE_DEF 0 313 #define ADV748X_SDP_HUE_MAX 128 314 315 /* Test Patterns / Default Values */ 316 #define ADV748X_SDP_DEF 0x0c /* user_map_rw_reg_0c */ 317 #define ADV748X_SDP_DEF_VAL_EN BIT(0) /* Force free run mode */ 318 #define ADV748X_SDP_DEF_VAL_AUTO_EN BIT(1) /* Free run when no signal */ 319 320 #define ADV748X_SDP_MAP_SEL 0x0e /* user_map_rw_reg_0e */ 321 #define ADV748X_SDP_MAP_SEL_RO_MAIN 1 322 323 /* Free run pattern select */ 324 #define ADV748X_SDP_FRP 0x14 325 #define ADV748X_SDP_FRP_MASK GENMASK(3, 1) 326 327 /* Saturation */ 328 #define ADV748X_SDP_SD_SAT_U 0xe3 /* user_map_rw_reg_e3 */ 329 #define ADV748X_SDP_SD_SAT_V 0xe4 /* user_map_rw_reg_e4 */ 330 #define ADV748X_SDP_SAT_MIN 0 331 #define ADV748X_SDP_SAT_DEF 128 332 #define ADV748X_SDP_SAT_MAX 255 333 334 /* SDP RO Main Map */ 335 #define ADV748X_SDP_RO_10 0x10 336 #define ADV748X_SDP_RO_10_IN_LOCK BIT(0) 337 338 /* CP Map */ 339 #define ADV748X_CP_PAT_GEN 0x37 /* int_pat_gen_1 */ 340 #define ADV748X_CP_PAT_GEN_EN BIT(7) 341 342 /* Contrast Control - Unsigned */ 343 #define ADV748X_CP_CON 0x3a /* contrast_cntrl */ 344 #define ADV748X_CP_CON_MIN 0 /* Minimum contrast */ 345 #define ADV748X_CP_CON_DEF 128 /* Default */ 346 #define ADV748X_CP_CON_MAX 255 /* Maximum contrast */ 347 348 /* Saturation Control - Unsigned */ 349 #define ADV748X_CP_SAT 0x3b /* saturation_cntrl */ 350 #define ADV748X_CP_SAT_MIN 0 /* Minimum saturation */ 351 #define ADV748X_CP_SAT_DEF 128 /* Default */ 352 #define ADV748X_CP_SAT_MAX 255 /* Maximum saturation */ 353 354 /* Brightness Control - Signed */ 355 #define ADV748X_CP_BRI 0x3c /* brightness_cntrl */ 356 #define ADV748X_CP_BRI_MIN -128 /* Luma is -512d */ 357 #define ADV748X_CP_BRI_DEF 0 /* Luma is 0 */ 358 #define ADV748X_CP_BRI_MAX 127 /* Luma is 508d */ 359 360 /* Hue Control */ 361 #define ADV748X_CP_HUE 0x3d /* hue_cntrl */ 362 #define ADV748X_CP_HUE_MIN 0 /* -90 degree */ 363 #define ADV748X_CP_HUE_DEF 0 /* -90 degree */ 364 #define ADV748X_CP_HUE_MAX 255 /* +90 degree */ 365 366 #define ADV748X_CP_VID_ADJ 0x3e /* vid_adj_0 */ 367 #define ADV748X_CP_VID_ADJ_ENABLE BIT(7) /* Enable colour controls */ 368 369 #define ADV748X_CP_DE_POS_HIGH 0x8b /* de_pos_adj_6 */ 370 #define ADV748X_CP_DE_POS_HIGH_SET BIT(6) 371 #define ADV748X_CP_DE_POS_END_LOW 0x8c /* de_pos_adj_7 */ 372 #define ADV748X_CP_DE_POS_START_LOW 0x8d /* de_pos_adj_8 */ 373 374 #define ADV748X_CP_VID_ADJ_2 0x91 375 #define ADV748X_CP_VID_ADJ_2_INTERLACED BIT(6) 376 #define ADV748X_CP_VID_ADJ_2_INTERLACED_3D BIT(4) 377 378 #define ADV748X_CP_CLMP_POS 0xc9 /* clmp_pos_cntrl_4 */ 379 #define ADV748X_CP_CLMP_POS_DIS_AUTO BIT(0) /* dis_auto_param_buff */ 380 381 /* CSI : TXA/TXB Maps */ 382 #define ADV748X_CSI_VC_REF 0x0d /* csi_tx_top_reg_0d */ 383 #define ADV748X_CSI_VC_REF_SHIFT 6 384 385 #define ADV748X_CSI_FS_AS_LS 0x1e /* csi_tx_top_reg_1e */ 386 #define ADV748X_CSI_FS_AS_LS_UNKNOWN BIT(6) /* Undocumented bit */ 387 388 /* Register handling */ 389 390 int adv748x_read(struct adv748x_state *state, u8 addr, u8 reg); 391 int adv748x_write(struct adv748x_state *state, u8 page, u8 reg, u8 value); 392 int adv748x_write_block(struct adv748x_state *state, int client_page, 393 unsigned int init_reg, const void *val, 394 size_t val_len); 395 396 #define io_read(s, r) adv748x_read(s, ADV748X_PAGE_IO, r) 397 #define io_write(s, r, v) adv748x_write(s, ADV748X_PAGE_IO, r, v) 398 #define io_clrset(s, r, m, v) io_write(s, r, (io_read(s, r) & ~(m)) | (v)) 399 400 #define hdmi_read(s, r) adv748x_read(s, ADV748X_PAGE_HDMI, r) 401 #define hdmi_read16(s, r, m) (((hdmi_read(s, r) << 8) | hdmi_read(s, (r)+1)) & (m)) 402 #define hdmi_write(s, r, v) adv748x_write(s, ADV748X_PAGE_HDMI, r, v) 403 404 #define repeater_read(s, r) adv748x_read(s, ADV748X_PAGE_REPEATER, r) 405 #define repeater_write(s, r, v) adv748x_write(s, ADV748X_PAGE_REPEATER, r, v) 406 407 #define sdp_read(s, r) adv748x_read(s, ADV748X_PAGE_SDP, r) 408 #define sdp_write(s, r, v) adv748x_write(s, ADV748X_PAGE_SDP, r, v) 409 #define sdp_clrset(s, r, m, v) sdp_write(s, r, (sdp_read(s, r) & ~(m)) | (v)) 410 411 #define cp_read(s, r) adv748x_read(s, ADV748X_PAGE_CP, r) 412 #define cp_write(s, r, v) adv748x_write(s, ADV748X_PAGE_CP, r, v) 413 #define cp_clrset(s, r, m, v) cp_write(s, r, (cp_read(s, r) & ~(m)) | (v)) 414 415 #define tx_read(t, r) adv748x_read(t->state, t->page, r) 416 #define tx_write(t, r, v) adv748x_write(t->state, t->page, r, v) 417 418 static inline struct v4l2_subdev *adv748x_get_remote_sd(struct media_pad *pad) 419 { 420 pad = media_pad_remote_pad_first(pad); 421 if (!pad) 422 return NULL; 423 424 return media_entity_to_v4l2_subdev(pad->entity); 425 } 426 427 void adv748x_subdev_init(struct v4l2_subdev *sd, struct adv748x_state *state, 428 const struct v4l2_subdev_ops *ops, u32 function, 429 const char *ident); 430 431 int adv748x_tx_power(struct adv748x_csi2 *tx, bool on); 432 433 int adv748x_afe_init(struct adv748x_afe *afe); 434 void adv748x_afe_cleanup(struct adv748x_afe *afe); 435 int adv748x_afe_s_input(struct adv748x_afe *afe, unsigned int input); 436 437 int adv748x_csi2_init(struct adv748x_state *state, struct adv748x_csi2 *tx); 438 void adv748x_csi2_cleanup(struct adv748x_csi2 *tx); 439 int adv748x_csi2_set_virtual_channel(struct adv748x_csi2 *tx, unsigned int vc); 440 int adv748x_csi2_set_pixelrate(struct v4l2_subdev *sd, s64 rate); 441 442 int adv748x_hdmi_init(struct adv748x_hdmi *hdmi); 443 void adv748x_hdmi_cleanup(struct adv748x_hdmi *hdmi); 444 445 #endif /* _ADV748X_H_ */ 446