1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * adv7180.c Analog Devices ADV7180 video decoder driver 4 * Copyright (c) 2009 Intel Corporation 5 * Copyright (C) 2013 Cogent Embedded, Inc. 6 * Copyright (C) 2013 Renesas Solutions Corp. 7 */ 8 #include <linux/mod_devicetable.h> 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/errno.h> 12 #include <linux/kernel.h> 13 #include <linux/interrupt.h> 14 #include <linux/i2c.h> 15 #include <linux/slab.h> 16 #include <linux/of.h> 17 #include <linux/gpio/consumer.h> 18 #include <linux/videodev2.h> 19 #include <media/v4l2-ioctl.h> 20 #include <media/v4l2-event.h> 21 #include <media/v4l2-device.h> 22 #include <media/v4l2-ctrls.h> 23 #include <linux/mutex.h> 24 #include <linux/delay.h> 25 26 #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM 0x0 27 #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM_PED 0x1 28 #define ADV7180_STD_AD_PAL_N_NTSC_J_SECAM 0x2 29 #define ADV7180_STD_AD_PAL_N_NTSC_M_SECAM 0x3 30 #define ADV7180_STD_NTSC_J 0x4 31 #define ADV7180_STD_NTSC_M 0x5 32 #define ADV7180_STD_PAL60 0x6 33 #define ADV7180_STD_NTSC_443 0x7 34 #define ADV7180_STD_PAL_BG 0x8 35 #define ADV7180_STD_PAL_N 0x9 36 #define ADV7180_STD_PAL_M 0xa 37 #define ADV7180_STD_PAL_M_PED 0xb 38 #define ADV7180_STD_PAL_COMB_N 0xc 39 #define ADV7180_STD_PAL_COMB_N_PED 0xd 40 #define ADV7180_STD_PAL_SECAM 0xe 41 #define ADV7180_STD_PAL_SECAM_PED 0xf 42 43 #define ADV7180_REG_INPUT_CONTROL 0x0000 44 #define ADV7180_INPUT_CONTROL_INSEL_MASK 0x0f 45 46 #define ADV7182_REG_INPUT_VIDSEL 0x0002 47 #define ADV7182_REG_INPUT_RESERVED BIT(2) 48 49 #define ADV7180_REG_OUTPUT_CONTROL 0x0003 50 #define ADV7180_REG_EXTENDED_OUTPUT_CONTROL 0x0004 51 #define ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS 0xC5 52 53 #define ADV7180_REG_AUTODETECT_ENABLE 0x0007 54 #define ADV7180_AUTODETECT_DEFAULT 0x7f 55 /* Contrast */ 56 #define ADV7180_REG_CON 0x0008 /*Unsigned */ 57 #define ADV7180_CON_MIN 0 58 #define ADV7180_CON_DEF 128 59 #define ADV7180_CON_MAX 255 60 /* Brightness*/ 61 #define ADV7180_REG_BRI 0x000a /*Signed */ 62 #define ADV7180_BRI_MIN -128 63 #define ADV7180_BRI_DEF 0 64 #define ADV7180_BRI_MAX 127 65 /* Hue */ 66 #define ADV7180_REG_HUE 0x000b /*Signed, inverted */ 67 #define ADV7180_HUE_MIN -127 68 #define ADV7180_HUE_DEF 0 69 #define ADV7180_HUE_MAX 128 70 71 #define ADV7180_REG_DEF_VALUE_Y 0x000c 72 #define ADV7180_DEF_VAL_EN 0x1 73 #define ADV7180_DEF_VAL_AUTO_EN 0x2 74 #define ADV7180_REG_CTRL 0x000e 75 #define ADV7180_CTRL_IRQ_SPACE 0x20 76 77 #define ADV7180_REG_PWR_MAN 0x0f 78 #define ADV7180_PWR_MAN_ON 0x04 79 #define ADV7180_PWR_MAN_OFF 0x24 80 #define ADV7180_PWR_MAN_RES 0x80 81 82 #define ADV7180_REG_STATUS1 0x0010 83 #define ADV7180_STATUS1_IN_LOCK 0x01 84 #define ADV7180_STATUS1_AUTOD_MASK 0x70 85 #define ADV7180_STATUS1_AUTOD_NTSM_M_J 0x00 86 #define ADV7180_STATUS1_AUTOD_NTSC_4_43 0x10 87 #define ADV7180_STATUS1_AUTOD_PAL_M 0x20 88 #define ADV7180_STATUS1_AUTOD_PAL_60 0x30 89 #define ADV7180_STATUS1_AUTOD_PAL_B_G 0x40 90 #define ADV7180_STATUS1_AUTOD_SECAM 0x50 91 #define ADV7180_STATUS1_AUTOD_PAL_COMB 0x60 92 #define ADV7180_STATUS1_AUTOD_SECAM_525 0x70 93 94 #define ADV7180_REG_IDENT 0x0011 95 #define ADV7180_ID_7180 0x18 96 97 #define ADV7180_REG_STATUS3 0x0013 98 #define ADV7180_REG_ANALOG_CLAMP_CTL 0x0014 99 #define ADV7180_REG_SHAP_FILTER_CTL_1 0x0017 100 #define ADV7180_REG_CTRL_2 0x001d 101 #define ADV7180_REG_VSYNC_FIELD_CTL_1 0x0031 102 #define ADV7180_VSYNC_FIELD_CTL_1_NEWAV 0x12 103 #define ADV7180_REG_MANUAL_WIN_CTL_1 0x003d 104 #define ADV7180_REG_MANUAL_WIN_CTL_2 0x003e 105 #define ADV7180_REG_MANUAL_WIN_CTL_3 0x003f 106 #define ADV7180_REG_LOCK_CNT 0x0051 107 #define ADV7180_REG_CVBS_TRIM 0x0052 108 #define ADV7180_REG_CLAMP_ADJ 0x005a 109 #define ADV7180_REG_RES_CIR 0x005f 110 #define ADV7180_REG_DIFF_MODE 0x0060 111 112 #define ADV7180_REG_ICONF1 0x2040 113 #define ADV7180_ICONF1_ACTIVE_LOW 0x01 114 #define ADV7180_ICONF1_PSYNC_ONLY 0x10 115 #define ADV7180_ICONF1_ACTIVE_TO_CLR 0xC0 116 /* Saturation */ 117 #define ADV7180_REG_SD_SAT_CB 0x00e3 /*Unsigned */ 118 #define ADV7180_REG_SD_SAT_CR 0x00e4 /*Unsigned */ 119 #define ADV7180_SAT_MIN 0 120 #define ADV7180_SAT_DEF 128 121 #define ADV7180_SAT_MAX 255 122 123 #define ADV7180_IRQ1_LOCK 0x01 124 #define ADV7180_IRQ1_UNLOCK 0x02 125 #define ADV7180_REG_ISR1 0x2042 126 #define ADV7180_REG_ICR1 0x2043 127 #define ADV7180_REG_IMR1 0x2044 128 #define ADV7180_REG_IMR2 0x2048 129 #define ADV7180_IRQ3_AD_CHANGE 0x08 130 #define ADV7180_REG_ISR3 0x204A 131 #define ADV7180_REG_ICR3 0x204B 132 #define ADV7180_REG_IMR3 0x204C 133 #define ADV7180_REG_IMR4 0x2050 134 135 #define ADV7180_REG_NTSC_V_BIT_END 0x00E6 136 #define ADV7180_NTSC_V_BIT_END_MANUAL_NVEND 0x4F 137 138 #define ADV7180_REG_VPP_SLAVE_ADDR 0xFD 139 #define ADV7180_REG_CSI_SLAVE_ADDR 0xFE 140 141 #define ADV7180_REG_ACE_CTRL1 0x4080 142 #define ADV7180_REG_ACE_CTRL5 0x4084 143 #define ADV7180_REG_FLCONTROL 0x40e0 144 #define ADV7180_FLCONTROL_FL_ENABLE 0x1 145 146 #define ADV7180_REG_RST_CLAMP 0x809c 147 #define ADV7180_REG_AGC_ADJ1 0x80b6 148 #define ADV7180_REG_AGC_ADJ2 0x80c0 149 150 #define ADV7180_CSI_REG_PWRDN 0x00 151 #define ADV7180_CSI_PWRDN 0x80 152 153 #define ADV7180_INPUT_CVBS_AIN1 0x00 154 #define ADV7180_INPUT_CVBS_AIN2 0x01 155 #define ADV7180_INPUT_CVBS_AIN3 0x02 156 #define ADV7180_INPUT_CVBS_AIN4 0x03 157 #define ADV7180_INPUT_CVBS_AIN5 0x04 158 #define ADV7180_INPUT_CVBS_AIN6 0x05 159 #define ADV7180_INPUT_SVIDEO_AIN1_AIN2 0x06 160 #define ADV7180_INPUT_SVIDEO_AIN3_AIN4 0x07 161 #define ADV7180_INPUT_SVIDEO_AIN5_AIN6 0x08 162 #define ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3 0x09 163 #define ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0a 164 165 #define ADV7182_INPUT_CVBS_AIN1 0x00 166 #define ADV7182_INPUT_CVBS_AIN2 0x01 167 #define ADV7182_INPUT_CVBS_AIN3 0x02 168 #define ADV7182_INPUT_CVBS_AIN4 0x03 169 #define ADV7182_INPUT_CVBS_AIN5 0x04 170 #define ADV7182_INPUT_CVBS_AIN6 0x05 171 #define ADV7182_INPUT_CVBS_AIN7 0x06 172 #define ADV7182_INPUT_CVBS_AIN8 0x07 173 #define ADV7182_INPUT_SVIDEO_AIN1_AIN2 0x08 174 #define ADV7182_INPUT_SVIDEO_AIN3_AIN4 0x09 175 #define ADV7182_INPUT_SVIDEO_AIN5_AIN6 0x0a 176 #define ADV7182_INPUT_SVIDEO_AIN7_AIN8 0x0b 177 #define ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3 0x0c 178 #define ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0d 179 #define ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2 0x0e 180 #define ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4 0x0f 181 #define ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6 0x10 182 #define ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8 0x11 183 184 #define ADV7180_DEFAULT_CSI_I2C_ADDR 0x44 185 #define ADV7180_DEFAULT_VPP_I2C_ADDR 0x42 186 187 #define V4L2_CID_ADV_FAST_SWITCH (V4L2_CID_USER_ADV7180_BASE + 0x00) 188 189 /* Initial number of frames to skip to avoid possible garbage */ 190 #define ADV7180_NUM_OF_SKIP_FRAMES 2 191 192 struct adv7180_state; 193 194 #define ADV7180_FLAG_RESET_POWERED BIT(0) 195 #define ADV7180_FLAG_V2 BIT(1) 196 #define ADV7180_FLAG_MIPI_CSI2 BIT(2) 197 #define ADV7180_FLAG_I2P BIT(3) 198 199 struct adv7180_chip_info { 200 unsigned int flags; 201 unsigned int valid_input_mask; 202 int (*set_std)(struct adv7180_state *st, unsigned int std); 203 int (*select_input)(struct adv7180_state *st, unsigned int input); 204 int (*init)(struct adv7180_state *state); 205 }; 206 207 struct adv7180_state { 208 struct v4l2_ctrl_handler ctrl_hdl; 209 struct v4l2_subdev sd; 210 struct media_pad pad; 211 struct mutex mutex; /* mutual excl. when accessing chip */ 212 int irq; 213 struct gpio_desc *pwdn_gpio; 214 struct gpio_desc *rst_gpio; 215 v4l2_std_id curr_norm; 216 bool powered; 217 bool streaming; 218 u8 input; 219 220 struct i2c_client *client; 221 unsigned int register_page; 222 struct i2c_client *csi_client; 223 struct i2c_client *vpp_client; 224 const struct adv7180_chip_info *chip_info; 225 enum v4l2_field field; 226 bool force_bt656_4; 227 }; 228 #define to_adv7180_sd(_ctrl) (&container_of(_ctrl->handler, \ 229 struct adv7180_state, \ 230 ctrl_hdl)->sd) 231 232 static int adv7180_select_page(struct adv7180_state *state, unsigned int page) 233 { 234 if (state->register_page != page) { 235 i2c_smbus_write_byte_data(state->client, ADV7180_REG_CTRL, 236 page); 237 state->register_page = page; 238 } 239 240 return 0; 241 } 242 243 static int adv7180_write(struct adv7180_state *state, unsigned int reg, 244 unsigned int value) 245 { 246 lockdep_assert_held(&state->mutex); 247 adv7180_select_page(state, reg >> 8); 248 return i2c_smbus_write_byte_data(state->client, reg & 0xff, value); 249 } 250 251 static int adv7180_read(struct adv7180_state *state, unsigned int reg) 252 { 253 lockdep_assert_held(&state->mutex); 254 adv7180_select_page(state, reg >> 8); 255 return i2c_smbus_read_byte_data(state->client, reg & 0xff); 256 } 257 258 static int adv7180_csi_write(struct adv7180_state *state, unsigned int reg, 259 unsigned int value) 260 { 261 return i2c_smbus_write_byte_data(state->csi_client, reg, value); 262 } 263 264 static int adv7180_set_video_standard(struct adv7180_state *state, 265 unsigned int std) 266 { 267 return state->chip_info->set_std(state, std); 268 } 269 270 static int adv7180_vpp_write(struct adv7180_state *state, unsigned int reg, 271 unsigned int value) 272 { 273 return i2c_smbus_write_byte_data(state->vpp_client, reg, value); 274 } 275 276 static v4l2_std_id adv7180_std_to_v4l2(u8 status1) 277 { 278 /* in case V4L2_IN_ST_NO_SIGNAL */ 279 if (!(status1 & ADV7180_STATUS1_IN_LOCK)) 280 return V4L2_STD_UNKNOWN; 281 282 switch (status1 & ADV7180_STATUS1_AUTOD_MASK) { 283 case ADV7180_STATUS1_AUTOD_NTSM_M_J: 284 return V4L2_STD_NTSC; 285 case ADV7180_STATUS1_AUTOD_NTSC_4_43: 286 return V4L2_STD_NTSC_443; 287 case ADV7180_STATUS1_AUTOD_PAL_M: 288 return V4L2_STD_PAL_M; 289 case ADV7180_STATUS1_AUTOD_PAL_60: 290 return V4L2_STD_PAL_60; 291 case ADV7180_STATUS1_AUTOD_PAL_B_G: 292 return V4L2_STD_PAL; 293 case ADV7180_STATUS1_AUTOD_SECAM: 294 return V4L2_STD_SECAM; 295 case ADV7180_STATUS1_AUTOD_PAL_COMB: 296 return V4L2_STD_PAL_Nc | V4L2_STD_PAL_N; 297 case ADV7180_STATUS1_AUTOD_SECAM_525: 298 return V4L2_STD_SECAM; 299 default: 300 return V4L2_STD_UNKNOWN; 301 } 302 } 303 304 static int v4l2_std_to_adv7180(v4l2_std_id std) 305 { 306 if (std == V4L2_STD_PAL_60) 307 return ADV7180_STD_PAL60; 308 if (std == V4L2_STD_NTSC_443) 309 return ADV7180_STD_NTSC_443; 310 if (std == V4L2_STD_PAL_N) 311 return ADV7180_STD_PAL_N; 312 if (std == V4L2_STD_PAL_M) 313 return ADV7180_STD_PAL_M; 314 if (std == V4L2_STD_PAL_Nc) 315 return ADV7180_STD_PAL_COMB_N; 316 317 if (std & V4L2_STD_PAL) 318 return ADV7180_STD_PAL_BG; 319 if (std & V4L2_STD_NTSC) 320 return ADV7180_STD_NTSC_M; 321 if (std & V4L2_STD_SECAM) 322 return ADV7180_STD_PAL_SECAM; 323 324 return -EINVAL; 325 } 326 327 static u32 adv7180_status_to_v4l2(u8 status1) 328 { 329 if (!(status1 & ADV7180_STATUS1_IN_LOCK)) 330 return V4L2_IN_ST_NO_SIGNAL; 331 332 return 0; 333 } 334 335 static int __adv7180_status(struct adv7180_state *state, u32 *status, 336 v4l2_std_id *std) 337 { 338 int status1 = adv7180_read(state, ADV7180_REG_STATUS1); 339 340 if (status1 < 0) 341 return status1; 342 343 if (status) 344 *status = adv7180_status_to_v4l2(status1); 345 if (std) 346 *std = adv7180_std_to_v4l2(status1); 347 348 return 0; 349 } 350 351 static inline struct adv7180_state *to_state(struct v4l2_subdev *sd) 352 { 353 return container_of(sd, struct adv7180_state, sd); 354 } 355 356 static int adv7180_querystd(struct v4l2_subdev *sd, v4l2_std_id *std) 357 { 358 struct adv7180_state *state = to_state(sd); 359 int err = mutex_lock_interruptible(&state->mutex); 360 if (err) 361 return err; 362 363 if (state->streaming) { 364 err = -EBUSY; 365 goto unlock; 366 } 367 368 err = adv7180_set_video_standard(state, 369 ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM); 370 if (err) 371 goto unlock; 372 373 msleep(100); 374 __adv7180_status(state, NULL, std); 375 376 err = v4l2_std_to_adv7180(state->curr_norm); 377 if (err < 0) 378 goto unlock; 379 380 err = adv7180_set_video_standard(state, err); 381 382 unlock: 383 mutex_unlock(&state->mutex); 384 return err; 385 } 386 387 static int adv7180_s_routing(struct v4l2_subdev *sd, u32 input, 388 u32 output, u32 config) 389 { 390 struct adv7180_state *state = to_state(sd); 391 int ret = mutex_lock_interruptible(&state->mutex); 392 393 if (ret) 394 return ret; 395 396 if (input > 31 || !(BIT(input) & state->chip_info->valid_input_mask)) { 397 ret = -EINVAL; 398 goto out; 399 } 400 401 ret = state->chip_info->select_input(state, input); 402 403 if (ret == 0) 404 state->input = input; 405 out: 406 mutex_unlock(&state->mutex); 407 return ret; 408 } 409 410 static int adv7180_g_input_status(struct v4l2_subdev *sd, u32 *status) 411 { 412 struct adv7180_state *state = to_state(sd); 413 int ret = mutex_lock_interruptible(&state->mutex); 414 if (ret) 415 return ret; 416 417 ret = __adv7180_status(state, status, NULL); 418 mutex_unlock(&state->mutex); 419 return ret; 420 } 421 422 static int adv7180_program_std(struct adv7180_state *state) 423 { 424 int ret; 425 426 ret = v4l2_std_to_adv7180(state->curr_norm); 427 if (ret < 0) 428 return ret; 429 430 ret = adv7180_set_video_standard(state, ret); 431 if (ret < 0) 432 return ret; 433 return 0; 434 } 435 436 static int adv7180_s_std(struct v4l2_subdev *sd, v4l2_std_id std) 437 { 438 struct adv7180_state *state = to_state(sd); 439 int ret = mutex_lock_interruptible(&state->mutex); 440 441 if (ret) 442 return ret; 443 444 /* Make sure we can support this std */ 445 ret = v4l2_std_to_adv7180(std); 446 if (ret < 0) 447 goto out; 448 449 state->curr_norm = std; 450 451 ret = adv7180_program_std(state); 452 out: 453 mutex_unlock(&state->mutex); 454 return ret; 455 } 456 457 static int adv7180_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm) 458 { 459 struct adv7180_state *state = to_state(sd); 460 461 *norm = state->curr_norm; 462 463 return 0; 464 } 465 466 static int adv7180_g_frame_interval(struct v4l2_subdev *sd, 467 struct v4l2_subdev_frame_interval *fi) 468 { 469 struct adv7180_state *state = to_state(sd); 470 471 if (state->curr_norm & V4L2_STD_525_60) { 472 fi->interval.numerator = 1001; 473 fi->interval.denominator = 30000; 474 } else { 475 fi->interval.numerator = 1; 476 fi->interval.denominator = 25; 477 } 478 479 return 0; 480 } 481 482 static void adv7180_set_power_pin(struct adv7180_state *state, bool on) 483 { 484 if (!state->pwdn_gpio) 485 return; 486 487 if (on) { 488 gpiod_set_value_cansleep(state->pwdn_gpio, 0); 489 usleep_range(5000, 10000); 490 } else { 491 gpiod_set_value_cansleep(state->pwdn_gpio, 1); 492 } 493 } 494 495 static void adv7180_set_reset_pin(struct adv7180_state *state, bool on) 496 { 497 if (!state->rst_gpio) 498 return; 499 500 if (on) { 501 gpiod_set_value_cansleep(state->rst_gpio, 1); 502 } else { 503 gpiod_set_value_cansleep(state->rst_gpio, 0); 504 usleep_range(5000, 10000); 505 } 506 } 507 508 static int adv7180_set_power(struct adv7180_state *state, bool on) 509 { 510 u8 val; 511 int ret; 512 513 if (on) 514 val = ADV7180_PWR_MAN_ON; 515 else 516 val = ADV7180_PWR_MAN_OFF; 517 518 ret = adv7180_write(state, ADV7180_REG_PWR_MAN, val); 519 if (ret) 520 return ret; 521 522 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 523 if (on) { 524 adv7180_csi_write(state, 0xDE, 0x02); 525 adv7180_csi_write(state, 0xD2, 0xF7); 526 adv7180_csi_write(state, 0xD8, 0x65); 527 adv7180_csi_write(state, 0xE0, 0x09); 528 adv7180_csi_write(state, 0x2C, 0x00); 529 if (state->field == V4L2_FIELD_NONE) 530 adv7180_csi_write(state, 0x1D, 0x80); 531 adv7180_csi_write(state, 0x00, 0x00); 532 } else { 533 adv7180_csi_write(state, 0x00, 0x80); 534 } 535 } 536 537 return 0; 538 } 539 540 static int adv7180_s_power(struct v4l2_subdev *sd, int on) 541 { 542 struct adv7180_state *state = to_state(sd); 543 int ret; 544 545 ret = mutex_lock_interruptible(&state->mutex); 546 if (ret) 547 return ret; 548 549 ret = adv7180_set_power(state, on); 550 if (ret == 0) 551 state->powered = on; 552 553 mutex_unlock(&state->mutex); 554 return ret; 555 } 556 557 static const char * const test_pattern_menu[] = { 558 "Single color", 559 "Color bars", 560 "Luma ramp", 561 "Boundary box", 562 "Disable", 563 }; 564 565 static int adv7180_test_pattern(struct adv7180_state *state, int value) 566 { 567 unsigned int reg = 0; 568 569 /* Map menu value into register value */ 570 if (value < 3) 571 reg = value; 572 if (value == 3) 573 reg = 5; 574 575 adv7180_write(state, ADV7180_REG_ANALOG_CLAMP_CTL, reg); 576 577 if (value == ARRAY_SIZE(test_pattern_menu) - 1) { 578 reg = adv7180_read(state, ADV7180_REG_DEF_VALUE_Y); 579 reg &= ~ADV7180_DEF_VAL_EN; 580 adv7180_write(state, ADV7180_REG_DEF_VALUE_Y, reg); 581 return 0; 582 } 583 584 reg = adv7180_read(state, ADV7180_REG_DEF_VALUE_Y); 585 reg |= ADV7180_DEF_VAL_EN | ADV7180_DEF_VAL_AUTO_EN; 586 adv7180_write(state, ADV7180_REG_DEF_VALUE_Y, reg); 587 588 return 0; 589 } 590 591 static int adv7180_s_ctrl(struct v4l2_ctrl *ctrl) 592 { 593 struct v4l2_subdev *sd = to_adv7180_sd(ctrl); 594 struct adv7180_state *state = to_state(sd); 595 int ret = mutex_lock_interruptible(&state->mutex); 596 int val; 597 598 if (ret) 599 return ret; 600 val = ctrl->val; 601 switch (ctrl->id) { 602 case V4L2_CID_BRIGHTNESS: 603 ret = adv7180_write(state, ADV7180_REG_BRI, val); 604 break; 605 case V4L2_CID_HUE: 606 /*Hue is inverted according to HSL chart */ 607 ret = adv7180_write(state, ADV7180_REG_HUE, -val); 608 break; 609 case V4L2_CID_CONTRAST: 610 ret = adv7180_write(state, ADV7180_REG_CON, val); 611 break; 612 case V4L2_CID_SATURATION: 613 /* 614 *This could be V4L2_CID_BLUE_BALANCE/V4L2_CID_RED_BALANCE 615 *Let's not confuse the user, everybody understands saturation 616 */ 617 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CB, val); 618 if (ret < 0) 619 break; 620 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CR, val); 621 break; 622 case V4L2_CID_ADV_FAST_SWITCH: 623 if (ctrl->val) { 624 /* ADI required write */ 625 adv7180_write(state, 0x80d9, 0x44); 626 adv7180_write(state, ADV7180_REG_FLCONTROL, 627 ADV7180_FLCONTROL_FL_ENABLE); 628 } else { 629 /* ADI required write */ 630 adv7180_write(state, 0x80d9, 0xc4); 631 adv7180_write(state, ADV7180_REG_FLCONTROL, 0x00); 632 } 633 break; 634 case V4L2_CID_TEST_PATTERN: 635 ret = adv7180_test_pattern(state, val); 636 break; 637 default: 638 ret = -EINVAL; 639 } 640 641 mutex_unlock(&state->mutex); 642 return ret; 643 } 644 645 static const struct v4l2_ctrl_ops adv7180_ctrl_ops = { 646 .s_ctrl = adv7180_s_ctrl, 647 }; 648 649 static const struct v4l2_ctrl_config adv7180_ctrl_fast_switch = { 650 .ops = &adv7180_ctrl_ops, 651 .id = V4L2_CID_ADV_FAST_SWITCH, 652 .name = "Fast Switching", 653 .type = V4L2_CTRL_TYPE_BOOLEAN, 654 .min = 0, 655 .max = 1, 656 .step = 1, 657 }; 658 659 static int adv7180_init_controls(struct adv7180_state *state) 660 { 661 v4l2_ctrl_handler_init(&state->ctrl_hdl, 4); 662 663 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, 664 V4L2_CID_BRIGHTNESS, ADV7180_BRI_MIN, 665 ADV7180_BRI_MAX, 1, ADV7180_BRI_DEF); 666 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, 667 V4L2_CID_CONTRAST, ADV7180_CON_MIN, 668 ADV7180_CON_MAX, 1, ADV7180_CON_DEF); 669 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, 670 V4L2_CID_SATURATION, ADV7180_SAT_MIN, 671 ADV7180_SAT_MAX, 1, ADV7180_SAT_DEF); 672 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, 673 V4L2_CID_HUE, ADV7180_HUE_MIN, 674 ADV7180_HUE_MAX, 1, ADV7180_HUE_DEF); 675 v4l2_ctrl_new_custom(&state->ctrl_hdl, &adv7180_ctrl_fast_switch, NULL); 676 677 v4l2_ctrl_new_std_menu_items(&state->ctrl_hdl, &adv7180_ctrl_ops, 678 V4L2_CID_TEST_PATTERN, 679 ARRAY_SIZE(test_pattern_menu) - 1, 680 0, ARRAY_SIZE(test_pattern_menu) - 1, 681 test_pattern_menu); 682 683 state->sd.ctrl_handler = &state->ctrl_hdl; 684 if (state->ctrl_hdl.error) { 685 int err = state->ctrl_hdl.error; 686 687 v4l2_ctrl_handler_free(&state->ctrl_hdl); 688 return err; 689 } 690 v4l2_ctrl_handler_setup(&state->ctrl_hdl); 691 692 return 0; 693 } 694 static void adv7180_exit_controls(struct adv7180_state *state) 695 { 696 v4l2_ctrl_handler_free(&state->ctrl_hdl); 697 } 698 699 static int adv7180_enum_mbus_code(struct v4l2_subdev *sd, 700 struct v4l2_subdev_state *sd_state, 701 struct v4l2_subdev_mbus_code_enum *code) 702 { 703 if (code->index != 0) 704 return -EINVAL; 705 706 code->code = MEDIA_BUS_FMT_UYVY8_2X8; 707 708 return 0; 709 } 710 711 static int adv7180_mbus_fmt(struct v4l2_subdev *sd, 712 struct v4l2_mbus_framefmt *fmt) 713 { 714 struct adv7180_state *state = to_state(sd); 715 716 fmt->code = MEDIA_BUS_FMT_UYVY8_2X8; 717 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M; 718 fmt->width = 720; 719 fmt->height = state->curr_norm & V4L2_STD_525_60 ? 480 : 576; 720 721 if (state->field == V4L2_FIELD_ALTERNATE) 722 fmt->height /= 2; 723 724 return 0; 725 } 726 727 static int adv7180_set_field_mode(struct adv7180_state *state) 728 { 729 if (!(state->chip_info->flags & ADV7180_FLAG_I2P)) 730 return 0; 731 732 if (state->field == V4L2_FIELD_NONE) { 733 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 734 adv7180_csi_write(state, 0x01, 0x20); 735 adv7180_csi_write(state, 0x02, 0x28); 736 adv7180_csi_write(state, 0x03, 0x38); 737 adv7180_csi_write(state, 0x04, 0x30); 738 adv7180_csi_write(state, 0x05, 0x30); 739 adv7180_csi_write(state, 0x06, 0x80); 740 adv7180_csi_write(state, 0x07, 0x70); 741 adv7180_csi_write(state, 0x08, 0x50); 742 } 743 adv7180_vpp_write(state, 0xa3, 0x00); 744 adv7180_vpp_write(state, 0x5b, 0x00); 745 adv7180_vpp_write(state, 0x55, 0x80); 746 } else { 747 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 748 adv7180_csi_write(state, 0x01, 0x18); 749 adv7180_csi_write(state, 0x02, 0x18); 750 adv7180_csi_write(state, 0x03, 0x30); 751 adv7180_csi_write(state, 0x04, 0x20); 752 adv7180_csi_write(state, 0x05, 0x28); 753 adv7180_csi_write(state, 0x06, 0x40); 754 adv7180_csi_write(state, 0x07, 0x58); 755 adv7180_csi_write(state, 0x08, 0x30); 756 } 757 adv7180_vpp_write(state, 0xa3, 0x70); 758 adv7180_vpp_write(state, 0x5b, 0x80); 759 adv7180_vpp_write(state, 0x55, 0x00); 760 } 761 762 return 0; 763 } 764 765 static int adv7180_get_pad_format(struct v4l2_subdev *sd, 766 struct v4l2_subdev_state *sd_state, 767 struct v4l2_subdev_format *format) 768 { 769 struct adv7180_state *state = to_state(sd); 770 771 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 772 format->format = *v4l2_subdev_state_get_format(sd_state, 0); 773 } else { 774 adv7180_mbus_fmt(sd, &format->format); 775 format->format.field = state->field; 776 } 777 778 return 0; 779 } 780 781 static int adv7180_set_pad_format(struct v4l2_subdev *sd, 782 struct v4l2_subdev_state *sd_state, 783 struct v4l2_subdev_format *format) 784 { 785 struct adv7180_state *state = to_state(sd); 786 struct v4l2_mbus_framefmt *framefmt; 787 int ret; 788 789 switch (format->format.field) { 790 case V4L2_FIELD_NONE: 791 if (state->chip_info->flags & ADV7180_FLAG_I2P) 792 break; 793 fallthrough; 794 default: 795 format->format.field = V4L2_FIELD_ALTERNATE; 796 break; 797 } 798 799 ret = adv7180_mbus_fmt(sd, &format->format); 800 801 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 802 if (state->field != format->format.field) { 803 state->field = format->format.field; 804 adv7180_set_power(state, false); 805 adv7180_set_field_mode(state); 806 adv7180_set_power(state, true); 807 } 808 } else { 809 framefmt = v4l2_subdev_state_get_format(sd_state, 0); 810 *framefmt = format->format; 811 } 812 813 return ret; 814 } 815 816 static int adv7180_init_state(struct v4l2_subdev *sd, 817 struct v4l2_subdev_state *sd_state) 818 { 819 struct v4l2_subdev_format fmt = { 820 .which = sd_state ? V4L2_SUBDEV_FORMAT_TRY 821 : V4L2_SUBDEV_FORMAT_ACTIVE, 822 }; 823 824 return adv7180_set_pad_format(sd, sd_state, &fmt); 825 } 826 827 static int adv7180_get_mbus_config(struct v4l2_subdev *sd, 828 unsigned int pad, 829 struct v4l2_mbus_config *cfg) 830 { 831 struct adv7180_state *state = to_state(sd); 832 833 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 834 cfg->type = V4L2_MBUS_CSI2_DPHY; 835 cfg->bus.mipi_csi2.num_data_lanes = 1; 836 cfg->bus.mipi_csi2.flags = 0; 837 } else { 838 /* 839 * The ADV7180 sensor supports BT.601/656 output modes. 840 * The BT.656 is default and not yet configurable by s/w. 841 */ 842 cfg->bus.parallel.flags = V4L2_MBUS_MASTER | 843 V4L2_MBUS_PCLK_SAMPLE_RISING | 844 V4L2_MBUS_DATA_ACTIVE_HIGH; 845 cfg->type = V4L2_MBUS_BT656; 846 } 847 848 return 0; 849 } 850 851 static int adv7180_get_skip_frames(struct v4l2_subdev *sd, u32 *frames) 852 { 853 *frames = ADV7180_NUM_OF_SKIP_FRAMES; 854 855 return 0; 856 } 857 858 static int adv7180_g_pixelaspect(struct v4l2_subdev *sd, struct v4l2_fract *aspect) 859 { 860 struct adv7180_state *state = to_state(sd); 861 862 if (state->curr_norm & V4L2_STD_525_60) { 863 aspect->numerator = 11; 864 aspect->denominator = 10; 865 } else { 866 aspect->numerator = 54; 867 aspect->denominator = 59; 868 } 869 870 return 0; 871 } 872 873 static int adv7180_g_tvnorms(struct v4l2_subdev *sd, v4l2_std_id *norm) 874 { 875 *norm = V4L2_STD_ALL; 876 return 0; 877 } 878 879 static int adv7180_s_stream(struct v4l2_subdev *sd, int enable) 880 { 881 struct adv7180_state *state = to_state(sd); 882 int ret; 883 884 /* It's always safe to stop streaming, no need to take the lock */ 885 if (!enable) { 886 state->streaming = enable; 887 return 0; 888 } 889 890 /* Must wait until querystd released the lock */ 891 ret = mutex_lock_interruptible(&state->mutex); 892 if (ret) 893 return ret; 894 state->streaming = enable; 895 mutex_unlock(&state->mutex); 896 return 0; 897 } 898 899 static int adv7180_subscribe_event(struct v4l2_subdev *sd, 900 struct v4l2_fh *fh, 901 struct v4l2_event_subscription *sub) 902 { 903 switch (sub->type) { 904 case V4L2_EVENT_SOURCE_CHANGE: 905 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub); 906 case V4L2_EVENT_CTRL: 907 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub); 908 default: 909 return -EINVAL; 910 } 911 } 912 913 static const struct v4l2_subdev_video_ops adv7180_video_ops = { 914 .s_std = adv7180_s_std, 915 .g_std = adv7180_g_std, 916 .g_frame_interval = adv7180_g_frame_interval, 917 .querystd = adv7180_querystd, 918 .g_input_status = adv7180_g_input_status, 919 .s_routing = adv7180_s_routing, 920 .g_pixelaspect = adv7180_g_pixelaspect, 921 .g_tvnorms = adv7180_g_tvnorms, 922 .s_stream = adv7180_s_stream, 923 }; 924 925 static const struct v4l2_subdev_core_ops adv7180_core_ops = { 926 .s_power = adv7180_s_power, 927 .subscribe_event = adv7180_subscribe_event, 928 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 929 }; 930 931 static const struct v4l2_subdev_pad_ops adv7180_pad_ops = { 932 .enum_mbus_code = adv7180_enum_mbus_code, 933 .set_fmt = adv7180_set_pad_format, 934 .get_fmt = adv7180_get_pad_format, 935 .get_mbus_config = adv7180_get_mbus_config, 936 }; 937 938 static const struct v4l2_subdev_sensor_ops adv7180_sensor_ops = { 939 .g_skip_frames = adv7180_get_skip_frames, 940 }; 941 942 static const struct v4l2_subdev_ops adv7180_ops = { 943 .core = &adv7180_core_ops, 944 .video = &adv7180_video_ops, 945 .pad = &adv7180_pad_ops, 946 .sensor = &adv7180_sensor_ops, 947 }; 948 949 static const struct v4l2_subdev_internal_ops adv7180_internal_ops = { 950 .init_state = adv7180_init_state, 951 }; 952 953 static irqreturn_t adv7180_irq(int irq, void *devid) 954 { 955 struct adv7180_state *state = devid; 956 u8 isr3; 957 958 mutex_lock(&state->mutex); 959 isr3 = adv7180_read(state, ADV7180_REG_ISR3); 960 /* clear */ 961 adv7180_write(state, ADV7180_REG_ICR3, isr3); 962 963 if (isr3 & ADV7180_IRQ3_AD_CHANGE) { 964 static const struct v4l2_event src_ch = { 965 .type = V4L2_EVENT_SOURCE_CHANGE, 966 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, 967 }; 968 969 v4l2_subdev_notify_event(&state->sd, &src_ch); 970 } 971 mutex_unlock(&state->mutex); 972 973 return IRQ_HANDLED; 974 } 975 976 static int adv7180_init(struct adv7180_state *state) 977 { 978 int ret; 979 980 /* ITU-R BT.656-4 compatible */ 981 ret = adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 982 ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS); 983 if (ret < 0) 984 return ret; 985 986 /* Manually set V bit end position in NTSC mode */ 987 return adv7180_write(state, ADV7180_REG_NTSC_V_BIT_END, 988 ADV7180_NTSC_V_BIT_END_MANUAL_NVEND); 989 } 990 991 static int adv7180_set_std(struct adv7180_state *state, unsigned int std) 992 { 993 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, 994 (std << 4) | state->input); 995 } 996 997 static int adv7180_select_input(struct adv7180_state *state, unsigned int input) 998 { 999 int ret; 1000 1001 ret = adv7180_read(state, ADV7180_REG_INPUT_CONTROL); 1002 if (ret < 0) 1003 return ret; 1004 1005 ret &= ~ADV7180_INPUT_CONTROL_INSEL_MASK; 1006 ret |= input; 1007 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, ret); 1008 } 1009 1010 static int adv7182_init(struct adv7180_state *state) 1011 { 1012 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) 1013 adv7180_write(state, ADV7180_REG_CSI_SLAVE_ADDR, 1014 ADV7180_DEFAULT_CSI_I2C_ADDR << 1); 1015 1016 if (state->chip_info->flags & ADV7180_FLAG_I2P) 1017 adv7180_write(state, ADV7180_REG_VPP_SLAVE_ADDR, 1018 ADV7180_DEFAULT_VPP_I2C_ADDR << 1); 1019 1020 if (state->chip_info->flags & ADV7180_FLAG_V2) { 1021 /* ADI recommended writes for improved video quality */ 1022 adv7180_write(state, 0x0080, 0x51); 1023 adv7180_write(state, 0x0081, 0x51); 1024 adv7180_write(state, 0x0082, 0x68); 1025 } 1026 1027 /* ADI required writes */ 1028 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 1029 adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x4e); 1030 adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 0x57); 1031 adv7180_write(state, ADV7180_REG_CTRL_2, 0xc0); 1032 } else { 1033 if (state->chip_info->flags & ADV7180_FLAG_V2) { 1034 if (state->force_bt656_4) { 1035 /* ITU-R BT.656-4 compatible */ 1036 adv7180_write(state, 1037 ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 1038 ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS); 1039 /* Manually set NEWAVMODE */ 1040 adv7180_write(state, 1041 ADV7180_REG_VSYNC_FIELD_CTL_1, 1042 ADV7180_VSYNC_FIELD_CTL_1_NEWAV); 1043 /* Manually set V bit end position in NTSC mode */ 1044 adv7180_write(state, 1045 ADV7180_REG_NTSC_V_BIT_END, 1046 ADV7180_NTSC_V_BIT_END_MANUAL_NVEND); 1047 } else { 1048 adv7180_write(state, 1049 ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 1050 0x17); 1051 } 1052 } 1053 else 1054 adv7180_write(state, 1055 ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 1056 0x07); 1057 adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x0c); 1058 adv7180_write(state, ADV7180_REG_CTRL_2, 0x40); 1059 } 1060 1061 adv7180_write(state, 0x0013, 0x00); 1062 1063 return 0; 1064 } 1065 1066 static int adv7182_set_std(struct adv7180_state *state, unsigned int std) 1067 { 1068 /* Failing to set the reserved bit can result in increased video noise */ 1069 return adv7180_write(state, ADV7182_REG_INPUT_VIDSEL, 1070 (std << 4) | ADV7182_REG_INPUT_RESERVED); 1071 } 1072 1073 enum adv7182_input_type { 1074 ADV7182_INPUT_TYPE_CVBS, 1075 ADV7182_INPUT_TYPE_DIFF_CVBS, 1076 ADV7182_INPUT_TYPE_SVIDEO, 1077 ADV7182_INPUT_TYPE_YPBPR, 1078 }; 1079 1080 static enum adv7182_input_type adv7182_get_input_type(unsigned int input) 1081 { 1082 switch (input) { 1083 case ADV7182_INPUT_CVBS_AIN1: 1084 case ADV7182_INPUT_CVBS_AIN2: 1085 case ADV7182_INPUT_CVBS_AIN3: 1086 case ADV7182_INPUT_CVBS_AIN4: 1087 case ADV7182_INPUT_CVBS_AIN5: 1088 case ADV7182_INPUT_CVBS_AIN6: 1089 case ADV7182_INPUT_CVBS_AIN7: 1090 case ADV7182_INPUT_CVBS_AIN8: 1091 return ADV7182_INPUT_TYPE_CVBS; 1092 case ADV7182_INPUT_SVIDEO_AIN1_AIN2: 1093 case ADV7182_INPUT_SVIDEO_AIN3_AIN4: 1094 case ADV7182_INPUT_SVIDEO_AIN5_AIN6: 1095 case ADV7182_INPUT_SVIDEO_AIN7_AIN8: 1096 return ADV7182_INPUT_TYPE_SVIDEO; 1097 case ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3: 1098 case ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6: 1099 return ADV7182_INPUT_TYPE_YPBPR; 1100 case ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2: 1101 case ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4: 1102 case ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6: 1103 case ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8: 1104 return ADV7182_INPUT_TYPE_DIFF_CVBS; 1105 default: /* Will never happen */ 1106 return 0; 1107 } 1108 } 1109 1110 /* ADI recommended writes to registers 0x52, 0x53, 0x54 */ 1111 static unsigned int adv7182_lbias_settings[][3] = { 1112 [ADV7182_INPUT_TYPE_CVBS] = { 0xCB, 0x4E, 0x80 }, 1113 [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 }, 1114 [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 }, 1115 [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 }, 1116 }; 1117 1118 static unsigned int adv7280_lbias_settings[][3] = { 1119 [ADV7182_INPUT_TYPE_CVBS] = { 0xCD, 0x4E, 0x80 }, 1120 [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 }, 1121 [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 }, 1122 [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 }, 1123 }; 1124 1125 static int adv7182_select_input(struct adv7180_state *state, unsigned int input) 1126 { 1127 enum adv7182_input_type input_type; 1128 unsigned int *lbias; 1129 unsigned int i; 1130 int ret; 1131 1132 ret = adv7180_write(state, ADV7180_REG_INPUT_CONTROL, input); 1133 if (ret) 1134 return ret; 1135 1136 /* Reset clamp circuitry - ADI recommended writes */ 1137 adv7180_write(state, ADV7180_REG_RST_CLAMP, 0x00); 1138 adv7180_write(state, ADV7180_REG_RST_CLAMP, 0xff); 1139 1140 input_type = adv7182_get_input_type(input); 1141 1142 switch (input_type) { 1143 case ADV7182_INPUT_TYPE_CVBS: 1144 case ADV7182_INPUT_TYPE_DIFF_CVBS: 1145 /* ADI recommends to use the SH1 filter */ 1146 adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x41); 1147 break; 1148 default: 1149 adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x01); 1150 break; 1151 } 1152 1153 if (state->chip_info->flags & ADV7180_FLAG_V2) 1154 lbias = adv7280_lbias_settings[input_type]; 1155 else 1156 lbias = adv7182_lbias_settings[input_type]; 1157 1158 for (i = 0; i < ARRAY_SIZE(adv7182_lbias_settings[0]); i++) 1159 adv7180_write(state, ADV7180_REG_CVBS_TRIM + i, lbias[i]); 1160 1161 if (input_type == ADV7182_INPUT_TYPE_DIFF_CVBS) { 1162 /* ADI required writes to make differential CVBS work */ 1163 adv7180_write(state, ADV7180_REG_RES_CIR, 0xa8); 1164 adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0x90); 1165 adv7180_write(state, ADV7180_REG_DIFF_MODE, 0xb0); 1166 adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x08); 1167 adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0xa0); 1168 } else { 1169 adv7180_write(state, ADV7180_REG_RES_CIR, 0xf0); 1170 adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0xd0); 1171 adv7180_write(state, ADV7180_REG_DIFF_MODE, 0x10); 1172 adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x9c); 1173 adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0x00); 1174 } 1175 1176 return 0; 1177 } 1178 1179 static const struct adv7180_chip_info adv7180_info = { 1180 .flags = ADV7180_FLAG_RESET_POWERED, 1181 /* We cannot discriminate between LQFP and 40-pin LFCSP, so accept 1182 * all inputs and let the card driver take care of validation 1183 */ 1184 .valid_input_mask = BIT(ADV7180_INPUT_CVBS_AIN1) | 1185 BIT(ADV7180_INPUT_CVBS_AIN2) | 1186 BIT(ADV7180_INPUT_CVBS_AIN3) | 1187 BIT(ADV7180_INPUT_CVBS_AIN4) | 1188 BIT(ADV7180_INPUT_CVBS_AIN5) | 1189 BIT(ADV7180_INPUT_CVBS_AIN6) | 1190 BIT(ADV7180_INPUT_SVIDEO_AIN1_AIN2) | 1191 BIT(ADV7180_INPUT_SVIDEO_AIN3_AIN4) | 1192 BIT(ADV7180_INPUT_SVIDEO_AIN5_AIN6) | 1193 BIT(ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1194 BIT(ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6), 1195 .init = adv7180_init, 1196 .set_std = adv7180_set_std, 1197 .select_input = adv7180_select_input, 1198 }; 1199 1200 static const struct adv7180_chip_info adv7182_info = { 1201 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1202 BIT(ADV7182_INPUT_CVBS_AIN2) | 1203 BIT(ADV7182_INPUT_CVBS_AIN3) | 1204 BIT(ADV7182_INPUT_CVBS_AIN4) | 1205 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1206 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1207 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1208 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1209 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4), 1210 .init = adv7182_init, 1211 .set_std = adv7182_set_std, 1212 .select_input = adv7182_select_input, 1213 }; 1214 1215 static const struct adv7180_chip_info adv7280_info = { 1216 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P, 1217 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1218 BIT(ADV7182_INPUT_CVBS_AIN2) | 1219 BIT(ADV7182_INPUT_CVBS_AIN3) | 1220 BIT(ADV7182_INPUT_CVBS_AIN4) | 1221 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1222 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1223 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3), 1224 .init = adv7182_init, 1225 .set_std = adv7182_set_std, 1226 .select_input = adv7182_select_input, 1227 }; 1228 1229 static const struct adv7180_chip_info adv7280_m_info = { 1230 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P, 1231 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1232 BIT(ADV7182_INPUT_CVBS_AIN2) | 1233 BIT(ADV7182_INPUT_CVBS_AIN3) | 1234 BIT(ADV7182_INPUT_CVBS_AIN4) | 1235 BIT(ADV7182_INPUT_CVBS_AIN5) | 1236 BIT(ADV7182_INPUT_CVBS_AIN6) | 1237 BIT(ADV7182_INPUT_CVBS_AIN7) | 1238 BIT(ADV7182_INPUT_CVBS_AIN8) | 1239 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1240 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1241 BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) | 1242 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1243 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1244 BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6), 1245 .init = adv7182_init, 1246 .set_std = adv7182_set_std, 1247 .select_input = adv7182_select_input, 1248 }; 1249 1250 static const struct adv7180_chip_info adv7281_info = { 1251 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2, 1252 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1253 BIT(ADV7182_INPUT_CVBS_AIN2) | 1254 BIT(ADV7182_INPUT_CVBS_AIN7) | 1255 BIT(ADV7182_INPUT_CVBS_AIN8) | 1256 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1257 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1258 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1259 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1260 .init = adv7182_init, 1261 .set_std = adv7182_set_std, 1262 .select_input = adv7182_select_input, 1263 }; 1264 1265 static const struct adv7180_chip_info adv7281_m_info = { 1266 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2, 1267 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1268 BIT(ADV7182_INPUT_CVBS_AIN2) | 1269 BIT(ADV7182_INPUT_CVBS_AIN3) | 1270 BIT(ADV7182_INPUT_CVBS_AIN4) | 1271 BIT(ADV7182_INPUT_CVBS_AIN7) | 1272 BIT(ADV7182_INPUT_CVBS_AIN8) | 1273 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1274 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1275 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1276 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1277 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1278 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) | 1279 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1280 .init = adv7182_init, 1281 .set_std = adv7182_set_std, 1282 .select_input = adv7182_select_input, 1283 }; 1284 1285 static const struct adv7180_chip_info adv7281_ma_info = { 1286 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2, 1287 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1288 BIT(ADV7182_INPUT_CVBS_AIN2) | 1289 BIT(ADV7182_INPUT_CVBS_AIN3) | 1290 BIT(ADV7182_INPUT_CVBS_AIN4) | 1291 BIT(ADV7182_INPUT_CVBS_AIN5) | 1292 BIT(ADV7182_INPUT_CVBS_AIN6) | 1293 BIT(ADV7182_INPUT_CVBS_AIN7) | 1294 BIT(ADV7182_INPUT_CVBS_AIN8) | 1295 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1296 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1297 BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) | 1298 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1299 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1300 BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6) | 1301 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1302 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) | 1303 BIT(ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6) | 1304 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1305 .init = adv7182_init, 1306 .set_std = adv7182_set_std, 1307 .select_input = adv7182_select_input, 1308 }; 1309 1310 static const struct adv7180_chip_info adv7282_info = { 1311 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P, 1312 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1313 BIT(ADV7182_INPUT_CVBS_AIN2) | 1314 BIT(ADV7182_INPUT_CVBS_AIN7) | 1315 BIT(ADV7182_INPUT_CVBS_AIN8) | 1316 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1317 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1318 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1319 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1320 .init = adv7182_init, 1321 .set_std = adv7182_set_std, 1322 .select_input = adv7182_select_input, 1323 }; 1324 1325 static const struct adv7180_chip_info adv7282_m_info = { 1326 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P, 1327 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1328 BIT(ADV7182_INPUT_CVBS_AIN2) | 1329 BIT(ADV7182_INPUT_CVBS_AIN3) | 1330 BIT(ADV7182_INPUT_CVBS_AIN4) | 1331 BIT(ADV7182_INPUT_CVBS_AIN7) | 1332 BIT(ADV7182_INPUT_CVBS_AIN8) | 1333 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1334 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1335 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1336 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1337 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) | 1338 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1339 .init = adv7182_init, 1340 .set_std = adv7182_set_std, 1341 .select_input = adv7182_select_input, 1342 }; 1343 1344 static int init_device(struct adv7180_state *state) 1345 { 1346 int ret; 1347 1348 mutex_lock(&state->mutex); 1349 1350 adv7180_set_power_pin(state, true); 1351 adv7180_set_reset_pin(state, false); 1352 1353 adv7180_write(state, ADV7180_REG_PWR_MAN, ADV7180_PWR_MAN_RES); 1354 usleep_range(5000, 10000); 1355 1356 ret = state->chip_info->init(state); 1357 if (ret) 1358 goto out_unlock; 1359 1360 ret = adv7180_program_std(state); 1361 if (ret) 1362 goto out_unlock; 1363 1364 adv7180_set_field_mode(state); 1365 1366 /* register for interrupts */ 1367 if (state->irq > 0) { 1368 /* config the Interrupt pin to be active low */ 1369 ret = adv7180_write(state, ADV7180_REG_ICONF1, 1370 ADV7180_ICONF1_ACTIVE_LOW | 1371 ADV7180_ICONF1_PSYNC_ONLY); 1372 if (ret < 0) 1373 goto out_unlock; 1374 1375 ret = adv7180_write(state, ADV7180_REG_IMR1, 0); 1376 if (ret < 0) 1377 goto out_unlock; 1378 1379 ret = adv7180_write(state, ADV7180_REG_IMR2, 0); 1380 if (ret < 0) 1381 goto out_unlock; 1382 1383 /* enable AD change interrupts interrupts */ 1384 ret = adv7180_write(state, ADV7180_REG_IMR3, 1385 ADV7180_IRQ3_AD_CHANGE); 1386 if (ret < 0) 1387 goto out_unlock; 1388 1389 ret = adv7180_write(state, ADV7180_REG_IMR4, 0); 1390 if (ret < 0) 1391 goto out_unlock; 1392 } 1393 1394 out_unlock: 1395 mutex_unlock(&state->mutex); 1396 1397 return ret; 1398 } 1399 1400 static int adv7180_probe(struct i2c_client *client) 1401 { 1402 struct device_node *np = client->dev.of_node; 1403 struct adv7180_state *state; 1404 struct v4l2_subdev *sd; 1405 int ret; 1406 1407 /* Check if the adapter supports the needed features */ 1408 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 1409 return -EIO; 1410 1411 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); 1412 if (state == NULL) 1413 return -ENOMEM; 1414 1415 state->client = client; 1416 state->field = V4L2_FIELD_ALTERNATE; 1417 state->chip_info = i2c_get_match_data(client); 1418 1419 state->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown", 1420 GPIOD_OUT_HIGH); 1421 if (IS_ERR(state->pwdn_gpio)) { 1422 ret = PTR_ERR(state->pwdn_gpio); 1423 v4l_err(client, "request for power pin failed: %d\n", ret); 1424 return ret; 1425 } 1426 1427 state->rst_gpio = devm_gpiod_get_optional(&client->dev, "reset", 1428 GPIOD_OUT_HIGH); 1429 if (IS_ERR(state->rst_gpio)) { 1430 ret = PTR_ERR(state->rst_gpio); 1431 v4l_err(client, "request for reset pin failed: %d\n", ret); 1432 return ret; 1433 } 1434 1435 if (of_property_read_bool(np, "adv,force-bt656-4")) 1436 state->force_bt656_4 = true; 1437 1438 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 1439 state->csi_client = i2c_new_dummy_device(client->adapter, 1440 ADV7180_DEFAULT_CSI_I2C_ADDR); 1441 if (IS_ERR(state->csi_client)) 1442 return PTR_ERR(state->csi_client); 1443 } 1444 1445 if (state->chip_info->flags & ADV7180_FLAG_I2P) { 1446 state->vpp_client = i2c_new_dummy_device(client->adapter, 1447 ADV7180_DEFAULT_VPP_I2C_ADDR); 1448 if (IS_ERR(state->vpp_client)) { 1449 ret = PTR_ERR(state->vpp_client); 1450 goto err_unregister_csi_client; 1451 } 1452 } 1453 1454 state->irq = client->irq; 1455 mutex_init(&state->mutex); 1456 state->curr_norm = V4L2_STD_NTSC; 1457 if (state->chip_info->flags & ADV7180_FLAG_RESET_POWERED) 1458 state->powered = true; 1459 else 1460 state->powered = false; 1461 state->input = 0; 1462 sd = &state->sd; 1463 v4l2_i2c_subdev_init(sd, client, &adv7180_ops); 1464 sd->internal_ops = &adv7180_internal_ops; 1465 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; 1466 1467 ret = adv7180_init_controls(state); 1468 if (ret) 1469 goto err_unregister_vpp_client; 1470 1471 state->pad.flags = MEDIA_PAD_FL_SOURCE; 1472 sd->entity.function = MEDIA_ENT_F_ATV_DECODER; 1473 ret = media_entity_pads_init(&sd->entity, 1, &state->pad); 1474 if (ret) 1475 goto err_free_ctrl; 1476 1477 ret = init_device(state); 1478 if (ret) 1479 goto err_media_entity_cleanup; 1480 1481 if (state->irq) { 1482 ret = request_threaded_irq(client->irq, NULL, adv7180_irq, 1483 IRQF_ONESHOT | IRQF_TRIGGER_FALLING, 1484 KBUILD_MODNAME, state); 1485 if (ret) 1486 goto err_media_entity_cleanup; 1487 } 1488 1489 ret = v4l2_async_register_subdev(sd); 1490 if (ret) 1491 goto err_free_irq; 1492 1493 mutex_lock(&state->mutex); 1494 ret = adv7180_read(state, ADV7180_REG_IDENT); 1495 mutex_unlock(&state->mutex); 1496 if (ret < 0) 1497 goto err_v4l2_async_unregister; 1498 1499 v4l_info(client, "chip id 0x%x found @ 0x%02x (%s)\n", 1500 ret, client->addr, client->adapter->name); 1501 1502 return 0; 1503 1504 err_v4l2_async_unregister: 1505 v4l2_async_unregister_subdev(sd); 1506 err_free_irq: 1507 if (state->irq > 0) 1508 free_irq(client->irq, state); 1509 err_media_entity_cleanup: 1510 media_entity_cleanup(&sd->entity); 1511 err_free_ctrl: 1512 adv7180_exit_controls(state); 1513 err_unregister_vpp_client: 1514 i2c_unregister_device(state->vpp_client); 1515 err_unregister_csi_client: 1516 i2c_unregister_device(state->csi_client); 1517 mutex_destroy(&state->mutex); 1518 return ret; 1519 } 1520 1521 static void adv7180_remove(struct i2c_client *client) 1522 { 1523 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1524 struct adv7180_state *state = to_state(sd); 1525 1526 v4l2_async_unregister_subdev(sd); 1527 1528 if (state->irq > 0) 1529 free_irq(client->irq, state); 1530 1531 media_entity_cleanup(&sd->entity); 1532 adv7180_exit_controls(state); 1533 1534 i2c_unregister_device(state->vpp_client); 1535 i2c_unregister_device(state->csi_client); 1536 1537 adv7180_set_reset_pin(state, true); 1538 adv7180_set_power_pin(state, false); 1539 1540 mutex_destroy(&state->mutex); 1541 } 1542 1543 #ifdef CONFIG_PM_SLEEP 1544 static int adv7180_suspend(struct device *dev) 1545 { 1546 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1547 struct adv7180_state *state = to_state(sd); 1548 1549 return adv7180_set_power(state, false); 1550 } 1551 1552 static int adv7180_resume(struct device *dev) 1553 { 1554 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1555 struct adv7180_state *state = to_state(sd); 1556 int ret; 1557 1558 ret = init_device(state); 1559 if (ret < 0) 1560 return ret; 1561 1562 ret = adv7180_set_power(state, state->powered); 1563 if (ret) 1564 return ret; 1565 1566 return 0; 1567 } 1568 1569 static SIMPLE_DEV_PM_OPS(adv7180_pm_ops, adv7180_suspend, adv7180_resume); 1570 #define ADV7180_PM_OPS (&adv7180_pm_ops) 1571 1572 #else 1573 #define ADV7180_PM_OPS NULL 1574 #endif 1575 1576 static const struct i2c_device_id adv7180_id[] = { 1577 { "adv7180", (kernel_ulong_t)&adv7180_info }, 1578 { "adv7180cp", (kernel_ulong_t)&adv7180_info }, 1579 { "adv7180st", (kernel_ulong_t)&adv7180_info }, 1580 { "adv7182", (kernel_ulong_t)&adv7182_info }, 1581 { "adv7280", (kernel_ulong_t)&adv7280_info }, 1582 { "adv7280-m", (kernel_ulong_t)&adv7280_m_info }, 1583 { "adv7281", (kernel_ulong_t)&adv7281_info }, 1584 { "adv7281-m", (kernel_ulong_t)&adv7281_m_info }, 1585 { "adv7281-ma", (kernel_ulong_t)&adv7281_ma_info }, 1586 { "adv7282", (kernel_ulong_t)&adv7282_info }, 1587 { "adv7282-m", (kernel_ulong_t)&adv7282_m_info }, 1588 {} 1589 }; 1590 MODULE_DEVICE_TABLE(i2c, adv7180_id); 1591 1592 static const struct of_device_id adv7180_of_id[] = { 1593 { .compatible = "adi,adv7180", &adv7180_info }, 1594 { .compatible = "adi,adv7180cp", &adv7180_info }, 1595 { .compatible = "adi,adv7180st", &adv7180_info }, 1596 { .compatible = "adi,adv7182", &adv7182_info }, 1597 { .compatible = "adi,adv7280", &adv7280_info }, 1598 { .compatible = "adi,adv7280-m", &adv7280_m_info }, 1599 { .compatible = "adi,adv7281", &adv7281_info }, 1600 { .compatible = "adi,adv7281-m", &adv7281_m_info }, 1601 { .compatible = "adi,adv7281-ma", &adv7281_ma_info }, 1602 { .compatible = "adi,adv7282", &adv7282_info }, 1603 { .compatible = "adi,adv7282-m", &adv7282_m_info }, 1604 {} 1605 }; 1606 MODULE_DEVICE_TABLE(of, adv7180_of_id); 1607 1608 static struct i2c_driver adv7180_driver = { 1609 .driver = { 1610 .name = KBUILD_MODNAME, 1611 .pm = ADV7180_PM_OPS, 1612 .of_match_table = adv7180_of_id, 1613 }, 1614 .probe = adv7180_probe, 1615 .remove = adv7180_remove, 1616 .id_table = adv7180_id, 1617 }; 1618 1619 module_i2c_driver(adv7180_driver); 1620 1621 MODULE_DESCRIPTION("Analog Devices ADV7180 video decoder driver"); 1622 MODULE_AUTHOR("Mocean Laboratories"); 1623 MODULE_LICENSE("GPL v2"); 1624