1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * adv7180.c Analog Devices ADV7180 video decoder driver 4 * Copyright (c) 2009 Intel Corporation 5 * Copyright (C) 2013 Cogent Embedded, Inc. 6 * Copyright (C) 2013 Renesas Solutions Corp. 7 */ 8 #include <linux/mod_devicetable.h> 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/errno.h> 12 #include <linux/kernel.h> 13 #include <linux/interrupt.h> 14 #include <linux/i2c.h> 15 #include <linux/slab.h> 16 #include <linux/of.h> 17 #include <linux/gpio/consumer.h> 18 #include <linux/videodev2.h> 19 #include <media/v4l2-ioctl.h> 20 #include <media/v4l2-event.h> 21 #include <media/v4l2-device.h> 22 #include <media/v4l2-ctrls.h> 23 #include <linux/mutex.h> 24 #include <linux/delay.h> 25 26 #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM 0x0 27 #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM_PED 0x1 28 #define ADV7180_STD_AD_PAL_N_NTSC_J_SECAM 0x2 29 #define ADV7180_STD_AD_PAL_N_NTSC_M_SECAM 0x3 30 #define ADV7180_STD_NTSC_J 0x4 31 #define ADV7180_STD_NTSC_M 0x5 32 #define ADV7180_STD_PAL60 0x6 33 #define ADV7180_STD_NTSC_443 0x7 34 #define ADV7180_STD_PAL_BG 0x8 35 #define ADV7180_STD_PAL_N 0x9 36 #define ADV7180_STD_PAL_M 0xa 37 #define ADV7180_STD_PAL_M_PED 0xb 38 #define ADV7180_STD_PAL_COMB_N 0xc 39 #define ADV7180_STD_PAL_COMB_N_PED 0xd 40 #define ADV7180_STD_PAL_SECAM 0xe 41 #define ADV7180_STD_PAL_SECAM_PED 0xf 42 43 #define ADV7180_REG_INPUT_CONTROL 0x0000 44 #define ADV7180_INPUT_CONTROL_INSEL_MASK 0x0f 45 46 #define ADV7182_REG_INPUT_VIDSEL 0x0002 47 #define ADV7182_REG_INPUT_RESERVED BIT(2) 48 49 #define ADV7180_REG_OUTPUT_CONTROL 0x0003 50 #define ADV7180_REG_EXTENDED_OUTPUT_CONTROL 0x0004 51 #define ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS 0xC5 52 53 #define ADV7180_REG_AUTODETECT_ENABLE 0x0007 54 #define ADV7180_AUTODETECT_DEFAULT 0x7f 55 /* Contrast */ 56 #define ADV7180_REG_CON 0x0008 /*Unsigned */ 57 #define ADV7180_CON_MIN 0 58 #define ADV7180_CON_DEF 128 59 #define ADV7180_CON_MAX 255 60 /* Brightness*/ 61 #define ADV7180_REG_BRI 0x000a /*Signed */ 62 #define ADV7180_BRI_MIN -128 63 #define ADV7180_BRI_DEF 0 64 #define ADV7180_BRI_MAX 127 65 /* Hue */ 66 #define ADV7180_REG_HUE 0x000b /*Signed, inverted */ 67 #define ADV7180_HUE_MIN -127 68 #define ADV7180_HUE_DEF 0 69 #define ADV7180_HUE_MAX 128 70 71 #define ADV7180_REG_DEF_VALUE_Y 0x000c 72 #define ADV7180_DEF_VAL_EN 0x1 73 #define ADV7180_DEF_VAL_AUTO_EN 0x2 74 #define ADV7180_REG_CTRL 0x000e 75 #define ADV7180_CTRL_IRQ_SPACE 0x20 76 77 #define ADV7180_REG_PWR_MAN 0x0f 78 #define ADV7180_PWR_MAN_ON 0x04 79 #define ADV7180_PWR_MAN_OFF 0x24 80 #define ADV7180_PWR_MAN_RES 0x80 81 82 #define ADV7180_REG_STATUS1 0x0010 83 #define ADV7180_STATUS1_IN_LOCK 0x01 84 #define ADV7180_STATUS1_AUTOD_MASK 0x70 85 #define ADV7180_STATUS1_AUTOD_NTSM_M_J 0x00 86 #define ADV7180_STATUS1_AUTOD_NTSC_4_43 0x10 87 #define ADV7180_STATUS1_AUTOD_PAL_M 0x20 88 #define ADV7180_STATUS1_AUTOD_PAL_60 0x30 89 #define ADV7180_STATUS1_AUTOD_PAL_B_G 0x40 90 #define ADV7180_STATUS1_AUTOD_SECAM 0x50 91 #define ADV7180_STATUS1_AUTOD_PAL_COMB 0x60 92 #define ADV7180_STATUS1_AUTOD_SECAM_525 0x70 93 94 #define ADV7180_REG_IDENT 0x0011 95 #define ADV7180_ID_7180 0x18 96 97 #define ADV7180_REG_STATUS3 0x0013 98 #define ADV7180_REG_ANALOG_CLAMP_CTL 0x0014 99 #define ADV7180_REG_SHAP_FILTER_CTL_1 0x0017 100 #define ADV7180_REG_CTRL_2 0x001d 101 #define ADV7180_REG_VSYNC_FIELD_CTL_1 0x0031 102 #define ADV7180_VSYNC_FIELD_CTL_1_NEWAV 0x12 103 #define ADV7180_REG_MANUAL_WIN_CTL_1 0x003d 104 #define ADV7180_REG_MANUAL_WIN_CTL_2 0x003e 105 #define ADV7180_REG_MANUAL_WIN_CTL_3 0x003f 106 #define ADV7180_REG_LOCK_CNT 0x0051 107 #define ADV7180_REG_CVBS_TRIM 0x0052 108 #define ADV7180_REG_CLAMP_ADJ 0x005a 109 #define ADV7180_REG_RES_CIR 0x005f 110 #define ADV7180_REG_DIFF_MODE 0x0060 111 112 #define ADV7180_REG_ICONF1 0x2040 113 #define ADV7180_ICONF1_ACTIVE_LOW 0x01 114 #define ADV7180_ICONF1_PSYNC_ONLY 0x10 115 #define ADV7180_ICONF1_ACTIVE_TO_CLR 0xC0 116 /* Saturation */ 117 #define ADV7180_REG_SD_SAT_CB 0x00e3 /*Unsigned */ 118 #define ADV7180_REG_SD_SAT_CR 0x00e4 /*Unsigned */ 119 #define ADV7180_SAT_MIN 0 120 #define ADV7180_SAT_DEF 128 121 #define ADV7180_SAT_MAX 255 122 123 #define ADV7180_IRQ1_LOCK 0x01 124 #define ADV7180_IRQ1_UNLOCK 0x02 125 #define ADV7180_REG_ISR1 0x2042 126 #define ADV7180_REG_ICR1 0x2043 127 #define ADV7180_REG_IMR1 0x2044 128 #define ADV7180_REG_IMR2 0x2048 129 #define ADV7180_IRQ3_AD_CHANGE 0x08 130 #define ADV7180_REG_ISR3 0x204A 131 #define ADV7180_REG_ICR3 0x204B 132 #define ADV7180_REG_IMR3 0x204C 133 #define ADV7180_REG_IMR4 0x2050 134 135 #define ADV7180_REG_NTSC_V_BIT_END 0x00E6 136 #define ADV7180_NTSC_V_BIT_END_MANUAL_NVEND 0x4F 137 138 #define ADV7180_REG_VPP_SLAVE_ADDR 0xFD 139 #define ADV7180_REG_CSI_SLAVE_ADDR 0xFE 140 141 #define ADV7180_REG_ACE_CTRL1 0x4080 142 #define ADV7180_REG_ACE_CTRL5 0x4084 143 #define ADV7180_REG_FLCONTROL 0x40e0 144 #define ADV7180_FLCONTROL_FL_ENABLE 0x1 145 146 #define ADV7180_REG_RST_CLAMP 0x809c 147 #define ADV7180_REG_AGC_ADJ1 0x80b6 148 #define ADV7180_REG_AGC_ADJ2 0x80c0 149 150 #define ADV7180_CSI_REG_PWRDN 0x00 151 #define ADV7180_CSI_PWRDN 0x80 152 153 #define ADV7180_INPUT_CVBS_AIN1 0x00 154 #define ADV7180_INPUT_CVBS_AIN2 0x01 155 #define ADV7180_INPUT_CVBS_AIN3 0x02 156 #define ADV7180_INPUT_CVBS_AIN4 0x03 157 #define ADV7180_INPUT_CVBS_AIN5 0x04 158 #define ADV7180_INPUT_CVBS_AIN6 0x05 159 #define ADV7180_INPUT_SVIDEO_AIN1_AIN2 0x06 160 #define ADV7180_INPUT_SVIDEO_AIN3_AIN4 0x07 161 #define ADV7180_INPUT_SVIDEO_AIN5_AIN6 0x08 162 #define ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3 0x09 163 #define ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0a 164 165 #define ADV7182_INPUT_CVBS_AIN1 0x00 166 #define ADV7182_INPUT_CVBS_AIN2 0x01 167 #define ADV7182_INPUT_CVBS_AIN3 0x02 168 #define ADV7182_INPUT_CVBS_AIN4 0x03 169 #define ADV7182_INPUT_CVBS_AIN5 0x04 170 #define ADV7182_INPUT_CVBS_AIN6 0x05 171 #define ADV7182_INPUT_CVBS_AIN7 0x06 172 #define ADV7182_INPUT_CVBS_AIN8 0x07 173 #define ADV7182_INPUT_SVIDEO_AIN1_AIN2 0x08 174 #define ADV7182_INPUT_SVIDEO_AIN3_AIN4 0x09 175 #define ADV7182_INPUT_SVIDEO_AIN5_AIN6 0x0a 176 #define ADV7182_INPUT_SVIDEO_AIN7_AIN8 0x0b 177 #define ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3 0x0c 178 #define ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0d 179 #define ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2 0x0e 180 #define ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4 0x0f 181 #define ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6 0x10 182 #define ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8 0x11 183 184 #define ADV7180_DEFAULT_CSI_I2C_ADDR 0x44 185 #define ADV7180_DEFAULT_VPP_I2C_ADDR 0x42 186 187 #define V4L2_CID_ADV_FAST_SWITCH (V4L2_CID_USER_ADV7180_BASE + 0x00) 188 189 /* Initial number of frames to skip to avoid possible garbage */ 190 #define ADV7180_NUM_OF_SKIP_FRAMES 2 191 192 struct adv7180_state; 193 194 #define ADV7180_FLAG_RESET_POWERED BIT(0) 195 #define ADV7180_FLAG_V2 BIT(1) 196 #define ADV7180_FLAG_MIPI_CSI2 BIT(2) 197 #define ADV7180_FLAG_I2P BIT(3) 198 #define ADV7180_FLAG_TEST_PATTERN BIT(4) 199 200 struct adv7180_chip_info { 201 unsigned int flags; 202 unsigned int valid_input_mask; 203 int (*set_std)(struct adv7180_state *st, unsigned int std); 204 int (*select_input)(struct adv7180_state *st, unsigned int input); 205 int (*init)(struct adv7180_state *state); 206 }; 207 208 struct adv7180_state { 209 struct v4l2_ctrl_handler ctrl_hdl; 210 struct v4l2_subdev sd; 211 struct media_pad pad; 212 struct mutex mutex; /* mutual excl. when accessing chip */ 213 int irq; 214 struct gpio_desc *pwdn_gpio; 215 struct gpio_desc *rst_gpio; 216 v4l2_std_id curr_norm; 217 bool streaming; 218 u8 input; 219 220 struct i2c_client *client; 221 unsigned int register_page; 222 struct i2c_client *csi_client; 223 struct i2c_client *vpp_client; 224 const struct adv7180_chip_info *chip_info; 225 enum v4l2_field field; 226 bool force_bt656_4; 227 }; 228 #define to_adv7180_sd(_ctrl) (&container_of(_ctrl->handler, \ 229 struct adv7180_state, \ 230 ctrl_hdl)->sd) 231 232 static int adv7180_select_page(struct adv7180_state *state, unsigned int page) 233 { 234 if (state->register_page != page) { 235 i2c_smbus_write_byte_data(state->client, ADV7180_REG_CTRL, 236 page); 237 state->register_page = page; 238 } 239 240 return 0; 241 } 242 243 static int adv7180_write(struct adv7180_state *state, unsigned int reg, 244 unsigned int value) 245 { 246 lockdep_assert_held(&state->mutex); 247 adv7180_select_page(state, reg >> 8); 248 return i2c_smbus_write_byte_data(state->client, reg & 0xff, value); 249 } 250 251 static int adv7180_read(struct adv7180_state *state, unsigned int reg) 252 { 253 lockdep_assert_held(&state->mutex); 254 adv7180_select_page(state, reg >> 8); 255 return i2c_smbus_read_byte_data(state->client, reg & 0xff); 256 } 257 258 static int adv7180_csi_write(struct adv7180_state *state, unsigned int reg, 259 unsigned int value) 260 { 261 return i2c_smbus_write_byte_data(state->csi_client, reg, value); 262 } 263 264 static int adv7180_set_video_standard(struct adv7180_state *state, 265 unsigned int std) 266 { 267 return state->chip_info->set_std(state, std); 268 } 269 270 static int adv7180_vpp_write(struct adv7180_state *state, unsigned int reg, 271 unsigned int value) 272 { 273 return i2c_smbus_write_byte_data(state->vpp_client, reg, value); 274 } 275 276 static int adv7180_set_power(struct adv7180_state *state, bool on) 277 { 278 u8 val; 279 int ret; 280 281 if (on) 282 val = ADV7180_PWR_MAN_ON; 283 else 284 val = ADV7180_PWR_MAN_OFF; 285 286 ret = adv7180_write(state, ADV7180_REG_PWR_MAN, val); 287 if (ret) 288 return ret; 289 290 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 291 if (on) { 292 adv7180_csi_write(state, 0xDE, 0x02); 293 adv7180_csi_write(state, 0xD2, 0xF7); 294 adv7180_csi_write(state, 0xD8, 0x65); 295 adv7180_csi_write(state, 0xE0, 0x09); 296 adv7180_csi_write(state, 0x2C, 0x00); 297 if (state->field == V4L2_FIELD_NONE) 298 adv7180_csi_write(state, 0x1D, 0x80); 299 adv7180_csi_write(state, 0x00, 0x00); 300 } else { 301 adv7180_csi_write(state, 0x00, 0x80); 302 } 303 } 304 305 return 0; 306 } 307 308 static v4l2_std_id adv7180_std_to_v4l2(u8 status1) 309 { 310 /* in case V4L2_IN_ST_NO_SIGNAL */ 311 if (!(status1 & ADV7180_STATUS1_IN_LOCK)) 312 return V4L2_STD_UNKNOWN; 313 314 switch (status1 & ADV7180_STATUS1_AUTOD_MASK) { 315 case ADV7180_STATUS1_AUTOD_NTSM_M_J: 316 return V4L2_STD_NTSC; 317 case ADV7180_STATUS1_AUTOD_NTSC_4_43: 318 return V4L2_STD_NTSC_443; 319 case ADV7180_STATUS1_AUTOD_PAL_M: 320 return V4L2_STD_PAL_M; 321 case ADV7180_STATUS1_AUTOD_PAL_60: 322 return V4L2_STD_PAL_60; 323 case ADV7180_STATUS1_AUTOD_PAL_B_G: 324 return V4L2_STD_PAL; 325 case ADV7180_STATUS1_AUTOD_SECAM: 326 return V4L2_STD_SECAM; 327 case ADV7180_STATUS1_AUTOD_PAL_COMB: 328 return V4L2_STD_PAL_Nc | V4L2_STD_PAL_N; 329 case ADV7180_STATUS1_AUTOD_SECAM_525: 330 return V4L2_STD_SECAM; 331 default: 332 return V4L2_STD_UNKNOWN; 333 } 334 } 335 336 static int v4l2_std_to_adv7180(v4l2_std_id std) 337 { 338 if (std == V4L2_STD_PAL_60) 339 return ADV7180_STD_PAL60; 340 if (std == V4L2_STD_NTSC_443) 341 return ADV7180_STD_NTSC_443; 342 if (std == V4L2_STD_PAL_N) 343 return ADV7180_STD_PAL_N; 344 if (std == V4L2_STD_PAL_M) 345 return ADV7180_STD_PAL_M; 346 if (std == V4L2_STD_PAL_Nc) 347 return ADV7180_STD_PAL_COMB_N; 348 349 if (std & V4L2_STD_PAL) 350 return ADV7180_STD_PAL_BG; 351 if (std & V4L2_STD_NTSC) 352 return ADV7180_STD_NTSC_M; 353 if (std & V4L2_STD_SECAM) 354 return ADV7180_STD_PAL_SECAM; 355 356 return -EINVAL; 357 } 358 359 static u32 adv7180_status_to_v4l2(u8 status1) 360 { 361 if (!(status1 & ADV7180_STATUS1_IN_LOCK)) 362 return V4L2_IN_ST_NO_SIGNAL; 363 364 return 0; 365 } 366 367 static int __adv7180_status(struct adv7180_state *state, u32 *status, 368 v4l2_std_id *std) 369 { 370 int status1 = adv7180_read(state, ADV7180_REG_STATUS1); 371 372 if (status1 < 0) 373 return status1; 374 375 if (status) 376 *status = adv7180_status_to_v4l2(status1); 377 if (std) 378 *std = adv7180_std_to_v4l2(status1); 379 380 return 0; 381 } 382 383 static inline struct adv7180_state *to_state(struct v4l2_subdev *sd) 384 { 385 return container_of(sd, struct adv7180_state, sd); 386 } 387 388 static int adv7180_querystd(struct v4l2_subdev *sd, v4l2_std_id *std) 389 { 390 struct adv7180_state *state = to_state(sd); 391 int ret; 392 393 guard(mutex)(&state->mutex); 394 395 /* 396 * We can't sample the standard if the device is streaming as that would 397 * interfere with the capture session as the VID_SEL reg is touched. 398 */ 399 if (state->streaming) 400 return -EBUSY; 401 402 /* Set the standard to autodetect PAL B/G/H/I/D, NTSC J or SECAM */ 403 ret = adv7180_set_video_standard(state, 404 ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM); 405 if (ret) 406 return ret; 407 408 /* Allow some time for the autodetection to run. */ 409 msleep(100); 410 411 return __adv7180_status(state, NULL, std); 412 } 413 414 static int adv7180_s_routing(struct v4l2_subdev *sd, u32 input, 415 u32 output, u32 config) 416 { 417 struct adv7180_state *state = to_state(sd); 418 int ret = mutex_lock_interruptible(&state->mutex); 419 420 if (ret) 421 return ret; 422 423 if (input > 31 || !(BIT(input) & state->chip_info->valid_input_mask)) { 424 ret = -EINVAL; 425 goto out; 426 } 427 428 ret = state->chip_info->select_input(state, input); 429 430 if (ret == 0) 431 state->input = input; 432 out: 433 mutex_unlock(&state->mutex); 434 return ret; 435 } 436 437 static int adv7180_g_input_status(struct v4l2_subdev *sd, u32 *status) 438 { 439 struct adv7180_state *state = to_state(sd); 440 int ret = mutex_lock_interruptible(&state->mutex); 441 if (ret) 442 return ret; 443 444 ret = __adv7180_status(state, status, NULL); 445 mutex_unlock(&state->mutex); 446 return ret; 447 } 448 449 static int adv7180_program_std(struct adv7180_state *state) 450 { 451 int ret; 452 453 ret = v4l2_std_to_adv7180(state->curr_norm); 454 if (ret < 0) 455 return ret; 456 457 ret = adv7180_set_video_standard(state, ret); 458 if (ret < 0) 459 return ret; 460 return 0; 461 } 462 463 static int adv7180_s_std(struct v4l2_subdev *sd, v4l2_std_id std) 464 { 465 struct adv7180_state *state = to_state(sd); 466 int ret; 467 468 guard(mutex)(&state->mutex); 469 470 /* Make sure we can support this std */ 471 ret = v4l2_std_to_adv7180(std); 472 if (ret < 0) 473 return ret; 474 475 state->curr_norm = std; 476 477 return 0; 478 } 479 480 static int adv7180_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm) 481 { 482 struct adv7180_state *state = to_state(sd); 483 484 *norm = state->curr_norm; 485 486 return 0; 487 } 488 489 static int adv7180_get_frame_interval(struct v4l2_subdev *sd, 490 struct v4l2_subdev_state *sd_state, 491 struct v4l2_subdev_frame_interval *fi) 492 { 493 struct adv7180_state *state = to_state(sd); 494 495 /* 496 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2 497 * subdev active state API. 498 */ 499 if (fi->which != V4L2_SUBDEV_FORMAT_ACTIVE) 500 return -EINVAL; 501 502 if (state->curr_norm & V4L2_STD_525_60) { 503 fi->interval.numerator = 1001; 504 fi->interval.denominator = 30000; 505 } else { 506 fi->interval.numerator = 1; 507 fi->interval.denominator = 25; 508 } 509 510 /* 511 * If the de-interlacer is active, the chip produces full video frames 512 * at the field rate. 513 */ 514 if (state->field == V4L2_FIELD_NONE) 515 fi->interval.denominator *= 2; 516 517 return 0; 518 } 519 520 static void adv7180_set_power_pin(struct adv7180_state *state, bool on) 521 { 522 if (!state->pwdn_gpio) 523 return; 524 525 if (on) { 526 gpiod_set_value_cansleep(state->pwdn_gpio, 0); 527 usleep_range(5000, 10000); 528 } else { 529 gpiod_set_value_cansleep(state->pwdn_gpio, 1); 530 } 531 } 532 533 static void adv7180_set_reset_pin(struct adv7180_state *state, bool on) 534 { 535 if (!state->rst_gpio) 536 return; 537 538 if (on) { 539 gpiod_set_value_cansleep(state->rst_gpio, 1); 540 } else { 541 gpiod_set_value_cansleep(state->rst_gpio, 0); 542 usleep_range(5000, 10000); 543 } 544 } 545 546 static const char * const test_pattern_menu[] = { 547 "Single color", 548 "Color bars", 549 "Luma ramp", 550 "Boundary box", 551 "Disable", 552 }; 553 554 static int adv7180_test_pattern(struct adv7180_state *state, int value) 555 { 556 unsigned int reg = 0; 557 558 /* Map menu value into register value */ 559 if (value < 3) 560 reg = value; 561 if (value == 3) 562 reg = 5; 563 564 adv7180_write(state, ADV7180_REG_ANALOG_CLAMP_CTL, reg); 565 566 if (value == ARRAY_SIZE(test_pattern_menu) - 1) { 567 reg = adv7180_read(state, ADV7180_REG_DEF_VALUE_Y); 568 reg &= ~ADV7180_DEF_VAL_EN; 569 adv7180_write(state, ADV7180_REG_DEF_VALUE_Y, reg); 570 return 0; 571 } 572 573 reg = adv7180_read(state, ADV7180_REG_DEF_VALUE_Y); 574 reg |= ADV7180_DEF_VAL_EN | ADV7180_DEF_VAL_AUTO_EN; 575 adv7180_write(state, ADV7180_REG_DEF_VALUE_Y, reg); 576 577 return 0; 578 } 579 580 static int adv7180_s_ctrl(struct v4l2_ctrl *ctrl) 581 { 582 struct v4l2_subdev *sd = to_adv7180_sd(ctrl); 583 struct adv7180_state *state = to_state(sd); 584 int ret = 0; 585 int val; 586 587 lockdep_assert_held(&state->mutex); 588 589 val = ctrl->val; 590 switch (ctrl->id) { 591 case V4L2_CID_BRIGHTNESS: 592 ret = adv7180_write(state, ADV7180_REG_BRI, val); 593 break; 594 case V4L2_CID_HUE: 595 /*Hue is inverted according to HSL chart */ 596 ret = adv7180_write(state, ADV7180_REG_HUE, -val); 597 break; 598 case V4L2_CID_CONTRAST: 599 ret = adv7180_write(state, ADV7180_REG_CON, val); 600 break; 601 case V4L2_CID_SATURATION: 602 /* 603 *This could be V4L2_CID_BLUE_BALANCE/V4L2_CID_RED_BALANCE 604 *Let's not confuse the user, everybody understands saturation 605 */ 606 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CB, val); 607 if (ret < 0) 608 break; 609 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CR, val); 610 break; 611 case V4L2_CID_ADV_FAST_SWITCH: 612 if (ctrl->val) { 613 /* ADI required write */ 614 adv7180_write(state, 0x80d9, 0x44); 615 adv7180_write(state, ADV7180_REG_FLCONTROL, 616 ADV7180_FLCONTROL_FL_ENABLE); 617 } else { 618 /* ADI required write */ 619 adv7180_write(state, 0x80d9, 0xc4); 620 adv7180_write(state, ADV7180_REG_FLCONTROL, 0x00); 621 } 622 break; 623 case V4L2_CID_TEST_PATTERN: 624 ret = adv7180_test_pattern(state, val); 625 break; 626 default: 627 ret = -EINVAL; 628 } 629 630 return ret; 631 } 632 633 static const struct v4l2_ctrl_ops adv7180_ctrl_ops = { 634 .s_ctrl = adv7180_s_ctrl, 635 }; 636 637 static const struct v4l2_ctrl_config adv7180_ctrl_fast_switch = { 638 .ops = &adv7180_ctrl_ops, 639 .id = V4L2_CID_ADV_FAST_SWITCH, 640 .name = "Fast Switching", 641 .type = V4L2_CTRL_TYPE_BOOLEAN, 642 .min = 0, 643 .max = 1, 644 .step = 1, 645 }; 646 647 static int adv7180_init_controls(struct adv7180_state *state) 648 { 649 v4l2_ctrl_handler_init(&state->ctrl_hdl, 4); 650 state->ctrl_hdl.lock = &state->mutex; 651 652 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, 653 V4L2_CID_BRIGHTNESS, ADV7180_BRI_MIN, 654 ADV7180_BRI_MAX, 1, ADV7180_BRI_DEF); 655 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, 656 V4L2_CID_CONTRAST, ADV7180_CON_MIN, 657 ADV7180_CON_MAX, 1, ADV7180_CON_DEF); 658 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, 659 V4L2_CID_SATURATION, ADV7180_SAT_MIN, 660 ADV7180_SAT_MAX, 1, ADV7180_SAT_DEF); 661 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, 662 V4L2_CID_HUE, ADV7180_HUE_MIN, 663 ADV7180_HUE_MAX, 1, ADV7180_HUE_DEF); 664 v4l2_ctrl_new_custom(&state->ctrl_hdl, &adv7180_ctrl_fast_switch, NULL); 665 666 if (state->chip_info->flags & ADV7180_FLAG_TEST_PATTERN) { 667 v4l2_ctrl_new_std_menu_items(&state->ctrl_hdl, 668 &adv7180_ctrl_ops, 669 V4L2_CID_TEST_PATTERN, 670 ARRAY_SIZE(test_pattern_menu) - 1, 671 0, 672 ARRAY_SIZE(test_pattern_menu) - 1, 673 test_pattern_menu); 674 } 675 676 state->sd.ctrl_handler = &state->ctrl_hdl; 677 if (state->ctrl_hdl.error) { 678 int err = state->ctrl_hdl.error; 679 680 v4l2_ctrl_handler_free(&state->ctrl_hdl); 681 return err; 682 } 683 684 return 0; 685 } 686 static void adv7180_exit_controls(struct adv7180_state *state) 687 { 688 v4l2_ctrl_handler_free(&state->ctrl_hdl); 689 } 690 691 static int adv7180_enum_mbus_code(struct v4l2_subdev *sd, 692 struct v4l2_subdev_state *sd_state, 693 struct v4l2_subdev_mbus_code_enum *code) 694 { 695 if (code->index != 0) 696 return -EINVAL; 697 698 code->code = MEDIA_BUS_FMT_UYVY8_2X8; 699 700 return 0; 701 } 702 703 static int adv7180_mbus_fmt(struct v4l2_subdev *sd, 704 struct v4l2_mbus_framefmt *fmt) 705 { 706 struct adv7180_state *state = to_state(sd); 707 708 fmt->code = MEDIA_BUS_FMT_UYVY8_2X8; 709 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M; 710 fmt->width = 720; 711 fmt->height = state->curr_norm & V4L2_STD_525_60 ? 480 : 576; 712 713 if (state->field == V4L2_FIELD_ALTERNATE) 714 fmt->height /= 2; 715 716 return 0; 717 } 718 719 static int adv7180_set_field_mode(struct adv7180_state *state) 720 { 721 if (!(state->chip_info->flags & ADV7180_FLAG_I2P)) 722 return 0; 723 724 if (state->field == V4L2_FIELD_NONE) { 725 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 726 adv7180_csi_write(state, 0x01, 0x20); 727 adv7180_csi_write(state, 0x02, 0x28); 728 adv7180_csi_write(state, 0x03, 0x38); 729 adv7180_csi_write(state, 0x04, 0x30); 730 adv7180_csi_write(state, 0x05, 0x30); 731 adv7180_csi_write(state, 0x06, 0x80); 732 adv7180_csi_write(state, 0x07, 0x70); 733 adv7180_csi_write(state, 0x08, 0x50); 734 } 735 adv7180_vpp_write(state, 0xa3, 0x00); 736 adv7180_vpp_write(state, 0x5b, 0x00); 737 adv7180_vpp_write(state, 0x55, 0x80); 738 } else { 739 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 740 adv7180_csi_write(state, 0x01, 0x18); 741 adv7180_csi_write(state, 0x02, 0x18); 742 adv7180_csi_write(state, 0x03, 0x30); 743 adv7180_csi_write(state, 0x04, 0x20); 744 adv7180_csi_write(state, 0x05, 0x28); 745 adv7180_csi_write(state, 0x06, 0x40); 746 adv7180_csi_write(state, 0x07, 0x58); 747 adv7180_csi_write(state, 0x08, 0x30); 748 } 749 adv7180_vpp_write(state, 0xa3, 0x70); 750 adv7180_vpp_write(state, 0x5b, 0x80); 751 adv7180_vpp_write(state, 0x55, 0x00); 752 } 753 754 return 0; 755 } 756 757 static int adv7180_get_pad_format(struct v4l2_subdev *sd, 758 struct v4l2_subdev_state *sd_state, 759 struct v4l2_subdev_format *format) 760 { 761 struct adv7180_state *state = to_state(sd); 762 763 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 764 format->format = *v4l2_subdev_state_get_format(sd_state, 0); 765 } else { 766 adv7180_mbus_fmt(sd, &format->format); 767 format->format.field = state->field; 768 } 769 770 return 0; 771 } 772 773 static int adv7180_set_pad_format(struct v4l2_subdev *sd, 774 struct v4l2_subdev_state *sd_state, 775 struct v4l2_subdev_format *format) 776 { 777 struct adv7180_state *state = to_state(sd); 778 struct v4l2_mbus_framefmt *framefmt; 779 int ret; 780 781 switch (format->format.field) { 782 case V4L2_FIELD_NONE: 783 if (state->chip_info->flags & ADV7180_FLAG_I2P) 784 break; 785 fallthrough; 786 default: 787 format->format.field = V4L2_FIELD_ALTERNATE; 788 break; 789 } 790 791 ret = adv7180_mbus_fmt(sd, &format->format); 792 793 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 794 state->field = format->format.field; 795 } else { 796 framefmt = v4l2_subdev_state_get_format(sd_state, 0); 797 *framefmt = format->format; 798 } 799 800 return ret; 801 } 802 803 static int adv7180_init_state(struct v4l2_subdev *sd, 804 struct v4l2_subdev_state *sd_state) 805 { 806 struct v4l2_subdev_format fmt = { 807 .which = sd_state ? V4L2_SUBDEV_FORMAT_TRY 808 : V4L2_SUBDEV_FORMAT_ACTIVE, 809 }; 810 811 return adv7180_set_pad_format(sd, sd_state, &fmt); 812 } 813 814 static int adv7180_get_mbus_config(struct v4l2_subdev *sd, 815 unsigned int pad, 816 struct v4l2_mbus_config *cfg) 817 { 818 struct adv7180_state *state = to_state(sd); 819 820 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 821 cfg->type = V4L2_MBUS_CSI2_DPHY; 822 cfg->bus.mipi_csi2.num_data_lanes = 1; 823 cfg->bus.mipi_csi2.flags = 0; 824 } else { 825 /* 826 * The ADV7180 sensor supports BT.601/656 output modes. 827 * The BT.656 is default and not yet configurable by s/w. 828 */ 829 cfg->bus.parallel.flags = V4L2_MBUS_MASTER | 830 V4L2_MBUS_PCLK_SAMPLE_RISING | 831 V4L2_MBUS_DATA_ACTIVE_HIGH; 832 cfg->type = V4L2_MBUS_BT656; 833 } 834 835 return 0; 836 } 837 838 static int adv7180_get_skip_frames(struct v4l2_subdev *sd, u32 *frames) 839 { 840 *frames = ADV7180_NUM_OF_SKIP_FRAMES; 841 842 return 0; 843 } 844 845 static int adv7180_g_tvnorms(struct v4l2_subdev *sd, v4l2_std_id *norm) 846 { 847 *norm = V4L2_STD_ALL; 848 return 0; 849 } 850 851 static int init_device(struct adv7180_state *state) 852 { 853 int ret; 854 855 lockdep_assert_held(&state->mutex); 856 857 ret = adv7180_program_std(state); 858 if (ret) 859 return ret; 860 861 adv7180_set_field_mode(state); 862 863 __v4l2_ctrl_handler_setup(&state->ctrl_hdl); 864 865 return ret; 866 } 867 868 static int adv7180_reset_device(struct adv7180_state *state) 869 { 870 int ret; 871 872 lockdep_assert_held(&state->mutex); 873 874 adv7180_set_power_pin(state, true); 875 adv7180_set_reset_pin(state, false); 876 877 adv7180_write(state, ADV7180_REG_PWR_MAN, ADV7180_PWR_MAN_RES); 878 usleep_range(5000, 10000); 879 880 /* 881 * If the devices decoder is power on after reset, power off so the 882 * device can be configured. 883 */ 884 if (state->chip_info->flags & ADV7180_FLAG_RESET_POWERED) 885 adv7180_set_power(state, false); 886 887 ret = state->chip_info->init(state); 888 if (ret) 889 return ret; 890 891 ret = init_device(state); 892 if (ret) 893 return ret; 894 895 /* register for interrupts */ 896 if (state->irq > 0) { 897 /* config the Interrupt pin to be active low */ 898 ret = adv7180_write(state, ADV7180_REG_ICONF1, 899 ADV7180_ICONF1_ACTIVE_LOW | 900 ADV7180_ICONF1_PSYNC_ONLY); 901 if (ret < 0) 902 return ret; 903 904 ret = adv7180_write(state, ADV7180_REG_IMR1, 0); 905 if (ret < 0) 906 return ret; 907 908 ret = adv7180_write(state, ADV7180_REG_IMR2, 0); 909 if (ret < 0) 910 return ret; 911 912 /* enable AD change interrupts */ 913 ret = adv7180_write(state, ADV7180_REG_IMR3, 914 ADV7180_IRQ3_AD_CHANGE); 915 if (ret < 0) 916 return ret; 917 918 ret = adv7180_write(state, ADV7180_REG_IMR4, 0); 919 if (ret < 0) 920 return ret; 921 } 922 923 /* 924 * If the devices decoder is power on after reset, restore the power 925 * after configuration. This is to preserve the behavior of the driver, 926 * not doing this result in the first 35+ frames captured being garbage. 927 */ 928 if (state->chip_info->flags & ADV7180_FLAG_RESET_POWERED) 929 adv7180_set_power(state, true); 930 931 return 0; 932 } 933 934 static int adv7180_s_stream(struct v4l2_subdev *sd, int enable) 935 { 936 struct adv7180_state *state = to_state(sd); 937 int ret; 938 939 /* Must wait until querystd released the lock */ 940 guard(mutex)(&state->mutex); 941 942 /* 943 * Always power off the decoder even if streaming is to be enabled, the 944 * decoder needs to be off for the device to be configured. 945 */ 946 ret = adv7180_set_power(state, false); 947 if (ret) 948 return ret; 949 950 if (enable) { 951 ret = init_device(state); 952 if (ret) 953 return ret; 954 955 ret = adv7180_set_power(state, true); 956 if (ret) 957 return ret; 958 } 959 960 state->streaming = enable; 961 962 return 0; 963 } 964 965 static int adv7180_subscribe_event(struct v4l2_subdev *sd, 966 struct v4l2_fh *fh, 967 struct v4l2_event_subscription *sub) 968 { 969 switch (sub->type) { 970 case V4L2_EVENT_SOURCE_CHANGE: 971 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub); 972 case V4L2_EVENT_CTRL: 973 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub); 974 default: 975 return -EINVAL; 976 } 977 } 978 979 #ifdef CONFIG_VIDEO_ADV_DEBUG 980 static int adv7180_g_register(struct v4l2_subdev *sd, 981 struct v4l2_dbg_register *reg) 982 { 983 struct adv7180_state *state = to_state(sd); 984 int ret; 985 986 ret = adv7180_read(state, reg->reg); 987 if (ret < 0) 988 return ret; 989 990 reg->val = ret; 991 reg->size = 1; 992 993 return 0; 994 } 995 996 static int adv7180_s_register(struct v4l2_subdev *sd, 997 const struct v4l2_dbg_register *reg) 998 { 999 struct adv7180_state *state = to_state(sd); 1000 1001 return adv7180_write(state, reg->reg, reg->val); 1002 } 1003 #endif 1004 1005 static const struct v4l2_subdev_video_ops adv7180_video_ops = { 1006 .s_std = adv7180_s_std, 1007 .g_std = adv7180_g_std, 1008 .querystd = adv7180_querystd, 1009 .g_input_status = adv7180_g_input_status, 1010 .s_routing = adv7180_s_routing, 1011 .g_tvnorms = adv7180_g_tvnorms, 1012 .s_stream = adv7180_s_stream, 1013 }; 1014 1015 static const struct v4l2_subdev_core_ops adv7180_core_ops = { 1016 .subscribe_event = adv7180_subscribe_event, 1017 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 1018 #ifdef CONFIG_VIDEO_ADV_DEBUG 1019 .g_register = adv7180_g_register, 1020 .s_register = adv7180_s_register, 1021 #endif 1022 }; 1023 1024 static const struct v4l2_subdev_pad_ops adv7180_pad_ops = { 1025 .enum_mbus_code = adv7180_enum_mbus_code, 1026 .set_fmt = adv7180_set_pad_format, 1027 .get_fmt = adv7180_get_pad_format, 1028 .get_frame_interval = adv7180_get_frame_interval, 1029 .get_mbus_config = adv7180_get_mbus_config, 1030 }; 1031 1032 static const struct v4l2_subdev_sensor_ops adv7180_sensor_ops = { 1033 .g_skip_frames = adv7180_get_skip_frames, 1034 }; 1035 1036 static const struct v4l2_subdev_ops adv7180_ops = { 1037 .core = &adv7180_core_ops, 1038 .video = &adv7180_video_ops, 1039 .pad = &adv7180_pad_ops, 1040 .sensor = &adv7180_sensor_ops, 1041 }; 1042 1043 static const struct v4l2_subdev_internal_ops adv7180_internal_ops = { 1044 .init_state = adv7180_init_state, 1045 }; 1046 1047 static irqreturn_t adv7180_irq(int irq, void *devid) 1048 { 1049 struct adv7180_state *state = devid; 1050 u8 isr3; 1051 1052 mutex_lock(&state->mutex); 1053 isr3 = adv7180_read(state, ADV7180_REG_ISR3); 1054 /* clear */ 1055 adv7180_write(state, ADV7180_REG_ICR3, isr3); 1056 1057 if (isr3 & ADV7180_IRQ3_AD_CHANGE) { 1058 static const struct v4l2_event src_ch = { 1059 .type = V4L2_EVENT_SOURCE_CHANGE, 1060 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, 1061 }; 1062 1063 v4l2_subdev_notify_event(&state->sd, &src_ch); 1064 } 1065 mutex_unlock(&state->mutex); 1066 1067 return IRQ_HANDLED; 1068 } 1069 1070 static int adv7180_init(struct adv7180_state *state) 1071 { 1072 int ret; 1073 1074 /* ITU-R BT.656-4 compatible */ 1075 ret = adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 1076 ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS); 1077 if (ret < 0) 1078 return ret; 1079 1080 /* Manually set V bit end position in NTSC mode */ 1081 return adv7180_write(state, ADV7180_REG_NTSC_V_BIT_END, 1082 ADV7180_NTSC_V_BIT_END_MANUAL_NVEND); 1083 } 1084 1085 static int adv7180_set_std(struct adv7180_state *state, unsigned int std) 1086 { 1087 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, 1088 (std << 4) | state->input); 1089 } 1090 1091 static int adv7180_select_input(struct adv7180_state *state, unsigned int input) 1092 { 1093 int ret; 1094 1095 ret = adv7180_read(state, ADV7180_REG_INPUT_CONTROL); 1096 if (ret < 0) 1097 return ret; 1098 1099 ret &= ~ADV7180_INPUT_CONTROL_INSEL_MASK; 1100 ret |= input; 1101 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, ret); 1102 } 1103 1104 static int adv7182_init(struct adv7180_state *state) 1105 { 1106 if (state->csi_client) 1107 adv7180_write(state, ADV7180_REG_CSI_SLAVE_ADDR, 1108 state->csi_client->addr << 1); 1109 1110 if (state->vpp_client) 1111 adv7180_write(state, ADV7180_REG_VPP_SLAVE_ADDR, 1112 state->vpp_client->addr << 1); 1113 1114 if (state->chip_info->flags & ADV7180_FLAG_V2) { 1115 /* ADI recommended writes for improved video quality */ 1116 adv7180_write(state, 0x0080, 0x51); 1117 adv7180_write(state, 0x0081, 0x51); 1118 adv7180_write(state, 0x0082, 0x68); 1119 } 1120 1121 /* ADI required writes */ 1122 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 1123 adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x4e); 1124 adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 0x57); 1125 adv7180_write(state, ADV7180_REG_CTRL_2, 0xc0); 1126 } else { 1127 if (state->chip_info->flags & ADV7180_FLAG_V2) { 1128 if (state->force_bt656_4) { 1129 /* ITU-R BT.656-4 compatible */ 1130 adv7180_write(state, 1131 ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 1132 ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS); 1133 /* Manually set NEWAVMODE */ 1134 adv7180_write(state, 1135 ADV7180_REG_VSYNC_FIELD_CTL_1, 1136 ADV7180_VSYNC_FIELD_CTL_1_NEWAV); 1137 /* Manually set V bit end position in NTSC mode */ 1138 adv7180_write(state, 1139 ADV7180_REG_NTSC_V_BIT_END, 1140 ADV7180_NTSC_V_BIT_END_MANUAL_NVEND); 1141 } else { 1142 adv7180_write(state, 1143 ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 1144 0x17); 1145 } 1146 } else { 1147 adv7180_write(state, 1148 ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 1149 0x07); 1150 } 1151 adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x0c); 1152 adv7180_write(state, ADV7180_REG_CTRL_2, 0x40); 1153 } 1154 1155 adv7180_write(state, 0x0013, 0x00); 1156 1157 return 0; 1158 } 1159 1160 static int adv7182_set_std(struct adv7180_state *state, unsigned int std) 1161 { 1162 /* Failing to set the reserved bit can result in increased video noise */ 1163 return adv7180_write(state, ADV7182_REG_INPUT_VIDSEL, 1164 (std << 4) | ADV7182_REG_INPUT_RESERVED); 1165 } 1166 1167 enum adv7182_input_type { 1168 ADV7182_INPUT_TYPE_CVBS, 1169 ADV7182_INPUT_TYPE_DIFF_CVBS, 1170 ADV7182_INPUT_TYPE_SVIDEO, 1171 ADV7182_INPUT_TYPE_YPBPR, 1172 }; 1173 1174 static enum adv7182_input_type adv7182_get_input_type(unsigned int input) 1175 { 1176 switch (input) { 1177 case ADV7182_INPUT_CVBS_AIN1: 1178 case ADV7182_INPUT_CVBS_AIN2: 1179 case ADV7182_INPUT_CVBS_AIN3: 1180 case ADV7182_INPUT_CVBS_AIN4: 1181 case ADV7182_INPUT_CVBS_AIN5: 1182 case ADV7182_INPUT_CVBS_AIN6: 1183 case ADV7182_INPUT_CVBS_AIN7: 1184 case ADV7182_INPUT_CVBS_AIN8: 1185 return ADV7182_INPUT_TYPE_CVBS; 1186 case ADV7182_INPUT_SVIDEO_AIN1_AIN2: 1187 case ADV7182_INPUT_SVIDEO_AIN3_AIN4: 1188 case ADV7182_INPUT_SVIDEO_AIN5_AIN6: 1189 case ADV7182_INPUT_SVIDEO_AIN7_AIN8: 1190 return ADV7182_INPUT_TYPE_SVIDEO; 1191 case ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3: 1192 case ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6: 1193 return ADV7182_INPUT_TYPE_YPBPR; 1194 case ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2: 1195 case ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4: 1196 case ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6: 1197 case ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8: 1198 return ADV7182_INPUT_TYPE_DIFF_CVBS; 1199 default: /* Will never happen */ 1200 return 0; 1201 } 1202 } 1203 1204 /* ADI recommended writes to registers 0x52, 0x53, 0x54 */ 1205 static unsigned int adv7182_lbias_settings[][3] = { 1206 [ADV7182_INPUT_TYPE_CVBS] = { 0xCB, 0x4E, 0x80 }, 1207 [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 }, 1208 [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 }, 1209 [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 }, 1210 }; 1211 1212 static unsigned int adv7280_lbias_settings[][3] = { 1213 [ADV7182_INPUT_TYPE_CVBS] = { 0xCD, 0x4E, 0x80 }, 1214 [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 }, 1215 [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 }, 1216 [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 }, 1217 }; 1218 1219 static int adv7182_select_input(struct adv7180_state *state, unsigned int input) 1220 { 1221 enum adv7182_input_type input_type; 1222 unsigned int *lbias; 1223 unsigned int i; 1224 int ret; 1225 1226 ret = adv7180_write(state, ADV7180_REG_INPUT_CONTROL, input); 1227 if (ret) 1228 return ret; 1229 1230 /* Reset clamp circuitry - ADI recommended writes */ 1231 adv7180_write(state, ADV7180_REG_RST_CLAMP, 0x00); 1232 adv7180_write(state, ADV7180_REG_RST_CLAMP, 0xff); 1233 1234 input_type = adv7182_get_input_type(input); 1235 1236 switch (input_type) { 1237 case ADV7182_INPUT_TYPE_CVBS: 1238 case ADV7182_INPUT_TYPE_DIFF_CVBS: 1239 /* ADI recommends to use the SH1 filter */ 1240 adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x41); 1241 break; 1242 default: 1243 adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x01); 1244 break; 1245 } 1246 1247 if (state->chip_info->flags & ADV7180_FLAG_V2) 1248 lbias = adv7280_lbias_settings[input_type]; 1249 else 1250 lbias = adv7182_lbias_settings[input_type]; 1251 1252 for (i = 0; i < ARRAY_SIZE(adv7182_lbias_settings[0]); i++) 1253 adv7180_write(state, ADV7180_REG_CVBS_TRIM + i, lbias[i]); 1254 1255 if (input_type == ADV7182_INPUT_TYPE_DIFF_CVBS) { 1256 /* ADI required writes to make differential CVBS work */ 1257 adv7180_write(state, ADV7180_REG_RES_CIR, 0xa8); 1258 adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0x90); 1259 adv7180_write(state, ADV7180_REG_DIFF_MODE, 0xb0); 1260 adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x08); 1261 adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0xa0); 1262 } else { 1263 adv7180_write(state, ADV7180_REG_RES_CIR, 0xf0); 1264 adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0xd0); 1265 adv7180_write(state, ADV7180_REG_DIFF_MODE, 0x10); 1266 adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x9c); 1267 adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0x00); 1268 } 1269 1270 return 0; 1271 } 1272 1273 static const struct adv7180_chip_info adv7180_info = { 1274 .flags = ADV7180_FLAG_RESET_POWERED, 1275 /* We cannot discriminate between LQFP and 40-pin LFCSP, so accept 1276 * all inputs and let the card driver take care of validation 1277 */ 1278 .valid_input_mask = BIT(ADV7180_INPUT_CVBS_AIN1) | 1279 BIT(ADV7180_INPUT_CVBS_AIN2) | 1280 BIT(ADV7180_INPUT_CVBS_AIN3) | 1281 BIT(ADV7180_INPUT_CVBS_AIN4) | 1282 BIT(ADV7180_INPUT_CVBS_AIN5) | 1283 BIT(ADV7180_INPUT_CVBS_AIN6) | 1284 BIT(ADV7180_INPUT_SVIDEO_AIN1_AIN2) | 1285 BIT(ADV7180_INPUT_SVIDEO_AIN3_AIN4) | 1286 BIT(ADV7180_INPUT_SVIDEO_AIN5_AIN6) | 1287 BIT(ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1288 BIT(ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6), 1289 .init = adv7180_init, 1290 .set_std = adv7180_set_std, 1291 .select_input = adv7180_select_input, 1292 }; 1293 1294 static const struct adv7180_chip_info adv7182_info = { 1295 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1296 BIT(ADV7182_INPUT_CVBS_AIN2) | 1297 BIT(ADV7182_INPUT_CVBS_AIN3) | 1298 BIT(ADV7182_INPUT_CVBS_AIN4) | 1299 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1300 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1301 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1302 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1303 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4), 1304 .init = adv7182_init, 1305 .set_std = adv7182_set_std, 1306 .select_input = adv7182_select_input, 1307 }; 1308 1309 static const struct adv7180_chip_info adv7280_info = { 1310 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P | ADV7180_FLAG_TEST_PATTERN, 1311 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1312 BIT(ADV7182_INPUT_CVBS_AIN2) | 1313 BIT(ADV7182_INPUT_CVBS_AIN3) | 1314 BIT(ADV7182_INPUT_CVBS_AIN4) | 1315 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1316 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1317 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3), 1318 .init = adv7182_init, 1319 .set_std = adv7182_set_std, 1320 .select_input = adv7182_select_input, 1321 }; 1322 1323 static const struct adv7180_chip_info adv7280_m_info = { 1324 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P | 1325 ADV7180_FLAG_TEST_PATTERN, 1326 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1327 BIT(ADV7182_INPUT_CVBS_AIN2) | 1328 BIT(ADV7182_INPUT_CVBS_AIN3) | 1329 BIT(ADV7182_INPUT_CVBS_AIN4) | 1330 BIT(ADV7182_INPUT_CVBS_AIN5) | 1331 BIT(ADV7182_INPUT_CVBS_AIN6) | 1332 BIT(ADV7182_INPUT_CVBS_AIN7) | 1333 BIT(ADV7182_INPUT_CVBS_AIN8) | 1334 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1335 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1336 BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) | 1337 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1338 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1339 BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6), 1340 .init = adv7182_init, 1341 .set_std = adv7182_set_std, 1342 .select_input = adv7182_select_input, 1343 }; 1344 1345 static const struct adv7180_chip_info adv7281_info = { 1346 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | 1347 ADV7180_FLAG_TEST_PATTERN, 1348 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1349 BIT(ADV7182_INPUT_CVBS_AIN2) | 1350 BIT(ADV7182_INPUT_CVBS_AIN7) | 1351 BIT(ADV7182_INPUT_CVBS_AIN8) | 1352 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1353 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1354 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1355 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1356 .init = adv7182_init, 1357 .set_std = adv7182_set_std, 1358 .select_input = adv7182_select_input, 1359 }; 1360 1361 static const struct adv7180_chip_info adv7281_m_info = { 1362 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | 1363 ADV7180_FLAG_TEST_PATTERN, 1364 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1365 BIT(ADV7182_INPUT_CVBS_AIN2) | 1366 BIT(ADV7182_INPUT_CVBS_AIN3) | 1367 BIT(ADV7182_INPUT_CVBS_AIN4) | 1368 BIT(ADV7182_INPUT_CVBS_AIN7) | 1369 BIT(ADV7182_INPUT_CVBS_AIN8) | 1370 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1371 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1372 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1373 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1374 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1375 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) | 1376 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1377 .init = adv7182_init, 1378 .set_std = adv7182_set_std, 1379 .select_input = adv7182_select_input, 1380 }; 1381 1382 static const struct adv7180_chip_info adv7281_ma_info = { 1383 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | 1384 ADV7180_FLAG_TEST_PATTERN, 1385 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1386 BIT(ADV7182_INPUT_CVBS_AIN2) | 1387 BIT(ADV7182_INPUT_CVBS_AIN3) | 1388 BIT(ADV7182_INPUT_CVBS_AIN4) | 1389 BIT(ADV7182_INPUT_CVBS_AIN5) | 1390 BIT(ADV7182_INPUT_CVBS_AIN6) | 1391 BIT(ADV7182_INPUT_CVBS_AIN7) | 1392 BIT(ADV7182_INPUT_CVBS_AIN8) | 1393 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1394 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1395 BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) | 1396 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1397 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1398 BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6) | 1399 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1400 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) | 1401 BIT(ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6) | 1402 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1403 .init = adv7182_init, 1404 .set_std = adv7182_set_std, 1405 .select_input = adv7182_select_input, 1406 }; 1407 1408 static const struct adv7180_chip_info adv7282_info = { 1409 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P | ADV7180_FLAG_TEST_PATTERN, 1410 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1411 BIT(ADV7182_INPUT_CVBS_AIN2) | 1412 BIT(ADV7182_INPUT_CVBS_AIN7) | 1413 BIT(ADV7182_INPUT_CVBS_AIN8) | 1414 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1415 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1416 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1417 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1418 .init = adv7182_init, 1419 .set_std = adv7182_set_std, 1420 .select_input = adv7182_select_input, 1421 }; 1422 1423 static const struct adv7180_chip_info adv7282_m_info = { 1424 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P | 1425 ADV7180_FLAG_TEST_PATTERN, 1426 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1427 BIT(ADV7182_INPUT_CVBS_AIN2) | 1428 BIT(ADV7182_INPUT_CVBS_AIN3) | 1429 BIT(ADV7182_INPUT_CVBS_AIN4) | 1430 BIT(ADV7182_INPUT_CVBS_AIN7) | 1431 BIT(ADV7182_INPUT_CVBS_AIN8) | 1432 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1433 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1434 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1435 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1436 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) | 1437 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1438 .init = adv7182_init, 1439 .set_std = adv7182_set_std, 1440 .select_input = adv7182_select_input, 1441 }; 1442 1443 static int adv7180_probe(struct i2c_client *client) 1444 { 1445 struct device_node *np = client->dev.of_node; 1446 struct adv7180_state *state; 1447 struct v4l2_subdev *sd; 1448 int ret; 1449 1450 /* Check if the adapter supports the needed features */ 1451 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 1452 return -EIO; 1453 1454 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); 1455 if (state == NULL) 1456 return -ENOMEM; 1457 1458 state->client = client; 1459 state->field = V4L2_FIELD_ALTERNATE; 1460 state->chip_info = i2c_get_match_data(client); 1461 1462 state->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown", 1463 GPIOD_OUT_HIGH); 1464 if (IS_ERR(state->pwdn_gpio)) { 1465 ret = PTR_ERR(state->pwdn_gpio); 1466 v4l_err(client, "request for power pin failed: %d\n", ret); 1467 return ret; 1468 } 1469 1470 state->rst_gpio = devm_gpiod_get_optional(&client->dev, "reset", 1471 GPIOD_OUT_HIGH); 1472 if (IS_ERR(state->rst_gpio)) { 1473 ret = PTR_ERR(state->rst_gpio); 1474 v4l_err(client, "request for reset pin failed: %d\n", ret); 1475 return ret; 1476 } 1477 1478 if (of_property_read_bool(np, "adv,force-bt656-4") || 1479 of_property_read_bool(np, "adi,force-bt656-4")) 1480 state->force_bt656_4 = true; 1481 1482 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 1483 state->csi_client = 1484 i2c_new_ancillary_device(client, "csi", 1485 ADV7180_DEFAULT_CSI_I2C_ADDR); 1486 if (IS_ERR(state->csi_client)) 1487 return PTR_ERR(state->csi_client); 1488 } 1489 1490 if (state->chip_info->flags & ADV7180_FLAG_I2P) { 1491 state->vpp_client = 1492 i2c_new_ancillary_device(client, "vpp", 1493 ADV7180_DEFAULT_VPP_I2C_ADDR); 1494 if (IS_ERR(state->vpp_client)) { 1495 ret = PTR_ERR(state->vpp_client); 1496 goto err_unregister_csi_client; 1497 } 1498 } 1499 1500 state->irq = client->irq; 1501 mutex_init(&state->mutex); 1502 state->curr_norm = V4L2_STD_NTSC; 1503 1504 state->input = 0; 1505 sd = &state->sd; 1506 v4l2_i2c_subdev_init(sd, client, &adv7180_ops); 1507 sd->internal_ops = &adv7180_internal_ops; 1508 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; 1509 1510 ret = adv7180_init_controls(state); 1511 if (ret) 1512 goto err_unregister_vpp_client; 1513 1514 state->pad.flags = MEDIA_PAD_FL_SOURCE; 1515 sd->entity.function = MEDIA_ENT_F_ATV_DECODER; 1516 ret = media_entity_pads_init(&sd->entity, 1, &state->pad); 1517 if (ret) 1518 goto err_free_ctrl; 1519 1520 mutex_lock(&state->mutex); 1521 ret = adv7180_reset_device(state); 1522 mutex_unlock(&state->mutex); 1523 if (ret) 1524 goto err_media_entity_cleanup; 1525 1526 if (state->irq > 0) { 1527 ret = request_threaded_irq(client->irq, NULL, adv7180_irq, 1528 IRQF_ONESHOT | IRQF_TRIGGER_FALLING, 1529 KBUILD_MODNAME, state); 1530 if (ret) 1531 goto err_media_entity_cleanup; 1532 } 1533 1534 ret = v4l2_async_register_subdev(sd); 1535 if (ret) 1536 goto err_free_irq; 1537 1538 mutex_lock(&state->mutex); 1539 ret = adv7180_read(state, ADV7180_REG_IDENT); 1540 mutex_unlock(&state->mutex); 1541 if (ret < 0) 1542 goto err_v4l2_async_unregister; 1543 1544 v4l_info(client, "chip id 0x%x found @ 0x%02x (%s)\n", 1545 ret, client->addr, client->adapter->name); 1546 1547 return 0; 1548 1549 err_v4l2_async_unregister: 1550 v4l2_async_unregister_subdev(sd); 1551 err_free_irq: 1552 if (state->irq > 0) 1553 free_irq(client->irq, state); 1554 err_media_entity_cleanup: 1555 media_entity_cleanup(&sd->entity); 1556 err_free_ctrl: 1557 adv7180_exit_controls(state); 1558 err_unregister_vpp_client: 1559 i2c_unregister_device(state->vpp_client); 1560 err_unregister_csi_client: 1561 i2c_unregister_device(state->csi_client); 1562 mutex_destroy(&state->mutex); 1563 return ret; 1564 } 1565 1566 static void adv7180_remove(struct i2c_client *client) 1567 { 1568 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1569 struct adv7180_state *state = to_state(sd); 1570 1571 v4l2_async_unregister_subdev(sd); 1572 1573 if (state->irq > 0) 1574 free_irq(client->irq, state); 1575 1576 media_entity_cleanup(&sd->entity); 1577 adv7180_exit_controls(state); 1578 1579 i2c_unregister_device(state->vpp_client); 1580 i2c_unregister_device(state->csi_client); 1581 1582 adv7180_set_reset_pin(state, true); 1583 adv7180_set_power_pin(state, false); 1584 1585 mutex_destroy(&state->mutex); 1586 } 1587 1588 #ifdef CONFIG_PM_SLEEP 1589 static int adv7180_suspend(struct device *dev) 1590 { 1591 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1592 struct adv7180_state *state = to_state(sd); 1593 1594 guard(mutex)(&state->mutex); 1595 1596 return adv7180_set_power(state, false); 1597 } 1598 1599 static int adv7180_resume(struct device *dev) 1600 { 1601 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1602 struct adv7180_state *state = to_state(sd); 1603 int ret; 1604 1605 guard(mutex)(&state->mutex); 1606 1607 ret = adv7180_reset_device(state); 1608 if (ret < 0) 1609 return ret; 1610 1611 /* If we were streaming when suspending, start decoder. */ 1612 if (state->streaming) { 1613 ret = adv7180_set_power(state, true); 1614 if (ret) 1615 return ret; 1616 } 1617 1618 return 0; 1619 } 1620 1621 static SIMPLE_DEV_PM_OPS(adv7180_pm_ops, adv7180_suspend, adv7180_resume); 1622 #define ADV7180_PM_OPS (&adv7180_pm_ops) 1623 1624 #else 1625 #define ADV7180_PM_OPS NULL 1626 #endif 1627 1628 static const struct i2c_device_id adv7180_id[] = { 1629 { "adv7180", (kernel_ulong_t)&adv7180_info }, 1630 { "adv7180cp", (kernel_ulong_t)&adv7180_info }, 1631 { "adv7180st", (kernel_ulong_t)&adv7180_info }, 1632 { "adv7182", (kernel_ulong_t)&adv7182_info }, 1633 { "adv7280", (kernel_ulong_t)&adv7280_info }, 1634 { "adv7280-m", (kernel_ulong_t)&adv7280_m_info }, 1635 { "adv7281", (kernel_ulong_t)&adv7281_info }, 1636 { "adv7281-m", (kernel_ulong_t)&adv7281_m_info }, 1637 { "adv7281-ma", (kernel_ulong_t)&adv7281_ma_info }, 1638 { "adv7282", (kernel_ulong_t)&adv7282_info }, 1639 { "adv7282-m", (kernel_ulong_t)&adv7282_m_info }, 1640 {} 1641 }; 1642 MODULE_DEVICE_TABLE(i2c, adv7180_id); 1643 1644 static const struct of_device_id adv7180_of_id[] = { 1645 { .compatible = "adi,adv7180", &adv7180_info }, 1646 { .compatible = "adi,adv7180cp", &adv7180_info }, 1647 { .compatible = "adi,adv7180st", &adv7180_info }, 1648 { .compatible = "adi,adv7182", &adv7182_info }, 1649 { .compatible = "adi,adv7280", &adv7280_info }, 1650 { .compatible = "adi,adv7280-m", &adv7280_m_info }, 1651 { .compatible = "adi,adv7281", &adv7281_info }, 1652 { .compatible = "adi,adv7281-m", &adv7281_m_info }, 1653 { .compatible = "adi,adv7281-ma", &adv7281_ma_info }, 1654 { .compatible = "adi,adv7282", &adv7282_info }, 1655 { .compatible = "adi,adv7282-m", &adv7282_m_info }, 1656 {} 1657 }; 1658 MODULE_DEVICE_TABLE(of, adv7180_of_id); 1659 1660 static struct i2c_driver adv7180_driver = { 1661 .driver = { 1662 .name = KBUILD_MODNAME, 1663 .pm = ADV7180_PM_OPS, 1664 .of_match_table = adv7180_of_id, 1665 }, 1666 .probe = adv7180_probe, 1667 .remove = adv7180_remove, 1668 .id_table = adv7180_id, 1669 }; 1670 1671 module_i2c_driver(adv7180_driver); 1672 1673 MODULE_DESCRIPTION("Analog Devices ADV7180 video decoder driver"); 1674 MODULE_AUTHOR("Mocean Laboratories"); 1675 MODULE_LICENSE("GPL v2"); 1676