1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * adv7180.c Analog Devices ADV7180 video decoder driver 4 * Copyright (c) 2009 Intel Corporation 5 * Copyright (C) 2013 Cogent Embedded, Inc. 6 * Copyright (C) 2013 Renesas Solutions Corp. 7 */ 8 #include <linux/mod_devicetable.h> 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/errno.h> 12 #include <linux/kernel.h> 13 #include <linux/interrupt.h> 14 #include <linux/i2c.h> 15 #include <linux/slab.h> 16 #include <linux/of.h> 17 #include <linux/gpio/consumer.h> 18 #include <linux/videodev2.h> 19 #include <media/v4l2-ioctl.h> 20 #include <media/v4l2-event.h> 21 #include <media/v4l2-device.h> 22 #include <media/v4l2-ctrls.h> 23 #include <linux/mutex.h> 24 #include <linux/delay.h> 25 26 #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM 0x0 27 #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM_PED 0x1 28 #define ADV7180_STD_AD_PAL_N_NTSC_J_SECAM 0x2 29 #define ADV7180_STD_AD_PAL_N_NTSC_M_SECAM 0x3 30 #define ADV7180_STD_NTSC_J 0x4 31 #define ADV7180_STD_NTSC_M 0x5 32 #define ADV7180_STD_PAL60 0x6 33 #define ADV7180_STD_NTSC_443 0x7 34 #define ADV7180_STD_PAL_BG 0x8 35 #define ADV7180_STD_PAL_N 0x9 36 #define ADV7180_STD_PAL_M 0xa 37 #define ADV7180_STD_PAL_M_PED 0xb 38 #define ADV7180_STD_PAL_COMB_N 0xc 39 #define ADV7180_STD_PAL_COMB_N_PED 0xd 40 #define ADV7180_STD_PAL_SECAM 0xe 41 #define ADV7180_STD_PAL_SECAM_PED 0xf 42 43 #define ADV7180_REG_INPUT_CONTROL 0x0000 44 #define ADV7180_INPUT_CONTROL_INSEL_MASK 0x0f 45 46 #define ADV7182_REG_INPUT_VIDSEL 0x0002 47 #define ADV7182_REG_INPUT_RESERVED BIT(2) 48 49 #define ADV7180_REG_OUTPUT_CONTROL 0x0003 50 #define ADV7180_REG_EXTENDED_OUTPUT_CONTROL 0x0004 51 #define ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS 0xC5 52 53 #define ADV7180_REG_AUTODETECT_ENABLE 0x0007 54 #define ADV7180_AUTODETECT_DEFAULT 0x7f 55 /* Contrast */ 56 #define ADV7180_REG_CON 0x0008 /*Unsigned */ 57 #define ADV7180_CON_MIN 0 58 #define ADV7180_CON_DEF 128 59 #define ADV7180_CON_MAX 255 60 /* Brightness*/ 61 #define ADV7180_REG_BRI 0x000a /*Signed */ 62 #define ADV7180_BRI_MIN -128 63 #define ADV7180_BRI_DEF 0 64 #define ADV7180_BRI_MAX 127 65 /* Hue */ 66 #define ADV7180_REG_HUE 0x000b /*Signed, inverted */ 67 #define ADV7180_HUE_MIN -127 68 #define ADV7180_HUE_DEF 0 69 #define ADV7180_HUE_MAX 128 70 71 #define ADV7180_REG_DEF_VALUE_Y 0x000c 72 #define ADV7180_DEF_VAL_EN 0x1 73 #define ADV7180_DEF_VAL_AUTO_EN 0x2 74 #define ADV7180_REG_CTRL 0x000e 75 #define ADV7180_CTRL_IRQ_SPACE 0x20 76 77 #define ADV7180_REG_PWR_MAN 0x0f 78 #define ADV7180_PWR_MAN_ON 0x04 79 #define ADV7180_PWR_MAN_OFF 0x24 80 #define ADV7180_PWR_MAN_RES 0x80 81 82 #define ADV7180_REG_STATUS1 0x0010 83 #define ADV7180_STATUS1_IN_LOCK 0x01 84 #define ADV7180_STATUS1_AUTOD_MASK 0x70 85 #define ADV7180_STATUS1_AUTOD_NTSM_M_J 0x00 86 #define ADV7180_STATUS1_AUTOD_NTSC_4_43 0x10 87 #define ADV7180_STATUS1_AUTOD_PAL_M 0x20 88 #define ADV7180_STATUS1_AUTOD_PAL_60 0x30 89 #define ADV7180_STATUS1_AUTOD_PAL_B_G 0x40 90 #define ADV7180_STATUS1_AUTOD_SECAM 0x50 91 #define ADV7180_STATUS1_AUTOD_PAL_COMB 0x60 92 #define ADV7180_STATUS1_AUTOD_SECAM_525 0x70 93 94 #define ADV7180_REG_IDENT 0x0011 95 #define ADV7180_ID_7180 0x18 96 97 #define ADV7180_REG_STATUS3 0x0013 98 #define ADV7180_REG_ANALOG_CLAMP_CTL 0x0014 99 #define ADV7180_REG_SHAP_FILTER_CTL_1 0x0017 100 #define ADV7180_REG_CTRL_2 0x001d 101 #define ADV7180_REG_VSYNC_FIELD_CTL_1 0x0031 102 #define ADV7180_VSYNC_FIELD_CTL_1_NEWAV 0x12 103 #define ADV7180_REG_MANUAL_WIN_CTL_1 0x003d 104 #define ADV7180_REG_MANUAL_WIN_CTL_2 0x003e 105 #define ADV7180_REG_MANUAL_WIN_CTL_3 0x003f 106 #define ADV7180_REG_LOCK_CNT 0x0051 107 #define ADV7180_REG_CVBS_TRIM 0x0052 108 #define ADV7180_REG_CLAMP_ADJ 0x005a 109 #define ADV7180_REG_RES_CIR 0x005f 110 #define ADV7180_REG_DIFF_MODE 0x0060 111 112 #define ADV7180_REG_ICONF1 0x2040 113 #define ADV7180_ICONF1_ACTIVE_LOW 0x01 114 #define ADV7180_ICONF1_PSYNC_ONLY 0x10 115 #define ADV7180_ICONF1_ACTIVE_TO_CLR 0xC0 116 /* Saturation */ 117 #define ADV7180_REG_SD_SAT_CB 0x00e3 /*Unsigned */ 118 #define ADV7180_REG_SD_SAT_CR 0x00e4 /*Unsigned */ 119 #define ADV7180_SAT_MIN 0 120 #define ADV7180_SAT_DEF 128 121 #define ADV7180_SAT_MAX 255 122 123 #define ADV7180_IRQ1_LOCK 0x01 124 #define ADV7180_IRQ1_UNLOCK 0x02 125 #define ADV7180_REG_ISR1 0x2042 126 #define ADV7180_REG_ICR1 0x2043 127 #define ADV7180_REG_IMR1 0x2044 128 #define ADV7180_REG_IMR2 0x2048 129 #define ADV7180_IRQ3_AD_CHANGE 0x08 130 #define ADV7180_REG_ISR3 0x204A 131 #define ADV7180_REG_ICR3 0x204B 132 #define ADV7180_REG_IMR3 0x204C 133 #define ADV7180_REG_IMR4 0x2050 134 135 #define ADV7180_REG_NTSC_V_BIT_END 0x00E6 136 #define ADV7180_NTSC_V_BIT_END_MANUAL_NVEND 0x4F 137 138 #define ADV7180_REG_VPP_SLAVE_ADDR 0xFD 139 #define ADV7180_REG_CSI_SLAVE_ADDR 0xFE 140 141 #define ADV7180_REG_ACE_CTRL1 0x4080 142 #define ADV7180_REG_ACE_CTRL5 0x4084 143 #define ADV7180_REG_FLCONTROL 0x40e0 144 #define ADV7180_FLCONTROL_FL_ENABLE 0x1 145 146 #define ADV7180_REG_RST_CLAMP 0x809c 147 #define ADV7180_REG_AGC_ADJ1 0x80b6 148 #define ADV7180_REG_AGC_ADJ2 0x80c0 149 150 #define ADV7180_CSI_REG_PWRDN 0x00 151 #define ADV7180_CSI_PWRDN 0x80 152 153 #define ADV7180_INPUT_CVBS_AIN1 0x00 154 #define ADV7180_INPUT_CVBS_AIN2 0x01 155 #define ADV7180_INPUT_CVBS_AIN3 0x02 156 #define ADV7180_INPUT_CVBS_AIN4 0x03 157 #define ADV7180_INPUT_CVBS_AIN5 0x04 158 #define ADV7180_INPUT_CVBS_AIN6 0x05 159 #define ADV7180_INPUT_SVIDEO_AIN1_AIN2 0x06 160 #define ADV7180_INPUT_SVIDEO_AIN3_AIN4 0x07 161 #define ADV7180_INPUT_SVIDEO_AIN5_AIN6 0x08 162 #define ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3 0x09 163 #define ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0a 164 165 #define ADV7182_INPUT_CVBS_AIN1 0x00 166 #define ADV7182_INPUT_CVBS_AIN2 0x01 167 #define ADV7182_INPUT_CVBS_AIN3 0x02 168 #define ADV7182_INPUT_CVBS_AIN4 0x03 169 #define ADV7182_INPUT_CVBS_AIN5 0x04 170 #define ADV7182_INPUT_CVBS_AIN6 0x05 171 #define ADV7182_INPUT_CVBS_AIN7 0x06 172 #define ADV7182_INPUT_CVBS_AIN8 0x07 173 #define ADV7182_INPUT_SVIDEO_AIN1_AIN2 0x08 174 #define ADV7182_INPUT_SVIDEO_AIN3_AIN4 0x09 175 #define ADV7182_INPUT_SVIDEO_AIN5_AIN6 0x0a 176 #define ADV7182_INPUT_SVIDEO_AIN7_AIN8 0x0b 177 #define ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3 0x0c 178 #define ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0d 179 #define ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2 0x0e 180 #define ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4 0x0f 181 #define ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6 0x10 182 #define ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8 0x11 183 184 #define ADV7180_DEFAULT_CSI_I2C_ADDR 0x44 185 #define ADV7180_DEFAULT_VPP_I2C_ADDR 0x42 186 187 #define V4L2_CID_ADV_FAST_SWITCH (V4L2_CID_USER_ADV7180_BASE + 0x00) 188 189 /* Initial number of frames to skip to avoid possible garbage */ 190 #define ADV7180_NUM_OF_SKIP_FRAMES 2 191 192 struct adv7180_state; 193 194 #define ADV7180_FLAG_RESET_POWERED BIT(0) 195 #define ADV7180_FLAG_V2 BIT(1) 196 #define ADV7180_FLAG_MIPI_CSI2 BIT(2) 197 #define ADV7180_FLAG_I2P BIT(3) 198 #define ADV7180_FLAG_TEST_PATTERN BIT(4) 199 200 struct adv7180_chip_info { 201 unsigned int flags; 202 unsigned int valid_input_mask; 203 int (*set_std)(struct adv7180_state *st, unsigned int std); 204 int (*select_input)(struct adv7180_state *st, unsigned int input); 205 int (*init)(struct adv7180_state *state); 206 }; 207 208 struct adv7180_state { 209 struct v4l2_ctrl_handler ctrl_hdl; 210 struct v4l2_subdev sd; 211 struct media_pad pad; 212 struct mutex mutex; /* mutual excl. when accessing chip */ 213 int irq; 214 struct gpio_desc *pwdn_gpio; 215 struct gpio_desc *rst_gpio; 216 v4l2_std_id curr_norm; 217 bool streaming; 218 u8 input; 219 220 struct i2c_client *client; 221 unsigned int register_page; 222 struct i2c_client *csi_client; 223 struct i2c_client *vpp_client; 224 const struct adv7180_chip_info *chip_info; 225 enum v4l2_field field; 226 bool force_bt656_4; 227 }; 228 #define to_adv7180_sd(_ctrl) (&container_of(_ctrl->handler, \ 229 struct adv7180_state, \ 230 ctrl_hdl)->sd) 231 232 static int adv7180_select_page(struct adv7180_state *state, unsigned int page) 233 { 234 if (state->register_page != page) { 235 i2c_smbus_write_byte_data(state->client, ADV7180_REG_CTRL, 236 page); 237 state->register_page = page; 238 } 239 240 return 0; 241 } 242 243 static int adv7180_write(struct adv7180_state *state, unsigned int reg, 244 unsigned int value) 245 { 246 lockdep_assert_held(&state->mutex); 247 adv7180_select_page(state, reg >> 8); 248 return i2c_smbus_write_byte_data(state->client, reg & 0xff, value); 249 } 250 251 static int adv7180_read(struct adv7180_state *state, unsigned int reg) 252 { 253 lockdep_assert_held(&state->mutex); 254 adv7180_select_page(state, reg >> 8); 255 return i2c_smbus_read_byte_data(state->client, reg & 0xff); 256 } 257 258 static int adv7180_csi_write(struct adv7180_state *state, unsigned int reg, 259 unsigned int value) 260 { 261 return i2c_smbus_write_byte_data(state->csi_client, reg, value); 262 } 263 264 static int adv7180_set_video_standard(struct adv7180_state *state, 265 unsigned int std) 266 { 267 return state->chip_info->set_std(state, std); 268 } 269 270 static int adv7180_vpp_write(struct adv7180_state *state, unsigned int reg, 271 unsigned int value) 272 { 273 return i2c_smbus_write_byte_data(state->vpp_client, reg, value); 274 } 275 276 static int adv7180_set_power(struct adv7180_state *state, bool on) 277 { 278 u8 val; 279 int ret; 280 281 if (on) 282 val = ADV7180_PWR_MAN_ON; 283 else 284 val = ADV7180_PWR_MAN_OFF; 285 286 ret = adv7180_write(state, ADV7180_REG_PWR_MAN, val); 287 if (ret) 288 return ret; 289 290 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 291 if (on) { 292 adv7180_csi_write(state, 0xDE, 0x02); 293 adv7180_csi_write(state, 0xD2, 0xF7); 294 adv7180_csi_write(state, 0xD8, 0x65); 295 adv7180_csi_write(state, 0xE0, 0x09); 296 adv7180_csi_write(state, 0x2C, 0x00); 297 if (state->field == V4L2_FIELD_NONE) 298 adv7180_csi_write(state, 0x1D, 0x80); 299 adv7180_csi_write(state, 0x00, 0x00); 300 } else { 301 adv7180_csi_write(state, 0x00, 0x80); 302 } 303 } 304 305 return 0; 306 } 307 308 static v4l2_std_id adv7180_std_to_v4l2(u8 status1) 309 { 310 /* in case V4L2_IN_ST_NO_SIGNAL */ 311 if (!(status1 & ADV7180_STATUS1_IN_LOCK)) 312 return V4L2_STD_UNKNOWN; 313 314 switch (status1 & ADV7180_STATUS1_AUTOD_MASK) { 315 case ADV7180_STATUS1_AUTOD_NTSM_M_J: 316 return V4L2_STD_NTSC; 317 case ADV7180_STATUS1_AUTOD_NTSC_4_43: 318 return V4L2_STD_NTSC_443; 319 case ADV7180_STATUS1_AUTOD_PAL_M: 320 return V4L2_STD_PAL_M; 321 case ADV7180_STATUS1_AUTOD_PAL_60: 322 return V4L2_STD_PAL_60; 323 case ADV7180_STATUS1_AUTOD_PAL_B_G: 324 return V4L2_STD_PAL; 325 case ADV7180_STATUS1_AUTOD_SECAM: 326 return V4L2_STD_SECAM; 327 case ADV7180_STATUS1_AUTOD_PAL_COMB: 328 return V4L2_STD_PAL_Nc | V4L2_STD_PAL_N; 329 case ADV7180_STATUS1_AUTOD_SECAM_525: 330 return V4L2_STD_SECAM; 331 default: 332 return V4L2_STD_UNKNOWN; 333 } 334 } 335 336 static int v4l2_std_to_adv7180(v4l2_std_id std) 337 { 338 if (std == V4L2_STD_PAL_60) 339 return ADV7180_STD_PAL60; 340 if (std == V4L2_STD_NTSC_443) 341 return ADV7180_STD_NTSC_443; 342 if (std == V4L2_STD_PAL_N) 343 return ADV7180_STD_PAL_N; 344 if (std == V4L2_STD_PAL_M) 345 return ADV7180_STD_PAL_M; 346 if (std == V4L2_STD_PAL_Nc) 347 return ADV7180_STD_PAL_COMB_N; 348 349 if (std & V4L2_STD_PAL) 350 return ADV7180_STD_PAL_BG; 351 if (std & V4L2_STD_NTSC) 352 return ADV7180_STD_NTSC_M; 353 if (std & V4L2_STD_SECAM) 354 return ADV7180_STD_PAL_SECAM; 355 356 return -EINVAL; 357 } 358 359 static u32 adv7180_status_to_v4l2(u8 status1) 360 { 361 if (!(status1 & ADV7180_STATUS1_IN_LOCK)) 362 return V4L2_IN_ST_NO_SIGNAL; 363 364 return 0; 365 } 366 367 static int __adv7180_status(struct adv7180_state *state, u32 *status, 368 v4l2_std_id *std) 369 { 370 int status1 = adv7180_read(state, ADV7180_REG_STATUS1); 371 372 if (status1 < 0) 373 return status1; 374 375 if (status) 376 *status = adv7180_status_to_v4l2(status1); 377 if (std) 378 *std = adv7180_std_to_v4l2(status1); 379 380 return 0; 381 } 382 383 static inline struct adv7180_state *to_state(struct v4l2_subdev *sd) 384 { 385 return container_of(sd, struct adv7180_state, sd); 386 } 387 388 static int adv7180_querystd(struct v4l2_subdev *sd, v4l2_std_id *std) 389 { 390 struct adv7180_state *state = to_state(sd); 391 int ret; 392 393 guard(mutex)(&state->mutex); 394 395 /* 396 * We can't sample the standard if the device is streaming as that would 397 * interfere with the capture session as the VID_SEL reg is touched. 398 */ 399 if (state->streaming) 400 return -EBUSY; 401 402 /* Set the standard to autodetect PAL B/G/H/I/D, NTSC J or SECAM */ 403 ret = adv7180_set_video_standard(state, 404 ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM); 405 if (ret) 406 return ret; 407 408 /* Allow some time for the autodetection to run. */ 409 msleep(100); 410 411 return __adv7180_status(state, NULL, std); 412 } 413 414 static int adv7180_s_routing(struct v4l2_subdev *sd, u32 input, 415 u32 output, u32 config) 416 { 417 struct adv7180_state *state = to_state(sd); 418 int ret = mutex_lock_interruptible(&state->mutex); 419 420 if (ret) 421 return ret; 422 423 if (input > 31 || !(BIT(input) & state->chip_info->valid_input_mask)) { 424 ret = -EINVAL; 425 goto out; 426 } 427 428 ret = state->chip_info->select_input(state, input); 429 430 if (ret == 0) 431 state->input = input; 432 out: 433 mutex_unlock(&state->mutex); 434 return ret; 435 } 436 437 static int adv7180_g_input_status(struct v4l2_subdev *sd, u32 *status) 438 { 439 struct adv7180_state *state = to_state(sd); 440 int ret = mutex_lock_interruptible(&state->mutex); 441 if (ret) 442 return ret; 443 444 ret = __adv7180_status(state, status, NULL); 445 mutex_unlock(&state->mutex); 446 return ret; 447 } 448 449 static int adv7180_program_std(struct adv7180_state *state) 450 { 451 int ret; 452 453 ret = v4l2_std_to_adv7180(state->curr_norm); 454 if (ret < 0) 455 return ret; 456 457 ret = adv7180_set_video_standard(state, ret); 458 if (ret < 0) 459 return ret; 460 return 0; 461 } 462 463 static int adv7180_s_std(struct v4l2_subdev *sd, v4l2_std_id std) 464 { 465 struct adv7180_state *state = to_state(sd); 466 int ret; 467 468 guard(mutex)(&state->mutex); 469 470 /* Make sure we can support this std */ 471 ret = v4l2_std_to_adv7180(std); 472 if (ret < 0) 473 return ret; 474 475 state->curr_norm = std; 476 477 return 0; 478 } 479 480 static int adv7180_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm) 481 { 482 struct adv7180_state *state = to_state(sd); 483 484 *norm = state->curr_norm; 485 486 return 0; 487 } 488 489 static int adv7180_get_frame_interval(struct v4l2_subdev *sd, 490 struct v4l2_subdev_state *sd_state, 491 struct v4l2_subdev_frame_interval *fi) 492 { 493 struct adv7180_state *state = to_state(sd); 494 495 /* 496 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2 497 * subdev active state API. 498 */ 499 if (fi->which != V4L2_SUBDEV_FORMAT_ACTIVE) 500 return -EINVAL; 501 502 if (state->curr_norm & V4L2_STD_525_60) { 503 fi->interval.numerator = 1001; 504 fi->interval.denominator = 30000; 505 } else { 506 fi->interval.numerator = 1; 507 fi->interval.denominator = 25; 508 } 509 510 return 0; 511 } 512 513 static void adv7180_set_power_pin(struct adv7180_state *state, bool on) 514 { 515 if (!state->pwdn_gpio) 516 return; 517 518 if (on) { 519 gpiod_set_value_cansleep(state->pwdn_gpio, 0); 520 usleep_range(5000, 10000); 521 } else { 522 gpiod_set_value_cansleep(state->pwdn_gpio, 1); 523 } 524 } 525 526 static void adv7180_set_reset_pin(struct adv7180_state *state, bool on) 527 { 528 if (!state->rst_gpio) 529 return; 530 531 if (on) { 532 gpiod_set_value_cansleep(state->rst_gpio, 1); 533 } else { 534 gpiod_set_value_cansleep(state->rst_gpio, 0); 535 usleep_range(5000, 10000); 536 } 537 } 538 539 static const char * const test_pattern_menu[] = { 540 "Single color", 541 "Color bars", 542 "Luma ramp", 543 "Boundary box", 544 "Disable", 545 }; 546 547 static int adv7180_test_pattern(struct adv7180_state *state, int value) 548 { 549 unsigned int reg = 0; 550 551 /* Map menu value into register value */ 552 if (value < 3) 553 reg = value; 554 if (value == 3) 555 reg = 5; 556 557 adv7180_write(state, ADV7180_REG_ANALOG_CLAMP_CTL, reg); 558 559 if (value == ARRAY_SIZE(test_pattern_menu) - 1) { 560 reg = adv7180_read(state, ADV7180_REG_DEF_VALUE_Y); 561 reg &= ~ADV7180_DEF_VAL_EN; 562 adv7180_write(state, ADV7180_REG_DEF_VALUE_Y, reg); 563 return 0; 564 } 565 566 reg = adv7180_read(state, ADV7180_REG_DEF_VALUE_Y); 567 reg |= ADV7180_DEF_VAL_EN | ADV7180_DEF_VAL_AUTO_EN; 568 adv7180_write(state, ADV7180_REG_DEF_VALUE_Y, reg); 569 570 return 0; 571 } 572 573 static int adv7180_s_ctrl(struct v4l2_ctrl *ctrl) 574 { 575 struct v4l2_subdev *sd = to_adv7180_sd(ctrl); 576 struct adv7180_state *state = to_state(sd); 577 int ret = 0; 578 int val; 579 580 lockdep_assert_held(&state->mutex); 581 582 val = ctrl->val; 583 switch (ctrl->id) { 584 case V4L2_CID_BRIGHTNESS: 585 ret = adv7180_write(state, ADV7180_REG_BRI, val); 586 break; 587 case V4L2_CID_HUE: 588 /*Hue is inverted according to HSL chart */ 589 ret = adv7180_write(state, ADV7180_REG_HUE, -val); 590 break; 591 case V4L2_CID_CONTRAST: 592 ret = adv7180_write(state, ADV7180_REG_CON, val); 593 break; 594 case V4L2_CID_SATURATION: 595 /* 596 *This could be V4L2_CID_BLUE_BALANCE/V4L2_CID_RED_BALANCE 597 *Let's not confuse the user, everybody understands saturation 598 */ 599 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CB, val); 600 if (ret < 0) 601 break; 602 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CR, val); 603 break; 604 case V4L2_CID_ADV_FAST_SWITCH: 605 if (ctrl->val) { 606 /* ADI required write */ 607 adv7180_write(state, 0x80d9, 0x44); 608 adv7180_write(state, ADV7180_REG_FLCONTROL, 609 ADV7180_FLCONTROL_FL_ENABLE); 610 } else { 611 /* ADI required write */ 612 adv7180_write(state, 0x80d9, 0xc4); 613 adv7180_write(state, ADV7180_REG_FLCONTROL, 0x00); 614 } 615 break; 616 case V4L2_CID_TEST_PATTERN: 617 ret = adv7180_test_pattern(state, val); 618 break; 619 default: 620 ret = -EINVAL; 621 } 622 623 return ret; 624 } 625 626 static const struct v4l2_ctrl_ops adv7180_ctrl_ops = { 627 .s_ctrl = adv7180_s_ctrl, 628 }; 629 630 static const struct v4l2_ctrl_config adv7180_ctrl_fast_switch = { 631 .ops = &adv7180_ctrl_ops, 632 .id = V4L2_CID_ADV_FAST_SWITCH, 633 .name = "Fast Switching", 634 .type = V4L2_CTRL_TYPE_BOOLEAN, 635 .min = 0, 636 .max = 1, 637 .step = 1, 638 }; 639 640 static int adv7180_init_controls(struct adv7180_state *state) 641 { 642 v4l2_ctrl_handler_init(&state->ctrl_hdl, 4); 643 state->ctrl_hdl.lock = &state->mutex; 644 645 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, 646 V4L2_CID_BRIGHTNESS, ADV7180_BRI_MIN, 647 ADV7180_BRI_MAX, 1, ADV7180_BRI_DEF); 648 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, 649 V4L2_CID_CONTRAST, ADV7180_CON_MIN, 650 ADV7180_CON_MAX, 1, ADV7180_CON_DEF); 651 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, 652 V4L2_CID_SATURATION, ADV7180_SAT_MIN, 653 ADV7180_SAT_MAX, 1, ADV7180_SAT_DEF); 654 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, 655 V4L2_CID_HUE, ADV7180_HUE_MIN, 656 ADV7180_HUE_MAX, 1, ADV7180_HUE_DEF); 657 v4l2_ctrl_new_custom(&state->ctrl_hdl, &adv7180_ctrl_fast_switch, NULL); 658 659 if (state->chip_info->flags & ADV7180_FLAG_TEST_PATTERN) { 660 v4l2_ctrl_new_std_menu_items(&state->ctrl_hdl, 661 &adv7180_ctrl_ops, 662 V4L2_CID_TEST_PATTERN, 663 ARRAY_SIZE(test_pattern_menu) - 1, 664 0, 665 ARRAY_SIZE(test_pattern_menu) - 1, 666 test_pattern_menu); 667 } 668 669 state->sd.ctrl_handler = &state->ctrl_hdl; 670 if (state->ctrl_hdl.error) { 671 int err = state->ctrl_hdl.error; 672 673 v4l2_ctrl_handler_free(&state->ctrl_hdl); 674 return err; 675 } 676 677 return 0; 678 } 679 static void adv7180_exit_controls(struct adv7180_state *state) 680 { 681 v4l2_ctrl_handler_free(&state->ctrl_hdl); 682 } 683 684 static int adv7180_enum_mbus_code(struct v4l2_subdev *sd, 685 struct v4l2_subdev_state *sd_state, 686 struct v4l2_subdev_mbus_code_enum *code) 687 { 688 if (code->index != 0) 689 return -EINVAL; 690 691 code->code = MEDIA_BUS_FMT_UYVY8_2X8; 692 693 return 0; 694 } 695 696 static int adv7180_mbus_fmt(struct v4l2_subdev *sd, 697 struct v4l2_mbus_framefmt *fmt) 698 { 699 struct adv7180_state *state = to_state(sd); 700 701 fmt->code = MEDIA_BUS_FMT_UYVY8_2X8; 702 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M; 703 fmt->width = 720; 704 fmt->height = state->curr_norm & V4L2_STD_525_60 ? 480 : 576; 705 706 if (state->field == V4L2_FIELD_ALTERNATE) 707 fmt->height /= 2; 708 709 return 0; 710 } 711 712 static int adv7180_set_field_mode(struct adv7180_state *state) 713 { 714 if (!(state->chip_info->flags & ADV7180_FLAG_I2P)) 715 return 0; 716 717 if (state->field == V4L2_FIELD_NONE) { 718 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 719 adv7180_csi_write(state, 0x01, 0x20); 720 adv7180_csi_write(state, 0x02, 0x28); 721 adv7180_csi_write(state, 0x03, 0x38); 722 adv7180_csi_write(state, 0x04, 0x30); 723 adv7180_csi_write(state, 0x05, 0x30); 724 adv7180_csi_write(state, 0x06, 0x80); 725 adv7180_csi_write(state, 0x07, 0x70); 726 adv7180_csi_write(state, 0x08, 0x50); 727 } 728 adv7180_vpp_write(state, 0xa3, 0x00); 729 adv7180_vpp_write(state, 0x5b, 0x00); 730 adv7180_vpp_write(state, 0x55, 0x80); 731 } else { 732 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 733 adv7180_csi_write(state, 0x01, 0x18); 734 adv7180_csi_write(state, 0x02, 0x18); 735 adv7180_csi_write(state, 0x03, 0x30); 736 adv7180_csi_write(state, 0x04, 0x20); 737 adv7180_csi_write(state, 0x05, 0x28); 738 adv7180_csi_write(state, 0x06, 0x40); 739 adv7180_csi_write(state, 0x07, 0x58); 740 adv7180_csi_write(state, 0x08, 0x30); 741 } 742 adv7180_vpp_write(state, 0xa3, 0x70); 743 adv7180_vpp_write(state, 0x5b, 0x80); 744 adv7180_vpp_write(state, 0x55, 0x00); 745 } 746 747 return 0; 748 } 749 750 static int adv7180_get_pad_format(struct v4l2_subdev *sd, 751 struct v4l2_subdev_state *sd_state, 752 struct v4l2_subdev_format *format) 753 { 754 struct adv7180_state *state = to_state(sd); 755 756 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 757 format->format = *v4l2_subdev_state_get_format(sd_state, 0); 758 } else { 759 adv7180_mbus_fmt(sd, &format->format); 760 format->format.field = state->field; 761 } 762 763 return 0; 764 } 765 766 static int adv7180_set_pad_format(struct v4l2_subdev *sd, 767 struct v4l2_subdev_state *sd_state, 768 struct v4l2_subdev_format *format) 769 { 770 struct adv7180_state *state = to_state(sd); 771 struct v4l2_mbus_framefmt *framefmt; 772 int ret; 773 774 switch (format->format.field) { 775 case V4L2_FIELD_NONE: 776 if (state->chip_info->flags & ADV7180_FLAG_I2P) 777 break; 778 fallthrough; 779 default: 780 format->format.field = V4L2_FIELD_ALTERNATE; 781 break; 782 } 783 784 ret = adv7180_mbus_fmt(sd, &format->format); 785 786 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 787 state->field = format->format.field; 788 } else { 789 framefmt = v4l2_subdev_state_get_format(sd_state, 0); 790 *framefmt = format->format; 791 } 792 793 return ret; 794 } 795 796 static int adv7180_init_state(struct v4l2_subdev *sd, 797 struct v4l2_subdev_state *sd_state) 798 { 799 struct v4l2_subdev_format fmt = { 800 .which = sd_state ? V4L2_SUBDEV_FORMAT_TRY 801 : V4L2_SUBDEV_FORMAT_ACTIVE, 802 }; 803 804 return adv7180_set_pad_format(sd, sd_state, &fmt); 805 } 806 807 static int adv7180_get_mbus_config(struct v4l2_subdev *sd, 808 unsigned int pad, 809 struct v4l2_mbus_config *cfg) 810 { 811 struct adv7180_state *state = to_state(sd); 812 813 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 814 cfg->type = V4L2_MBUS_CSI2_DPHY; 815 cfg->bus.mipi_csi2.num_data_lanes = 1; 816 cfg->bus.mipi_csi2.flags = 0; 817 } else { 818 /* 819 * The ADV7180 sensor supports BT.601/656 output modes. 820 * The BT.656 is default and not yet configurable by s/w. 821 */ 822 cfg->bus.parallel.flags = V4L2_MBUS_MASTER | 823 V4L2_MBUS_PCLK_SAMPLE_RISING | 824 V4L2_MBUS_DATA_ACTIVE_HIGH; 825 cfg->type = V4L2_MBUS_BT656; 826 } 827 828 return 0; 829 } 830 831 static int adv7180_get_skip_frames(struct v4l2_subdev *sd, u32 *frames) 832 { 833 *frames = ADV7180_NUM_OF_SKIP_FRAMES; 834 835 return 0; 836 } 837 838 static int adv7180_g_tvnorms(struct v4l2_subdev *sd, v4l2_std_id *norm) 839 { 840 *norm = V4L2_STD_ALL; 841 return 0; 842 } 843 844 static int init_device(struct adv7180_state *state) 845 { 846 int ret; 847 848 lockdep_assert_held(&state->mutex); 849 850 ret = adv7180_program_std(state); 851 if (ret) 852 return ret; 853 854 adv7180_set_field_mode(state); 855 856 __v4l2_ctrl_handler_setup(&state->ctrl_hdl); 857 858 return ret; 859 } 860 861 static int adv7180_reset_device(struct adv7180_state *state) 862 { 863 int ret; 864 865 lockdep_assert_held(&state->mutex); 866 867 adv7180_set_power_pin(state, true); 868 adv7180_set_reset_pin(state, false); 869 870 adv7180_write(state, ADV7180_REG_PWR_MAN, ADV7180_PWR_MAN_RES); 871 usleep_range(5000, 10000); 872 873 /* 874 * If the devices decoder is power on after reset, power off so the 875 * device can be configured. 876 */ 877 if (state->chip_info->flags & ADV7180_FLAG_RESET_POWERED) 878 adv7180_set_power(state, false); 879 880 ret = state->chip_info->init(state); 881 if (ret) 882 return ret; 883 884 ret = init_device(state); 885 if (ret) 886 return ret; 887 888 /* register for interrupts */ 889 if (state->irq > 0) { 890 /* config the Interrupt pin to be active low */ 891 ret = adv7180_write(state, ADV7180_REG_ICONF1, 892 ADV7180_ICONF1_ACTIVE_LOW | 893 ADV7180_ICONF1_PSYNC_ONLY); 894 if (ret < 0) 895 return ret; 896 897 ret = adv7180_write(state, ADV7180_REG_IMR1, 0); 898 if (ret < 0) 899 return ret; 900 901 ret = adv7180_write(state, ADV7180_REG_IMR2, 0); 902 if (ret < 0) 903 return ret; 904 905 /* enable AD change interrupts */ 906 ret = adv7180_write(state, ADV7180_REG_IMR3, 907 ADV7180_IRQ3_AD_CHANGE); 908 if (ret < 0) 909 return ret; 910 911 ret = adv7180_write(state, ADV7180_REG_IMR4, 0); 912 if (ret < 0) 913 return ret; 914 } 915 916 /* 917 * If the devices decoder is power on after reset, restore the power 918 * after configuration. This is to preserve the behavior of the driver, 919 * not doing this result in the first 35+ frames captured being garbage. 920 */ 921 if (state->chip_info->flags & ADV7180_FLAG_RESET_POWERED) 922 adv7180_set_power(state, true); 923 924 return 0; 925 } 926 927 static int adv7180_s_stream(struct v4l2_subdev *sd, int enable) 928 { 929 struct adv7180_state *state = to_state(sd); 930 int ret; 931 932 /* Must wait until querystd released the lock */ 933 guard(mutex)(&state->mutex); 934 935 /* 936 * Always power off the decoder even if streaming is to be enabled, the 937 * decoder needs to be off for the device to be configured. 938 */ 939 ret = adv7180_set_power(state, false); 940 if (ret) 941 return ret; 942 943 if (enable) { 944 ret = init_device(state); 945 if (ret) 946 return ret; 947 948 ret = adv7180_set_power(state, true); 949 if (ret) 950 return ret; 951 } 952 953 state->streaming = enable; 954 955 return 0; 956 } 957 958 static int adv7180_subscribe_event(struct v4l2_subdev *sd, 959 struct v4l2_fh *fh, 960 struct v4l2_event_subscription *sub) 961 { 962 switch (sub->type) { 963 case V4L2_EVENT_SOURCE_CHANGE: 964 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub); 965 case V4L2_EVENT_CTRL: 966 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub); 967 default: 968 return -EINVAL; 969 } 970 } 971 972 static const struct v4l2_subdev_video_ops adv7180_video_ops = { 973 .s_std = adv7180_s_std, 974 .g_std = adv7180_g_std, 975 .querystd = adv7180_querystd, 976 .g_input_status = adv7180_g_input_status, 977 .s_routing = adv7180_s_routing, 978 .g_tvnorms = adv7180_g_tvnorms, 979 .s_stream = adv7180_s_stream, 980 }; 981 982 static const struct v4l2_subdev_core_ops adv7180_core_ops = { 983 .subscribe_event = adv7180_subscribe_event, 984 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 985 }; 986 987 static const struct v4l2_subdev_pad_ops adv7180_pad_ops = { 988 .enum_mbus_code = adv7180_enum_mbus_code, 989 .set_fmt = adv7180_set_pad_format, 990 .get_fmt = adv7180_get_pad_format, 991 .get_frame_interval = adv7180_get_frame_interval, 992 .get_mbus_config = adv7180_get_mbus_config, 993 }; 994 995 static const struct v4l2_subdev_sensor_ops adv7180_sensor_ops = { 996 .g_skip_frames = adv7180_get_skip_frames, 997 }; 998 999 static const struct v4l2_subdev_ops adv7180_ops = { 1000 .core = &adv7180_core_ops, 1001 .video = &adv7180_video_ops, 1002 .pad = &adv7180_pad_ops, 1003 .sensor = &adv7180_sensor_ops, 1004 }; 1005 1006 static const struct v4l2_subdev_internal_ops adv7180_internal_ops = { 1007 .init_state = adv7180_init_state, 1008 }; 1009 1010 static irqreturn_t adv7180_irq(int irq, void *devid) 1011 { 1012 struct adv7180_state *state = devid; 1013 u8 isr3; 1014 1015 mutex_lock(&state->mutex); 1016 isr3 = adv7180_read(state, ADV7180_REG_ISR3); 1017 /* clear */ 1018 adv7180_write(state, ADV7180_REG_ICR3, isr3); 1019 1020 if (isr3 & ADV7180_IRQ3_AD_CHANGE) { 1021 static const struct v4l2_event src_ch = { 1022 .type = V4L2_EVENT_SOURCE_CHANGE, 1023 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, 1024 }; 1025 1026 v4l2_subdev_notify_event(&state->sd, &src_ch); 1027 } 1028 mutex_unlock(&state->mutex); 1029 1030 return IRQ_HANDLED; 1031 } 1032 1033 static int adv7180_init(struct adv7180_state *state) 1034 { 1035 int ret; 1036 1037 /* ITU-R BT.656-4 compatible */ 1038 ret = adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 1039 ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS); 1040 if (ret < 0) 1041 return ret; 1042 1043 /* Manually set V bit end position in NTSC mode */ 1044 return adv7180_write(state, ADV7180_REG_NTSC_V_BIT_END, 1045 ADV7180_NTSC_V_BIT_END_MANUAL_NVEND); 1046 } 1047 1048 static int adv7180_set_std(struct adv7180_state *state, unsigned int std) 1049 { 1050 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, 1051 (std << 4) | state->input); 1052 } 1053 1054 static int adv7180_select_input(struct adv7180_state *state, unsigned int input) 1055 { 1056 int ret; 1057 1058 ret = adv7180_read(state, ADV7180_REG_INPUT_CONTROL); 1059 if (ret < 0) 1060 return ret; 1061 1062 ret &= ~ADV7180_INPUT_CONTROL_INSEL_MASK; 1063 ret |= input; 1064 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, ret); 1065 } 1066 1067 static int adv7182_init(struct adv7180_state *state) 1068 { 1069 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) 1070 adv7180_write(state, ADV7180_REG_CSI_SLAVE_ADDR, 1071 ADV7180_DEFAULT_CSI_I2C_ADDR << 1); 1072 1073 if (state->chip_info->flags & ADV7180_FLAG_I2P) 1074 adv7180_write(state, ADV7180_REG_VPP_SLAVE_ADDR, 1075 ADV7180_DEFAULT_VPP_I2C_ADDR << 1); 1076 1077 if (state->chip_info->flags & ADV7180_FLAG_V2) { 1078 /* ADI recommended writes for improved video quality */ 1079 adv7180_write(state, 0x0080, 0x51); 1080 adv7180_write(state, 0x0081, 0x51); 1081 adv7180_write(state, 0x0082, 0x68); 1082 } 1083 1084 /* ADI required writes */ 1085 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 1086 adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x4e); 1087 adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 0x57); 1088 adv7180_write(state, ADV7180_REG_CTRL_2, 0xc0); 1089 } else { 1090 if (state->chip_info->flags & ADV7180_FLAG_V2) { 1091 if (state->force_bt656_4) { 1092 /* ITU-R BT.656-4 compatible */ 1093 adv7180_write(state, 1094 ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 1095 ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS); 1096 /* Manually set NEWAVMODE */ 1097 adv7180_write(state, 1098 ADV7180_REG_VSYNC_FIELD_CTL_1, 1099 ADV7180_VSYNC_FIELD_CTL_1_NEWAV); 1100 /* Manually set V bit end position in NTSC mode */ 1101 adv7180_write(state, 1102 ADV7180_REG_NTSC_V_BIT_END, 1103 ADV7180_NTSC_V_BIT_END_MANUAL_NVEND); 1104 } else { 1105 adv7180_write(state, 1106 ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 1107 0x17); 1108 } 1109 } else { 1110 adv7180_write(state, 1111 ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 1112 0x07); 1113 } 1114 adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x0c); 1115 adv7180_write(state, ADV7180_REG_CTRL_2, 0x40); 1116 } 1117 1118 adv7180_write(state, 0x0013, 0x00); 1119 1120 return 0; 1121 } 1122 1123 static int adv7182_set_std(struct adv7180_state *state, unsigned int std) 1124 { 1125 /* Failing to set the reserved bit can result in increased video noise */ 1126 return adv7180_write(state, ADV7182_REG_INPUT_VIDSEL, 1127 (std << 4) | ADV7182_REG_INPUT_RESERVED); 1128 } 1129 1130 enum adv7182_input_type { 1131 ADV7182_INPUT_TYPE_CVBS, 1132 ADV7182_INPUT_TYPE_DIFF_CVBS, 1133 ADV7182_INPUT_TYPE_SVIDEO, 1134 ADV7182_INPUT_TYPE_YPBPR, 1135 }; 1136 1137 static enum adv7182_input_type adv7182_get_input_type(unsigned int input) 1138 { 1139 switch (input) { 1140 case ADV7182_INPUT_CVBS_AIN1: 1141 case ADV7182_INPUT_CVBS_AIN2: 1142 case ADV7182_INPUT_CVBS_AIN3: 1143 case ADV7182_INPUT_CVBS_AIN4: 1144 case ADV7182_INPUT_CVBS_AIN5: 1145 case ADV7182_INPUT_CVBS_AIN6: 1146 case ADV7182_INPUT_CVBS_AIN7: 1147 case ADV7182_INPUT_CVBS_AIN8: 1148 return ADV7182_INPUT_TYPE_CVBS; 1149 case ADV7182_INPUT_SVIDEO_AIN1_AIN2: 1150 case ADV7182_INPUT_SVIDEO_AIN3_AIN4: 1151 case ADV7182_INPUT_SVIDEO_AIN5_AIN6: 1152 case ADV7182_INPUT_SVIDEO_AIN7_AIN8: 1153 return ADV7182_INPUT_TYPE_SVIDEO; 1154 case ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3: 1155 case ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6: 1156 return ADV7182_INPUT_TYPE_YPBPR; 1157 case ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2: 1158 case ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4: 1159 case ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6: 1160 case ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8: 1161 return ADV7182_INPUT_TYPE_DIFF_CVBS; 1162 default: /* Will never happen */ 1163 return 0; 1164 } 1165 } 1166 1167 /* ADI recommended writes to registers 0x52, 0x53, 0x54 */ 1168 static unsigned int adv7182_lbias_settings[][3] = { 1169 [ADV7182_INPUT_TYPE_CVBS] = { 0xCB, 0x4E, 0x80 }, 1170 [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 }, 1171 [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 }, 1172 [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 }, 1173 }; 1174 1175 static unsigned int adv7280_lbias_settings[][3] = { 1176 [ADV7182_INPUT_TYPE_CVBS] = { 0xCD, 0x4E, 0x80 }, 1177 [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 }, 1178 [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 }, 1179 [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 }, 1180 }; 1181 1182 static int adv7182_select_input(struct adv7180_state *state, unsigned int input) 1183 { 1184 enum adv7182_input_type input_type; 1185 unsigned int *lbias; 1186 unsigned int i; 1187 int ret; 1188 1189 ret = adv7180_write(state, ADV7180_REG_INPUT_CONTROL, input); 1190 if (ret) 1191 return ret; 1192 1193 /* Reset clamp circuitry - ADI recommended writes */ 1194 adv7180_write(state, ADV7180_REG_RST_CLAMP, 0x00); 1195 adv7180_write(state, ADV7180_REG_RST_CLAMP, 0xff); 1196 1197 input_type = adv7182_get_input_type(input); 1198 1199 switch (input_type) { 1200 case ADV7182_INPUT_TYPE_CVBS: 1201 case ADV7182_INPUT_TYPE_DIFF_CVBS: 1202 /* ADI recommends to use the SH1 filter */ 1203 adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x41); 1204 break; 1205 default: 1206 adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x01); 1207 break; 1208 } 1209 1210 if (state->chip_info->flags & ADV7180_FLAG_V2) 1211 lbias = adv7280_lbias_settings[input_type]; 1212 else 1213 lbias = adv7182_lbias_settings[input_type]; 1214 1215 for (i = 0; i < ARRAY_SIZE(adv7182_lbias_settings[0]); i++) 1216 adv7180_write(state, ADV7180_REG_CVBS_TRIM + i, lbias[i]); 1217 1218 if (input_type == ADV7182_INPUT_TYPE_DIFF_CVBS) { 1219 /* ADI required writes to make differential CVBS work */ 1220 adv7180_write(state, ADV7180_REG_RES_CIR, 0xa8); 1221 adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0x90); 1222 adv7180_write(state, ADV7180_REG_DIFF_MODE, 0xb0); 1223 adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x08); 1224 adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0xa0); 1225 } else { 1226 adv7180_write(state, ADV7180_REG_RES_CIR, 0xf0); 1227 adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0xd0); 1228 adv7180_write(state, ADV7180_REG_DIFF_MODE, 0x10); 1229 adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x9c); 1230 adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0x00); 1231 } 1232 1233 return 0; 1234 } 1235 1236 static const struct adv7180_chip_info adv7180_info = { 1237 .flags = ADV7180_FLAG_RESET_POWERED, 1238 /* We cannot discriminate between LQFP and 40-pin LFCSP, so accept 1239 * all inputs and let the card driver take care of validation 1240 */ 1241 .valid_input_mask = BIT(ADV7180_INPUT_CVBS_AIN1) | 1242 BIT(ADV7180_INPUT_CVBS_AIN2) | 1243 BIT(ADV7180_INPUT_CVBS_AIN3) | 1244 BIT(ADV7180_INPUT_CVBS_AIN4) | 1245 BIT(ADV7180_INPUT_CVBS_AIN5) | 1246 BIT(ADV7180_INPUT_CVBS_AIN6) | 1247 BIT(ADV7180_INPUT_SVIDEO_AIN1_AIN2) | 1248 BIT(ADV7180_INPUT_SVIDEO_AIN3_AIN4) | 1249 BIT(ADV7180_INPUT_SVIDEO_AIN5_AIN6) | 1250 BIT(ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1251 BIT(ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6), 1252 .init = adv7180_init, 1253 .set_std = adv7180_set_std, 1254 .select_input = adv7180_select_input, 1255 }; 1256 1257 static const struct adv7180_chip_info adv7182_info = { 1258 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1259 BIT(ADV7182_INPUT_CVBS_AIN2) | 1260 BIT(ADV7182_INPUT_CVBS_AIN3) | 1261 BIT(ADV7182_INPUT_CVBS_AIN4) | 1262 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1263 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1264 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1265 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1266 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4), 1267 .init = adv7182_init, 1268 .set_std = adv7182_set_std, 1269 .select_input = adv7182_select_input, 1270 }; 1271 1272 static const struct adv7180_chip_info adv7280_info = { 1273 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P | ADV7180_FLAG_TEST_PATTERN, 1274 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1275 BIT(ADV7182_INPUT_CVBS_AIN2) | 1276 BIT(ADV7182_INPUT_CVBS_AIN3) | 1277 BIT(ADV7182_INPUT_CVBS_AIN4) | 1278 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1279 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1280 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3), 1281 .init = adv7182_init, 1282 .set_std = adv7182_set_std, 1283 .select_input = adv7182_select_input, 1284 }; 1285 1286 static const struct adv7180_chip_info adv7280_m_info = { 1287 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P | 1288 ADV7180_FLAG_TEST_PATTERN, 1289 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1290 BIT(ADV7182_INPUT_CVBS_AIN2) | 1291 BIT(ADV7182_INPUT_CVBS_AIN3) | 1292 BIT(ADV7182_INPUT_CVBS_AIN4) | 1293 BIT(ADV7182_INPUT_CVBS_AIN5) | 1294 BIT(ADV7182_INPUT_CVBS_AIN6) | 1295 BIT(ADV7182_INPUT_CVBS_AIN7) | 1296 BIT(ADV7182_INPUT_CVBS_AIN8) | 1297 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1298 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1299 BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) | 1300 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1301 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1302 BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6), 1303 .init = adv7182_init, 1304 .set_std = adv7182_set_std, 1305 .select_input = adv7182_select_input, 1306 }; 1307 1308 static const struct adv7180_chip_info adv7281_info = { 1309 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | 1310 ADV7180_FLAG_TEST_PATTERN, 1311 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1312 BIT(ADV7182_INPUT_CVBS_AIN2) | 1313 BIT(ADV7182_INPUT_CVBS_AIN7) | 1314 BIT(ADV7182_INPUT_CVBS_AIN8) | 1315 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1316 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1317 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1318 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1319 .init = adv7182_init, 1320 .set_std = adv7182_set_std, 1321 .select_input = adv7182_select_input, 1322 }; 1323 1324 static const struct adv7180_chip_info adv7281_m_info = { 1325 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | 1326 ADV7180_FLAG_TEST_PATTERN, 1327 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1328 BIT(ADV7182_INPUT_CVBS_AIN2) | 1329 BIT(ADV7182_INPUT_CVBS_AIN3) | 1330 BIT(ADV7182_INPUT_CVBS_AIN4) | 1331 BIT(ADV7182_INPUT_CVBS_AIN7) | 1332 BIT(ADV7182_INPUT_CVBS_AIN8) | 1333 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1334 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1335 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1336 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1337 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1338 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) | 1339 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1340 .init = adv7182_init, 1341 .set_std = adv7182_set_std, 1342 .select_input = adv7182_select_input, 1343 }; 1344 1345 static const struct adv7180_chip_info adv7281_ma_info = { 1346 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | 1347 ADV7180_FLAG_TEST_PATTERN, 1348 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1349 BIT(ADV7182_INPUT_CVBS_AIN2) | 1350 BIT(ADV7182_INPUT_CVBS_AIN3) | 1351 BIT(ADV7182_INPUT_CVBS_AIN4) | 1352 BIT(ADV7182_INPUT_CVBS_AIN5) | 1353 BIT(ADV7182_INPUT_CVBS_AIN6) | 1354 BIT(ADV7182_INPUT_CVBS_AIN7) | 1355 BIT(ADV7182_INPUT_CVBS_AIN8) | 1356 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1357 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1358 BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) | 1359 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1360 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1361 BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6) | 1362 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1363 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) | 1364 BIT(ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6) | 1365 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1366 .init = adv7182_init, 1367 .set_std = adv7182_set_std, 1368 .select_input = adv7182_select_input, 1369 }; 1370 1371 static const struct adv7180_chip_info adv7282_info = { 1372 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P | ADV7180_FLAG_TEST_PATTERN, 1373 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1374 BIT(ADV7182_INPUT_CVBS_AIN2) | 1375 BIT(ADV7182_INPUT_CVBS_AIN7) | 1376 BIT(ADV7182_INPUT_CVBS_AIN8) | 1377 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1378 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1379 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1380 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1381 .init = adv7182_init, 1382 .set_std = adv7182_set_std, 1383 .select_input = adv7182_select_input, 1384 }; 1385 1386 static const struct adv7180_chip_info adv7282_m_info = { 1387 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P | 1388 ADV7180_FLAG_TEST_PATTERN, 1389 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1390 BIT(ADV7182_INPUT_CVBS_AIN2) | 1391 BIT(ADV7182_INPUT_CVBS_AIN3) | 1392 BIT(ADV7182_INPUT_CVBS_AIN4) | 1393 BIT(ADV7182_INPUT_CVBS_AIN7) | 1394 BIT(ADV7182_INPUT_CVBS_AIN8) | 1395 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1396 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1397 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1398 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1399 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) | 1400 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1401 .init = adv7182_init, 1402 .set_std = adv7182_set_std, 1403 .select_input = adv7182_select_input, 1404 }; 1405 1406 static int adv7180_probe(struct i2c_client *client) 1407 { 1408 struct device_node *np = client->dev.of_node; 1409 struct adv7180_state *state; 1410 struct v4l2_subdev *sd; 1411 int ret; 1412 1413 /* Check if the adapter supports the needed features */ 1414 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 1415 return -EIO; 1416 1417 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); 1418 if (state == NULL) 1419 return -ENOMEM; 1420 1421 state->client = client; 1422 state->field = V4L2_FIELD_ALTERNATE; 1423 state->chip_info = i2c_get_match_data(client); 1424 1425 state->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown", 1426 GPIOD_OUT_HIGH); 1427 if (IS_ERR(state->pwdn_gpio)) { 1428 ret = PTR_ERR(state->pwdn_gpio); 1429 v4l_err(client, "request for power pin failed: %d\n", ret); 1430 return ret; 1431 } 1432 1433 state->rst_gpio = devm_gpiod_get_optional(&client->dev, "reset", 1434 GPIOD_OUT_HIGH); 1435 if (IS_ERR(state->rst_gpio)) { 1436 ret = PTR_ERR(state->rst_gpio); 1437 v4l_err(client, "request for reset pin failed: %d\n", ret); 1438 return ret; 1439 } 1440 1441 if (of_property_read_bool(np, "adv,force-bt656-4") || 1442 of_property_read_bool(np, "adi,force-bt656-4")) 1443 state->force_bt656_4 = true; 1444 1445 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 1446 state->csi_client = i2c_new_dummy_device(client->adapter, 1447 ADV7180_DEFAULT_CSI_I2C_ADDR); 1448 if (IS_ERR(state->csi_client)) 1449 return PTR_ERR(state->csi_client); 1450 } 1451 1452 if (state->chip_info->flags & ADV7180_FLAG_I2P) { 1453 state->vpp_client = i2c_new_dummy_device(client->adapter, 1454 ADV7180_DEFAULT_VPP_I2C_ADDR); 1455 if (IS_ERR(state->vpp_client)) { 1456 ret = PTR_ERR(state->vpp_client); 1457 goto err_unregister_csi_client; 1458 } 1459 } 1460 1461 state->irq = client->irq; 1462 mutex_init(&state->mutex); 1463 state->curr_norm = V4L2_STD_NTSC; 1464 1465 state->input = 0; 1466 sd = &state->sd; 1467 v4l2_i2c_subdev_init(sd, client, &adv7180_ops); 1468 sd->internal_ops = &adv7180_internal_ops; 1469 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; 1470 1471 ret = adv7180_init_controls(state); 1472 if (ret) 1473 goto err_unregister_vpp_client; 1474 1475 state->pad.flags = MEDIA_PAD_FL_SOURCE; 1476 sd->entity.function = MEDIA_ENT_F_ATV_DECODER; 1477 ret = media_entity_pads_init(&sd->entity, 1, &state->pad); 1478 if (ret) 1479 goto err_free_ctrl; 1480 1481 mutex_lock(&state->mutex); 1482 ret = adv7180_reset_device(state); 1483 mutex_unlock(&state->mutex); 1484 if (ret) 1485 goto err_media_entity_cleanup; 1486 1487 if (state->irq > 0) { 1488 ret = request_threaded_irq(client->irq, NULL, adv7180_irq, 1489 IRQF_ONESHOT | IRQF_TRIGGER_FALLING, 1490 KBUILD_MODNAME, state); 1491 if (ret) 1492 goto err_media_entity_cleanup; 1493 } 1494 1495 ret = v4l2_async_register_subdev(sd); 1496 if (ret) 1497 goto err_free_irq; 1498 1499 mutex_lock(&state->mutex); 1500 ret = adv7180_read(state, ADV7180_REG_IDENT); 1501 mutex_unlock(&state->mutex); 1502 if (ret < 0) 1503 goto err_v4l2_async_unregister; 1504 1505 v4l_info(client, "chip id 0x%x found @ 0x%02x (%s)\n", 1506 ret, client->addr, client->adapter->name); 1507 1508 return 0; 1509 1510 err_v4l2_async_unregister: 1511 v4l2_async_unregister_subdev(sd); 1512 err_free_irq: 1513 if (state->irq > 0) 1514 free_irq(client->irq, state); 1515 err_media_entity_cleanup: 1516 media_entity_cleanup(&sd->entity); 1517 err_free_ctrl: 1518 adv7180_exit_controls(state); 1519 err_unregister_vpp_client: 1520 i2c_unregister_device(state->vpp_client); 1521 err_unregister_csi_client: 1522 i2c_unregister_device(state->csi_client); 1523 mutex_destroy(&state->mutex); 1524 return ret; 1525 } 1526 1527 static void adv7180_remove(struct i2c_client *client) 1528 { 1529 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1530 struct adv7180_state *state = to_state(sd); 1531 1532 v4l2_async_unregister_subdev(sd); 1533 1534 if (state->irq > 0) 1535 free_irq(client->irq, state); 1536 1537 media_entity_cleanup(&sd->entity); 1538 adv7180_exit_controls(state); 1539 1540 i2c_unregister_device(state->vpp_client); 1541 i2c_unregister_device(state->csi_client); 1542 1543 adv7180_set_reset_pin(state, true); 1544 adv7180_set_power_pin(state, false); 1545 1546 mutex_destroy(&state->mutex); 1547 } 1548 1549 #ifdef CONFIG_PM_SLEEP 1550 static int adv7180_suspend(struct device *dev) 1551 { 1552 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1553 struct adv7180_state *state = to_state(sd); 1554 1555 guard(mutex)(&state->mutex); 1556 1557 return adv7180_set_power(state, false); 1558 } 1559 1560 static int adv7180_resume(struct device *dev) 1561 { 1562 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1563 struct adv7180_state *state = to_state(sd); 1564 int ret; 1565 1566 guard(mutex)(&state->mutex); 1567 1568 ret = adv7180_reset_device(state); 1569 if (ret < 0) 1570 return ret; 1571 1572 /* If we were streaming when suspending, start decoder. */ 1573 if (state->streaming) { 1574 ret = adv7180_set_power(state, true); 1575 if (ret) 1576 return ret; 1577 } 1578 1579 return 0; 1580 } 1581 1582 static SIMPLE_DEV_PM_OPS(adv7180_pm_ops, adv7180_suspend, adv7180_resume); 1583 #define ADV7180_PM_OPS (&adv7180_pm_ops) 1584 1585 #else 1586 #define ADV7180_PM_OPS NULL 1587 #endif 1588 1589 static const struct i2c_device_id adv7180_id[] = { 1590 { "adv7180", (kernel_ulong_t)&adv7180_info }, 1591 { "adv7180cp", (kernel_ulong_t)&adv7180_info }, 1592 { "adv7180st", (kernel_ulong_t)&adv7180_info }, 1593 { "adv7182", (kernel_ulong_t)&adv7182_info }, 1594 { "adv7280", (kernel_ulong_t)&adv7280_info }, 1595 { "adv7280-m", (kernel_ulong_t)&adv7280_m_info }, 1596 { "adv7281", (kernel_ulong_t)&adv7281_info }, 1597 { "adv7281-m", (kernel_ulong_t)&adv7281_m_info }, 1598 { "adv7281-ma", (kernel_ulong_t)&adv7281_ma_info }, 1599 { "adv7282", (kernel_ulong_t)&adv7282_info }, 1600 { "adv7282-m", (kernel_ulong_t)&adv7282_m_info }, 1601 {} 1602 }; 1603 MODULE_DEVICE_TABLE(i2c, adv7180_id); 1604 1605 static const struct of_device_id adv7180_of_id[] = { 1606 { .compatible = "adi,adv7180", &adv7180_info }, 1607 { .compatible = "adi,adv7180cp", &adv7180_info }, 1608 { .compatible = "adi,adv7180st", &adv7180_info }, 1609 { .compatible = "adi,adv7182", &adv7182_info }, 1610 { .compatible = "adi,adv7280", &adv7280_info }, 1611 { .compatible = "adi,adv7280-m", &adv7280_m_info }, 1612 { .compatible = "adi,adv7281", &adv7281_info }, 1613 { .compatible = "adi,adv7281-m", &adv7281_m_info }, 1614 { .compatible = "adi,adv7281-ma", &adv7281_ma_info }, 1615 { .compatible = "adi,adv7282", &adv7282_info }, 1616 { .compatible = "adi,adv7282-m", &adv7282_m_info }, 1617 {} 1618 }; 1619 MODULE_DEVICE_TABLE(of, adv7180_of_id); 1620 1621 static struct i2c_driver adv7180_driver = { 1622 .driver = { 1623 .name = KBUILD_MODNAME, 1624 .pm = ADV7180_PM_OPS, 1625 .of_match_table = adv7180_of_id, 1626 }, 1627 .probe = adv7180_probe, 1628 .remove = adv7180_remove, 1629 .id_table = adv7180_id, 1630 }; 1631 1632 module_i2c_driver(adv7180_driver); 1633 1634 MODULE_DESCRIPTION("Analog Devices ADV7180 video decoder driver"); 1635 MODULE_AUTHOR("Mocean Laboratories"); 1636 MODULE_LICENSE("GPL v2"); 1637