1*c942fddfSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 29a0bf528SMauro Carvalho Chehab /* 39a0bf528SMauro Carvalho Chehab * Driver for Zarlink DVB-T ZL10353 demodulator 49a0bf528SMauro Carvalho Chehab * 59a0bf528SMauro Carvalho Chehab * Copyright (C) 2006, 2007 Christopher Pascoe <c.pascoe@itee.uq.edu.au> 69a0bf528SMauro Carvalho Chehab */ 79a0bf528SMauro Carvalho Chehab 89a0bf528SMauro Carvalho Chehab #ifndef _ZL10353_PRIV_ 99a0bf528SMauro Carvalho Chehab #define _ZL10353_PRIV_ 109a0bf528SMauro Carvalho Chehab 119a0bf528SMauro Carvalho Chehab #define ID_ZL10353 0x14 /* Zarlink ZL10353 */ 129a0bf528SMauro Carvalho Chehab #define ID_CE6230 0x18 /* Intel CE6230 */ 139a0bf528SMauro Carvalho Chehab #define ID_CE6231 0x19 /* Intel CE6231 */ 149a0bf528SMauro Carvalho Chehab 159a0bf528SMauro Carvalho Chehab #define msb(x) (((x) >> 8) & 0xff) 169a0bf528SMauro Carvalho Chehab #define lsb(x) ((x) & 0xff) 179a0bf528SMauro Carvalho Chehab 189a0bf528SMauro Carvalho Chehab enum zl10353_reg_addr { 199a0bf528SMauro Carvalho Chehab INTERRUPT_0 = 0x00, 209a0bf528SMauro Carvalho Chehab INTERRUPT_1 = 0x01, 219a0bf528SMauro Carvalho Chehab INTERRUPT_2 = 0x02, 229a0bf528SMauro Carvalho Chehab INTERRUPT_3 = 0x03, 239a0bf528SMauro Carvalho Chehab INTERRUPT_4 = 0x04, 249a0bf528SMauro Carvalho Chehab INTERRUPT_5 = 0x05, 259a0bf528SMauro Carvalho Chehab STATUS_6 = 0x06, 269a0bf528SMauro Carvalho Chehab STATUS_7 = 0x07, 279a0bf528SMauro Carvalho Chehab STATUS_8 = 0x08, 289a0bf528SMauro Carvalho Chehab STATUS_9 = 0x09, 299a0bf528SMauro Carvalho Chehab AGC_GAIN_1 = 0x0A, 309a0bf528SMauro Carvalho Chehab AGC_GAIN_0 = 0x0B, 319a0bf528SMauro Carvalho Chehab SNR = 0x10, 329a0bf528SMauro Carvalho Chehab RS_ERR_CNT_2 = 0x11, 339a0bf528SMauro Carvalho Chehab RS_ERR_CNT_1 = 0x12, 349a0bf528SMauro Carvalho Chehab RS_ERR_CNT_0 = 0x13, 359a0bf528SMauro Carvalho Chehab RS_UBC_1 = 0x14, 369a0bf528SMauro Carvalho Chehab RS_UBC_0 = 0x15, 379a0bf528SMauro Carvalho Chehab TPS_RECEIVED_1 = 0x1D, 389a0bf528SMauro Carvalho Chehab TPS_RECEIVED_0 = 0x1E, 399a0bf528SMauro Carvalho Chehab TPS_CURRENT_1 = 0x1F, 409a0bf528SMauro Carvalho Chehab TPS_CURRENT_0 = 0x20, 419a0bf528SMauro Carvalho Chehab CLOCK_CTL_0 = 0x51, 429a0bf528SMauro Carvalho Chehab CLOCK_CTL_1 = 0x52, 439a0bf528SMauro Carvalho Chehab PLL_0 = 0x53, 449a0bf528SMauro Carvalho Chehab PLL_1 = 0x54, 459a0bf528SMauro Carvalho Chehab RESET = 0x55, 469a0bf528SMauro Carvalho Chehab AGC_TARGET = 0x56, 479a0bf528SMauro Carvalho Chehab MCLK_RATIO = 0x5C, 489a0bf528SMauro Carvalho Chehab ACQ_CTL = 0x5E, 499a0bf528SMauro Carvalho Chehab TRL_NOMINAL_RATE_1 = 0x65, 509a0bf528SMauro Carvalho Chehab TRL_NOMINAL_RATE_0 = 0x66, 519a0bf528SMauro Carvalho Chehab INPUT_FREQ_1 = 0x6C, 529a0bf528SMauro Carvalho Chehab INPUT_FREQ_0 = 0x6D, 539a0bf528SMauro Carvalho Chehab TPS_GIVEN_1 = 0x6E, 549a0bf528SMauro Carvalho Chehab TPS_GIVEN_0 = 0x6F, 559a0bf528SMauro Carvalho Chehab TUNER_GO = 0x70, 569a0bf528SMauro Carvalho Chehab FSM_GO = 0x71, 579a0bf528SMauro Carvalho Chehab CHIP_ID = 0x7F, 589a0bf528SMauro Carvalho Chehab CHAN_STEP_1 = 0xE4, 599a0bf528SMauro Carvalho Chehab CHAN_STEP_0 = 0xE5, 609a0bf528SMauro Carvalho Chehab OFDM_LOCK_TIME = 0xE7, 619a0bf528SMauro Carvalho Chehab FEC_LOCK_TIME = 0xE8, 629a0bf528SMauro Carvalho Chehab ACQ_DELAY = 0xE9, 639a0bf528SMauro Carvalho Chehab }; 649a0bf528SMauro Carvalho Chehab 659a0bf528SMauro Carvalho Chehab #endif /* _ZL10353_PRIV_ */ 66