1 /* 2 * Driver for Zarlink DVB-T ZL10353 demodulator 3 * 4 * Copyright (C) 2006, 2007 Christopher Pascoe <c.pascoe@itee.uq.edu.au> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/init.h> 21 #include <linux/delay.h> 22 #include <linux/string.h> 23 #include <linux/slab.h> 24 #include <asm/div64.h> 25 26 #include "dvb_frontend.h" 27 #include "zl10353_priv.h" 28 #include "zl10353.h" 29 30 struct zl10353_state { 31 struct i2c_adapter *i2c; 32 struct dvb_frontend frontend; 33 34 struct zl10353_config config; 35 36 u32 bandwidth; 37 u32 ucblocks; 38 u32 frequency; 39 }; 40 41 static int debug; 42 #define dprintk(args...) \ 43 do { \ 44 if (debug) printk(KERN_DEBUG "zl10353: " args); \ 45 } while (0) 46 47 static int debug_regs; 48 49 static int zl10353_single_write(struct dvb_frontend *fe, u8 reg, u8 val) 50 { 51 struct zl10353_state *state = fe->demodulator_priv; 52 u8 buf[2] = { reg, val }; 53 struct i2c_msg msg = { .addr = state->config.demod_address, .flags = 0, 54 .buf = buf, .len = 2 }; 55 int err = i2c_transfer(state->i2c, &msg, 1); 56 if (err != 1) { 57 printk("zl10353: write to reg %x failed (err = %d)!\n", reg, err); 58 return err; 59 } 60 return 0; 61 } 62 63 static int zl10353_write(struct dvb_frontend *fe, const u8 ibuf[], int ilen) 64 { 65 int err, i; 66 for (i = 0; i < ilen - 1; i++) 67 if ((err = zl10353_single_write(fe, ibuf[0] + i, ibuf[i + 1]))) 68 return err; 69 70 return 0; 71 } 72 73 static int zl10353_read_register(struct zl10353_state *state, u8 reg) 74 { 75 int ret; 76 u8 b0[1] = { reg }; 77 u8 b1[1] = { 0 }; 78 struct i2c_msg msg[2] = { { .addr = state->config.demod_address, 79 .flags = 0, 80 .buf = b0, .len = 1 }, 81 { .addr = state->config.demod_address, 82 .flags = I2C_M_RD, 83 .buf = b1, .len = 1 } }; 84 85 ret = i2c_transfer(state->i2c, msg, 2); 86 87 if (ret != 2) { 88 printk("%s: readreg error (reg=%d, ret==%i)\n", 89 __func__, reg, ret); 90 return ret; 91 } 92 93 return b1[0]; 94 } 95 96 static void zl10353_dump_regs(struct dvb_frontend *fe) 97 { 98 struct zl10353_state *state = fe->demodulator_priv; 99 int ret; 100 u8 reg; 101 102 /* Dump all registers. */ 103 for (reg = 0; ; reg++) { 104 if (reg % 16 == 0) { 105 if (reg) 106 printk(KERN_CONT "\n"); 107 printk(KERN_DEBUG "%02x:", reg); 108 } 109 ret = zl10353_read_register(state, reg); 110 if (ret >= 0) 111 printk(KERN_CONT " %02x", (u8)ret); 112 else 113 printk(KERN_CONT " --"); 114 if (reg == 0xff) 115 break; 116 } 117 printk(KERN_CONT "\n"); 118 } 119 120 static void zl10353_calc_nominal_rate(struct dvb_frontend *fe, 121 u32 bandwidth, 122 u16 *nominal_rate) 123 { 124 struct zl10353_state *state = fe->demodulator_priv; 125 u32 adc_clock = 450560; /* 45.056 MHz */ 126 u64 value; 127 u8 bw = bandwidth / 1000000; 128 129 if (state->config.adc_clock) 130 adc_clock = state->config.adc_clock; 131 132 value = (u64)10 * (1 << 23) / 7 * 125; 133 value = (bw * value) + adc_clock / 2; 134 *nominal_rate = div_u64(value, adc_clock); 135 136 dprintk("%s: bw %d, adc_clock %d => 0x%x\n", 137 __func__, bw, adc_clock, *nominal_rate); 138 } 139 140 static void zl10353_calc_input_freq(struct dvb_frontend *fe, 141 u16 *input_freq) 142 { 143 struct zl10353_state *state = fe->demodulator_priv; 144 u32 adc_clock = 450560; /* 45.056 MHz */ 145 int if2 = 361667; /* 36.1667 MHz */ 146 int ife; 147 u64 value; 148 149 if (state->config.adc_clock) 150 adc_clock = state->config.adc_clock; 151 if (state->config.if2) 152 if2 = state->config.if2; 153 154 if (adc_clock >= if2 * 2) 155 ife = if2; 156 else { 157 ife = adc_clock - (if2 % adc_clock); 158 if (ife > adc_clock / 2) 159 ife = adc_clock - ife; 160 } 161 value = div_u64((u64)65536 * ife + adc_clock / 2, adc_clock); 162 *input_freq = -value; 163 164 dprintk("%s: if2 %d, ife %d, adc_clock %d => %d / 0x%x\n", 165 __func__, if2, ife, adc_clock, -(int)value, *input_freq); 166 } 167 168 static int zl10353_sleep(struct dvb_frontend *fe) 169 { 170 static u8 zl10353_softdown[] = { 0x50, 0x0C, 0x44 }; 171 172 zl10353_write(fe, zl10353_softdown, sizeof(zl10353_softdown)); 173 return 0; 174 } 175 176 static int zl10353_set_parameters(struct dvb_frontend *fe) 177 { 178 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 179 struct zl10353_state *state = fe->demodulator_priv; 180 u16 nominal_rate, input_freq; 181 u8 pllbuf[6] = { 0x67 }, acq_ctl = 0; 182 u16 tps = 0; 183 184 state->frequency = c->frequency; 185 186 zl10353_single_write(fe, RESET, 0x80); 187 udelay(200); 188 zl10353_single_write(fe, 0xEA, 0x01); 189 udelay(200); 190 zl10353_single_write(fe, 0xEA, 0x00); 191 192 zl10353_single_write(fe, AGC_TARGET, 0x28); 193 194 if (c->transmission_mode != TRANSMISSION_MODE_AUTO) 195 acq_ctl |= (1 << 0); 196 if (c->guard_interval != GUARD_INTERVAL_AUTO) 197 acq_ctl |= (1 << 1); 198 zl10353_single_write(fe, ACQ_CTL, acq_ctl); 199 200 switch (c->bandwidth_hz) { 201 case 6000000: 202 /* These are extrapolated from the 7 and 8MHz values */ 203 zl10353_single_write(fe, MCLK_RATIO, 0x97); 204 zl10353_single_write(fe, 0x64, 0x34); 205 zl10353_single_write(fe, 0xcc, 0xdd); 206 break; 207 case 7000000: 208 zl10353_single_write(fe, MCLK_RATIO, 0x86); 209 zl10353_single_write(fe, 0x64, 0x35); 210 zl10353_single_write(fe, 0xcc, 0x73); 211 break; 212 default: 213 c->bandwidth_hz = 8000000; 214 /* fall though */ 215 case 8000000: 216 zl10353_single_write(fe, MCLK_RATIO, 0x75); 217 zl10353_single_write(fe, 0x64, 0x36); 218 zl10353_single_write(fe, 0xcc, 0x73); 219 } 220 221 zl10353_calc_nominal_rate(fe, c->bandwidth_hz, &nominal_rate); 222 zl10353_single_write(fe, TRL_NOMINAL_RATE_1, msb(nominal_rate)); 223 zl10353_single_write(fe, TRL_NOMINAL_RATE_0, lsb(nominal_rate)); 224 state->bandwidth = c->bandwidth_hz; 225 226 zl10353_calc_input_freq(fe, &input_freq); 227 zl10353_single_write(fe, INPUT_FREQ_1, msb(input_freq)); 228 zl10353_single_write(fe, INPUT_FREQ_0, lsb(input_freq)); 229 230 /* Hint at TPS settings */ 231 switch (c->code_rate_HP) { 232 case FEC_2_3: 233 tps |= (1 << 7); 234 break; 235 case FEC_3_4: 236 tps |= (2 << 7); 237 break; 238 case FEC_5_6: 239 tps |= (3 << 7); 240 break; 241 case FEC_7_8: 242 tps |= (4 << 7); 243 break; 244 case FEC_1_2: 245 case FEC_AUTO: 246 break; 247 default: 248 return -EINVAL; 249 } 250 251 switch (c->code_rate_LP) { 252 case FEC_2_3: 253 tps |= (1 << 4); 254 break; 255 case FEC_3_4: 256 tps |= (2 << 4); 257 break; 258 case FEC_5_6: 259 tps |= (3 << 4); 260 break; 261 case FEC_7_8: 262 tps |= (4 << 4); 263 break; 264 case FEC_1_2: 265 case FEC_AUTO: 266 break; 267 case FEC_NONE: 268 if (c->hierarchy == HIERARCHY_AUTO || 269 c->hierarchy == HIERARCHY_NONE) 270 break; 271 default: 272 return -EINVAL; 273 } 274 275 switch (c->modulation) { 276 case QPSK: 277 break; 278 case QAM_AUTO: 279 case QAM_16: 280 tps |= (1 << 13); 281 break; 282 case QAM_64: 283 tps |= (2 << 13); 284 break; 285 default: 286 return -EINVAL; 287 } 288 289 switch (c->transmission_mode) { 290 case TRANSMISSION_MODE_2K: 291 case TRANSMISSION_MODE_AUTO: 292 break; 293 case TRANSMISSION_MODE_8K: 294 tps |= (1 << 0); 295 break; 296 default: 297 return -EINVAL; 298 } 299 300 switch (c->guard_interval) { 301 case GUARD_INTERVAL_1_32: 302 case GUARD_INTERVAL_AUTO: 303 break; 304 case GUARD_INTERVAL_1_16: 305 tps |= (1 << 2); 306 break; 307 case GUARD_INTERVAL_1_8: 308 tps |= (2 << 2); 309 break; 310 case GUARD_INTERVAL_1_4: 311 tps |= (3 << 2); 312 break; 313 default: 314 return -EINVAL; 315 } 316 317 switch (c->hierarchy) { 318 case HIERARCHY_AUTO: 319 case HIERARCHY_NONE: 320 break; 321 case HIERARCHY_1: 322 tps |= (1 << 10); 323 break; 324 case HIERARCHY_2: 325 tps |= (2 << 10); 326 break; 327 case HIERARCHY_4: 328 tps |= (3 << 10); 329 break; 330 default: 331 return -EINVAL; 332 } 333 334 zl10353_single_write(fe, TPS_GIVEN_1, msb(tps)); 335 zl10353_single_write(fe, TPS_GIVEN_0, lsb(tps)); 336 337 if (fe->ops.i2c_gate_ctrl) 338 fe->ops.i2c_gate_ctrl(fe, 0); 339 340 /* 341 * If there is no tuner attached to the secondary I2C bus, we call 342 * set_params to program a potential tuner attached somewhere else. 343 * Otherwise, we update the PLL registers via calc_regs. 344 */ 345 if (state->config.no_tuner) { 346 if (fe->ops.tuner_ops.set_params) { 347 fe->ops.tuner_ops.set_params(fe); 348 if (fe->ops.i2c_gate_ctrl) 349 fe->ops.i2c_gate_ctrl(fe, 0); 350 } 351 } else if (fe->ops.tuner_ops.calc_regs) { 352 fe->ops.tuner_ops.calc_regs(fe, pllbuf + 1, 5); 353 pllbuf[1] <<= 1; 354 zl10353_write(fe, pllbuf, sizeof(pllbuf)); 355 } 356 357 zl10353_single_write(fe, 0x5F, 0x13); 358 359 /* If no attached tuner or invalid PLL registers, just start the FSM. */ 360 if (state->config.no_tuner || fe->ops.tuner_ops.calc_regs == NULL) 361 zl10353_single_write(fe, FSM_GO, 0x01); 362 else 363 zl10353_single_write(fe, TUNER_GO, 0x01); 364 365 return 0; 366 } 367 368 static int zl10353_get_parameters(struct dvb_frontend *fe, 369 struct dtv_frontend_properties *c) 370 { 371 struct zl10353_state *state = fe->demodulator_priv; 372 int s6, s9; 373 u16 tps; 374 static const u8 tps_fec_to_api[8] = { 375 FEC_1_2, 376 FEC_2_3, 377 FEC_3_4, 378 FEC_5_6, 379 FEC_7_8, 380 FEC_AUTO, 381 FEC_AUTO, 382 FEC_AUTO 383 }; 384 385 s6 = zl10353_read_register(state, STATUS_6); 386 s9 = zl10353_read_register(state, STATUS_9); 387 if (s6 < 0 || s9 < 0) 388 return -EREMOTEIO; 389 if ((s6 & (1 << 5)) == 0 || (s9 & (1 << 4)) == 0) 390 return -EINVAL; /* no FE or TPS lock */ 391 392 tps = zl10353_read_register(state, TPS_RECEIVED_1) << 8 | 393 zl10353_read_register(state, TPS_RECEIVED_0); 394 395 c->code_rate_HP = tps_fec_to_api[(tps >> 7) & 7]; 396 c->code_rate_LP = tps_fec_to_api[(tps >> 4) & 7]; 397 398 switch ((tps >> 13) & 3) { 399 case 0: 400 c->modulation = QPSK; 401 break; 402 case 1: 403 c->modulation = QAM_16; 404 break; 405 case 2: 406 c->modulation = QAM_64; 407 break; 408 default: 409 c->modulation = QAM_AUTO; 410 break; 411 } 412 413 c->transmission_mode = (tps & 0x01) ? TRANSMISSION_MODE_8K : 414 TRANSMISSION_MODE_2K; 415 416 switch ((tps >> 2) & 3) { 417 case 0: 418 c->guard_interval = GUARD_INTERVAL_1_32; 419 break; 420 case 1: 421 c->guard_interval = GUARD_INTERVAL_1_16; 422 break; 423 case 2: 424 c->guard_interval = GUARD_INTERVAL_1_8; 425 break; 426 case 3: 427 c->guard_interval = GUARD_INTERVAL_1_4; 428 break; 429 default: 430 c->guard_interval = GUARD_INTERVAL_AUTO; 431 break; 432 } 433 434 switch ((tps >> 10) & 7) { 435 case 0: 436 c->hierarchy = HIERARCHY_NONE; 437 break; 438 case 1: 439 c->hierarchy = HIERARCHY_1; 440 break; 441 case 2: 442 c->hierarchy = HIERARCHY_2; 443 break; 444 case 3: 445 c->hierarchy = HIERARCHY_4; 446 break; 447 default: 448 c->hierarchy = HIERARCHY_AUTO; 449 break; 450 } 451 452 c->frequency = state->frequency; 453 c->bandwidth_hz = state->bandwidth; 454 c->inversion = INVERSION_AUTO; 455 456 return 0; 457 } 458 459 static int zl10353_read_status(struct dvb_frontend *fe, enum fe_status *status) 460 { 461 struct zl10353_state *state = fe->demodulator_priv; 462 int s6, s7, s8; 463 464 if ((s6 = zl10353_read_register(state, STATUS_6)) < 0) 465 return -EREMOTEIO; 466 if ((s7 = zl10353_read_register(state, STATUS_7)) < 0) 467 return -EREMOTEIO; 468 if ((s8 = zl10353_read_register(state, STATUS_8)) < 0) 469 return -EREMOTEIO; 470 471 *status = 0; 472 if (s6 & (1 << 2)) 473 *status |= FE_HAS_CARRIER; 474 if (s6 & (1 << 1)) 475 *status |= FE_HAS_VITERBI; 476 if (s6 & (1 << 5)) 477 *status |= FE_HAS_LOCK; 478 if (s7 & (1 << 4)) 479 *status |= FE_HAS_SYNC; 480 if (s8 & (1 << 6)) 481 *status |= FE_HAS_SIGNAL; 482 483 if ((*status & (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)) != 484 (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)) 485 *status &= ~FE_HAS_LOCK; 486 487 return 0; 488 } 489 490 static int zl10353_read_ber(struct dvb_frontend *fe, u32 *ber) 491 { 492 struct zl10353_state *state = fe->demodulator_priv; 493 494 *ber = zl10353_read_register(state, RS_ERR_CNT_2) << 16 | 495 zl10353_read_register(state, RS_ERR_CNT_1) << 8 | 496 zl10353_read_register(state, RS_ERR_CNT_0); 497 498 return 0; 499 } 500 501 static int zl10353_read_signal_strength(struct dvb_frontend *fe, u16 *strength) 502 { 503 struct zl10353_state *state = fe->demodulator_priv; 504 505 u16 signal = zl10353_read_register(state, AGC_GAIN_1) << 10 | 506 zl10353_read_register(state, AGC_GAIN_0) << 2 | 3; 507 508 *strength = ~signal; 509 510 return 0; 511 } 512 513 static int zl10353_read_snr(struct dvb_frontend *fe, u16 *snr) 514 { 515 struct zl10353_state *state = fe->demodulator_priv; 516 u8 _snr; 517 518 if (debug_regs) 519 zl10353_dump_regs(fe); 520 521 _snr = zl10353_read_register(state, SNR); 522 *snr = 10 * _snr / 8; 523 524 return 0; 525 } 526 527 static int zl10353_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 528 { 529 struct zl10353_state *state = fe->demodulator_priv; 530 u32 ubl = 0; 531 532 ubl = zl10353_read_register(state, RS_UBC_1) << 8 | 533 zl10353_read_register(state, RS_UBC_0); 534 535 state->ucblocks += ubl; 536 *ucblocks = state->ucblocks; 537 538 return 0; 539 } 540 541 static int zl10353_get_tune_settings(struct dvb_frontend *fe, 542 struct dvb_frontend_tune_settings 543 *fe_tune_settings) 544 { 545 fe_tune_settings->min_delay_ms = 1000; 546 fe_tune_settings->step_size = 0; 547 fe_tune_settings->max_drift = 0; 548 549 return 0; 550 } 551 552 static int zl10353_init(struct dvb_frontend *fe) 553 { 554 struct zl10353_state *state = fe->demodulator_priv; 555 u8 zl10353_reset_attach[6] = { 0x50, 0x03, 0x64, 0x46, 0x15, 0x0F }; 556 557 if (debug_regs) 558 zl10353_dump_regs(fe); 559 if (state->config.parallel_ts) 560 zl10353_reset_attach[2] &= ~0x20; 561 if (state->config.clock_ctl_1) 562 zl10353_reset_attach[3] = state->config.clock_ctl_1; 563 if (state->config.pll_0) 564 zl10353_reset_attach[4] = state->config.pll_0; 565 566 /* Do a "hard" reset if not already done */ 567 if (zl10353_read_register(state, 0x50) != zl10353_reset_attach[1] || 568 zl10353_read_register(state, 0x51) != zl10353_reset_attach[2]) { 569 zl10353_write(fe, zl10353_reset_attach, 570 sizeof(zl10353_reset_attach)); 571 if (debug_regs) 572 zl10353_dump_regs(fe); 573 } 574 575 return 0; 576 } 577 578 static int zl10353_i2c_gate_ctrl(struct dvb_frontend* fe, int enable) 579 { 580 struct zl10353_state *state = fe->demodulator_priv; 581 u8 val = 0x0a; 582 583 if (state->config.disable_i2c_gate_ctrl) { 584 /* No tuner attached to the internal I2C bus */ 585 /* If set enable I2C bridge, the main I2C bus stopped hardly */ 586 return 0; 587 } 588 589 if (enable) 590 val |= 0x10; 591 592 return zl10353_single_write(fe, 0x62, val); 593 } 594 595 static void zl10353_release(struct dvb_frontend *fe) 596 { 597 struct zl10353_state *state = fe->demodulator_priv; 598 kfree(state); 599 } 600 601 static const struct dvb_frontend_ops zl10353_ops; 602 603 struct dvb_frontend *zl10353_attach(const struct zl10353_config *config, 604 struct i2c_adapter *i2c) 605 { 606 struct zl10353_state *state = NULL; 607 int id; 608 609 /* allocate memory for the internal state */ 610 state = kzalloc(sizeof(struct zl10353_state), GFP_KERNEL); 611 if (state == NULL) 612 goto error; 613 614 /* setup the state */ 615 state->i2c = i2c; 616 memcpy(&state->config, config, sizeof(struct zl10353_config)); 617 618 /* check if the demod is there */ 619 id = zl10353_read_register(state, CHIP_ID); 620 if ((id != ID_ZL10353) && (id != ID_CE6230) && (id != ID_CE6231)) 621 goto error; 622 623 /* create dvb_frontend */ 624 memcpy(&state->frontend.ops, &zl10353_ops, sizeof(struct dvb_frontend_ops)); 625 state->frontend.demodulator_priv = state; 626 627 return &state->frontend; 628 error: 629 kfree(state); 630 return NULL; 631 } 632 633 static const struct dvb_frontend_ops zl10353_ops = { 634 .delsys = { SYS_DVBT }, 635 .info = { 636 .name = "Zarlink ZL10353 DVB-T", 637 .frequency_min = 174000000, 638 .frequency_max = 862000000, 639 .frequency_stepsize = 166667, 640 .frequency_tolerance = 0, 641 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | 642 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | 643 FE_CAN_FEC_AUTO | 644 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | 645 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | 646 FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | 647 FE_CAN_MUTE_TS 648 }, 649 650 .release = zl10353_release, 651 652 .init = zl10353_init, 653 .sleep = zl10353_sleep, 654 .i2c_gate_ctrl = zl10353_i2c_gate_ctrl, 655 .write = zl10353_write, 656 657 .set_frontend = zl10353_set_parameters, 658 .get_frontend = zl10353_get_parameters, 659 .get_tune_settings = zl10353_get_tune_settings, 660 661 .read_status = zl10353_read_status, 662 .read_ber = zl10353_read_ber, 663 .read_signal_strength = zl10353_read_signal_strength, 664 .read_snr = zl10353_read_snr, 665 .read_ucblocks = zl10353_read_ucblocks, 666 }; 667 668 module_param(debug, int, 0644); 669 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); 670 671 module_param(debug_regs, int, 0644); 672 MODULE_PARM_DESC(debug_regs, "Turn on/off frontend register dumps (default:off)."); 673 674 MODULE_DESCRIPTION("Zarlink ZL10353 DVB-T demodulator driver"); 675 MODULE_AUTHOR("Chris Pascoe"); 676 MODULE_LICENSE("GPL"); 677 678 EXPORT_SYMBOL(zl10353_attach); 679