1 /* 2 Driver for Philips tda1004xh OFDM Demodulator 3 4 (c) 2003, 2004 Andrew de Quincey & Robert Schlabbach 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 2 of the License, or 9 (at your option) any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program; if not, write to the Free Software 19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 21 */ 22 /* 23 * This driver needs external firmware. Please use the commands 24 * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10045", 25 * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10046" to 26 * download/extract them, and then copy them to /usr/lib/hotplug/firmware 27 * or /lib/firmware (depending on configuration of firmware hotplug). 28 */ 29 #define TDA10045_DEFAULT_FIRMWARE "dvb-fe-tda10045.fw" 30 #define TDA10046_DEFAULT_FIRMWARE "dvb-fe-tda10046.fw" 31 32 #include <linux/init.h> 33 #include <linux/module.h> 34 #include <linux/device.h> 35 #include <linux/jiffies.h> 36 #include <linux/string.h> 37 #include <linux/slab.h> 38 39 #include "dvb_frontend.h" 40 #include "tda1004x.h" 41 42 static int debug; 43 #define dprintk(args...) \ 44 do { \ 45 if (debug) printk(KERN_DEBUG "tda1004x: " args); \ 46 } while (0) 47 48 #define TDA1004X_CHIPID 0x00 49 #define TDA1004X_AUTO 0x01 50 #define TDA1004X_IN_CONF1 0x02 51 #define TDA1004X_IN_CONF2 0x03 52 #define TDA1004X_OUT_CONF1 0x04 53 #define TDA1004X_OUT_CONF2 0x05 54 #define TDA1004X_STATUS_CD 0x06 55 #define TDA1004X_CONFC4 0x07 56 #define TDA1004X_DSSPARE2 0x0C 57 #define TDA10045H_CODE_IN 0x0D 58 #define TDA10045H_FWPAGE 0x0E 59 #define TDA1004X_SCAN_CPT 0x10 60 #define TDA1004X_DSP_CMD 0x11 61 #define TDA1004X_DSP_ARG 0x12 62 #define TDA1004X_DSP_DATA1 0x13 63 #define TDA1004X_DSP_DATA2 0x14 64 #define TDA1004X_CONFADC1 0x15 65 #define TDA1004X_CONFC1 0x16 66 #define TDA10045H_S_AGC 0x1a 67 #define TDA10046H_AGC_TUN_LEVEL 0x1a 68 #define TDA1004X_SNR 0x1c 69 #define TDA1004X_CONF_TS1 0x1e 70 #define TDA1004X_CONF_TS2 0x1f 71 #define TDA1004X_CBER_RESET 0x20 72 #define TDA1004X_CBER_MSB 0x21 73 #define TDA1004X_CBER_LSB 0x22 74 #define TDA1004X_CVBER_LUT 0x23 75 #define TDA1004X_VBER_MSB 0x24 76 #define TDA1004X_VBER_MID 0x25 77 #define TDA1004X_VBER_LSB 0x26 78 #define TDA1004X_UNCOR 0x27 79 80 #define TDA10045H_CONFPLL_P 0x2D 81 #define TDA10045H_CONFPLL_M_MSB 0x2E 82 #define TDA10045H_CONFPLL_M_LSB 0x2F 83 #define TDA10045H_CONFPLL_N 0x30 84 85 #define TDA10046H_CONFPLL1 0x2D 86 #define TDA10046H_CONFPLL2 0x2F 87 #define TDA10046H_CONFPLL3 0x30 88 #define TDA10046H_TIME_WREF1 0x31 89 #define TDA10046H_TIME_WREF2 0x32 90 #define TDA10046H_TIME_WREF3 0x33 91 #define TDA10046H_TIME_WREF4 0x34 92 #define TDA10046H_TIME_WREF5 0x35 93 94 #define TDA10045H_UNSURW_MSB 0x31 95 #define TDA10045H_UNSURW_LSB 0x32 96 #define TDA10045H_WREF_MSB 0x33 97 #define TDA10045H_WREF_MID 0x34 98 #define TDA10045H_WREF_LSB 0x35 99 #define TDA10045H_MUXOUT 0x36 100 #define TDA1004X_CONFADC2 0x37 101 102 #define TDA10045H_IOFFSET 0x38 103 104 #define TDA10046H_CONF_TRISTATE1 0x3B 105 #define TDA10046H_CONF_TRISTATE2 0x3C 106 #define TDA10046H_CONF_POLARITY 0x3D 107 #define TDA10046H_FREQ_OFFSET 0x3E 108 #define TDA10046H_GPIO_OUT_SEL 0x41 109 #define TDA10046H_GPIO_SELECT 0x42 110 #define TDA10046H_AGC_CONF 0x43 111 #define TDA10046H_AGC_THR 0x44 112 #define TDA10046H_AGC_RENORM 0x45 113 #define TDA10046H_AGC_GAINS 0x46 114 #define TDA10046H_AGC_TUN_MIN 0x47 115 #define TDA10046H_AGC_TUN_MAX 0x48 116 #define TDA10046H_AGC_IF_MIN 0x49 117 #define TDA10046H_AGC_IF_MAX 0x4A 118 119 #define TDA10046H_FREQ_PHY2_MSB 0x4D 120 #define TDA10046H_FREQ_PHY2_LSB 0x4E 121 122 #define TDA10046H_CVBER_CTRL 0x4F 123 #define TDA10046H_AGC_IF_LEVEL 0x52 124 #define TDA10046H_CODE_CPT 0x57 125 #define TDA10046H_CODE_IN 0x58 126 127 128 static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data) 129 { 130 int ret; 131 u8 buf[] = { reg, data }; 132 struct i2c_msg msg = { .flags = 0, .buf = buf, .len = 2 }; 133 134 dprintk("%s: reg=0x%x, data=0x%x\n", __func__, reg, data); 135 136 msg.addr = state->config->demod_address; 137 ret = i2c_transfer(state->i2c, &msg, 1); 138 139 if (ret != 1) 140 dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n", 141 __func__, reg, data, ret); 142 143 dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __func__, 144 reg, data, ret); 145 return (ret != 1) ? -1 : 0; 146 } 147 148 static int tda1004x_read_byte(struct tda1004x_state *state, int reg) 149 { 150 int ret; 151 u8 b0[] = { reg }; 152 u8 b1[] = { 0 }; 153 struct i2c_msg msg[] = {{ .flags = 0, .buf = b0, .len = 1 }, 154 { .flags = I2C_M_RD, .buf = b1, .len = 1 }}; 155 156 dprintk("%s: reg=0x%x\n", __func__, reg); 157 158 msg[0].addr = state->config->demod_address; 159 msg[1].addr = state->config->demod_address; 160 ret = i2c_transfer(state->i2c, msg, 2); 161 162 if (ret != 2) { 163 dprintk("%s: error reg=0x%x, ret=%i\n", __func__, reg, 164 ret); 165 return -EINVAL; 166 } 167 168 dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __func__, 169 reg, b1[0], ret); 170 return b1[0]; 171 } 172 173 static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data) 174 { 175 int val; 176 dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __func__, reg, 177 mask, data); 178 179 // read a byte and check 180 val = tda1004x_read_byte(state, reg); 181 if (val < 0) 182 return val; 183 184 // mask if off 185 val = val & ~mask; 186 val |= data & 0xff; 187 188 // write it out again 189 return tda1004x_write_byteI(state, reg, val); 190 } 191 192 static int tda1004x_write_buf(struct tda1004x_state *state, int reg, unsigned char *buf, int len) 193 { 194 int i; 195 int result; 196 197 dprintk("%s: reg=0x%x, len=0x%x\n", __func__, reg, len); 198 199 result = 0; 200 for (i = 0; i < len; i++) { 201 result = tda1004x_write_byteI(state, reg + i, buf[i]); 202 if (result != 0) 203 break; 204 } 205 206 return result; 207 } 208 209 static int tda1004x_enable_tuner_i2c(struct tda1004x_state *state) 210 { 211 int result; 212 dprintk("%s\n", __func__); 213 214 result = tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 2); 215 msleep(20); 216 return result; 217 } 218 219 static int tda1004x_disable_tuner_i2c(struct tda1004x_state *state) 220 { 221 dprintk("%s\n", __func__); 222 223 return tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 0); 224 } 225 226 static int tda10045h_set_bandwidth(struct tda1004x_state *state, 227 u32 bandwidth) 228 { 229 static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f }; 230 static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb }; 231 static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 }; 232 233 switch (bandwidth) { 234 case 6000000: 235 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz)); 236 break; 237 238 case 7000000: 239 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz)); 240 break; 241 242 case 8000000: 243 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz)); 244 break; 245 246 default: 247 return -EINVAL; 248 } 249 250 tda1004x_write_byteI(state, TDA10045H_IOFFSET, 0); 251 252 return 0; 253 } 254 255 static int tda10046h_set_bandwidth(struct tda1004x_state *state, 256 u32 bandwidth) 257 { 258 static u8 bandwidth_6mhz_53M[] = { 0x7b, 0x2e, 0x11, 0xf0, 0xd2 }; 259 static u8 bandwidth_7mhz_53M[] = { 0x6a, 0x02, 0x6a, 0x43, 0x9f }; 260 static u8 bandwidth_8mhz_53M[] = { 0x5c, 0x32, 0xc2, 0x96, 0x6d }; 261 262 static u8 bandwidth_6mhz_48M[] = { 0x70, 0x02, 0x49, 0x24, 0x92 }; 263 static u8 bandwidth_7mhz_48M[] = { 0x60, 0x02, 0xaa, 0xaa, 0xab }; 264 static u8 bandwidth_8mhz_48M[] = { 0x54, 0x03, 0x0c, 0x30, 0xc3 }; 265 int tda10046_clk53m; 266 267 if ((state->config->if_freq == TDA10046_FREQ_045) || 268 (state->config->if_freq == TDA10046_FREQ_052)) 269 tda10046_clk53m = 0; 270 else 271 tda10046_clk53m = 1; 272 switch (bandwidth) { 273 case 6000000: 274 if (tda10046_clk53m) 275 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_53M, 276 sizeof(bandwidth_6mhz_53M)); 277 else 278 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_48M, 279 sizeof(bandwidth_6mhz_48M)); 280 if (state->config->if_freq == TDA10046_FREQ_045) { 281 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0a); 282 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xab); 283 } 284 break; 285 286 case 7000000: 287 if (tda10046_clk53m) 288 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_53M, 289 sizeof(bandwidth_7mhz_53M)); 290 else 291 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_48M, 292 sizeof(bandwidth_7mhz_48M)); 293 if (state->config->if_freq == TDA10046_FREQ_045) { 294 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c); 295 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00); 296 } 297 break; 298 299 case 8000000: 300 if (tda10046_clk53m) 301 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_53M, 302 sizeof(bandwidth_8mhz_53M)); 303 else 304 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_48M, 305 sizeof(bandwidth_8mhz_48M)); 306 if (state->config->if_freq == TDA10046_FREQ_045) { 307 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d); 308 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x55); 309 } 310 break; 311 312 default: 313 return -EINVAL; 314 } 315 316 return 0; 317 } 318 319 static int tda1004x_do_upload(struct tda1004x_state *state, 320 const unsigned char *mem, unsigned int len, 321 u8 dspCodeCounterReg, u8 dspCodeInReg) 322 { 323 u8 buf[65]; 324 struct i2c_msg fw_msg = { .flags = 0, .buf = buf, .len = 0 }; 325 int tx_size; 326 int pos = 0; 327 328 /* clear code counter */ 329 tda1004x_write_byteI(state, dspCodeCounterReg, 0); 330 fw_msg.addr = state->config->demod_address; 331 332 i2c_lock_adapter(state->i2c); 333 buf[0] = dspCodeInReg; 334 while (pos != len) { 335 // work out how much to send this time 336 tx_size = len - pos; 337 if (tx_size > 0x10) 338 tx_size = 0x10; 339 340 // send the chunk 341 memcpy(buf + 1, mem + pos, tx_size); 342 fw_msg.len = tx_size + 1; 343 if (__i2c_transfer(state->i2c, &fw_msg, 1) != 1) { 344 printk(KERN_ERR "tda1004x: Error during firmware upload\n"); 345 i2c_unlock_adapter(state->i2c); 346 return -EIO; 347 } 348 pos += tx_size; 349 350 dprintk("%s: fw_pos=0x%x\n", __func__, pos); 351 } 352 i2c_unlock_adapter(state->i2c); 353 354 /* give the DSP a chance to settle 03/10/05 Hac */ 355 msleep(100); 356 357 return 0; 358 } 359 360 static int tda1004x_check_upload_ok(struct tda1004x_state *state) 361 { 362 u8 data1, data2; 363 unsigned long timeout; 364 365 if (state->demod_type == TDA1004X_DEMOD_TDA10046) { 366 timeout = jiffies + 2 * HZ; 367 while(!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) { 368 if (time_after(jiffies, timeout)) { 369 printk(KERN_ERR "tda1004x: timeout waiting for DSP ready\n"); 370 break; 371 } 372 msleep(1); 373 } 374 } else 375 msleep(100); 376 377 // check upload was OK 378 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP 379 tda1004x_write_byteI(state, TDA1004X_DSP_CMD, 0x67); 380 381 data1 = tda1004x_read_byte(state, TDA1004X_DSP_DATA1); 382 data2 = tda1004x_read_byte(state, TDA1004X_DSP_DATA2); 383 if (data1 != 0x67 || data2 < 0x20 || data2 > 0x2e) { 384 printk(KERN_INFO "tda1004x: found firmware revision %x -- invalid\n", data2); 385 return -EIO; 386 } 387 printk(KERN_INFO "tda1004x: found firmware revision %x -- ok\n", data2); 388 return 0; 389 } 390 391 static int tda10045_fwupload(struct dvb_frontend* fe) 392 { 393 struct tda1004x_state* state = fe->demodulator_priv; 394 int ret; 395 const struct firmware *fw; 396 397 /* don't re-upload unless necessary */ 398 if (tda1004x_check_upload_ok(state) == 0) 399 return 0; 400 401 /* request the firmware, this will block until someone uploads it */ 402 printk(KERN_INFO "tda1004x: waiting for firmware upload (%s)...\n", TDA10045_DEFAULT_FIRMWARE); 403 ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE); 404 if (ret) { 405 printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n"); 406 return ret; 407 } 408 409 /* reset chip */ 410 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); 411 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); 412 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0); 413 msleep(10); 414 415 /* set parameters */ 416 tda10045h_set_bandwidth(state, 8000000); 417 418 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN); 419 release_firmware(fw); 420 if (ret) 421 return ret; 422 printk(KERN_INFO "tda1004x: firmware upload complete\n"); 423 424 /* wait for DSP to initialise */ 425 /* DSPREADY doesn't seem to work on the TDA10045H */ 426 msleep(100); 427 428 return tda1004x_check_upload_ok(state); 429 } 430 431 static void tda10046_init_plls(struct dvb_frontend* fe) 432 { 433 struct tda1004x_state* state = fe->demodulator_priv; 434 int tda10046_clk53m; 435 436 if ((state->config->if_freq == TDA10046_FREQ_045) || 437 (state->config->if_freq == TDA10046_FREQ_052)) 438 tda10046_clk53m = 0; 439 else 440 tda10046_clk53m = 1; 441 442 tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0); 443 if(tda10046_clk53m) { 444 printk(KERN_INFO "tda1004x: setting up plls for 53MHz sampling clock\n"); 445 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x08); // PLL M = 8 446 } else { 447 printk(KERN_INFO "tda1004x: setting up plls for 48MHz sampling clock\n"); 448 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x03); // PLL M = 3 449 } 450 if (state->config->xtal_freq == TDA10046_XTAL_4M ) { 451 dprintk("%s: setting up PLLs for a 4 MHz Xtal\n", __func__); 452 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0 453 } else { 454 dprintk("%s: setting up PLLs for a 16 MHz Xtal\n", __func__); 455 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3 456 } 457 if(tda10046_clk53m) 458 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x67); 459 else 460 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x72); 461 /* Note clock frequency is handled implicitly */ 462 switch (state->config->if_freq) { 463 case TDA10046_FREQ_045: 464 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c); 465 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00); 466 break; 467 case TDA10046_FREQ_052: 468 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d); 469 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xc7); 470 break; 471 case TDA10046_FREQ_3617: 472 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7); 473 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x59); 474 break; 475 case TDA10046_FREQ_3613: 476 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7); 477 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x3f); 478 break; 479 } 480 tda10046h_set_bandwidth(state, 8000000); /* default bandwidth 8 MHz */ 481 /* let the PLLs settle */ 482 msleep(120); 483 } 484 485 static int tda10046_fwupload(struct dvb_frontend* fe) 486 { 487 struct tda1004x_state* state = fe->demodulator_priv; 488 int ret, confc4; 489 const struct firmware *fw; 490 491 /* reset + wake up chip */ 492 if (state->config->xtal_freq == TDA10046_XTAL_4M) { 493 confc4 = 0; 494 } else { 495 dprintk("%s: 16MHz Xtal, reducing I2C speed\n", __func__); 496 confc4 = 0x80; 497 } 498 tda1004x_write_byteI(state, TDA1004X_CONFC4, confc4); 499 500 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0); 501 /* set GPIO 1 and 3 */ 502 if (state->config->gpio_config != TDA10046_GPTRI) { 503 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE2, 0x33); 504 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f, state->config->gpio_config &0x0f); 505 } 506 /* let the clocks recover from sleep */ 507 msleep(10); 508 509 /* The PLLs need to be reprogrammed after sleep */ 510 tda10046_init_plls(fe); 511 tda1004x_write_mask(state, TDA1004X_CONFADC2, 0xc0, 0); 512 513 /* don't re-upload unless necessary */ 514 if (tda1004x_check_upload_ok(state) == 0) 515 return 0; 516 517 /* 518 For i2c normal work, we need to slow down the bus speed. 519 However, the slow down breaks the eeprom firmware load. 520 So, use normal speed for eeprom booting and then restore the 521 i2c speed after that. Tested with MSI TV @nyware A/D board, 522 that comes with firmware version 29 inside their eeprom. 523 524 It should also be noticed that no other I2C transfer should 525 be in course while booting from eeprom, otherwise, tda10046 526 goes into an instable state. So, proper locking are needed 527 at the i2c bus master. 528 */ 529 printk(KERN_INFO "tda1004x: trying to boot from eeprom\n"); 530 tda1004x_write_byteI(state, TDA1004X_CONFC4, 4); 531 msleep(300); 532 tda1004x_write_byteI(state, TDA1004X_CONFC4, confc4); 533 534 /* Checks if eeprom firmware went without troubles */ 535 if (tda1004x_check_upload_ok(state) == 0) 536 return 0; 537 538 /* eeprom firmware didn't work. Load one manually. */ 539 540 if (state->config->request_firmware != NULL) { 541 /* request the firmware, this will block until someone uploads it */ 542 printk(KERN_INFO "tda1004x: waiting for firmware upload...\n"); 543 ret = state->config->request_firmware(fe, &fw, TDA10046_DEFAULT_FIRMWARE); 544 if (ret) { 545 /* remain compatible to old bug: try to load with tda10045 image name */ 546 ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE); 547 if (ret) { 548 printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n"); 549 return ret; 550 } else { 551 printk(KERN_INFO "tda1004x: please rename the firmware file to %s\n", 552 TDA10046_DEFAULT_FIRMWARE); 553 } 554 } 555 } else { 556 printk(KERN_ERR "tda1004x: no request function defined, can't upload from file\n"); 557 return -EIO; 558 } 559 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST 560 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN); 561 release_firmware(fw); 562 return tda1004x_check_upload_ok(state); 563 } 564 565 static int tda1004x_encode_fec(int fec) 566 { 567 // convert known FEC values 568 switch (fec) { 569 case FEC_1_2: 570 return 0; 571 case FEC_2_3: 572 return 1; 573 case FEC_3_4: 574 return 2; 575 case FEC_5_6: 576 return 3; 577 case FEC_7_8: 578 return 4; 579 } 580 581 // unsupported 582 return -EINVAL; 583 } 584 585 static int tda1004x_decode_fec(int tdafec) 586 { 587 // convert known FEC values 588 switch (tdafec) { 589 case 0: 590 return FEC_1_2; 591 case 1: 592 return FEC_2_3; 593 case 2: 594 return FEC_3_4; 595 case 3: 596 return FEC_5_6; 597 case 4: 598 return FEC_7_8; 599 } 600 601 // unsupported 602 return -1; 603 } 604 605 static int tda1004x_write(struct dvb_frontend* fe, const u8 buf[], int len) 606 { 607 struct tda1004x_state* state = fe->demodulator_priv; 608 609 if (len != 2) 610 return -EINVAL; 611 612 return tda1004x_write_byteI(state, buf[0], buf[1]); 613 } 614 615 static int tda10045_init(struct dvb_frontend* fe) 616 { 617 struct tda1004x_state* state = fe->demodulator_priv; 618 619 dprintk("%s\n", __func__); 620 621 if (tda10045_fwupload(fe)) { 622 printk("tda1004x: firmware upload failed\n"); 623 return -EIO; 624 } 625 626 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC 627 628 // tda setup 629 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer 630 tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream 631 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0); // set polarity of VAGC signal 632 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer 633 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset 634 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset 635 tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface 636 tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface 637 tda1004x_write_mask(state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits 638 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity 639 tda1004x_write_byteI(state, TDA1004X_CONFADC1, 0x2e); 640 641 tda1004x_write_mask(state, 0x1f, 0x01, state->config->invert_oclk); 642 643 return 0; 644 } 645 646 static int tda10046_init(struct dvb_frontend* fe) 647 { 648 struct tda1004x_state* state = fe->demodulator_priv; 649 dprintk("%s\n", __func__); 650 651 if (tda10046_fwupload(fe)) { 652 printk("tda1004x: firmware upload failed\n"); 653 return -EIO; 654 } 655 656 // tda setup 657 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer 658 tda1004x_write_byteI(state, TDA1004X_AUTO, 0x87); // 100 ppm crystal, select HP stream 659 tda1004x_write_byteI(state, TDA1004X_CONFC1, 0x88); // enable pulse killer 660 661 switch (state->config->agc_config) { 662 case TDA10046_AGC_DEFAULT: 663 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x00); // AGC setup 664 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities 665 break; 666 case TDA10046_AGC_IFO_AUTO_NEG: 667 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup 668 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities 669 break; 670 case TDA10046_AGC_IFO_AUTO_POS: 671 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup 672 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x00); // set AGC polarities 673 break; 674 case TDA10046_AGC_TDA827X: 675 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02); // AGC setup 676 tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70); // AGC Threshold 677 tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x08); // Gain Renormalize 678 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities 679 break; 680 } 681 if (state->config->ts_mode == 0) { 682 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x40); 683 tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7); 684 } else { 685 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x80); 686 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x10, 687 state->config->invert_oclk << 4); 688 } 689 tda1004x_write_byteI(state, TDA1004X_CONFADC2, 0x38); 690 tda1004x_write_mask (state, TDA10046H_CONF_TRISTATE1, 0x3e, 0x38); // Turn IF AGC output on 691 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0); // } 692 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values 693 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0); // } 694 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff); // } 695 tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 0x12); // IF gain 2, TUN gain 1 696 tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, 0x1a); // 10^6 VBER measurement bits 697 tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config 698 tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config 699 // tda1004x_write_mask(state, 0x50, 0x80, 0x80); // handle out of guard echoes 700 701 return 0; 702 } 703 704 static int tda1004x_set_fe(struct dvb_frontend *fe) 705 { 706 struct dtv_frontend_properties *fe_params = &fe->dtv_property_cache; 707 struct tda1004x_state* state = fe->demodulator_priv; 708 int tmp; 709 int inversion; 710 711 dprintk("%s\n", __func__); 712 713 if (state->demod_type == TDA1004X_DEMOD_TDA10046) { 714 // setup auto offset 715 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); 716 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x80, 0); 717 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0); 718 719 // disable agc_conf[2] 720 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 0); 721 } 722 723 // set frequency 724 if (fe->ops.tuner_ops.set_params) { 725 fe->ops.tuner_ops.set_params(fe); 726 if (fe->ops.i2c_gate_ctrl) 727 fe->ops.i2c_gate_ctrl(fe, 0); 728 } 729 730 // Hardcoded to use auto as much as possible on the TDA10045 as it 731 // is very unreliable if AUTO mode is _not_ used. 732 if (state->demod_type == TDA1004X_DEMOD_TDA10045) { 733 fe_params->code_rate_HP = FEC_AUTO; 734 fe_params->guard_interval = GUARD_INTERVAL_AUTO; 735 fe_params->transmission_mode = TRANSMISSION_MODE_AUTO; 736 } 737 738 // Set standard params.. or put them to auto 739 if ((fe_params->code_rate_HP == FEC_AUTO) || 740 (fe_params->code_rate_LP == FEC_AUTO) || 741 (fe_params->modulation == QAM_AUTO) || 742 (fe_params->hierarchy == HIERARCHY_AUTO)) { 743 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1); // enable auto 744 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); /* turn off modulation bits */ 745 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits 746 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits 747 } else { 748 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0); // disable auto 749 750 // set HP FEC 751 tmp = tda1004x_encode_fec(fe_params->code_rate_HP); 752 if (tmp < 0) 753 return tmp; 754 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp); 755 756 // set LP FEC 757 tmp = tda1004x_encode_fec(fe_params->code_rate_LP); 758 if (tmp < 0) 759 return tmp; 760 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3); 761 762 /* set modulation */ 763 switch (fe_params->modulation) { 764 case QPSK: 765 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0); 766 break; 767 768 case QAM_16: 769 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 1); 770 break; 771 772 case QAM_64: 773 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 2); 774 break; 775 776 default: 777 return -EINVAL; 778 } 779 780 // set hierarchy 781 switch (fe_params->hierarchy) { 782 case HIERARCHY_NONE: 783 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5); 784 break; 785 786 case HIERARCHY_1: 787 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 1 << 5); 788 break; 789 790 case HIERARCHY_2: 791 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 2 << 5); 792 break; 793 794 case HIERARCHY_4: 795 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 3 << 5); 796 break; 797 798 default: 799 return -EINVAL; 800 } 801 } 802 803 // set bandwidth 804 switch (state->demod_type) { 805 case TDA1004X_DEMOD_TDA10045: 806 tda10045h_set_bandwidth(state, fe_params->bandwidth_hz); 807 break; 808 809 case TDA1004X_DEMOD_TDA10046: 810 tda10046h_set_bandwidth(state, fe_params->bandwidth_hz); 811 break; 812 } 813 814 // set inversion 815 inversion = fe_params->inversion; 816 if (state->config->invert) 817 inversion = inversion ? INVERSION_OFF : INVERSION_ON; 818 switch (inversion) { 819 case INVERSION_OFF: 820 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0); 821 break; 822 823 case INVERSION_ON: 824 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0x20); 825 break; 826 827 default: 828 return -EINVAL; 829 } 830 831 // set guard interval 832 switch (fe_params->guard_interval) { 833 case GUARD_INTERVAL_1_32: 834 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); 835 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2); 836 break; 837 838 case GUARD_INTERVAL_1_16: 839 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); 840 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 1 << 2); 841 break; 842 843 case GUARD_INTERVAL_1_8: 844 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); 845 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 2 << 2); 846 break; 847 848 case GUARD_INTERVAL_1_4: 849 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); 850 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 3 << 2); 851 break; 852 853 case GUARD_INTERVAL_AUTO: 854 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 2); 855 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2); 856 break; 857 858 default: 859 return -EINVAL; 860 } 861 862 // set transmission mode 863 switch (fe_params->transmission_mode) { 864 case TRANSMISSION_MODE_2K: 865 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0); 866 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4); 867 break; 868 869 case TRANSMISSION_MODE_8K: 870 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0); 871 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 1 << 4); 872 break; 873 874 case TRANSMISSION_MODE_AUTO: 875 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 4); 876 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0); 877 break; 878 879 default: 880 return -EINVAL; 881 } 882 883 // start the lock 884 switch (state->demod_type) { 885 case TDA1004X_DEMOD_TDA10045: 886 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); 887 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0); 888 break; 889 890 case TDA1004X_DEMOD_TDA10046: 891 tda1004x_write_mask(state, TDA1004X_AUTO, 0x40, 0x40); 892 msleep(1); 893 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 1); 894 break; 895 } 896 897 msleep(10); 898 899 return 0; 900 } 901 902 static int tda1004x_get_fe(struct dvb_frontend *fe) 903 { 904 struct dtv_frontend_properties *fe_params = &fe->dtv_property_cache; 905 struct tda1004x_state* state = fe->demodulator_priv; 906 907 dprintk("%s\n", __func__); 908 909 // inversion status 910 fe_params->inversion = INVERSION_OFF; 911 if (tda1004x_read_byte(state, TDA1004X_CONFC1) & 0x20) 912 fe_params->inversion = INVERSION_ON; 913 if (state->config->invert) 914 fe_params->inversion = fe_params->inversion ? INVERSION_OFF : INVERSION_ON; 915 916 // bandwidth 917 switch (state->demod_type) { 918 case TDA1004X_DEMOD_TDA10045: 919 switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) { 920 case 0x14: 921 fe_params->bandwidth_hz = 8000000; 922 break; 923 case 0xdb: 924 fe_params->bandwidth_hz = 7000000; 925 break; 926 case 0x4f: 927 fe_params->bandwidth_hz = 6000000; 928 break; 929 } 930 break; 931 case TDA1004X_DEMOD_TDA10046: 932 switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) { 933 case 0x5c: 934 case 0x54: 935 fe_params->bandwidth_hz = 8000000; 936 break; 937 case 0x6a: 938 case 0x60: 939 fe_params->bandwidth_hz = 7000000; 940 break; 941 case 0x7b: 942 case 0x70: 943 fe_params->bandwidth_hz = 6000000; 944 break; 945 } 946 break; 947 } 948 949 // FEC 950 fe_params->code_rate_HP = 951 tda1004x_decode_fec(tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7); 952 fe_params->code_rate_LP = 953 tda1004x_decode_fec((tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7); 954 955 /* modulation */ 956 switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) { 957 case 0: 958 fe_params->modulation = QPSK; 959 break; 960 case 1: 961 fe_params->modulation = QAM_16; 962 break; 963 case 2: 964 fe_params->modulation = QAM_64; 965 break; 966 } 967 968 // transmission mode 969 fe_params->transmission_mode = TRANSMISSION_MODE_2K; 970 if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10) 971 fe_params->transmission_mode = TRANSMISSION_MODE_8K; 972 973 // guard interval 974 switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) { 975 case 0: 976 fe_params->guard_interval = GUARD_INTERVAL_1_32; 977 break; 978 case 1: 979 fe_params->guard_interval = GUARD_INTERVAL_1_16; 980 break; 981 case 2: 982 fe_params->guard_interval = GUARD_INTERVAL_1_8; 983 break; 984 case 3: 985 fe_params->guard_interval = GUARD_INTERVAL_1_4; 986 break; 987 } 988 989 // hierarchy 990 switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) { 991 case 0: 992 fe_params->hierarchy = HIERARCHY_NONE; 993 break; 994 case 1: 995 fe_params->hierarchy = HIERARCHY_1; 996 break; 997 case 2: 998 fe_params->hierarchy = HIERARCHY_2; 999 break; 1000 case 3: 1001 fe_params->hierarchy = HIERARCHY_4; 1002 break; 1003 } 1004 1005 return 0; 1006 } 1007 1008 static int tda1004x_read_status(struct dvb_frontend *fe, 1009 enum fe_status *fe_status) 1010 { 1011 struct tda1004x_state* state = fe->demodulator_priv; 1012 int status; 1013 int cber; 1014 int vber; 1015 1016 dprintk("%s\n", __func__); 1017 1018 // read status 1019 status = tda1004x_read_byte(state, TDA1004X_STATUS_CD); 1020 if (status == -1) 1021 return -EIO; 1022 1023 // decode 1024 *fe_status = 0; 1025 if (status & 4) 1026 *fe_status |= FE_HAS_SIGNAL; 1027 if (status & 2) 1028 *fe_status |= FE_HAS_CARRIER; 1029 if (status & 8) 1030 *fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK; 1031 1032 // if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi 1033 // is getting anything valid 1034 if (!(*fe_status & FE_HAS_VITERBI)) { 1035 // read the CBER 1036 cber = tda1004x_read_byte(state, TDA1004X_CBER_LSB); 1037 if (cber == -1) 1038 return -EIO; 1039 status = tda1004x_read_byte(state, TDA1004X_CBER_MSB); 1040 if (status == -1) 1041 return -EIO; 1042 cber |= (status << 8); 1043 // The address 0x20 should be read to cope with a TDA10046 bug 1044 tda1004x_read_byte(state, TDA1004X_CBER_RESET); 1045 1046 if (cber != 65535) 1047 *fe_status |= FE_HAS_VITERBI; 1048 } 1049 1050 // if we DO have some valid VITERBI output, but don't already have SYNC 1051 // bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid. 1052 if ((*fe_status & FE_HAS_VITERBI) && (!(*fe_status & FE_HAS_SYNC))) { 1053 // read the VBER 1054 vber = tda1004x_read_byte(state, TDA1004X_VBER_LSB); 1055 if (vber == -1) 1056 return -EIO; 1057 status = tda1004x_read_byte(state, TDA1004X_VBER_MID); 1058 if (status == -1) 1059 return -EIO; 1060 vber |= (status << 8); 1061 status = tda1004x_read_byte(state, TDA1004X_VBER_MSB); 1062 if (status == -1) 1063 return -EIO; 1064 vber |= (status & 0x0f) << 16; 1065 // The CVBER_LUT should be read to cope with TDA10046 hardware bug 1066 tda1004x_read_byte(state, TDA1004X_CVBER_LUT); 1067 1068 // if RS has passed some valid TS packets, then we must be 1069 // getting some SYNC bytes 1070 if (vber < 16632) 1071 *fe_status |= FE_HAS_SYNC; 1072 } 1073 1074 // success 1075 dprintk("%s: fe_status=0x%x\n", __func__, *fe_status); 1076 return 0; 1077 } 1078 1079 static int tda1004x_read_signal_strength(struct dvb_frontend* fe, u16 * signal) 1080 { 1081 struct tda1004x_state* state = fe->demodulator_priv; 1082 int tmp; 1083 int reg = 0; 1084 1085 dprintk("%s\n", __func__); 1086 1087 // determine the register to use 1088 switch (state->demod_type) { 1089 case TDA1004X_DEMOD_TDA10045: 1090 reg = TDA10045H_S_AGC; 1091 break; 1092 1093 case TDA1004X_DEMOD_TDA10046: 1094 reg = TDA10046H_AGC_IF_LEVEL; 1095 break; 1096 } 1097 1098 // read it 1099 tmp = tda1004x_read_byte(state, reg); 1100 if (tmp < 0) 1101 return -EIO; 1102 1103 *signal = (tmp << 8) | tmp; 1104 dprintk("%s: signal=0x%x\n", __func__, *signal); 1105 return 0; 1106 } 1107 1108 static int tda1004x_read_snr(struct dvb_frontend* fe, u16 * snr) 1109 { 1110 struct tda1004x_state* state = fe->demodulator_priv; 1111 int tmp; 1112 1113 dprintk("%s\n", __func__); 1114 1115 // read it 1116 tmp = tda1004x_read_byte(state, TDA1004X_SNR); 1117 if (tmp < 0) 1118 return -EIO; 1119 tmp = 255 - tmp; 1120 1121 *snr = ((tmp << 8) | tmp); 1122 dprintk("%s: snr=0x%x\n", __func__, *snr); 1123 return 0; 1124 } 1125 1126 static int tda1004x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks) 1127 { 1128 struct tda1004x_state* state = fe->demodulator_priv; 1129 int tmp; 1130 int tmp2; 1131 int counter; 1132 1133 dprintk("%s\n", __func__); 1134 1135 // read the UCBLOCKS and reset 1136 counter = 0; 1137 tmp = tda1004x_read_byte(state, TDA1004X_UNCOR); 1138 if (tmp < 0) 1139 return -EIO; 1140 tmp &= 0x7f; 1141 while (counter++ < 5) { 1142 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0); 1143 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0); 1144 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0); 1145 1146 tmp2 = tda1004x_read_byte(state, TDA1004X_UNCOR); 1147 if (tmp2 < 0) 1148 return -EIO; 1149 tmp2 &= 0x7f; 1150 if ((tmp2 < tmp) || (tmp2 == 0)) 1151 break; 1152 } 1153 1154 if (tmp != 0x7f) 1155 *ucblocks = tmp; 1156 else 1157 *ucblocks = 0xffffffff; 1158 1159 dprintk("%s: ucblocks=0x%x\n", __func__, *ucblocks); 1160 return 0; 1161 } 1162 1163 static int tda1004x_read_ber(struct dvb_frontend* fe, u32* ber) 1164 { 1165 struct tda1004x_state* state = fe->demodulator_priv; 1166 int tmp; 1167 1168 dprintk("%s\n", __func__); 1169 1170 // read it in 1171 tmp = tda1004x_read_byte(state, TDA1004X_CBER_LSB); 1172 if (tmp < 0) 1173 return -EIO; 1174 *ber = tmp << 1; 1175 tmp = tda1004x_read_byte(state, TDA1004X_CBER_MSB); 1176 if (tmp < 0) 1177 return -EIO; 1178 *ber |= (tmp << 9); 1179 // The address 0x20 should be read to cope with a TDA10046 bug 1180 tda1004x_read_byte(state, TDA1004X_CBER_RESET); 1181 1182 dprintk("%s: ber=0x%x\n", __func__, *ber); 1183 return 0; 1184 } 1185 1186 static int tda1004x_sleep(struct dvb_frontend* fe) 1187 { 1188 struct tda1004x_state* state = fe->demodulator_priv; 1189 int gpio_conf; 1190 1191 switch (state->demod_type) { 1192 case TDA1004X_DEMOD_TDA10045: 1193 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0x10); 1194 break; 1195 1196 case TDA1004X_DEMOD_TDA10046: 1197 /* set outputs to tristate */ 1198 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0xff); 1199 /* invert GPIO 1 and 3 if desired*/ 1200 gpio_conf = state->config->gpio_config; 1201 if (gpio_conf >= TDA10046_GP00_I) 1202 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f, 1203 (gpio_conf & 0x0f) ^ 0x0a); 1204 1205 tda1004x_write_mask(state, TDA1004X_CONFADC2, 0xc0, 0xc0); 1206 tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1); 1207 break; 1208 } 1209 1210 return 0; 1211 } 1212 1213 static int tda1004x_i2c_gate_ctrl(struct dvb_frontend* fe, int enable) 1214 { 1215 struct tda1004x_state* state = fe->demodulator_priv; 1216 1217 if (enable) { 1218 return tda1004x_enable_tuner_i2c(state); 1219 } else { 1220 return tda1004x_disable_tuner_i2c(state); 1221 } 1222 } 1223 1224 static int tda1004x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings) 1225 { 1226 fesettings->min_delay_ms = 800; 1227 /* Drift compensation makes no sense for DVB-T */ 1228 fesettings->step_size = 0; 1229 fesettings->max_drift = 0; 1230 return 0; 1231 } 1232 1233 static void tda1004x_release(struct dvb_frontend* fe) 1234 { 1235 struct tda1004x_state *state = fe->demodulator_priv; 1236 kfree(state); 1237 } 1238 1239 static struct dvb_frontend_ops tda10045_ops = { 1240 .delsys = { SYS_DVBT }, 1241 .info = { 1242 .name = "Philips TDA10045H DVB-T", 1243 .frequency_min = 51000000, 1244 .frequency_max = 858000000, 1245 .frequency_stepsize = 166667, 1246 .caps = 1247 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 1248 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 1249 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | 1250 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO 1251 }, 1252 1253 .release = tda1004x_release, 1254 1255 .init = tda10045_init, 1256 .sleep = tda1004x_sleep, 1257 .write = tda1004x_write, 1258 .i2c_gate_ctrl = tda1004x_i2c_gate_ctrl, 1259 1260 .set_frontend = tda1004x_set_fe, 1261 .get_frontend = tda1004x_get_fe, 1262 .get_tune_settings = tda1004x_get_tune_settings, 1263 1264 .read_status = tda1004x_read_status, 1265 .read_ber = tda1004x_read_ber, 1266 .read_signal_strength = tda1004x_read_signal_strength, 1267 .read_snr = tda1004x_read_snr, 1268 .read_ucblocks = tda1004x_read_ucblocks, 1269 }; 1270 1271 struct dvb_frontend* tda10045_attach(const struct tda1004x_config* config, 1272 struct i2c_adapter* i2c) 1273 { 1274 struct tda1004x_state *state; 1275 int id; 1276 1277 /* allocate memory for the internal state */ 1278 state = kzalloc(sizeof(struct tda1004x_state), GFP_KERNEL); 1279 if (!state) { 1280 printk(KERN_ERR "Can't allocate memory for tda10045 state\n"); 1281 return NULL; 1282 } 1283 1284 /* setup the state */ 1285 state->config = config; 1286 state->i2c = i2c; 1287 state->demod_type = TDA1004X_DEMOD_TDA10045; 1288 1289 /* check if the demod is there */ 1290 id = tda1004x_read_byte(state, TDA1004X_CHIPID); 1291 if (id < 0) { 1292 printk(KERN_ERR "tda10045: chip is not answering. Giving up.\n"); 1293 kfree(state); 1294 return NULL; 1295 } 1296 1297 if (id != 0x25) { 1298 printk(KERN_ERR "Invalid tda1004x ID = 0x%02x. Can't proceed\n", id); 1299 kfree(state); 1300 return NULL; 1301 } 1302 1303 /* create dvb_frontend */ 1304 memcpy(&state->frontend.ops, &tda10045_ops, sizeof(struct dvb_frontend_ops)); 1305 state->frontend.demodulator_priv = state; 1306 return &state->frontend; 1307 } 1308 1309 static struct dvb_frontend_ops tda10046_ops = { 1310 .delsys = { SYS_DVBT }, 1311 .info = { 1312 .name = "Philips TDA10046H DVB-T", 1313 .frequency_min = 51000000, 1314 .frequency_max = 858000000, 1315 .frequency_stepsize = 166667, 1316 .caps = 1317 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 1318 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 1319 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | 1320 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO 1321 }, 1322 1323 .release = tda1004x_release, 1324 1325 .init = tda10046_init, 1326 .sleep = tda1004x_sleep, 1327 .write = tda1004x_write, 1328 .i2c_gate_ctrl = tda1004x_i2c_gate_ctrl, 1329 1330 .set_frontend = tda1004x_set_fe, 1331 .get_frontend = tda1004x_get_fe, 1332 .get_tune_settings = tda1004x_get_tune_settings, 1333 1334 .read_status = tda1004x_read_status, 1335 .read_ber = tda1004x_read_ber, 1336 .read_signal_strength = tda1004x_read_signal_strength, 1337 .read_snr = tda1004x_read_snr, 1338 .read_ucblocks = tda1004x_read_ucblocks, 1339 }; 1340 1341 struct dvb_frontend* tda10046_attach(const struct tda1004x_config* config, 1342 struct i2c_adapter* i2c) 1343 { 1344 struct tda1004x_state *state; 1345 int id; 1346 1347 /* allocate memory for the internal state */ 1348 state = kzalloc(sizeof(struct tda1004x_state), GFP_KERNEL); 1349 if (!state) { 1350 printk(KERN_ERR "Can't allocate memory for tda10046 state\n"); 1351 return NULL; 1352 } 1353 1354 /* setup the state */ 1355 state->config = config; 1356 state->i2c = i2c; 1357 state->demod_type = TDA1004X_DEMOD_TDA10046; 1358 1359 /* check if the demod is there */ 1360 id = tda1004x_read_byte(state, TDA1004X_CHIPID); 1361 if (id < 0) { 1362 printk(KERN_ERR "tda10046: chip is not answering. Giving up.\n"); 1363 kfree(state); 1364 return NULL; 1365 } 1366 if (id != 0x46) { 1367 printk(KERN_ERR "Invalid tda1004x ID = 0x%02x. Can't proceed\n", id); 1368 kfree(state); 1369 return NULL; 1370 } 1371 1372 /* create dvb_frontend */ 1373 memcpy(&state->frontend.ops, &tda10046_ops, sizeof(struct dvb_frontend_ops)); 1374 state->frontend.demodulator_priv = state; 1375 return &state->frontend; 1376 } 1377 1378 module_param(debug, int, 0644); 1379 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); 1380 1381 MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Demodulator"); 1382 MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach"); 1383 MODULE_LICENSE("GPL"); 1384 1385 EXPORT_SYMBOL(tda10045_attach); 1386 EXPORT_SYMBOL(tda10046_attach); 1387