1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 STV0900/0903 Multistandard Broadcast Frontend driver 4 Copyright (C) Manu Abraham <abraham.manu@gmail.com> 5 6 Copyright (C) ST Microelectronics 7 8 */ 9 10 #include <linux/init.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/string.h> 14 #include <linux/slab.h> 15 #include <linux/mutex.h> 16 17 #include <linux/dvb/frontend.h> 18 #include <media/dvb_frontend.h> 19 20 #include "stv6110x.h" /* for demodulator internal modes */ 21 22 #include "stv090x_reg.h" 23 #include "stv090x.h" 24 #include "stv090x_priv.h" 25 26 /* Max transfer size done by I2C transfer functions */ 27 #define MAX_XFER_SIZE 64 28 29 static unsigned int verbose; 30 module_param(verbose, int, 0644); 31 32 /* internal params node */ 33 struct stv090x_dev { 34 /* pointer for internal params, one for each pair of demods */ 35 struct stv090x_internal *internal; 36 struct stv090x_dev *next_dev; 37 }; 38 39 /* first internal params */ 40 static struct stv090x_dev *stv090x_first_dev; 41 42 /* find chip by i2c adapter and i2c address */ 43 static struct stv090x_dev *find_dev(struct i2c_adapter *i2c_adap, 44 u8 i2c_addr) 45 { 46 struct stv090x_dev *temp_dev = stv090x_first_dev; 47 48 /* 49 Search of the last stv0900 chip or 50 find it by i2c adapter and i2c address */ 51 while ((temp_dev != NULL) && 52 ((temp_dev->internal->i2c_adap != i2c_adap) || 53 (temp_dev->internal->i2c_addr != i2c_addr))) { 54 55 temp_dev = temp_dev->next_dev; 56 } 57 58 return temp_dev; 59 } 60 61 /* deallocating chip */ 62 static void remove_dev(struct stv090x_internal *internal) 63 { 64 struct stv090x_dev *prev_dev = stv090x_first_dev; 65 struct stv090x_dev *del_dev = find_dev(internal->i2c_adap, 66 internal->i2c_addr); 67 68 if (del_dev != NULL) { 69 if (del_dev == stv090x_first_dev) { 70 stv090x_first_dev = del_dev->next_dev; 71 } else { 72 while (prev_dev->next_dev != del_dev) 73 prev_dev = prev_dev->next_dev; 74 75 prev_dev->next_dev = del_dev->next_dev; 76 } 77 78 kfree(del_dev); 79 } 80 } 81 82 /* allocating new chip */ 83 static struct stv090x_dev *append_internal(struct stv090x_internal *internal) 84 { 85 struct stv090x_dev *new_dev; 86 struct stv090x_dev *temp_dev; 87 88 new_dev = kmalloc(sizeof(struct stv090x_dev), GFP_KERNEL); 89 if (new_dev != NULL) { 90 new_dev->internal = internal; 91 new_dev->next_dev = NULL; 92 93 /* append to list */ 94 if (stv090x_first_dev == NULL) { 95 stv090x_first_dev = new_dev; 96 } else { 97 temp_dev = stv090x_first_dev; 98 while (temp_dev->next_dev != NULL) 99 temp_dev = temp_dev->next_dev; 100 101 temp_dev->next_dev = new_dev; 102 } 103 } 104 105 return new_dev; 106 } 107 108 109 /* DVBS1 and DSS C/N Lookup table */ 110 static const struct stv090x_tab stv090x_s1cn_tab[] = { 111 { 0, 8917 }, /* 0.0dB */ 112 { 5, 8801 }, /* 0.5dB */ 113 { 10, 8667 }, /* 1.0dB */ 114 { 15, 8522 }, /* 1.5dB */ 115 { 20, 8355 }, /* 2.0dB */ 116 { 25, 8175 }, /* 2.5dB */ 117 { 30, 7979 }, /* 3.0dB */ 118 { 35, 7763 }, /* 3.5dB */ 119 { 40, 7530 }, /* 4.0dB */ 120 { 45, 7282 }, /* 4.5dB */ 121 { 50, 7026 }, /* 5.0dB */ 122 { 55, 6781 }, /* 5.5dB */ 123 { 60, 6514 }, /* 6.0dB */ 124 { 65, 6241 }, /* 6.5dB */ 125 { 70, 5965 }, /* 7.0dB */ 126 { 75, 5690 }, /* 7.5dB */ 127 { 80, 5424 }, /* 8.0dB */ 128 { 85, 5161 }, /* 8.5dB */ 129 { 90, 4902 }, /* 9.0dB */ 130 { 95, 4654 }, /* 9.5dB */ 131 { 100, 4417 }, /* 10.0dB */ 132 { 105, 4186 }, /* 10.5dB */ 133 { 110, 3968 }, /* 11.0dB */ 134 { 115, 3757 }, /* 11.5dB */ 135 { 120, 3558 }, /* 12.0dB */ 136 { 125, 3366 }, /* 12.5dB */ 137 { 130, 3185 }, /* 13.0dB */ 138 { 135, 3012 }, /* 13.5dB */ 139 { 140, 2850 }, /* 14.0dB */ 140 { 145, 2698 }, /* 14.5dB */ 141 { 150, 2550 }, /* 15.0dB */ 142 { 160, 2283 }, /* 16.0dB */ 143 { 170, 2042 }, /* 17.0dB */ 144 { 180, 1827 }, /* 18.0dB */ 145 { 190, 1636 }, /* 19.0dB */ 146 { 200, 1466 }, /* 20.0dB */ 147 { 210, 1315 }, /* 21.0dB */ 148 { 220, 1181 }, /* 22.0dB */ 149 { 230, 1064 }, /* 23.0dB */ 150 { 240, 960 }, /* 24.0dB */ 151 { 250, 869 }, /* 25.0dB */ 152 { 260, 792 }, /* 26.0dB */ 153 { 270, 724 }, /* 27.0dB */ 154 { 280, 665 }, /* 28.0dB */ 155 { 290, 616 }, /* 29.0dB */ 156 { 300, 573 }, /* 30.0dB */ 157 { 310, 537 }, /* 31.0dB */ 158 { 320, 507 }, /* 32.0dB */ 159 { 330, 483 }, /* 33.0dB */ 160 { 400, 398 }, /* 40.0dB */ 161 { 450, 381 }, /* 45.0dB */ 162 { 500, 377 } /* 50.0dB */ 163 }; 164 165 /* DVBS2 C/N Lookup table */ 166 static const struct stv090x_tab stv090x_s2cn_tab[] = { 167 { -30, 13348 }, /* -3.0dB */ 168 { -20, 12640 }, /* -2d.0B */ 169 { -10, 11883 }, /* -1.0dB */ 170 { 0, 11101 }, /* -0.0dB */ 171 { 5, 10718 }, /* 0.5dB */ 172 { 10, 10339 }, /* 1.0dB */ 173 { 15, 9947 }, /* 1.5dB */ 174 { 20, 9552 }, /* 2.0dB */ 175 { 25, 9183 }, /* 2.5dB */ 176 { 30, 8799 }, /* 3.0dB */ 177 { 35, 8422 }, /* 3.5dB */ 178 { 40, 8062 }, /* 4.0dB */ 179 { 45, 7707 }, /* 4.5dB */ 180 { 50, 7353 }, /* 5.0dB */ 181 { 55, 7025 }, /* 5.5dB */ 182 { 60, 6684 }, /* 6.0dB */ 183 { 65, 6331 }, /* 6.5dB */ 184 { 70, 6036 }, /* 7.0dB */ 185 { 75, 5727 }, /* 7.5dB */ 186 { 80, 5437 }, /* 8.0dB */ 187 { 85, 5164 }, /* 8.5dB */ 188 { 90, 4902 }, /* 9.0dB */ 189 { 95, 4653 }, /* 9.5dB */ 190 { 100, 4408 }, /* 10.0dB */ 191 { 105, 4187 }, /* 10.5dB */ 192 { 110, 3961 }, /* 11.0dB */ 193 { 115, 3751 }, /* 11.5dB */ 194 { 120, 3558 }, /* 12.0dB */ 195 { 125, 3368 }, /* 12.5dB */ 196 { 130, 3191 }, /* 13.0dB */ 197 { 135, 3017 }, /* 13.5dB */ 198 { 140, 2862 }, /* 14.0dB */ 199 { 145, 2710 }, /* 14.5dB */ 200 { 150, 2565 }, /* 15.0dB */ 201 { 160, 2300 }, /* 16.0dB */ 202 { 170, 2058 }, /* 17.0dB */ 203 { 180, 1849 }, /* 18.0dB */ 204 { 190, 1663 }, /* 19.0dB */ 205 { 200, 1495 }, /* 20.0dB */ 206 { 210, 1349 }, /* 21.0dB */ 207 { 220, 1222 }, /* 22.0dB */ 208 { 230, 1110 }, /* 23.0dB */ 209 { 240, 1011 }, /* 24.0dB */ 210 { 250, 925 }, /* 25.0dB */ 211 { 260, 853 }, /* 26.0dB */ 212 { 270, 789 }, /* 27.0dB */ 213 { 280, 734 }, /* 28.0dB */ 214 { 290, 690 }, /* 29.0dB */ 215 { 300, 650 }, /* 30.0dB */ 216 { 310, 619 }, /* 31.0dB */ 217 { 320, 593 }, /* 32.0dB */ 218 { 330, 571 }, /* 33.0dB */ 219 { 400, 498 }, /* 40.0dB */ 220 { 450, 484 }, /* 45.0dB */ 221 { 500, 481 } /* 50.0dB */ 222 }; 223 224 /* RF level C/N lookup table */ 225 static const struct stv090x_tab stv090x_rf_tab[] = { 226 { -5, 0xcaa1 }, /* -5dBm */ 227 { -10, 0xc229 }, /* -10dBm */ 228 { -15, 0xbb08 }, /* -15dBm */ 229 { -20, 0xb4bc }, /* -20dBm */ 230 { -25, 0xad5a }, /* -25dBm */ 231 { -30, 0xa298 }, /* -30dBm */ 232 { -35, 0x98a8 }, /* -35dBm */ 233 { -40, 0x8389 }, /* -40dBm */ 234 { -45, 0x59be }, /* -45dBm */ 235 { -50, 0x3a14 }, /* -50dBm */ 236 { -55, 0x2d11 }, /* -55dBm */ 237 { -60, 0x210d }, /* -60dBm */ 238 { -65, 0xa14f }, /* -65dBm */ 239 { -70, 0x07aa } /* -70dBm */ 240 }; 241 242 243 static struct stv090x_reg stv0900_initval[] = { 244 245 { STV090x_OUTCFG, 0x00 }, 246 { STV090x_MODECFG, 0xff }, 247 { STV090x_AGCRF1CFG, 0x11 }, 248 { STV090x_AGCRF2CFG, 0x13 }, 249 { STV090x_TSGENERAL1X, 0x14 }, 250 { STV090x_TSTTNR2, 0x21 }, 251 { STV090x_TSTTNR4, 0x21 }, 252 { STV090x_P2_DISTXCTL, 0x22 }, 253 { STV090x_P2_F22TX, 0xc0 }, 254 { STV090x_P2_F22RX, 0xc0 }, 255 { STV090x_P2_DISRXCTL, 0x00 }, 256 { STV090x_P2_DMDCFGMD, 0xF9 }, 257 { STV090x_P2_DEMOD, 0x08 }, 258 { STV090x_P2_DMDCFG3, 0xc4 }, 259 { STV090x_P2_CARFREQ, 0xed }, 260 { STV090x_P2_LDT, 0xd0 }, 261 { STV090x_P2_LDT2, 0xb8 }, 262 { STV090x_P2_TMGCFG, 0xd2 }, 263 { STV090x_P2_TMGTHRISE, 0x20 }, 264 { STV090x_P1_TMGCFG, 0xd2 }, 265 266 { STV090x_P2_TMGTHFALL, 0x00 }, 267 { STV090x_P2_FECSPY, 0x88 }, 268 { STV090x_P2_FSPYDATA, 0x3a }, 269 { STV090x_P2_FBERCPT4, 0x00 }, 270 { STV090x_P2_FSPYBER, 0x10 }, 271 { STV090x_P2_ERRCTRL1, 0x35 }, 272 { STV090x_P2_ERRCTRL2, 0xc1 }, 273 { STV090x_P2_CFRICFG, 0xf8 }, 274 { STV090x_P2_NOSCFG, 0x1c }, 275 { STV090x_P2_DMDTOM, 0x20 }, 276 { STV090x_P2_CORRELMANT, 0x70 }, 277 { STV090x_P2_CORRELABS, 0x88 }, 278 { STV090x_P2_AGC2O, 0x5b }, 279 { STV090x_P2_AGC2REF, 0x38 }, 280 { STV090x_P2_CARCFG, 0xe4 }, 281 { STV090x_P2_ACLC, 0x1A }, 282 { STV090x_P2_BCLC, 0x09 }, 283 { STV090x_P2_CARHDR, 0x08 }, 284 { STV090x_P2_KREFTMG, 0xc1 }, 285 { STV090x_P2_SFRUPRATIO, 0xf0 }, 286 { STV090x_P2_SFRLOWRATIO, 0x70 }, 287 { STV090x_P2_SFRSTEP, 0x58 }, 288 { STV090x_P2_TMGCFG2, 0x01 }, 289 { STV090x_P2_CAR2CFG, 0x26 }, 290 { STV090x_P2_BCLC2S2Q, 0x86 }, 291 { STV090x_P2_BCLC2S28, 0x86 }, 292 { STV090x_P2_SMAPCOEF7, 0x77 }, 293 { STV090x_P2_SMAPCOEF6, 0x85 }, 294 { STV090x_P2_SMAPCOEF5, 0x77 }, 295 { STV090x_P2_TSCFGL, 0x20 }, 296 { STV090x_P2_DMDCFG2, 0x3b }, 297 { STV090x_P2_MODCODLST0, 0xff }, 298 { STV090x_P2_MODCODLST1, 0xff }, 299 { STV090x_P2_MODCODLST2, 0xff }, 300 { STV090x_P2_MODCODLST3, 0xff }, 301 { STV090x_P2_MODCODLST4, 0xff }, 302 { STV090x_P2_MODCODLST5, 0xff }, 303 { STV090x_P2_MODCODLST6, 0xff }, 304 { STV090x_P2_MODCODLST7, 0xcc }, 305 { STV090x_P2_MODCODLST8, 0xcc }, 306 { STV090x_P2_MODCODLST9, 0xcc }, 307 { STV090x_P2_MODCODLSTA, 0xcc }, 308 { STV090x_P2_MODCODLSTB, 0xcc }, 309 { STV090x_P2_MODCODLSTC, 0xcc }, 310 { STV090x_P2_MODCODLSTD, 0xcc }, 311 { STV090x_P2_MODCODLSTE, 0xcc }, 312 { STV090x_P2_MODCODLSTF, 0xcf }, 313 { STV090x_P1_DISTXCTL, 0x22 }, 314 { STV090x_P1_F22TX, 0xc0 }, 315 { STV090x_P1_F22RX, 0xc0 }, 316 { STV090x_P1_DISRXCTL, 0x00 }, 317 { STV090x_P1_DMDCFGMD, 0xf9 }, 318 { STV090x_P1_DEMOD, 0x08 }, 319 { STV090x_P1_DMDCFG3, 0xc4 }, 320 { STV090x_P1_DMDTOM, 0x20 }, 321 { STV090x_P1_CARFREQ, 0xed }, 322 { STV090x_P1_LDT, 0xd0 }, 323 { STV090x_P1_LDT2, 0xb8 }, 324 { STV090x_P1_TMGCFG, 0xd2 }, 325 { STV090x_P1_TMGTHRISE, 0x20 }, 326 { STV090x_P1_TMGTHFALL, 0x00 }, 327 { STV090x_P1_SFRUPRATIO, 0xf0 }, 328 { STV090x_P1_SFRLOWRATIO, 0x70 }, 329 { STV090x_P1_TSCFGL, 0x20 }, 330 { STV090x_P1_FECSPY, 0x88 }, 331 { STV090x_P1_FSPYDATA, 0x3a }, 332 { STV090x_P1_FBERCPT4, 0x00 }, 333 { STV090x_P1_FSPYBER, 0x10 }, 334 { STV090x_P1_ERRCTRL1, 0x35 }, 335 { STV090x_P1_ERRCTRL2, 0xc1 }, 336 { STV090x_P1_CFRICFG, 0xf8 }, 337 { STV090x_P1_NOSCFG, 0x1c }, 338 { STV090x_P1_CORRELMANT, 0x70 }, 339 { STV090x_P1_CORRELABS, 0x88 }, 340 { STV090x_P1_AGC2O, 0x5b }, 341 { STV090x_P1_AGC2REF, 0x38 }, 342 { STV090x_P1_CARCFG, 0xe4 }, 343 { STV090x_P1_ACLC, 0x1A }, 344 { STV090x_P1_BCLC, 0x09 }, 345 { STV090x_P1_CARHDR, 0x08 }, 346 { STV090x_P1_KREFTMG, 0xc1 }, 347 { STV090x_P1_SFRSTEP, 0x58 }, 348 { STV090x_P1_TMGCFG2, 0x01 }, 349 { STV090x_P1_CAR2CFG, 0x26 }, 350 { STV090x_P1_BCLC2S2Q, 0x86 }, 351 { STV090x_P1_BCLC2S28, 0x86 }, 352 { STV090x_P1_SMAPCOEF7, 0x77 }, 353 { STV090x_P1_SMAPCOEF6, 0x85 }, 354 { STV090x_P1_SMAPCOEF5, 0x77 }, 355 { STV090x_P1_DMDCFG2, 0x3b }, 356 { STV090x_P1_MODCODLST0, 0xff }, 357 { STV090x_P1_MODCODLST1, 0xff }, 358 { STV090x_P1_MODCODLST2, 0xff }, 359 { STV090x_P1_MODCODLST3, 0xff }, 360 { STV090x_P1_MODCODLST4, 0xff }, 361 { STV090x_P1_MODCODLST5, 0xff }, 362 { STV090x_P1_MODCODLST6, 0xff }, 363 { STV090x_P1_MODCODLST7, 0xcc }, 364 { STV090x_P1_MODCODLST8, 0xcc }, 365 { STV090x_P1_MODCODLST9, 0xcc }, 366 { STV090x_P1_MODCODLSTA, 0xcc }, 367 { STV090x_P1_MODCODLSTB, 0xcc }, 368 { STV090x_P1_MODCODLSTC, 0xcc }, 369 { STV090x_P1_MODCODLSTD, 0xcc }, 370 { STV090x_P1_MODCODLSTE, 0xcc }, 371 { STV090x_P1_MODCODLSTF, 0xcf }, 372 { STV090x_GENCFG, 0x1d }, 373 { STV090x_NBITER_NF4, 0x37 }, 374 { STV090x_NBITER_NF5, 0x29 }, 375 { STV090x_NBITER_NF6, 0x37 }, 376 { STV090x_NBITER_NF7, 0x33 }, 377 { STV090x_NBITER_NF8, 0x31 }, 378 { STV090x_NBITER_NF9, 0x2f }, 379 { STV090x_NBITER_NF10, 0x39 }, 380 { STV090x_NBITER_NF11, 0x3a }, 381 { STV090x_NBITER_NF12, 0x29 }, 382 { STV090x_NBITER_NF13, 0x37 }, 383 { STV090x_NBITER_NF14, 0x33 }, 384 { STV090x_NBITER_NF15, 0x2f }, 385 { STV090x_NBITER_NF16, 0x39 }, 386 { STV090x_NBITER_NF17, 0x3a }, 387 { STV090x_NBITERNOERR, 0x04 }, 388 { STV090x_GAINLLR_NF4, 0x0C }, 389 { STV090x_GAINLLR_NF5, 0x0F }, 390 { STV090x_GAINLLR_NF6, 0x11 }, 391 { STV090x_GAINLLR_NF7, 0x14 }, 392 { STV090x_GAINLLR_NF8, 0x17 }, 393 { STV090x_GAINLLR_NF9, 0x19 }, 394 { STV090x_GAINLLR_NF10, 0x20 }, 395 { STV090x_GAINLLR_NF11, 0x21 }, 396 { STV090x_GAINLLR_NF12, 0x0D }, 397 { STV090x_GAINLLR_NF13, 0x0F }, 398 { STV090x_GAINLLR_NF14, 0x13 }, 399 { STV090x_GAINLLR_NF15, 0x1A }, 400 { STV090x_GAINLLR_NF16, 0x1F }, 401 { STV090x_GAINLLR_NF17, 0x21 }, 402 { STV090x_RCCFGH, 0x20 }, 403 { STV090x_P1_FECM, 0x01 }, /* disable DSS modes */ 404 { STV090x_P2_FECM, 0x01 }, /* disable DSS modes */ 405 { STV090x_P1_PRVIT, 0x2F }, /* disable PR 6/7 */ 406 { STV090x_P2_PRVIT, 0x2F }, /* disable PR 6/7 */ 407 }; 408 409 static struct stv090x_reg stv0903_initval[] = { 410 { STV090x_OUTCFG, 0x00 }, 411 { STV090x_AGCRF1CFG, 0x11 }, 412 { STV090x_STOPCLK1, 0x48 }, 413 { STV090x_STOPCLK2, 0x14 }, 414 { STV090x_TSTTNR1, 0x27 }, 415 { STV090x_TSTTNR2, 0x21 }, 416 { STV090x_P1_DISTXCTL, 0x22 }, 417 { STV090x_P1_F22TX, 0xc0 }, 418 { STV090x_P1_F22RX, 0xc0 }, 419 { STV090x_P1_DISRXCTL, 0x00 }, 420 { STV090x_P1_DMDCFGMD, 0xF9 }, 421 { STV090x_P1_DEMOD, 0x08 }, 422 { STV090x_P1_DMDCFG3, 0xc4 }, 423 { STV090x_P1_CARFREQ, 0xed }, 424 { STV090x_P1_TNRCFG2, 0x82 }, 425 { STV090x_P1_LDT, 0xd0 }, 426 { STV090x_P1_LDT2, 0xb8 }, 427 { STV090x_P1_TMGCFG, 0xd2 }, 428 { STV090x_P1_TMGTHRISE, 0x20 }, 429 { STV090x_P1_TMGTHFALL, 0x00 }, 430 { STV090x_P1_SFRUPRATIO, 0xf0 }, 431 { STV090x_P1_SFRLOWRATIO, 0x70 }, 432 { STV090x_P1_TSCFGL, 0x20 }, 433 { STV090x_P1_FECSPY, 0x88 }, 434 { STV090x_P1_FSPYDATA, 0x3a }, 435 { STV090x_P1_FBERCPT4, 0x00 }, 436 { STV090x_P1_FSPYBER, 0x10 }, 437 { STV090x_P1_ERRCTRL1, 0x35 }, 438 { STV090x_P1_ERRCTRL2, 0xc1 }, 439 { STV090x_P1_CFRICFG, 0xf8 }, 440 { STV090x_P1_NOSCFG, 0x1c }, 441 { STV090x_P1_DMDTOM, 0x20 }, 442 { STV090x_P1_CORRELMANT, 0x70 }, 443 { STV090x_P1_CORRELABS, 0x88 }, 444 { STV090x_P1_AGC2O, 0x5b }, 445 { STV090x_P1_AGC2REF, 0x38 }, 446 { STV090x_P1_CARCFG, 0xe4 }, 447 { STV090x_P1_ACLC, 0x1A }, 448 { STV090x_P1_BCLC, 0x09 }, 449 { STV090x_P1_CARHDR, 0x08 }, 450 { STV090x_P1_KREFTMG, 0xc1 }, 451 { STV090x_P1_SFRSTEP, 0x58 }, 452 { STV090x_P1_TMGCFG2, 0x01 }, 453 { STV090x_P1_CAR2CFG, 0x26 }, 454 { STV090x_P1_BCLC2S2Q, 0x86 }, 455 { STV090x_P1_BCLC2S28, 0x86 }, 456 { STV090x_P1_SMAPCOEF7, 0x77 }, 457 { STV090x_P1_SMAPCOEF6, 0x85 }, 458 { STV090x_P1_SMAPCOEF5, 0x77 }, 459 { STV090x_P1_DMDCFG2, 0x3b }, 460 { STV090x_P1_MODCODLST0, 0xff }, 461 { STV090x_P1_MODCODLST1, 0xff }, 462 { STV090x_P1_MODCODLST2, 0xff }, 463 { STV090x_P1_MODCODLST3, 0xff }, 464 { STV090x_P1_MODCODLST4, 0xff }, 465 { STV090x_P1_MODCODLST5, 0xff }, 466 { STV090x_P1_MODCODLST6, 0xff }, 467 { STV090x_P1_MODCODLST7, 0xcc }, 468 { STV090x_P1_MODCODLST8, 0xcc }, 469 { STV090x_P1_MODCODLST9, 0xcc }, 470 { STV090x_P1_MODCODLSTA, 0xcc }, 471 { STV090x_P1_MODCODLSTB, 0xcc }, 472 { STV090x_P1_MODCODLSTC, 0xcc }, 473 { STV090x_P1_MODCODLSTD, 0xcc }, 474 { STV090x_P1_MODCODLSTE, 0xcc }, 475 { STV090x_P1_MODCODLSTF, 0xcf }, 476 { STV090x_GENCFG, 0x1c }, 477 { STV090x_NBITER_NF4, 0x37 }, 478 { STV090x_NBITER_NF5, 0x29 }, 479 { STV090x_NBITER_NF6, 0x37 }, 480 { STV090x_NBITER_NF7, 0x33 }, 481 { STV090x_NBITER_NF8, 0x31 }, 482 { STV090x_NBITER_NF9, 0x2f }, 483 { STV090x_NBITER_NF10, 0x39 }, 484 { STV090x_NBITER_NF11, 0x3a }, 485 { STV090x_NBITER_NF12, 0x29 }, 486 { STV090x_NBITER_NF13, 0x37 }, 487 { STV090x_NBITER_NF14, 0x33 }, 488 { STV090x_NBITER_NF15, 0x2f }, 489 { STV090x_NBITER_NF16, 0x39 }, 490 { STV090x_NBITER_NF17, 0x3a }, 491 { STV090x_NBITERNOERR, 0x04 }, 492 { STV090x_GAINLLR_NF4, 0x0C }, 493 { STV090x_GAINLLR_NF5, 0x0F }, 494 { STV090x_GAINLLR_NF6, 0x11 }, 495 { STV090x_GAINLLR_NF7, 0x14 }, 496 { STV090x_GAINLLR_NF8, 0x17 }, 497 { STV090x_GAINLLR_NF9, 0x19 }, 498 { STV090x_GAINLLR_NF10, 0x20 }, 499 { STV090x_GAINLLR_NF11, 0x21 }, 500 { STV090x_GAINLLR_NF12, 0x0D }, 501 { STV090x_GAINLLR_NF13, 0x0F }, 502 { STV090x_GAINLLR_NF14, 0x13 }, 503 { STV090x_GAINLLR_NF15, 0x1A }, 504 { STV090x_GAINLLR_NF16, 0x1F }, 505 { STV090x_GAINLLR_NF17, 0x21 }, 506 { STV090x_RCCFGH, 0x20 }, 507 { STV090x_P1_FECM, 0x01 }, /*disable the DSS mode */ 508 { STV090x_P1_PRVIT, 0x2f } /*disable puncture rate 6/7*/ 509 }; 510 511 static struct stv090x_reg stv0900_cut20_val[] = { 512 513 { STV090x_P2_DMDCFG3, 0xe8 }, 514 { STV090x_P2_DMDCFG4, 0x10 }, 515 { STV090x_P2_CARFREQ, 0x38 }, 516 { STV090x_P2_CARHDR, 0x20 }, 517 { STV090x_P2_KREFTMG, 0x5a }, 518 { STV090x_P2_SMAPCOEF7, 0x06 }, 519 { STV090x_P2_SMAPCOEF6, 0x00 }, 520 { STV090x_P2_SMAPCOEF5, 0x04 }, 521 { STV090x_P2_NOSCFG, 0x0c }, 522 { STV090x_P1_DMDCFG3, 0xe8 }, 523 { STV090x_P1_DMDCFG4, 0x10 }, 524 { STV090x_P1_CARFREQ, 0x38 }, 525 { STV090x_P1_CARHDR, 0x20 }, 526 { STV090x_P1_KREFTMG, 0x5a }, 527 { STV090x_P1_SMAPCOEF7, 0x06 }, 528 { STV090x_P1_SMAPCOEF6, 0x00 }, 529 { STV090x_P1_SMAPCOEF5, 0x04 }, 530 { STV090x_P1_NOSCFG, 0x0c }, 531 { STV090x_GAINLLR_NF4, 0x21 }, 532 { STV090x_GAINLLR_NF5, 0x21 }, 533 { STV090x_GAINLLR_NF6, 0x20 }, 534 { STV090x_GAINLLR_NF7, 0x1F }, 535 { STV090x_GAINLLR_NF8, 0x1E }, 536 { STV090x_GAINLLR_NF9, 0x1E }, 537 { STV090x_GAINLLR_NF10, 0x1D }, 538 { STV090x_GAINLLR_NF11, 0x1B }, 539 { STV090x_GAINLLR_NF12, 0x20 }, 540 { STV090x_GAINLLR_NF13, 0x20 }, 541 { STV090x_GAINLLR_NF14, 0x20 }, 542 { STV090x_GAINLLR_NF15, 0x20 }, 543 { STV090x_GAINLLR_NF16, 0x20 }, 544 { STV090x_GAINLLR_NF17, 0x21 }, 545 }; 546 547 static struct stv090x_reg stv0903_cut20_val[] = { 548 { STV090x_P1_DMDCFG3, 0xe8 }, 549 { STV090x_P1_DMDCFG4, 0x10 }, 550 { STV090x_P1_CARFREQ, 0x38 }, 551 { STV090x_P1_CARHDR, 0x20 }, 552 { STV090x_P1_KREFTMG, 0x5a }, 553 { STV090x_P1_SMAPCOEF7, 0x06 }, 554 { STV090x_P1_SMAPCOEF6, 0x00 }, 555 { STV090x_P1_SMAPCOEF5, 0x04 }, 556 { STV090x_P1_NOSCFG, 0x0c }, 557 { STV090x_GAINLLR_NF4, 0x21 }, 558 { STV090x_GAINLLR_NF5, 0x21 }, 559 { STV090x_GAINLLR_NF6, 0x20 }, 560 { STV090x_GAINLLR_NF7, 0x1F }, 561 { STV090x_GAINLLR_NF8, 0x1E }, 562 { STV090x_GAINLLR_NF9, 0x1E }, 563 { STV090x_GAINLLR_NF10, 0x1D }, 564 { STV090x_GAINLLR_NF11, 0x1B }, 565 { STV090x_GAINLLR_NF12, 0x20 }, 566 { STV090x_GAINLLR_NF13, 0x20 }, 567 { STV090x_GAINLLR_NF14, 0x20 }, 568 { STV090x_GAINLLR_NF15, 0x20 }, 569 { STV090x_GAINLLR_NF16, 0x20 }, 570 { STV090x_GAINLLR_NF17, 0x21 } 571 }; 572 573 /* Cut 2.0 Long Frame Tracking CR loop */ 574 static struct stv090x_long_frame_crloop stv090x_s2_crl_cut20[] = { 575 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ 576 { STV090x_QPSK_12, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x1e }, 577 { STV090x_QPSK_35, 0x2f, 0x3f, 0x2e, 0x2f, 0x3d, 0x0f, 0x0e, 0x2e, 0x3d, 0x0e }, 578 { STV090x_QPSK_23, 0x2f, 0x3f, 0x2e, 0x2f, 0x0e, 0x0f, 0x0e, 0x1e, 0x3d, 0x3d }, 579 { STV090x_QPSK_34, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d }, 580 { STV090x_QPSK_45, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d }, 581 { STV090x_QPSK_56, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d }, 582 { STV090x_QPSK_89, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d }, 583 { STV090x_QPSK_910, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d }, 584 { STV090x_8PSK_35, 0x3c, 0x3e, 0x1c, 0x2e, 0x0c, 0x1e, 0x2b, 0x2d, 0x1b, 0x1d }, 585 { STV090x_8PSK_23, 0x1d, 0x3e, 0x3c, 0x2e, 0x2c, 0x1e, 0x0c, 0x2d, 0x2b, 0x1d }, 586 { STV090x_8PSK_34, 0x0e, 0x3e, 0x3d, 0x2e, 0x0d, 0x1e, 0x2c, 0x2d, 0x0c, 0x1d }, 587 { STV090x_8PSK_56, 0x2e, 0x3e, 0x1e, 0x2e, 0x2d, 0x1e, 0x3c, 0x2d, 0x2c, 0x1d }, 588 { STV090x_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x0d, 0x2d, 0x3c, 0x1d }, 589 { STV090x_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x1d, 0x2d, 0x0d, 0x1d } 590 }; 591 592 /* Cut 3.0 Long Frame Tracking CR loop */ 593 static struct stv090x_long_frame_crloop stv090x_s2_crl_cut30[] = { 594 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ 595 { STV090x_QPSK_12, 0x3c, 0x2c, 0x0c, 0x2c, 0x1b, 0x2c, 0x1b, 0x1c, 0x0b, 0x3b }, 596 { STV090x_QPSK_35, 0x0d, 0x0d, 0x0c, 0x0d, 0x1b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b }, 597 { STV090x_QPSK_23, 0x1d, 0x0d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b }, 598 { STV090x_QPSK_34, 0x1d, 0x1d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b }, 599 { STV090x_QPSK_45, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b }, 600 { STV090x_QPSK_56, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b }, 601 { STV090x_QPSK_89, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b }, 602 { STV090x_QPSK_910, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b }, 603 { STV090x_8PSK_35, 0x39, 0x29, 0x39, 0x19, 0x19, 0x19, 0x19, 0x19, 0x09, 0x19 }, 604 { STV090x_8PSK_23, 0x2a, 0x39, 0x1a, 0x0a, 0x39, 0x0a, 0x29, 0x39, 0x29, 0x0a }, 605 { STV090x_8PSK_34, 0x2b, 0x3a, 0x1b, 0x1b, 0x3a, 0x1b, 0x1a, 0x0b, 0x1a, 0x3a }, 606 { STV090x_8PSK_56, 0x0c, 0x1b, 0x3b, 0x3b, 0x1b, 0x3b, 0x3a, 0x3b, 0x3a, 0x1b }, 607 { STV090x_8PSK_89, 0x0d, 0x3c, 0x2c, 0x2c, 0x2b, 0x0c, 0x0b, 0x3b, 0x0b, 0x1b }, 608 { STV090x_8PSK_910, 0x0d, 0x0d, 0x2c, 0x3c, 0x3b, 0x1c, 0x0b, 0x3b, 0x0b, 0x1b } 609 }; 610 611 /* Cut 2.0 Long Frame Tracking CR Loop */ 612 static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut20[] = { 613 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ 614 { STV090x_16APSK_23, 0x0c, 0x0c, 0x0c, 0x0c, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c, 0x0c }, 615 { STV090x_16APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0e, 0x0c, 0x2d, 0x0c, 0x1d, 0x0c }, 616 { STV090x_16APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c }, 617 { STV090x_16APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c }, 618 { STV090x_16APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c }, 619 { STV090x_16APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c }, 620 { STV090x_32APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }, 621 { STV090x_32APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }, 622 { STV090x_32APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }, 623 { STV090x_32APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }, 624 { STV090x_32APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c } 625 }; 626 627 /* Cut 3.0 Long Frame Tracking CR Loop */ 628 static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut30[] = { 629 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ 630 { STV090x_16APSK_23, 0x0a, 0x0a, 0x0a, 0x0a, 0x1a, 0x0a, 0x3a, 0x0a, 0x2a, 0x0a }, 631 { STV090x_16APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0b, 0x0a, 0x3b, 0x0a, 0x1b, 0x0a }, 632 { STV090x_16APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a }, 633 { STV090x_16APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a }, 634 { STV090x_16APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a }, 635 { STV090x_16APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a }, 636 { STV090x_32APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }, 637 { STV090x_32APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }, 638 { STV090x_32APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }, 639 { STV090x_32APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }, 640 { STV090x_32APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a } 641 }; 642 643 static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut20[] = { 644 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ 645 { STV090x_QPSK_14, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x2d, 0x1f, 0x3d, 0x3e }, 646 { STV090x_QPSK_13, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x3d, 0x0f, 0x3d, 0x2e }, 647 { STV090x_QPSK_25, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x2e } 648 }; 649 650 static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut30[] = { 651 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ 652 { STV090x_QPSK_14, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x2a, 0x1c, 0x3a, 0x3b }, 653 { STV090x_QPSK_13, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x3a, 0x0c, 0x3a, 0x2b }, 654 { STV090x_QPSK_25, 0x1c, 0x3c, 0x1b, 0x3c, 0x3a, 0x1c, 0x3a, 0x3b, 0x3a, 0x2b } 655 }; 656 657 /* Cut 2.0 Short Frame Tracking CR Loop */ 658 static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut20[] = { 659 /* MODCOD 2M 5M 10M 20M 30M */ 660 { STV090x_QPSK, 0x2f, 0x2e, 0x0e, 0x0e, 0x3d }, 661 { STV090x_8PSK, 0x3e, 0x0e, 0x2d, 0x0d, 0x3c }, 662 { STV090x_16APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d }, 663 { STV090x_32APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d } 664 }; 665 666 /* Cut 3.0 Short Frame Tracking CR Loop */ 667 static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut30[] = { 668 /* MODCOD 2M 5M 10M 20M 30M */ 669 { STV090x_QPSK, 0x2C, 0x2B, 0x0B, 0x0B, 0x3A }, 670 { STV090x_8PSK, 0x3B, 0x0B, 0x2A, 0x0A, 0x39 }, 671 { STV090x_16APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A }, 672 { STV090x_32APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A } 673 }; 674 675 static inline s32 comp2(s32 __x, s32 __width) 676 { 677 if (__width == 32) 678 return __x; 679 else 680 return (__x >= (1 << (__width - 1))) ? (__x - (1 << __width)) : __x; 681 } 682 683 static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg) 684 { 685 const struct stv090x_config *config = state->config; 686 int ret; 687 688 u8 b0[] = { reg >> 8, reg & 0xff }; 689 u8 buf; 690 691 struct i2c_msg msg[] = { 692 { .addr = config->address, .flags = 0, .buf = b0, .len = 2 }, 693 { .addr = config->address, .flags = I2C_M_RD, .buf = &buf, .len = 1 } 694 }; 695 696 ret = i2c_transfer(state->i2c, msg, 2); 697 if (ret != 2) { 698 if (ret != -ERESTARTSYS) 699 dprintk(FE_ERROR, 1, 700 "Read error, Reg=[0x%02x], Status=%d", 701 reg, ret); 702 703 return ret < 0 ? ret : -EREMOTEIO; 704 } 705 if (unlikely(*state->verbose >= FE_DEBUGREG)) 706 dprintk(FE_ERROR, 1, "Reg=[0x%02x], data=%02x", 707 reg, buf); 708 709 return (unsigned int) buf; 710 } 711 712 static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 *data, u32 count) 713 { 714 const struct stv090x_config *config = state->config; 715 int ret; 716 u8 buf[MAX_XFER_SIZE]; 717 struct i2c_msg i2c_msg = { .addr = config->address, .flags = 0, .buf = buf, .len = 2 + count }; 718 719 if (2 + count > sizeof(buf)) { 720 printk(KERN_WARNING 721 "%s: i2c wr reg=%04x: len=%d is too big!\n", 722 KBUILD_MODNAME, reg, count); 723 return -EINVAL; 724 } 725 726 buf[0] = reg >> 8; 727 buf[1] = reg & 0xff; 728 memcpy(&buf[2], data, count); 729 730 dprintk(FE_DEBUGREG, 1, "%s [0x%04x]: %*ph", 731 __func__, reg, count, data); 732 733 ret = i2c_transfer(state->i2c, &i2c_msg, 1); 734 if (ret != 1) { 735 if (ret != -ERESTARTSYS) 736 dprintk(FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d", 737 reg, data[0], count, ret); 738 return ret < 0 ? ret : -EREMOTEIO; 739 } 740 741 return 0; 742 } 743 744 static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data) 745 { 746 u8 tmp = data; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */ 747 748 return stv090x_write_regs(state, reg, &tmp, 1); 749 } 750 751 static int stv090x_i2c_gate_ctrl(struct stv090x_state *state, int enable) 752 { 753 u32 reg; 754 755 /* 756 * NOTE! A lock is used as a FSM to control the state in which 757 * access is serialized between two tuners on the same demod. 758 * This has nothing to do with a lock to protect a critical section 759 * which may in some other cases be confused with protecting I/O 760 * access to the demodulator gate. 761 * In case of any error, the lock is unlocked and exit within the 762 * relevant operations themselves. 763 */ 764 if (enable) { 765 if (state->config->tuner_i2c_lock) 766 state->config->tuner_i2c_lock(&state->frontend, 1); 767 else 768 mutex_lock(&state->internal->tuner_lock); 769 } 770 771 reg = STV090x_READ_DEMOD(state, I2CRPT); 772 if (enable) { 773 dprintk(FE_DEBUG, 1, "Enable Gate"); 774 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 1); 775 if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0) 776 goto err; 777 778 } else { 779 dprintk(FE_DEBUG, 1, "Disable Gate"); 780 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 0); 781 if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0) 782 goto err; 783 } 784 785 if (!enable) { 786 if (state->config->tuner_i2c_lock) 787 state->config->tuner_i2c_lock(&state->frontend, 0); 788 else 789 mutex_unlock(&state->internal->tuner_lock); 790 } 791 792 return 0; 793 err: 794 dprintk(FE_ERROR, 1, "I/O error"); 795 if (state->config->tuner_i2c_lock) 796 state->config->tuner_i2c_lock(&state->frontend, 0); 797 else 798 mutex_unlock(&state->internal->tuner_lock); 799 return -1; 800 } 801 802 static void stv090x_get_lock_tmg(struct stv090x_state *state) 803 { 804 switch (state->algo) { 805 case STV090x_BLIND_SEARCH: 806 dprintk(FE_DEBUG, 1, "Blind Search"); 807 if (state->srate <= 1500000) { /*10Msps< SR <=15Msps*/ 808 state->DemodTimeout = 1500; 809 state->FecTimeout = 400; 810 } else if (state->srate <= 5000000) { /*10Msps< SR <=15Msps*/ 811 state->DemodTimeout = 1000; 812 state->FecTimeout = 300; 813 } else { /*SR >20Msps*/ 814 state->DemodTimeout = 700; 815 state->FecTimeout = 100; 816 } 817 break; 818 819 case STV090x_COLD_SEARCH: 820 case STV090x_WARM_SEARCH: 821 default: 822 dprintk(FE_DEBUG, 1, "Normal Search"); 823 if (state->srate <= 1000000) { /*SR <=1Msps*/ 824 state->DemodTimeout = 4500; 825 state->FecTimeout = 1700; 826 } else if (state->srate <= 2000000) { /*1Msps < SR <= 2Msps */ 827 state->DemodTimeout = 2500; 828 state->FecTimeout = 1100; 829 } else if (state->srate <= 5000000) { /*2Msps < SR <= 5Msps */ 830 state->DemodTimeout = 1000; 831 state->FecTimeout = 550; 832 } else if (state->srate <= 10000000) { /*5Msps < SR <= 10Msps */ 833 state->DemodTimeout = 700; 834 state->FecTimeout = 250; 835 } else if (state->srate <= 20000000) { /*10Msps < SR <= 20Msps */ 836 state->DemodTimeout = 400; 837 state->FecTimeout = 130; 838 } else { /*SR >20Msps*/ 839 state->DemodTimeout = 300; 840 state->FecTimeout = 100; 841 } 842 break; 843 } 844 845 if (state->algo == STV090x_WARM_SEARCH) 846 state->DemodTimeout /= 2; 847 } 848 849 static int stv090x_set_srate(struct stv090x_state *state, u32 srate) 850 { 851 u32 sym; 852 853 if (srate > 60000000) { 854 sym = (srate << 4); /* SR * 2^16 / master_clk */ 855 sym /= (state->internal->mclk >> 12); 856 } else if (srate > 6000000) { 857 sym = (srate << 6); 858 sym /= (state->internal->mclk >> 10); 859 } else { 860 sym = (srate << 9); 861 sym /= (state->internal->mclk >> 7); 862 } 863 864 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0x7f) < 0) /* MSB */ 865 goto err; 866 if (STV090x_WRITE_DEMOD(state, SFRINIT0, (sym & 0xff)) < 0) /* LSB */ 867 goto err; 868 869 return 0; 870 err: 871 dprintk(FE_ERROR, 1, "I/O error"); 872 return -1; 873 } 874 875 static int stv090x_set_max_srate(struct stv090x_state *state, u32 clk, u32 srate) 876 { 877 u32 sym; 878 879 srate = 105 * (srate / 100); 880 if (srate > 60000000) { 881 sym = (srate << 4); /* SR * 2^16 / master_clk */ 882 sym /= (state->internal->mclk >> 12); 883 } else if (srate > 6000000) { 884 sym = (srate << 6); 885 sym /= (state->internal->mclk >> 10); 886 } else { 887 sym = (srate << 9); 888 sym /= (state->internal->mclk >> 7); 889 } 890 891 if (sym < 0x7fff) { 892 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) /* MSB */ 893 goto err; 894 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) /* LSB */ 895 goto err; 896 } else { 897 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x7f) < 0) /* MSB */ 898 goto err; 899 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xff) < 0) /* LSB */ 900 goto err; 901 } 902 903 return 0; 904 err: 905 dprintk(FE_ERROR, 1, "I/O error"); 906 return -1; 907 } 908 909 static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate) 910 { 911 u32 sym; 912 913 srate = 95 * (srate / 100); 914 if (srate > 60000000) { 915 sym = (srate << 4); /* SR * 2^16 / master_clk */ 916 sym /= (state->internal->mclk >> 12); 917 } else if (srate > 6000000) { 918 sym = (srate << 6); 919 sym /= (state->internal->mclk >> 10); 920 } else { 921 sym = (srate << 9); 922 sym /= (state->internal->mclk >> 7); 923 } 924 925 if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0x7f)) < 0) /* MSB */ 926 goto err; 927 if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */ 928 goto err; 929 return 0; 930 err: 931 dprintk(FE_ERROR, 1, "I/O error"); 932 return -1; 933 } 934 935 static u32 stv090x_car_width(u32 srate, enum stv090x_rolloff rolloff) 936 { 937 u32 ro; 938 939 switch (rolloff) { 940 case STV090x_RO_20: 941 ro = 20; 942 break; 943 case STV090x_RO_25: 944 ro = 25; 945 break; 946 case STV090x_RO_35: 947 default: 948 ro = 35; 949 break; 950 } 951 952 return srate + (srate * ro) / 100; 953 } 954 955 static int stv090x_set_vit_thacq(struct stv090x_state *state) 956 { 957 if (STV090x_WRITE_DEMOD(state, VTH12, 0x96) < 0) 958 goto err; 959 if (STV090x_WRITE_DEMOD(state, VTH23, 0x64) < 0) 960 goto err; 961 if (STV090x_WRITE_DEMOD(state, VTH34, 0x36) < 0) 962 goto err; 963 if (STV090x_WRITE_DEMOD(state, VTH56, 0x23) < 0) 964 goto err; 965 if (STV090x_WRITE_DEMOD(state, VTH67, 0x1e) < 0) 966 goto err; 967 if (STV090x_WRITE_DEMOD(state, VTH78, 0x19) < 0) 968 goto err; 969 return 0; 970 err: 971 dprintk(FE_ERROR, 1, "I/O error"); 972 return -1; 973 } 974 975 static int stv090x_set_vit_thtracq(struct stv090x_state *state) 976 { 977 if (STV090x_WRITE_DEMOD(state, VTH12, 0xd0) < 0) 978 goto err; 979 if (STV090x_WRITE_DEMOD(state, VTH23, 0x7d) < 0) 980 goto err; 981 if (STV090x_WRITE_DEMOD(state, VTH34, 0x53) < 0) 982 goto err; 983 if (STV090x_WRITE_DEMOD(state, VTH56, 0x2f) < 0) 984 goto err; 985 if (STV090x_WRITE_DEMOD(state, VTH67, 0x24) < 0) 986 goto err; 987 if (STV090x_WRITE_DEMOD(state, VTH78, 0x1f) < 0) 988 goto err; 989 return 0; 990 err: 991 dprintk(FE_ERROR, 1, "I/O error"); 992 return -1; 993 } 994 995 static int stv090x_set_viterbi(struct stv090x_state *state) 996 { 997 switch (state->search_mode) { 998 case STV090x_SEARCH_AUTO: 999 if (STV090x_WRITE_DEMOD(state, FECM, 0x10) < 0) /* DVB-S and DVB-S2 */ 1000 goto err; 1001 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x3f) < 0) /* all puncture rate */ 1002 goto err; 1003 break; 1004 case STV090x_SEARCH_DVBS1: 1005 if (STV090x_WRITE_DEMOD(state, FECM, 0x00) < 0) /* disable DSS */ 1006 goto err; 1007 switch (state->fec) { 1008 case STV090x_PR12: 1009 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0) 1010 goto err; 1011 break; 1012 1013 case STV090x_PR23: 1014 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0) 1015 goto err; 1016 break; 1017 1018 case STV090x_PR34: 1019 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x04) < 0) 1020 goto err; 1021 break; 1022 1023 case STV090x_PR56: 1024 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x08) < 0) 1025 goto err; 1026 break; 1027 1028 case STV090x_PR78: 1029 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x20) < 0) 1030 goto err; 1031 break; 1032 1033 default: 1034 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x2f) < 0) /* all */ 1035 goto err; 1036 break; 1037 } 1038 break; 1039 case STV090x_SEARCH_DSS: 1040 if (STV090x_WRITE_DEMOD(state, FECM, 0x80) < 0) 1041 goto err; 1042 switch (state->fec) { 1043 case STV090x_PR12: 1044 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0) 1045 goto err; 1046 break; 1047 1048 case STV090x_PR23: 1049 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0) 1050 goto err; 1051 break; 1052 1053 case STV090x_PR67: 1054 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x10) < 0) 1055 goto err; 1056 break; 1057 1058 default: 1059 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x13) < 0) /* 1/2, 2/3, 6/7 */ 1060 goto err; 1061 break; 1062 } 1063 break; 1064 default: 1065 break; 1066 } 1067 return 0; 1068 err: 1069 dprintk(FE_ERROR, 1, "I/O error"); 1070 return -1; 1071 } 1072 1073 static int stv090x_stop_modcod(struct stv090x_state *state) 1074 { 1075 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0) 1076 goto err; 1077 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0) 1078 goto err; 1079 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0) 1080 goto err; 1081 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0) 1082 goto err; 1083 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0) 1084 goto err; 1085 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0) 1086 goto err; 1087 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0) 1088 goto err; 1089 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xff) < 0) 1090 goto err; 1091 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xff) < 0) 1092 goto err; 1093 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xff) < 0) 1094 goto err; 1095 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xff) < 0) 1096 goto err; 1097 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xff) < 0) 1098 goto err; 1099 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xff) < 0) 1100 goto err; 1101 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xff) < 0) 1102 goto err; 1103 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0) 1104 goto err; 1105 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xff) < 0) 1106 goto err; 1107 return 0; 1108 err: 1109 dprintk(FE_ERROR, 1, "I/O error"); 1110 return -1; 1111 } 1112 1113 static int stv090x_activate_modcod(struct stv090x_state *state) 1114 { 1115 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0) 1116 goto err; 1117 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xfc) < 0) 1118 goto err; 1119 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xcc) < 0) 1120 goto err; 1121 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xcc) < 0) 1122 goto err; 1123 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xcc) < 0) 1124 goto err; 1125 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xcc) < 0) 1126 goto err; 1127 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xcc) < 0) 1128 goto err; 1129 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0) 1130 goto err; 1131 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0) 1132 goto err; 1133 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0) 1134 goto err; 1135 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0) 1136 goto err; 1137 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0) 1138 goto err; 1139 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0) 1140 goto err; 1141 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0) 1142 goto err; 1143 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xcc) < 0) 1144 goto err; 1145 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0) 1146 goto err; 1147 1148 return 0; 1149 err: 1150 dprintk(FE_ERROR, 1, "I/O error"); 1151 return -1; 1152 } 1153 1154 static int stv090x_activate_modcod_single(struct stv090x_state *state) 1155 { 1156 1157 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0) 1158 goto err; 1159 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xf0) < 0) 1160 goto err; 1161 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0x00) < 0) 1162 goto err; 1163 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0x00) < 0) 1164 goto err; 1165 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0x00) < 0) 1166 goto err; 1167 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0x00) < 0) 1168 goto err; 1169 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0x00) < 0) 1170 goto err; 1171 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0x00) < 0) 1172 goto err; 1173 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0x00) < 0) 1174 goto err; 1175 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0x00) < 0) 1176 goto err; 1177 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0x00) < 0) 1178 goto err; 1179 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0x00) < 0) 1180 goto err; 1181 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0x00) < 0) 1182 goto err; 1183 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0x00) < 0) 1184 goto err; 1185 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0x00) < 0) 1186 goto err; 1187 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0x0f) < 0) 1188 goto err; 1189 1190 return 0; 1191 1192 err: 1193 dprintk(FE_ERROR, 1, "I/O error"); 1194 return -1; 1195 } 1196 1197 static int stv090x_vitclk_ctl(struct stv090x_state *state, int enable) 1198 { 1199 u32 reg; 1200 1201 switch (state->demod) { 1202 case STV090x_DEMODULATOR_0: 1203 mutex_lock(&state->internal->demod_lock); 1204 reg = stv090x_read_reg(state, STV090x_STOPCLK2); 1205 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, enable); 1206 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) 1207 goto err; 1208 mutex_unlock(&state->internal->demod_lock); 1209 break; 1210 1211 case STV090x_DEMODULATOR_1: 1212 mutex_lock(&state->internal->demod_lock); 1213 reg = stv090x_read_reg(state, STV090x_STOPCLK2); 1214 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, enable); 1215 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) 1216 goto err; 1217 mutex_unlock(&state->internal->demod_lock); 1218 break; 1219 1220 default: 1221 dprintk(FE_ERROR, 1, "Wrong demodulator!"); 1222 break; 1223 } 1224 return 0; 1225 err: 1226 mutex_unlock(&state->internal->demod_lock); 1227 dprintk(FE_ERROR, 1, "I/O error"); 1228 return -1; 1229 } 1230 1231 static int stv090x_dvbs_track_crl(struct stv090x_state *state) 1232 { 1233 if (state->internal->dev_ver >= 0x30) { 1234 /* Set ACLC BCLC optimised value vs SR */ 1235 if (state->srate >= 15000000) { 1236 if (STV090x_WRITE_DEMOD(state, ACLC, 0x2b) < 0) 1237 goto err; 1238 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1a) < 0) 1239 goto err; 1240 } else if ((state->srate >= 7000000) && (15000000 > state->srate)) { 1241 if (STV090x_WRITE_DEMOD(state, ACLC, 0x0c) < 0) 1242 goto err; 1243 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1b) < 0) 1244 goto err; 1245 } else if (state->srate < 7000000) { 1246 if (STV090x_WRITE_DEMOD(state, ACLC, 0x2c) < 0) 1247 goto err; 1248 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1c) < 0) 1249 goto err; 1250 } 1251 1252 } else { 1253 /* Cut 2.0 */ 1254 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) 1255 goto err; 1256 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0) 1257 goto err; 1258 } 1259 return 0; 1260 err: 1261 dprintk(FE_ERROR, 1, "I/O error"); 1262 return -1; 1263 } 1264 1265 static int stv090x_delivery_search(struct stv090x_state *state) 1266 { 1267 u32 reg; 1268 1269 switch (state->search_mode) { 1270 case STV090x_SEARCH_DVBS1: 1271 case STV090x_SEARCH_DSS: 1272 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 1273 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); 1274 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0); 1275 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1276 goto err; 1277 1278 /* Activate Viterbi decoder in legacy search, 1279 * do not use FRESVIT1, might impact VITERBI2 1280 */ 1281 if (stv090x_vitclk_ctl(state, 0) < 0) 1282 goto err; 1283 1284 if (stv090x_dvbs_track_crl(state) < 0) 1285 goto err; 1286 1287 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x22) < 0) /* disable DVB-S2 */ 1288 goto err; 1289 1290 if (stv090x_set_vit_thacq(state) < 0) 1291 goto err; 1292 if (stv090x_set_viterbi(state) < 0) 1293 goto err; 1294 break; 1295 1296 case STV090x_SEARCH_DVBS2: 1297 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 1298 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0); 1299 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0); 1300 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1301 goto err; 1302 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); 1303 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1); 1304 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1305 goto err; 1306 1307 if (stv090x_vitclk_ctl(state, 1) < 0) 1308 goto err; 1309 1310 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) /* stop DVB-S CR loop */ 1311 goto err; 1312 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0) 1313 goto err; 1314 1315 if (state->internal->dev_ver <= 0x20) { 1316 /* enable S2 carrier loop */ 1317 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0) 1318 goto err; 1319 } else { 1320 /* > Cut 3: Stop carrier 3 */ 1321 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0) 1322 goto err; 1323 } 1324 1325 if (state->demod_mode != STV090x_SINGLE) { 1326 /* Cut 2: enable link during search */ 1327 if (stv090x_activate_modcod(state) < 0) 1328 goto err; 1329 } else { 1330 /* Single demodulator 1331 * Authorize SHORT and LONG frames, 1332 * QPSK, 8PSK, 16APSK and 32APSK 1333 */ 1334 if (stv090x_activate_modcod_single(state) < 0) 1335 goto err; 1336 } 1337 1338 if (stv090x_set_vit_thtracq(state) < 0) 1339 goto err; 1340 break; 1341 1342 case STV090x_SEARCH_AUTO: 1343 default: 1344 /* enable DVB-S2 and DVB-S2 in Auto MODE */ 1345 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 1346 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0); 1347 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0); 1348 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1349 goto err; 1350 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); 1351 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1); 1352 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1353 goto err; 1354 1355 if (stv090x_vitclk_ctl(state, 0) < 0) 1356 goto err; 1357 1358 if (stv090x_dvbs_track_crl(state) < 0) 1359 goto err; 1360 1361 if (state->internal->dev_ver <= 0x20) { 1362 /* enable S2 carrier loop */ 1363 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0) 1364 goto err; 1365 } else { 1366 /* > Cut 3: Stop carrier 3 */ 1367 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0) 1368 goto err; 1369 } 1370 1371 if (state->demod_mode != STV090x_SINGLE) { 1372 /* Cut 2: enable link during search */ 1373 if (stv090x_activate_modcod(state) < 0) 1374 goto err; 1375 } else { 1376 /* Single demodulator 1377 * Authorize SHORT and LONG frames, 1378 * QPSK, 8PSK, 16APSK and 32APSK 1379 */ 1380 if (stv090x_activate_modcod_single(state) < 0) 1381 goto err; 1382 } 1383 1384 if (stv090x_set_vit_thacq(state) < 0) 1385 goto err; 1386 1387 if (stv090x_set_viterbi(state) < 0) 1388 goto err; 1389 break; 1390 } 1391 return 0; 1392 err: 1393 dprintk(FE_ERROR, 1, "I/O error"); 1394 return -1; 1395 } 1396 1397 static int stv090x_start_search(struct stv090x_state *state) 1398 { 1399 u32 reg, freq_abs; 1400 s16 freq; 1401 1402 /* Reset demodulator */ 1403 reg = STV090x_READ_DEMOD(state, DMDISTATE); 1404 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); 1405 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0) 1406 goto err; 1407 1408 if (state->internal->dev_ver <= 0x20) { 1409 if (state->srate <= 5000000) { 1410 if (STV090x_WRITE_DEMOD(state, CARCFG, 0x44) < 0) 1411 goto err; 1412 if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0) 1413 goto err; 1414 if (STV090x_WRITE_DEMOD(state, CFRUP0, 0xff) < 0) 1415 goto err; 1416 if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0) 1417 goto err; 1418 if (STV090x_WRITE_DEMOD(state, CFRLOW0, 0x00) < 0) 1419 goto err; 1420 1421 /*enlarge the timing bandwidth for Low SR*/ 1422 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) 1423 goto err; 1424 } else { 1425 /* If the symbol rate is >5 Msps 1426 Set The carrier search up and low to auto mode */ 1427 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0) 1428 goto err; 1429 /*reduce the timing bandwidth for high SR*/ 1430 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0) 1431 goto err; 1432 } 1433 } else { 1434 /* >= Cut 3 */ 1435 if (state->srate <= 5000000) { 1436 /* enlarge the timing bandwidth for Low SR */ 1437 STV090x_WRITE_DEMOD(state, RTCS2, 0x68); 1438 } else { 1439 /* reduce timing bandwidth for high SR */ 1440 STV090x_WRITE_DEMOD(state, RTCS2, 0x44); 1441 } 1442 1443 /* Set CFR min and max to manual mode */ 1444 STV090x_WRITE_DEMOD(state, CARCFG, 0x46); 1445 1446 if (state->algo == STV090x_WARM_SEARCH) { 1447 /* WARM Start 1448 * CFR min = -1MHz, 1449 * CFR max = +1MHz 1450 */ 1451 freq_abs = 1000 << 16; 1452 freq_abs /= (state->internal->mclk / 1000); 1453 freq = (s16) freq_abs; 1454 } else { 1455 /* COLD Start 1456 * CFR min =- (SearchRange / 2 + 600KHz) 1457 * CFR max = +(SearchRange / 2 + 600KHz) 1458 * (600KHz for the tuner step size) 1459 */ 1460 freq_abs = (state->search_range / 2000) + 600; 1461 freq_abs = freq_abs << 16; 1462 freq_abs /= (state->internal->mclk / 1000); 1463 freq = (s16) freq_abs; 1464 } 1465 1466 if (STV090x_WRITE_DEMOD(state, CFRUP1, MSB(freq)) < 0) 1467 goto err; 1468 if (STV090x_WRITE_DEMOD(state, CFRUP0, LSB(freq)) < 0) 1469 goto err; 1470 1471 freq *= -1; 1472 1473 if (STV090x_WRITE_DEMOD(state, CFRLOW1, MSB(freq)) < 0) 1474 goto err; 1475 if (STV090x_WRITE_DEMOD(state, CFRLOW0, LSB(freq)) < 0) 1476 goto err; 1477 1478 } 1479 1480 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0) < 0) 1481 goto err; 1482 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0) < 0) 1483 goto err; 1484 1485 if (state->internal->dev_ver >= 0x20) { 1486 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0) 1487 goto err; 1488 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0) 1489 goto err; 1490 1491 if ((state->search_mode == STV090x_SEARCH_DVBS1) || 1492 (state->search_mode == STV090x_SEARCH_DSS) || 1493 (state->search_mode == STV090x_SEARCH_AUTO)) { 1494 1495 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0) 1496 goto err; 1497 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) 1498 goto err; 1499 } 1500 } 1501 1502 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00) < 0) 1503 goto err; 1504 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xe0) < 0) 1505 goto err; 1506 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xc0) < 0) 1507 goto err; 1508 1509 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 1510 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0); 1511 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0); 1512 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1513 goto err; 1514 reg = STV090x_READ_DEMOD(state, DMDCFG2); 1515 STV090x_SETFIELD_Px(reg, S1S2_SEQUENTIAL_FIELD, 0x0); 1516 if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0) 1517 goto err; 1518 1519 if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) 1520 goto err; 1521 1522 if (state->internal->dev_ver >= 0x20) { 1523 /*Frequency offset detector setting*/ 1524 if (state->srate < 2000000) { 1525 if (state->internal->dev_ver <= 0x20) { 1526 /* Cut 2 */ 1527 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x39) < 0) 1528 goto err; 1529 } else { 1530 /* Cut 3 */ 1531 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x89) < 0) 1532 goto err; 1533 } 1534 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x40) < 0) 1535 goto err; 1536 } else if (state->srate < 10000000) { 1537 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0) 1538 goto err; 1539 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0) 1540 goto err; 1541 } else { 1542 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0) 1543 goto err; 1544 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0) 1545 goto err; 1546 } 1547 } else { 1548 if (state->srate < 10000000) { 1549 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0) 1550 goto err; 1551 } else { 1552 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0) 1553 goto err; 1554 } 1555 } 1556 1557 switch (state->algo) { 1558 case STV090x_WARM_SEARCH: 1559 /* The symbol rate and the exact 1560 * carrier Frequency are known 1561 */ 1562 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) 1563 goto err; 1564 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) 1565 goto err; 1566 break; 1567 1568 case STV090x_COLD_SEARCH: 1569 /* The symbol rate is known */ 1570 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) 1571 goto err; 1572 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) 1573 goto err; 1574 break; 1575 1576 default: 1577 break; 1578 } 1579 return 0; 1580 err: 1581 dprintk(FE_ERROR, 1, "I/O error"); 1582 return -1; 1583 } 1584 1585 static int stv090x_get_agc2_min_level(struct stv090x_state *state) 1586 { 1587 u32 agc2_min = 0xffff, agc2 = 0, freq_init, freq_step, reg; 1588 s32 i, j, steps, dir; 1589 1590 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) 1591 goto err; 1592 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 1593 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0); 1594 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0); 1595 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1596 goto err; 1597 1598 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) /* SR = 65 Msps Max */ 1599 goto err; 1600 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0) 1601 goto err; 1602 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) /* SR= 400 ksps Min */ 1603 goto err; 1604 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0) 1605 goto err; 1606 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) /* stop acq @ coarse carrier state */ 1607 goto err; 1608 if (stv090x_set_srate(state, 1000000) < 0) 1609 goto err; 1610 1611 steps = state->search_range / 1000000; 1612 if (steps <= 0) 1613 steps = 1; 1614 1615 dir = 1; 1616 freq_step = (1000000 * 256) / (state->internal->mclk / 256); 1617 freq_init = 0; 1618 1619 for (i = 0; i < steps; i++) { 1620 if (dir > 0) 1621 freq_init = freq_init + (freq_step * i); 1622 else 1623 freq_init = freq_init - (freq_step * i); 1624 1625 dir *= -1; 1626 1627 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */ 1628 goto err; 1629 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_init >> 8) & 0xff) < 0) 1630 goto err; 1631 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_init & 0xff) < 0) 1632 goto err; 1633 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */ 1634 goto err; 1635 msleep(10); 1636 1637 agc2 = 0; 1638 for (j = 0; j < 10; j++) { 1639 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) | 1640 STV090x_READ_DEMOD(state, AGC2I0); 1641 } 1642 agc2 /= 10; 1643 if (agc2 < agc2_min) 1644 agc2_min = agc2; 1645 } 1646 1647 return agc2_min; 1648 err: 1649 dprintk(FE_ERROR, 1, "I/O error"); 1650 return -1; 1651 } 1652 1653 static u32 stv090x_get_srate(struct stv090x_state *state, u32 clk) 1654 { 1655 u8 r3, r2, r1, r0; 1656 s32 srate, int_1, int_2, tmp_1, tmp_2; 1657 1658 r3 = STV090x_READ_DEMOD(state, SFR3); 1659 r2 = STV090x_READ_DEMOD(state, SFR2); 1660 r1 = STV090x_READ_DEMOD(state, SFR1); 1661 r0 = STV090x_READ_DEMOD(state, SFR0); 1662 1663 srate = ((r3 << 24) | (r2 << 16) | (r1 << 8) | r0); 1664 1665 int_1 = clk >> 16; 1666 int_2 = srate >> 16; 1667 1668 tmp_1 = clk % 0x10000; 1669 tmp_2 = srate % 0x10000; 1670 1671 srate = (int_1 * int_2) + 1672 ((int_1 * tmp_2) >> 16) + 1673 ((int_2 * tmp_1) >> 16); 1674 1675 return srate; 1676 } 1677 1678 static u32 stv090x_srate_srch_coarse(struct stv090x_state *state) 1679 { 1680 struct dvb_frontend *fe = &state->frontend; 1681 1682 int tmg_lock = 0, i; 1683 s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq; 1684 u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg; 1685 u32 agc2th; 1686 1687 if (state->internal->dev_ver >= 0x30) 1688 agc2th = 0x2e00; 1689 else 1690 agc2th = 0x1f00; 1691 1692 reg = STV090x_READ_DEMOD(state, DMDISTATE); 1693 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */ 1694 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0) 1695 goto err; 1696 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0) 1697 goto err; 1698 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0) 1699 goto err; 1700 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0) 1701 goto err; 1702 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0) 1703 goto err; 1704 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 1705 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1); 1706 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0); 1707 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1708 goto err; 1709 1710 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) 1711 goto err; 1712 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0) 1713 goto err; 1714 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) 1715 goto err; 1716 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0) 1717 goto err; 1718 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) 1719 goto err; 1720 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x50) < 0) 1721 goto err; 1722 1723 if (state->internal->dev_ver >= 0x30) { 1724 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x99) < 0) 1725 goto err; 1726 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x98) < 0) 1727 goto err; 1728 1729 } else if (state->internal->dev_ver >= 0x20) { 1730 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x6a) < 0) 1731 goto err; 1732 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0) 1733 goto err; 1734 } 1735 1736 if (state->srate <= 2000000) 1737 car_step = 1000; 1738 else if (state->srate <= 5000000) 1739 car_step = 2000; 1740 else if (state->srate <= 12000000) 1741 car_step = 3000; 1742 else 1743 car_step = 5000; 1744 1745 steps = -1 + ((state->search_range / 1000) / car_step); 1746 steps /= 2; 1747 steps = (2 * steps) + 1; 1748 if (steps < 0) 1749 steps = 1; 1750 else if (steps > 10) { 1751 steps = 11; 1752 car_step = (state->search_range / 1000) / 10; 1753 } 1754 cur_step = 0; 1755 dir = 1; 1756 freq = state->frequency; 1757 1758 while ((!tmg_lock) && (cur_step < steps)) { 1759 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */ 1760 goto err; 1761 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) 1762 goto err; 1763 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0) 1764 goto err; 1765 if (STV090x_WRITE_DEMOD(state, SFRINIT1, 0x00) < 0) 1766 goto err; 1767 if (STV090x_WRITE_DEMOD(state, SFRINIT0, 0x00) < 0) 1768 goto err; 1769 /* trigger acquisition */ 1770 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x40) < 0) 1771 goto err; 1772 msleep(50); 1773 for (i = 0; i < 10; i++) { 1774 reg = STV090x_READ_DEMOD(state, DSTATUS); 1775 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2) 1776 tmg_cpt++; 1777 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) | 1778 STV090x_READ_DEMOD(state, AGC2I0); 1779 } 1780 agc2 /= 10; 1781 srate_coarse = stv090x_get_srate(state, state->internal->mclk); 1782 cur_step++; 1783 dir *= -1; 1784 if ((tmg_cpt >= 5) && (agc2 < agc2th) && 1785 (srate_coarse < 50000000) && (srate_coarse > 850000)) 1786 tmg_lock = 1; 1787 else if (cur_step < steps) { 1788 if (dir > 0) 1789 freq += cur_step * car_step; 1790 else 1791 freq -= cur_step * car_step; 1792 1793 /* Setup tuner */ 1794 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 1795 goto err; 1796 1797 if (state->config->tuner_set_frequency) { 1798 if (state->config->tuner_set_frequency(fe, freq) < 0) 1799 goto err_gateoff; 1800 } 1801 1802 if (state->config->tuner_set_bandwidth) { 1803 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0) 1804 goto err_gateoff; 1805 } 1806 1807 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 1808 goto err; 1809 1810 msleep(50); 1811 1812 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 1813 goto err; 1814 1815 if (state->config->tuner_get_status) { 1816 if (state->config->tuner_get_status(fe, ®) < 0) 1817 goto err_gateoff; 1818 } 1819 1820 if (reg) 1821 dprintk(FE_DEBUG, 1, "Tuner phase locked"); 1822 else 1823 dprintk(FE_DEBUG, 1, "Tuner unlocked"); 1824 1825 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 1826 goto err; 1827 1828 } 1829 } 1830 if (!tmg_lock) 1831 srate_coarse = 0; 1832 else 1833 srate_coarse = stv090x_get_srate(state, state->internal->mclk); 1834 1835 return srate_coarse; 1836 1837 err_gateoff: 1838 stv090x_i2c_gate_ctrl(state, 0); 1839 err: 1840 dprintk(FE_ERROR, 1, "I/O error"); 1841 return -1; 1842 } 1843 1844 static u32 stv090x_srate_srch_fine(struct stv090x_state *state) 1845 { 1846 u32 srate_coarse, freq_coarse, sym, reg; 1847 1848 srate_coarse = stv090x_get_srate(state, state->internal->mclk); 1849 freq_coarse = STV090x_READ_DEMOD(state, CFR2) << 8; 1850 freq_coarse |= STV090x_READ_DEMOD(state, CFR1); 1851 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */ 1852 1853 if (sym < state->srate) 1854 srate_coarse = 0; 1855 else { 1856 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */ 1857 goto err; 1858 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) 1859 goto err; 1860 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0) 1861 goto err; 1862 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0) 1863 goto err; 1864 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0) 1865 goto err; 1866 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 1867 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); 1868 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1869 goto err; 1870 1871 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) 1872 goto err; 1873 1874 if (state->internal->dev_ver >= 0x30) { 1875 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x79) < 0) 1876 goto err; 1877 } else if (state->internal->dev_ver >= 0x20) { 1878 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0) 1879 goto err; 1880 } 1881 1882 if (srate_coarse > 3000000) { 1883 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */ 1884 sym = (sym / 1000) * 65536; 1885 sym /= (state->internal->mclk / 1000); 1886 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) 1887 goto err; 1888 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) 1889 goto err; 1890 sym = 10 * (srate_coarse / 13); /* SFRLOW = SFR - 30% */ 1891 sym = (sym / 1000) * 65536; 1892 sym /= (state->internal->mclk / 1000); 1893 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0) 1894 goto err; 1895 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0) 1896 goto err; 1897 sym = (srate_coarse / 1000) * 65536; 1898 sym /= (state->internal->mclk / 1000); 1899 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0) 1900 goto err; 1901 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0) 1902 goto err; 1903 } else { 1904 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */ 1905 sym = (sym / 100) * 65536; 1906 sym /= (state->internal->mclk / 100); 1907 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) 1908 goto err; 1909 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) 1910 goto err; 1911 sym = 10 * (srate_coarse / 14); /* SFRLOW = SFR - 30% */ 1912 sym = (sym / 100) * 65536; 1913 sym /= (state->internal->mclk / 100); 1914 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0) 1915 goto err; 1916 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0) 1917 goto err; 1918 sym = (srate_coarse / 100) * 65536; 1919 sym /= (state->internal->mclk / 100); 1920 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0) 1921 goto err; 1922 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0) 1923 goto err; 1924 } 1925 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0) 1926 goto err; 1927 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_coarse >> 8) & 0xff) < 0) 1928 goto err; 1929 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_coarse & 0xff) < 0) 1930 goto err; 1931 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) /* trigger acquisition */ 1932 goto err; 1933 } 1934 1935 return srate_coarse; 1936 1937 err: 1938 dprintk(FE_ERROR, 1, "I/O error"); 1939 return -1; 1940 } 1941 1942 static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout) 1943 { 1944 s32 timer = 0, lock = 0; 1945 u32 reg; 1946 u8 stat; 1947 1948 while ((timer < timeout) && (!lock)) { 1949 reg = STV090x_READ_DEMOD(state, DMDSTATE); 1950 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD); 1951 1952 switch (stat) { 1953 case 0: /* searching */ 1954 case 1: /* first PLH detected */ 1955 default: 1956 dprintk(FE_DEBUG, 1, "Demodulator searching .."); 1957 lock = 0; 1958 break; 1959 case 2: /* DVB-S2 mode */ 1960 case 3: /* DVB-S1/legacy mode */ 1961 reg = STV090x_READ_DEMOD(state, DSTATUS); 1962 lock = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD); 1963 break; 1964 } 1965 1966 if (!lock) 1967 msleep(10); 1968 else 1969 dprintk(FE_DEBUG, 1, "Demodulator acquired LOCK"); 1970 1971 timer += 10; 1972 } 1973 return lock; 1974 } 1975 1976 static int stv090x_blind_search(struct stv090x_state *state) 1977 { 1978 u32 agc2, reg, srate_coarse; 1979 s32 cpt_fail, agc2_ovflw, i; 1980 u8 k_ref, k_max, k_min; 1981 int coarse_fail = 0; 1982 int lock; 1983 1984 k_max = 110; 1985 k_min = 10; 1986 1987 agc2 = stv090x_get_agc2_min_level(state); 1988 1989 if (agc2 > STV090x_SEARCH_AGC2_TH(state->internal->dev_ver)) { 1990 lock = 0; 1991 } else { 1992 1993 if (state->internal->dev_ver <= 0x20) { 1994 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0) 1995 goto err; 1996 } else { 1997 /* > Cut 3 */ 1998 if (STV090x_WRITE_DEMOD(state, CARCFG, 0x06) < 0) 1999 goto err; 2000 } 2001 2002 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0) 2003 goto err; 2004 2005 if (state->internal->dev_ver >= 0x20) { 2006 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0) 2007 goto err; 2008 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0) 2009 goto err; 2010 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0) 2011 goto err; 2012 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) /* set viterbi hysteresis */ 2013 goto err; 2014 } 2015 2016 k_ref = k_max; 2017 do { 2018 if (STV090x_WRITE_DEMOD(state, KREFTMG, k_ref) < 0) 2019 goto err; 2020 if (stv090x_srate_srch_coarse(state) != 0) { 2021 srate_coarse = stv090x_srate_srch_fine(state); 2022 if (srate_coarse != 0) { 2023 stv090x_get_lock_tmg(state); 2024 lock = stv090x_get_dmdlock(state, 2025 state->DemodTimeout); 2026 } else { 2027 lock = 0; 2028 } 2029 } else { 2030 cpt_fail = 0; 2031 agc2_ovflw = 0; 2032 for (i = 0; i < 10; i++) { 2033 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) | 2034 STV090x_READ_DEMOD(state, AGC2I0); 2035 if (agc2 >= 0xff00) 2036 agc2_ovflw++; 2037 reg = STV090x_READ_DEMOD(state, DSTATUS2); 2038 if ((STV090x_GETFIELD_Px(reg, CFR_OVERFLOW_FIELD) == 0x01) && 2039 (STV090x_GETFIELD_Px(reg, DEMOD_DELOCK_FIELD) == 0x01)) 2040 2041 cpt_fail++; 2042 } 2043 if ((cpt_fail > 7) || (agc2_ovflw > 7)) 2044 coarse_fail = 1; 2045 2046 lock = 0; 2047 } 2048 k_ref -= 20; 2049 } while ((k_ref >= k_min) && (!lock) && (!coarse_fail)); 2050 } 2051 2052 return lock; 2053 2054 err: 2055 dprintk(FE_ERROR, 1, "I/O error"); 2056 return -1; 2057 } 2058 2059 static int stv090x_chk_tmg(struct stv090x_state *state) 2060 { 2061 u32 reg; 2062 s32 tmg_cpt = 0, i; 2063 u8 freq, tmg_thh, tmg_thl; 2064 int tmg_lock = 0; 2065 2066 freq = STV090x_READ_DEMOD(state, CARFREQ); 2067 tmg_thh = STV090x_READ_DEMOD(state, TMGTHRISE); 2068 tmg_thl = STV090x_READ_DEMOD(state, TMGTHFALL); 2069 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0) 2070 goto err; 2071 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0) 2072 goto err; 2073 2074 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 2075 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); /* stop carrier offset search */ 2076 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 2077 goto err; 2078 if (STV090x_WRITE_DEMOD(state, RTC, 0x80) < 0) 2079 goto err; 2080 2081 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x40) < 0) 2082 goto err; 2083 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x00) < 0) 2084 goto err; 2085 2086 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) /* set car ofset to 0 */ 2087 goto err; 2088 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0) 2089 goto err; 2090 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x65) < 0) 2091 goto err; 2092 2093 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* trigger acquisition */ 2094 goto err; 2095 msleep(10); 2096 2097 for (i = 0; i < 10; i++) { 2098 reg = STV090x_READ_DEMOD(state, DSTATUS); 2099 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2) 2100 tmg_cpt++; 2101 msleep(1); 2102 } 2103 if (tmg_cpt >= 3) 2104 tmg_lock = 1; 2105 2106 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) 2107 goto err; 2108 if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) /* DVB-S1 timing */ 2109 goto err; 2110 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) /* DVB-S2 timing */ 2111 goto err; 2112 2113 if (STV090x_WRITE_DEMOD(state, CARFREQ, freq) < 0) 2114 goto err; 2115 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, tmg_thh) < 0) 2116 goto err; 2117 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, tmg_thl) < 0) 2118 goto err; 2119 2120 return tmg_lock; 2121 2122 err: 2123 dprintk(FE_ERROR, 1, "I/O error"); 2124 return -1; 2125 } 2126 2127 static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd) 2128 { 2129 struct dvb_frontend *fe = &state->frontend; 2130 2131 u32 reg; 2132 s32 car_step, steps, cur_step, dir, freq, timeout_lock; 2133 int lock; 2134 2135 if (state->srate >= 10000000) 2136 timeout_lock = timeout_dmd / 3; 2137 else 2138 timeout_lock = timeout_dmd / 2; 2139 2140 lock = stv090x_get_dmdlock(state, timeout_lock); /* cold start wait */ 2141 if (lock) 2142 return lock; 2143 2144 if (state->srate >= 10000000) { 2145 if (stv090x_chk_tmg(state)) { 2146 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) 2147 goto err; 2148 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) 2149 goto err; 2150 return stv090x_get_dmdlock(state, timeout_dmd); 2151 } 2152 return 0; 2153 } 2154 2155 if (state->srate <= 4000000) 2156 car_step = 1000; 2157 else if (state->srate <= 7000000) 2158 car_step = 2000; 2159 else if (state->srate <= 10000000) 2160 car_step = 3000; 2161 else 2162 car_step = 5000; 2163 2164 steps = (state->search_range / 1000) / car_step; 2165 steps /= 2; 2166 steps = 2 * (steps + 1); 2167 if (steps < 0) 2168 steps = 2; 2169 else if (steps > 12) 2170 steps = 12; 2171 2172 cur_step = 1; 2173 dir = 1; 2174 2175 freq = state->frequency; 2176 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + state->srate; 2177 while ((cur_step <= steps) && (!lock)) { 2178 if (dir > 0) 2179 freq += cur_step * car_step; 2180 else 2181 freq -= cur_step * car_step; 2182 2183 /* Setup tuner */ 2184 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 2185 goto err; 2186 2187 if (state->config->tuner_set_frequency) { 2188 if (state->config->tuner_set_frequency(fe, freq) < 0) 2189 goto err_gateoff; 2190 } 2191 2192 if (state->config->tuner_set_bandwidth) { 2193 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0) 2194 goto err_gateoff; 2195 } 2196 2197 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 2198 goto err; 2199 2200 msleep(50); 2201 2202 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 2203 goto err; 2204 2205 if (state->config->tuner_get_status) { 2206 if (state->config->tuner_get_status(fe, ®) < 0) 2207 goto err_gateoff; 2208 if (reg) 2209 dprintk(FE_DEBUG, 1, "Tuner phase locked"); 2210 else 2211 dprintk(FE_DEBUG, 1, "Tuner unlocked"); 2212 } 2213 2214 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 2215 goto err; 2216 2217 STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c); 2218 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) 2219 goto err; 2220 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0) 2221 goto err; 2222 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) 2223 goto err; 2224 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) 2225 goto err; 2226 lock = stv090x_get_dmdlock(state, (timeout_dmd / 3)); 2227 2228 dir *= -1; 2229 cur_step++; 2230 } 2231 2232 return lock; 2233 2234 err_gateoff: 2235 stv090x_i2c_gate_ctrl(state, 0); 2236 err: 2237 dprintk(FE_ERROR, 1, "I/O error"); 2238 return -1; 2239 } 2240 2241 static int stv090x_get_loop_params(struct stv090x_state *state, s32 *freq_inc, s32 *timeout_sw, s32 *steps) 2242 { 2243 s32 timeout, inc, steps_max, srate, car_max; 2244 2245 srate = state->srate; 2246 car_max = state->search_range / 1000; 2247 car_max += car_max / 10; 2248 car_max = 65536 * (car_max / 2); 2249 car_max /= (state->internal->mclk / 1000); 2250 2251 if (car_max > 0x4000) 2252 car_max = 0x4000 ; /* maxcarrier should be<= +-1/4 Mclk */ 2253 2254 inc = srate; 2255 inc /= state->internal->mclk / 1000; 2256 inc *= 256; 2257 inc *= 256; 2258 inc /= 1000; 2259 2260 switch (state->search_mode) { 2261 case STV090x_SEARCH_DVBS1: 2262 case STV090x_SEARCH_DSS: 2263 inc *= 3; /* freq step = 3% of srate */ 2264 timeout = 20; 2265 break; 2266 2267 case STV090x_SEARCH_DVBS2: 2268 inc *= 4; 2269 timeout = 25; 2270 break; 2271 2272 case STV090x_SEARCH_AUTO: 2273 default: 2274 inc *= 3; 2275 timeout = 25; 2276 break; 2277 } 2278 inc /= 100; 2279 if ((inc > car_max) || (inc < 0)) 2280 inc = car_max / 2; /* increment <= 1/8 Mclk */ 2281 2282 timeout *= 27500; /* 27.5 Msps reference */ 2283 if (srate > 0) 2284 timeout /= (srate / 1000); 2285 2286 if ((timeout > 100) || (timeout < 0)) 2287 timeout = 100; 2288 2289 steps_max = (car_max / inc) + 1; /* min steps = 3 */ 2290 if ((steps_max > 100) || (steps_max < 0)) { 2291 steps_max = 100; /* max steps <= 100 */ 2292 inc = car_max / steps_max; 2293 } 2294 *freq_inc = inc; 2295 *timeout_sw = timeout; 2296 *steps = steps_max; 2297 2298 return 0; 2299 } 2300 2301 static int stv090x_chk_signal(struct stv090x_state *state) 2302 { 2303 s32 offst_car, agc2, car_max; 2304 int no_signal; 2305 2306 offst_car = STV090x_READ_DEMOD(state, CFR2) << 8; 2307 offst_car |= STV090x_READ_DEMOD(state, CFR1); 2308 offst_car = comp2(offst_car, 16); 2309 2310 agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8; 2311 agc2 |= STV090x_READ_DEMOD(state, AGC2I0); 2312 car_max = state->search_range / 1000; 2313 2314 car_max += (car_max / 10); /* 10% margin */ 2315 car_max = (65536 * car_max / 2); 2316 car_max /= state->internal->mclk / 1000; 2317 2318 if (car_max > 0x4000) 2319 car_max = 0x4000; 2320 2321 if ((agc2 > 0x2000) || (offst_car > 2 * car_max) || (offst_car < -2 * car_max)) { 2322 no_signal = 1; 2323 dprintk(FE_DEBUG, 1, "No Signal"); 2324 } else { 2325 no_signal = 0; 2326 dprintk(FE_DEBUG, 1, "Found Signal"); 2327 } 2328 2329 return no_signal; 2330 } 2331 2332 static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 timeout, int zigzag, s32 steps_max) 2333 { 2334 int no_signal, lock = 0; 2335 s32 cpt_step = 0, offst_freq, car_max; 2336 u32 reg; 2337 2338 car_max = state->search_range / 1000; 2339 car_max += (car_max / 10); 2340 car_max = (65536 * car_max / 2); 2341 car_max /= (state->internal->mclk / 1000); 2342 if (car_max > 0x4000) 2343 car_max = 0x4000; 2344 2345 if (zigzag) 2346 offst_freq = 0; 2347 else 2348 offst_freq = -car_max + inc; 2349 2350 do { 2351 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0) 2352 goto err; 2353 if (STV090x_WRITE_DEMOD(state, CFRINIT1, ((offst_freq / 256) & 0xff)) < 0) 2354 goto err; 2355 if (STV090x_WRITE_DEMOD(state, CFRINIT0, offst_freq & 0xff) < 0) 2356 goto err; 2357 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) 2358 goto err; 2359 2360 reg = STV090x_READ_DEMOD(state, PDELCTRL1); 2361 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x1); /* stop DVB-S2 packet delin */ 2362 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) 2363 goto err; 2364 2365 if (zigzag) { 2366 if (offst_freq >= 0) 2367 offst_freq = -offst_freq - 2 * inc; 2368 else 2369 offst_freq = -offst_freq; 2370 } else { 2371 offst_freq += 2 * inc; 2372 } 2373 2374 cpt_step++; 2375 2376 lock = stv090x_get_dmdlock(state, timeout); 2377 no_signal = stv090x_chk_signal(state); 2378 2379 } while ((!lock) && 2380 (!no_signal) && 2381 ((offst_freq - inc) < car_max) && 2382 ((offst_freq + inc) > -car_max) && 2383 (cpt_step < steps_max)); 2384 2385 reg = STV090x_READ_DEMOD(state, PDELCTRL1); 2386 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0); 2387 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) 2388 goto err; 2389 2390 return lock; 2391 err: 2392 dprintk(FE_ERROR, 1, "I/O error"); 2393 return -1; 2394 } 2395 2396 static int stv090x_sw_algo(struct stv090x_state *state) 2397 { 2398 int no_signal, zigzag, lock = 0; 2399 u32 reg; 2400 2401 s32 dvbs2_fly_wheel; 2402 s32 inc, timeout_step, trials, steps_max; 2403 2404 /* get params */ 2405 stv090x_get_loop_params(state, &inc, &timeout_step, &steps_max); 2406 2407 switch (state->search_mode) { 2408 case STV090x_SEARCH_DVBS1: 2409 case STV090x_SEARCH_DSS: 2410 /* accelerate the frequency detector */ 2411 if (state->internal->dev_ver >= 0x20) { 2412 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3B) < 0) 2413 goto err; 2414 } 2415 2416 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x49) < 0) 2417 goto err; 2418 zigzag = 0; 2419 break; 2420 2421 case STV090x_SEARCH_DVBS2: 2422 if (state->internal->dev_ver >= 0x20) { 2423 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0) 2424 goto err; 2425 } 2426 2427 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0) 2428 goto err; 2429 zigzag = 1; 2430 break; 2431 2432 case STV090x_SEARCH_AUTO: 2433 default: 2434 /* accelerate the frequency detector */ 2435 if (state->internal->dev_ver >= 0x20) { 2436 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3b) < 0) 2437 goto err; 2438 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0) 2439 goto err; 2440 } 2441 2442 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0xc9) < 0) 2443 goto err; 2444 zigzag = 0; 2445 break; 2446 } 2447 2448 trials = 0; 2449 do { 2450 lock = stv090x_search_car_loop(state, inc, timeout_step, zigzag, steps_max); 2451 no_signal = stv090x_chk_signal(state); 2452 trials++; 2453 2454 /*run the SW search 2 times maximum*/ 2455 if (lock || no_signal || (trials == 2)) { 2456 /*Check if the demod is not losing lock in DVBS2*/ 2457 if (state->internal->dev_ver >= 0x20) { 2458 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0) 2459 goto err; 2460 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0) 2461 goto err; 2462 } 2463 2464 reg = STV090x_READ_DEMOD(state, DMDSTATE); 2465 if ((lock) && (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == STV090x_DVBS2)) { 2466 /*Check if the demod is not losing lock in DVBS2*/ 2467 msleep(timeout_step); 2468 reg = STV090x_READ_DEMOD(state, DMDFLYW); 2469 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD); 2470 if (dvbs2_fly_wheel < 0xd) { /*if correct frames is decrementing */ 2471 msleep(timeout_step); 2472 reg = STV090x_READ_DEMOD(state, DMDFLYW); 2473 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD); 2474 } 2475 if (dvbs2_fly_wheel < 0xd) { 2476 /*FALSE lock, The demod is losing lock */ 2477 lock = 0; 2478 if (trials < 2) { 2479 if (state->internal->dev_ver >= 0x20) { 2480 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0) 2481 goto err; 2482 } 2483 2484 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0) 2485 goto err; 2486 } 2487 } 2488 } 2489 } 2490 } while ((!lock) && (trials < 2) && (!no_signal)); 2491 2492 return lock; 2493 err: 2494 dprintk(FE_ERROR, 1, "I/O error"); 2495 return -1; 2496 } 2497 2498 static enum stv090x_delsys stv090x_get_std(struct stv090x_state *state) 2499 { 2500 u32 reg; 2501 enum stv090x_delsys delsys; 2502 2503 reg = STV090x_READ_DEMOD(state, DMDSTATE); 2504 if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 2) 2505 delsys = STV090x_DVBS2; 2506 else if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) { 2507 reg = STV090x_READ_DEMOD(state, FECM); 2508 if (STV090x_GETFIELD_Px(reg, DSS_DVB_FIELD) == 1) 2509 delsys = STV090x_DSS; 2510 else 2511 delsys = STV090x_DVBS1; 2512 } else { 2513 delsys = STV090x_ERROR; 2514 } 2515 2516 return delsys; 2517 } 2518 2519 /* in Hz */ 2520 static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk) 2521 { 2522 s32 derot, int_1, int_2, tmp_1, tmp_2; 2523 2524 derot = STV090x_READ_DEMOD(state, CFR2) << 16; 2525 derot |= STV090x_READ_DEMOD(state, CFR1) << 8; 2526 derot |= STV090x_READ_DEMOD(state, CFR0); 2527 2528 derot = comp2(derot, 24); 2529 int_1 = mclk >> 12; 2530 int_2 = derot >> 12; 2531 2532 /* carrier_frequency = MasterClock * Reg / 2^24 */ 2533 tmp_1 = mclk % 0x1000; 2534 tmp_2 = derot % 0x1000; 2535 2536 derot = (int_1 * int_2) + 2537 ((int_1 * tmp_2) >> 12) + 2538 ((int_2 * tmp_1) >> 12); 2539 2540 return derot; 2541 } 2542 2543 static int stv090x_get_viterbi(struct stv090x_state *state) 2544 { 2545 u32 reg, rate; 2546 2547 reg = STV090x_READ_DEMOD(state, VITCURPUN); 2548 rate = STV090x_GETFIELD_Px(reg, VIT_CURPUN_FIELD); 2549 2550 switch (rate) { 2551 case 13: 2552 state->fec = STV090x_PR12; 2553 break; 2554 2555 case 18: 2556 state->fec = STV090x_PR23; 2557 break; 2558 2559 case 21: 2560 state->fec = STV090x_PR34; 2561 break; 2562 2563 case 24: 2564 state->fec = STV090x_PR56; 2565 break; 2566 2567 case 25: 2568 state->fec = STV090x_PR67; 2569 break; 2570 2571 case 26: 2572 state->fec = STV090x_PR78; 2573 break; 2574 2575 default: 2576 state->fec = STV090x_PRERR; 2577 break; 2578 } 2579 2580 return 0; 2581 } 2582 2583 static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *state) 2584 { 2585 struct dvb_frontend *fe = &state->frontend; 2586 2587 u8 tmg; 2588 u32 reg; 2589 s32 i = 0, offst_freq; 2590 2591 msleep(5); 2592 2593 if (state->algo == STV090x_BLIND_SEARCH) { 2594 tmg = STV090x_READ_DEMOD(state, TMGREG2); 2595 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x5c); 2596 while ((i <= 50) && (tmg != 0) && (tmg != 0xff)) { 2597 tmg = STV090x_READ_DEMOD(state, TMGREG2); 2598 msleep(5); 2599 i += 5; 2600 } 2601 } 2602 state->delsys = stv090x_get_std(state); 2603 2604 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 2605 goto err; 2606 2607 if (state->config->tuner_get_frequency) { 2608 if (state->config->tuner_get_frequency(fe, &state->frequency) < 0) 2609 goto err_gateoff; 2610 } 2611 2612 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 2613 goto err; 2614 2615 offst_freq = stv090x_get_car_freq(state, state->internal->mclk) / 1000; 2616 state->frequency += offst_freq; 2617 2618 if (stv090x_get_viterbi(state) < 0) 2619 goto err; 2620 2621 reg = STV090x_READ_DEMOD(state, DMDMODCOD); 2622 state->modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD); 2623 state->pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01; 2624 state->frame_len = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) >> 1; 2625 reg = STV090x_READ_DEMOD(state, TMGOBS); 2626 state->rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD); 2627 reg = STV090x_READ_DEMOD(state, FECM); 2628 state->inversion = STV090x_GETFIELD_Px(reg, IQINV_FIELD); 2629 2630 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) { 2631 2632 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 2633 goto err; 2634 2635 if (state->config->tuner_get_frequency) { 2636 if (state->config->tuner_get_frequency(fe, &state->frequency) < 0) 2637 goto err_gateoff; 2638 } 2639 2640 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 2641 goto err; 2642 2643 if (abs(offst_freq) <= ((state->search_range / 2000) + 500)) 2644 return STV090x_RANGEOK; 2645 else if (abs(offst_freq) <= (stv090x_car_width(state->srate, state->rolloff) / 2000)) 2646 return STV090x_RANGEOK; 2647 } else { 2648 if (abs(offst_freq) <= ((state->search_range / 2000) + 500)) 2649 return STV090x_RANGEOK; 2650 } 2651 2652 return STV090x_OUTOFRANGE; 2653 2654 err_gateoff: 2655 stv090x_i2c_gate_ctrl(state, 0); 2656 err: 2657 dprintk(FE_ERROR, 1, "I/O error"); 2658 return -1; 2659 } 2660 2661 static u32 stv090x_get_tmgoffst(struct stv090x_state *state, u32 srate) 2662 { 2663 s32 offst_tmg; 2664 2665 offst_tmg = STV090x_READ_DEMOD(state, TMGREG2) << 16; 2666 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG1) << 8; 2667 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG0); 2668 2669 offst_tmg = comp2(offst_tmg, 24); /* 2's complement */ 2670 if (!offst_tmg) 2671 offst_tmg = 1; 2672 2673 offst_tmg = ((s32) srate * 10) / ((s32) 0x1000000 / offst_tmg); 2674 offst_tmg /= 320; 2675 2676 return offst_tmg; 2677 } 2678 2679 static u8 stv090x_optimize_carloop(struct stv090x_state *state, enum stv090x_modcod modcod, s32 pilots) 2680 { 2681 u8 aclc = 0x29; 2682 s32 i; 2683 struct stv090x_long_frame_crloop *car_loop, *car_loop_qpsk_low, *car_loop_apsk_low; 2684 2685 if (state->internal->dev_ver == 0x20) { 2686 car_loop = stv090x_s2_crl_cut20; 2687 car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut20; 2688 car_loop_apsk_low = stv090x_s2_apsk_crl_cut20; 2689 } else { 2690 /* >= Cut 3 */ 2691 car_loop = stv090x_s2_crl_cut30; 2692 car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut30; 2693 car_loop_apsk_low = stv090x_s2_apsk_crl_cut30; 2694 } 2695 2696 if (modcod < STV090x_QPSK_12) { 2697 i = 0; 2698 while ((i < 3) && (modcod != car_loop_qpsk_low[i].modcod)) 2699 i++; 2700 2701 if (i >= 3) 2702 i = 2; 2703 2704 } else { 2705 i = 0; 2706 while ((i < 14) && (modcod != car_loop[i].modcod)) 2707 i++; 2708 2709 if (i >= 14) { 2710 i = 0; 2711 while ((i < 11) && (modcod != car_loop_apsk_low[i].modcod)) 2712 i++; 2713 2714 if (i >= 11) 2715 i = 10; 2716 } 2717 } 2718 2719 if (modcod <= STV090x_QPSK_25) { 2720 if (pilots) { 2721 if (state->srate <= 3000000) 2722 aclc = car_loop_qpsk_low[i].crl_pilots_on_2; 2723 else if (state->srate <= 7000000) 2724 aclc = car_loop_qpsk_low[i].crl_pilots_on_5; 2725 else if (state->srate <= 15000000) 2726 aclc = car_loop_qpsk_low[i].crl_pilots_on_10; 2727 else if (state->srate <= 25000000) 2728 aclc = car_loop_qpsk_low[i].crl_pilots_on_20; 2729 else 2730 aclc = car_loop_qpsk_low[i].crl_pilots_on_30; 2731 } else { 2732 if (state->srate <= 3000000) 2733 aclc = car_loop_qpsk_low[i].crl_pilots_off_2; 2734 else if (state->srate <= 7000000) 2735 aclc = car_loop_qpsk_low[i].crl_pilots_off_5; 2736 else if (state->srate <= 15000000) 2737 aclc = car_loop_qpsk_low[i].crl_pilots_off_10; 2738 else if (state->srate <= 25000000) 2739 aclc = car_loop_qpsk_low[i].crl_pilots_off_20; 2740 else 2741 aclc = car_loop_qpsk_low[i].crl_pilots_off_30; 2742 } 2743 2744 } else if (modcod <= STV090x_8PSK_910) { 2745 if (pilots) { 2746 if (state->srate <= 3000000) 2747 aclc = car_loop[i].crl_pilots_on_2; 2748 else if (state->srate <= 7000000) 2749 aclc = car_loop[i].crl_pilots_on_5; 2750 else if (state->srate <= 15000000) 2751 aclc = car_loop[i].crl_pilots_on_10; 2752 else if (state->srate <= 25000000) 2753 aclc = car_loop[i].crl_pilots_on_20; 2754 else 2755 aclc = car_loop[i].crl_pilots_on_30; 2756 } else { 2757 if (state->srate <= 3000000) 2758 aclc = car_loop[i].crl_pilots_off_2; 2759 else if (state->srate <= 7000000) 2760 aclc = car_loop[i].crl_pilots_off_5; 2761 else if (state->srate <= 15000000) 2762 aclc = car_loop[i].crl_pilots_off_10; 2763 else if (state->srate <= 25000000) 2764 aclc = car_loop[i].crl_pilots_off_20; 2765 else 2766 aclc = car_loop[i].crl_pilots_off_30; 2767 } 2768 } else { /* 16APSK and 32APSK */ 2769 /* 2770 * This should never happen in practice, except if 2771 * something is really wrong at the car_loop table. 2772 */ 2773 if (i >= 11) 2774 i = 10; 2775 if (state->srate <= 3000000) 2776 aclc = car_loop_apsk_low[i].crl_pilots_on_2; 2777 else if (state->srate <= 7000000) 2778 aclc = car_loop_apsk_low[i].crl_pilots_on_5; 2779 else if (state->srate <= 15000000) 2780 aclc = car_loop_apsk_low[i].crl_pilots_on_10; 2781 else if (state->srate <= 25000000) 2782 aclc = car_loop_apsk_low[i].crl_pilots_on_20; 2783 else 2784 aclc = car_loop_apsk_low[i].crl_pilots_on_30; 2785 } 2786 2787 return aclc; 2788 } 2789 2790 static u8 stv090x_optimize_carloop_short(struct stv090x_state *state) 2791 { 2792 struct stv090x_short_frame_crloop *short_crl = NULL; 2793 s32 index = 0; 2794 u8 aclc = 0x0b; 2795 2796 switch (state->modulation) { 2797 case STV090x_QPSK: 2798 default: 2799 index = 0; 2800 break; 2801 case STV090x_8PSK: 2802 index = 1; 2803 break; 2804 case STV090x_16APSK: 2805 index = 2; 2806 break; 2807 case STV090x_32APSK: 2808 index = 3; 2809 break; 2810 } 2811 2812 if (state->internal->dev_ver >= 0x30) { 2813 /* Cut 3.0 and up */ 2814 short_crl = stv090x_s2_short_crl_cut30; 2815 } else { 2816 /* Cut 2.0 and up: we don't support cuts older than 2.0 */ 2817 short_crl = stv090x_s2_short_crl_cut20; 2818 } 2819 2820 if (state->srate <= 3000000) 2821 aclc = short_crl[index].crl_2; 2822 else if (state->srate <= 7000000) 2823 aclc = short_crl[index].crl_5; 2824 else if (state->srate <= 15000000) 2825 aclc = short_crl[index].crl_10; 2826 else if (state->srate <= 25000000) 2827 aclc = short_crl[index].crl_20; 2828 else 2829 aclc = short_crl[index].crl_30; 2830 2831 return aclc; 2832 } 2833 2834 static int stv090x_optimize_track(struct stv090x_state *state) 2835 { 2836 struct dvb_frontend *fe = &state->frontend; 2837 2838 enum stv090x_modcod modcod; 2839 2840 s32 srate, pilots, aclc, f_1, f_0, i = 0, blind_tune = 0; 2841 u32 reg; 2842 2843 srate = stv090x_get_srate(state, state->internal->mclk); 2844 srate += stv090x_get_tmgoffst(state, srate); 2845 2846 switch (state->delsys) { 2847 case STV090x_DVBS1: 2848 case STV090x_DSS: 2849 if (state->search_mode == STV090x_SEARCH_AUTO) { 2850 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 2851 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); 2852 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0); 2853 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 2854 goto err; 2855 } 2856 reg = STV090x_READ_DEMOD(state, DEMOD); 2857 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff); 2858 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x01); 2859 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) 2860 goto err; 2861 2862 if (state->internal->dev_ver >= 0x30) { 2863 if (stv090x_get_viterbi(state) < 0) 2864 goto err; 2865 2866 if (state->fec == STV090x_PR12) { 2867 if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x98) < 0) 2868 goto err; 2869 if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0) 2870 goto err; 2871 } else { 2872 if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x18) < 0) 2873 goto err; 2874 if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0) 2875 goto err; 2876 } 2877 } 2878 2879 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0) 2880 goto err; 2881 break; 2882 2883 case STV090x_DVBS2: 2884 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 2885 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0); 2886 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1); 2887 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 2888 goto err; 2889 if (state->internal->dev_ver >= 0x30) { 2890 if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0) 2891 goto err; 2892 if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0) 2893 goto err; 2894 } 2895 if (state->frame_len == STV090x_LONG_FRAME) { 2896 reg = STV090x_READ_DEMOD(state, DMDMODCOD); 2897 modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD); 2898 pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01; 2899 aclc = stv090x_optimize_carloop(state, modcod, pilots); 2900 if (modcod <= STV090x_QPSK_910) { 2901 STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc); 2902 } else if (modcod <= STV090x_8PSK_910) { 2903 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) 2904 goto err; 2905 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0) 2906 goto err; 2907 } 2908 if ((state->demod_mode == STV090x_SINGLE) && (modcod > STV090x_8PSK_910)) { 2909 if (modcod <= STV090x_16APSK_910) { 2910 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) 2911 goto err; 2912 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0) 2913 goto err; 2914 } else { 2915 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) 2916 goto err; 2917 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0) 2918 goto err; 2919 } 2920 } 2921 } else { 2922 /*Carrier loop setting for short frame*/ 2923 aclc = stv090x_optimize_carloop_short(state); 2924 if (state->modulation == STV090x_QPSK) { 2925 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc) < 0) 2926 goto err; 2927 } else if (state->modulation == STV090x_8PSK) { 2928 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) 2929 goto err; 2930 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0) 2931 goto err; 2932 } else if (state->modulation == STV090x_16APSK) { 2933 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) 2934 goto err; 2935 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0) 2936 goto err; 2937 } else if (state->modulation == STV090x_32APSK) { 2938 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) 2939 goto err; 2940 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0) 2941 goto err; 2942 } 2943 } 2944 2945 STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67); /* PER */ 2946 break; 2947 2948 case STV090x_ERROR: 2949 default: 2950 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 2951 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); 2952 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1); 2953 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 2954 goto err; 2955 break; 2956 } 2957 2958 f_1 = STV090x_READ_DEMOD(state, CFR2); 2959 f_0 = STV090x_READ_DEMOD(state, CFR1); 2960 reg = STV090x_READ_DEMOD(state, TMGOBS); 2961 2962 if (state->algo == STV090x_BLIND_SEARCH) { 2963 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00); 2964 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 2965 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0x00); 2966 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); 2967 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 2968 goto err; 2969 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) 2970 goto err; 2971 2972 if (stv090x_set_srate(state, srate) < 0) 2973 goto err; 2974 blind_tune = 1; 2975 2976 if (stv090x_dvbs_track_crl(state) < 0) 2977 goto err; 2978 } 2979 2980 if (state->internal->dev_ver >= 0x20) { 2981 if ((state->search_mode == STV090x_SEARCH_DVBS1) || 2982 (state->search_mode == STV090x_SEARCH_DSS) || 2983 (state->search_mode == STV090x_SEARCH_AUTO)) { 2984 2985 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x0a) < 0) 2986 goto err; 2987 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x00) < 0) 2988 goto err; 2989 } 2990 } 2991 2992 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) 2993 goto err; 2994 2995 /* AUTO tracking MODE */ 2996 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x80) < 0) 2997 goto err; 2998 /* AUTO tracking MODE */ 2999 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x80) < 0) 3000 goto err; 3001 3002 if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1) || 3003 (state->srate < 10000000)) { 3004 /* update initial carrier freq with the found freq offset */ 3005 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0) 3006 goto err; 3007 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0) 3008 goto err; 3009 state->tuner_bw = stv090x_car_width(srate, state->rolloff) + 10000000; 3010 3011 if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1)) { 3012 3013 if (state->algo != STV090x_WARM_SEARCH) { 3014 3015 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 3016 goto err; 3017 3018 if (state->config->tuner_set_bandwidth) { 3019 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0) 3020 goto err_gateoff; 3021 } 3022 3023 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 3024 goto err; 3025 3026 } 3027 } 3028 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) 3029 msleep(50); /* blind search: wait 50ms for SR stabilization */ 3030 else 3031 msleep(5); 3032 3033 stv090x_get_lock_tmg(state); 3034 3035 if (!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) { 3036 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) 3037 goto err; 3038 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0) 3039 goto err; 3040 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0) 3041 goto err; 3042 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) 3043 goto err; 3044 3045 i = 0; 3046 3047 while ((!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) && (i <= 2)) { 3048 3049 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) 3050 goto err; 3051 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0) 3052 goto err; 3053 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0) 3054 goto err; 3055 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) 3056 goto err; 3057 i++; 3058 } 3059 } 3060 3061 } 3062 3063 if (state->internal->dev_ver >= 0x20) { 3064 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0) 3065 goto err; 3066 } 3067 3068 if ((state->delsys == STV090x_DVBS1) || (state->delsys == STV090x_DSS)) 3069 stv090x_set_vit_thtracq(state); 3070 3071 return 0; 3072 3073 err_gateoff: 3074 stv090x_i2c_gate_ctrl(state, 0); 3075 err: 3076 dprintk(FE_ERROR, 1, "I/O error"); 3077 return -1; 3078 } 3079 3080 static int stv090x_get_feclock(struct stv090x_state *state, s32 timeout) 3081 { 3082 s32 timer = 0, lock = 0, stat; 3083 u32 reg; 3084 3085 while ((timer < timeout) && (!lock)) { 3086 reg = STV090x_READ_DEMOD(state, DMDSTATE); 3087 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD); 3088 3089 switch (stat) { 3090 case 0: /* searching */ 3091 case 1: /* first PLH detected */ 3092 default: 3093 lock = 0; 3094 break; 3095 3096 case 2: /* DVB-S2 mode */ 3097 reg = STV090x_READ_DEMOD(state, PDELSTATUS1); 3098 lock = STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD); 3099 break; 3100 3101 case 3: /* DVB-S1/legacy mode */ 3102 reg = STV090x_READ_DEMOD(state, VSTATUSVIT); 3103 lock = STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD); 3104 break; 3105 } 3106 if (!lock) { 3107 msleep(10); 3108 timer += 10; 3109 } 3110 } 3111 return lock; 3112 } 3113 3114 static int stv090x_get_lock(struct stv090x_state *state, s32 timeout_dmd, s32 timeout_fec) 3115 { 3116 u32 reg; 3117 s32 timer = 0; 3118 int lock; 3119 3120 lock = stv090x_get_dmdlock(state, timeout_dmd); 3121 if (lock) 3122 lock = stv090x_get_feclock(state, timeout_fec); 3123 3124 if (lock) { 3125 lock = 0; 3126 3127 while ((timer < timeout_fec) && (!lock)) { 3128 reg = STV090x_READ_DEMOD(state, TSSTATUS); 3129 lock = STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD); 3130 msleep(1); 3131 timer++; 3132 } 3133 } 3134 3135 return lock; 3136 } 3137 3138 static int stv090x_set_s2rolloff(struct stv090x_state *state) 3139 { 3140 u32 reg; 3141 3142 if (state->internal->dev_ver <= 0x20) { 3143 /* rolloff to auto mode if DVBS2 */ 3144 reg = STV090x_READ_DEMOD(state, DEMOD); 3145 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x00); 3146 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) 3147 goto err; 3148 } else { 3149 /* DVB-S2 rolloff to auto mode if DVBS2 */ 3150 reg = STV090x_READ_DEMOD(state, DEMOD); 3151 STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 0x00); 3152 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) 3153 goto err; 3154 } 3155 return 0; 3156 err: 3157 dprintk(FE_ERROR, 1, "I/O error"); 3158 return -1; 3159 } 3160 3161 3162 static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state) 3163 { 3164 struct dvb_frontend *fe = &state->frontend; 3165 enum stv090x_signal_state signal_state = STV090x_NOCARRIER; 3166 u32 reg; 3167 s32 agc1_power, power_iq = 0, i; 3168 int lock = 0, low_sr = 0; 3169 3170 reg = STV090x_READ_DEMOD(state, TSCFGH); 3171 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* Stop path 1 stream merger */ 3172 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0) 3173 goto err; 3174 3175 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod stop */ 3176 goto err; 3177 3178 if (state->internal->dev_ver >= 0x20) { 3179 if (state->srate > 5000000) { 3180 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0) 3181 goto err; 3182 } else { 3183 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x82) < 0) 3184 goto err; 3185 } 3186 } 3187 3188 stv090x_get_lock_tmg(state); 3189 3190 if (state->algo == STV090x_BLIND_SEARCH) { 3191 state->tuner_bw = 2 * 36000000; /* wide bw for unknown srate */ 3192 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0) /* wider srate scan */ 3193 goto err; 3194 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0) 3195 goto err; 3196 if (stv090x_set_srate(state, 1000000) < 0) /* initial srate = 1Msps */ 3197 goto err; 3198 } else { 3199 /* known srate */ 3200 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0) 3201 goto err; 3202 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0) 3203 goto err; 3204 3205 if (state->srate < 2000000) { 3206 /* SR < 2MSPS */ 3207 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x63) < 0) 3208 goto err; 3209 } else { 3210 /* SR >= 2Msps */ 3211 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0) 3212 goto err; 3213 } 3214 3215 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) 3216 goto err; 3217 3218 if (state->internal->dev_ver >= 0x20) { 3219 if (STV090x_WRITE_DEMOD(state, KREFTMG, 0x5a) < 0) 3220 goto err; 3221 if (state->algo == STV090x_COLD_SEARCH) 3222 state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 10000000)) / 10; 3223 else if (state->algo == STV090x_WARM_SEARCH) 3224 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + 10000000; 3225 } 3226 3227 /* if cold start or warm (Symbolrate is known) 3228 * use a Narrow symbol rate scan range 3229 */ 3230 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) /* narrow srate scan */ 3231 goto err; 3232 3233 if (stv090x_set_srate(state, state->srate) < 0) 3234 goto err; 3235 3236 if (stv090x_set_max_srate(state, state->internal->mclk, 3237 state->srate) < 0) 3238 goto err; 3239 if (stv090x_set_min_srate(state, state->internal->mclk, 3240 state->srate) < 0) 3241 goto err; 3242 3243 if (state->srate >= 10000000) 3244 low_sr = 0; 3245 else 3246 low_sr = 1; 3247 } 3248 3249 /* Setup tuner */ 3250 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 3251 goto err; 3252 3253 if (state->config->tuner_set_bbgain) { 3254 reg = state->config->tuner_bbgain; 3255 if (reg == 0) 3256 reg = 10; /* default: 10dB */ 3257 if (state->config->tuner_set_bbgain(fe, reg) < 0) 3258 goto err_gateoff; 3259 } 3260 3261 if (state->config->tuner_set_frequency) { 3262 if (state->config->tuner_set_frequency(fe, state->frequency) < 0) 3263 goto err_gateoff; 3264 } 3265 3266 if (state->config->tuner_set_bandwidth) { 3267 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0) 3268 goto err_gateoff; 3269 } 3270 3271 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 3272 goto err; 3273 3274 msleep(50); 3275 3276 if (state->config->tuner_get_status) { 3277 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 3278 goto err; 3279 if (state->config->tuner_get_status(fe, ®) < 0) 3280 goto err_gateoff; 3281 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 3282 goto err; 3283 3284 if (reg) 3285 dprintk(FE_DEBUG, 1, "Tuner phase locked"); 3286 else { 3287 dprintk(FE_DEBUG, 1, "Tuner unlocked"); 3288 return STV090x_NOCARRIER; 3289 } 3290 } 3291 3292 msleep(10); 3293 agc1_power = MAKEWORD16(STV090x_READ_DEMOD(state, AGCIQIN1), 3294 STV090x_READ_DEMOD(state, AGCIQIN0)); 3295 3296 if (agc1_power == 0) { 3297 /* If AGC1 integrator value is 0 3298 * then read POWERI, POWERQ 3299 */ 3300 for (i = 0; i < 5; i++) { 3301 power_iq += (STV090x_READ_DEMOD(state, POWERI) + 3302 STV090x_READ_DEMOD(state, POWERQ)) >> 1; 3303 } 3304 power_iq /= 5; 3305 } 3306 3307 if ((agc1_power == 0) && (power_iq < STV090x_IQPOWER_THRESHOLD)) { 3308 dprintk(FE_ERROR, 1, "No Signal: POWER_IQ=0x%02x", power_iq); 3309 lock = 0; 3310 signal_state = STV090x_NOAGC1; 3311 } else { 3312 reg = STV090x_READ_DEMOD(state, DEMOD); 3313 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion); 3314 3315 if (state->internal->dev_ver <= 0x20) { 3316 /* rolloff to auto mode if DVBS2 */ 3317 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 1); 3318 } else { 3319 /* DVB-S2 rolloff to auto mode if DVBS2 */ 3320 STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 1); 3321 } 3322 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) 3323 goto err; 3324 3325 if (stv090x_delivery_search(state) < 0) 3326 goto err; 3327 3328 if (state->algo != STV090x_BLIND_SEARCH) { 3329 if (stv090x_start_search(state) < 0) 3330 goto err; 3331 } 3332 } 3333 3334 if (signal_state == STV090x_NOAGC1) 3335 return signal_state; 3336 3337 if (state->algo == STV090x_BLIND_SEARCH) 3338 lock = stv090x_blind_search(state); 3339 3340 else if (state->algo == STV090x_COLD_SEARCH) 3341 lock = stv090x_get_coldlock(state, state->DemodTimeout); 3342 3343 else if (state->algo == STV090x_WARM_SEARCH) 3344 lock = stv090x_get_dmdlock(state, state->DemodTimeout); 3345 3346 if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) { 3347 if (!low_sr) { 3348 if (stv090x_chk_tmg(state)) 3349 lock = stv090x_sw_algo(state); 3350 } 3351 } 3352 3353 if (lock) 3354 signal_state = stv090x_get_sig_params(state); 3355 3356 if ((lock) && (signal_state == STV090x_RANGEOK)) { /* signal within Range */ 3357 stv090x_optimize_track(state); 3358 3359 if (state->internal->dev_ver >= 0x20) { 3360 /* >= Cut 2.0 :release TS reset after 3361 * demod lock and optimized Tracking 3362 */ 3363 reg = STV090x_READ_DEMOD(state, TSCFGH); 3364 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */ 3365 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0) 3366 goto err; 3367 3368 msleep(3); 3369 3370 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */ 3371 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0) 3372 goto err; 3373 3374 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */ 3375 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0) 3376 goto err; 3377 } 3378 3379 lock = stv090x_get_lock(state, state->FecTimeout, 3380 state->FecTimeout); 3381 if (lock) { 3382 if (state->delsys == STV090x_DVBS2) { 3383 stv090x_set_s2rolloff(state); 3384 3385 reg = STV090x_READ_DEMOD(state, PDELCTRL2); 3386 STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 1); 3387 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0) 3388 goto err; 3389 /* Reset DVBS2 packet delinator error counter */ 3390 reg = STV090x_READ_DEMOD(state, PDELCTRL2); 3391 STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 0); 3392 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0) 3393 goto err; 3394 3395 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67) < 0) /* PER */ 3396 goto err; 3397 } else { 3398 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0) 3399 goto err; 3400 } 3401 /* Reset the Total packet counter */ 3402 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0x00) < 0) 3403 goto err; 3404 /* Reset the packet Error counter2 */ 3405 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0) 3406 goto err; 3407 } else { 3408 signal_state = STV090x_NODATA; 3409 stv090x_chk_signal(state); 3410 } 3411 } 3412 return signal_state; 3413 3414 err_gateoff: 3415 stv090x_i2c_gate_ctrl(state, 0); 3416 err: 3417 dprintk(FE_ERROR, 1, "I/O error"); 3418 return -1; 3419 } 3420 3421 static int stv090x_set_pls(struct stv090x_state *state, u32 pls_code) 3422 { 3423 dprintk(FE_DEBUG, 1, "Set Gold PLS code %d", pls_code); 3424 if (STV090x_WRITE_DEMOD(state, PLROOT0, pls_code & 0xff) < 0) 3425 goto err; 3426 if (STV090x_WRITE_DEMOD(state, PLROOT1, (pls_code >> 8) & 0xff) < 0) 3427 goto err; 3428 if (STV090x_WRITE_DEMOD(state, PLROOT2, 0x04 | (pls_code >> 16)) < 0) 3429 goto err; 3430 return 0; 3431 err: 3432 dprintk(FE_ERROR, 1, "I/O error"); 3433 return -1; 3434 } 3435 3436 static int stv090x_set_mis(struct stv090x_state *state, int mis) 3437 { 3438 u32 reg; 3439 3440 if (mis < 0 || mis > 255) { 3441 dprintk(FE_DEBUG, 1, "Disable MIS filtering"); 3442 reg = STV090x_READ_DEMOD(state, PDELCTRL1); 3443 STV090x_SETFIELD_Px(reg, FILTER_EN_FIELD, 0x00); 3444 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) 3445 goto err; 3446 } else { 3447 dprintk(FE_DEBUG, 1, "Enable MIS filtering - %d", mis); 3448 reg = STV090x_READ_DEMOD(state, PDELCTRL1); 3449 STV090x_SETFIELD_Px(reg, FILTER_EN_FIELD, 0x01); 3450 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) 3451 goto err; 3452 if (STV090x_WRITE_DEMOD(state, ISIENTRY, mis) < 0) 3453 goto err; 3454 if (STV090x_WRITE_DEMOD(state, ISIBITENA, 0xff) < 0) 3455 goto err; 3456 } 3457 return 0; 3458 err: 3459 dprintk(FE_ERROR, 1, "I/O error"); 3460 return -1; 3461 } 3462 3463 static enum dvbfe_search stv090x_search(struct dvb_frontend *fe) 3464 { 3465 struct stv090x_state *state = fe->demodulator_priv; 3466 struct dtv_frontend_properties *props = &fe->dtv_property_cache; 3467 3468 if (props->frequency == 0) 3469 return DVBFE_ALGO_SEARCH_INVALID; 3470 3471 switch (props->delivery_system) { 3472 case SYS_DSS: 3473 state->delsys = STV090x_DSS; 3474 break; 3475 case SYS_DVBS: 3476 state->delsys = STV090x_DVBS1; 3477 break; 3478 case SYS_DVBS2: 3479 state->delsys = STV090x_DVBS2; 3480 break; 3481 default: 3482 return DVBFE_ALGO_SEARCH_INVALID; 3483 } 3484 3485 state->frequency = props->frequency; 3486 state->srate = props->symbol_rate; 3487 state->search_mode = STV090x_SEARCH_AUTO; 3488 state->algo = STV090x_COLD_SEARCH; 3489 state->fec = STV090x_PRERR; 3490 if (state->srate > 10000000) { 3491 dprintk(FE_DEBUG, 1, "Search range: 10 MHz"); 3492 state->search_range = 10000000; 3493 } else { 3494 dprintk(FE_DEBUG, 1, "Search range: 5 MHz"); 3495 state->search_range = 5000000; 3496 } 3497 3498 stv090x_set_pls(state, props->scrambling_sequence_index); 3499 stv090x_set_mis(state, props->stream_id); 3500 3501 if (stv090x_algo(state) == STV090x_RANGEOK) { 3502 dprintk(FE_DEBUG, 1, "Search success!"); 3503 return DVBFE_ALGO_SEARCH_SUCCESS; 3504 } else { 3505 dprintk(FE_DEBUG, 1, "Search failed!"); 3506 return DVBFE_ALGO_SEARCH_FAILED; 3507 } 3508 3509 return DVBFE_ALGO_SEARCH_ERROR; 3510 } 3511 3512 static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status) 3513 { 3514 struct stv090x_state *state = fe->demodulator_priv; 3515 u32 reg, dstatus; 3516 u8 search_state; 3517 3518 *status = 0; 3519 3520 dstatus = STV090x_READ_DEMOD(state, DSTATUS); 3521 if (STV090x_GETFIELD_Px(dstatus, CAR_LOCK_FIELD)) 3522 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER; 3523 3524 reg = STV090x_READ_DEMOD(state, DMDSTATE); 3525 search_state = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD); 3526 3527 switch (search_state) { 3528 case 0: /* searching */ 3529 case 1: /* first PLH detected */ 3530 default: 3531 dprintk(FE_DEBUG, 1, "Status: Unlocked (Searching ..)"); 3532 break; 3533 3534 case 2: /* DVB-S2 mode */ 3535 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S2"); 3536 if (STV090x_GETFIELD_Px(dstatus, LOCK_DEFINITIF_FIELD)) { 3537 reg = STV090x_READ_DEMOD(state, PDELSTATUS1); 3538 if (STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD)) { 3539 *status |= FE_HAS_VITERBI; 3540 reg = STV090x_READ_DEMOD(state, TSSTATUS); 3541 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) 3542 *status |= FE_HAS_SYNC | FE_HAS_LOCK; 3543 } 3544 } 3545 break; 3546 3547 case 3: /* DVB-S1/legacy mode */ 3548 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S"); 3549 if (STV090x_GETFIELD_Px(dstatus, LOCK_DEFINITIF_FIELD)) { 3550 reg = STV090x_READ_DEMOD(state, VSTATUSVIT); 3551 if (STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD)) { 3552 *status |= FE_HAS_VITERBI; 3553 reg = STV090x_READ_DEMOD(state, TSSTATUS); 3554 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) 3555 *status |= FE_HAS_SYNC | FE_HAS_LOCK; 3556 } 3557 } 3558 break; 3559 } 3560 3561 return 0; 3562 } 3563 3564 static int stv090x_read_per(struct dvb_frontend *fe, u32 *per) 3565 { 3566 struct stv090x_state *state = fe->demodulator_priv; 3567 3568 s32 count_4, count_3, count_2, count_1, count_0, count; 3569 u32 reg, h, m, l; 3570 enum fe_status status; 3571 3572 stv090x_read_status(fe, &status); 3573 if (!(status & FE_HAS_LOCK)) { 3574 *per = 1 << 23; /* Max PER */ 3575 } else { 3576 /* Counter 2 */ 3577 reg = STV090x_READ_DEMOD(state, ERRCNT22); 3578 h = STV090x_GETFIELD_Px(reg, ERR_CNT2_FIELD); 3579 3580 reg = STV090x_READ_DEMOD(state, ERRCNT21); 3581 m = STV090x_GETFIELD_Px(reg, ERR_CNT21_FIELD); 3582 3583 reg = STV090x_READ_DEMOD(state, ERRCNT20); 3584 l = STV090x_GETFIELD_Px(reg, ERR_CNT20_FIELD); 3585 3586 *per = ((h << 16) | (m << 8) | l); 3587 3588 count_4 = STV090x_READ_DEMOD(state, FBERCPT4); 3589 count_3 = STV090x_READ_DEMOD(state, FBERCPT3); 3590 count_2 = STV090x_READ_DEMOD(state, FBERCPT2); 3591 count_1 = STV090x_READ_DEMOD(state, FBERCPT1); 3592 count_0 = STV090x_READ_DEMOD(state, FBERCPT0); 3593 3594 if ((!count_4) && (!count_3)) { 3595 count = (count_2 & 0xff) << 16; 3596 count |= (count_1 & 0xff) << 8; 3597 count |= count_0 & 0xff; 3598 } else { 3599 count = 1 << 24; 3600 } 3601 if (count == 0) 3602 *per = 1; 3603 } 3604 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0) < 0) 3605 goto err; 3606 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0) 3607 goto err; 3608 3609 return 0; 3610 err: 3611 dprintk(FE_ERROR, 1, "I/O error"); 3612 return -1; 3613 } 3614 3615 static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val) 3616 { 3617 int res = 0; 3618 int min = 0, med; 3619 3620 if ((val >= tab[min].read && val < tab[max].read) || 3621 (val >= tab[max].read && val < tab[min].read)) { 3622 while ((max - min) > 1) { 3623 med = (max + min) / 2; 3624 if ((val >= tab[min].read && val < tab[med].read) || 3625 (val >= tab[med].read && val < tab[min].read)) 3626 max = med; 3627 else 3628 min = med; 3629 } 3630 res = ((val - tab[min].read) * 3631 (tab[max].real - tab[min].real) / 3632 (tab[max].read - tab[min].read)) + 3633 tab[min].real; 3634 } else { 3635 if (tab[min].read < tab[max].read) { 3636 if (val < tab[min].read) 3637 res = tab[min].real; 3638 else if (val >= tab[max].read) 3639 res = tab[max].real; 3640 } else { 3641 if (val >= tab[min].read) 3642 res = tab[min].real; 3643 else if (val < tab[max].read) 3644 res = tab[max].real; 3645 } 3646 } 3647 3648 return res; 3649 } 3650 3651 static int stv090x_read_signal_strength(struct dvb_frontend *fe, u16 *strength) 3652 { 3653 struct stv090x_state *state = fe->demodulator_priv; 3654 u32 reg; 3655 s32 agc_0, agc_1, agc; 3656 s32 str; 3657 3658 reg = STV090x_READ_DEMOD(state, AGCIQIN1); 3659 agc_1 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD); 3660 reg = STV090x_READ_DEMOD(state, AGCIQIN0); 3661 agc_0 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD); 3662 agc = MAKEWORD16(agc_1, agc_0); 3663 3664 str = stv090x_table_lookup(stv090x_rf_tab, 3665 ARRAY_SIZE(stv090x_rf_tab) - 1, agc); 3666 if (agc > stv090x_rf_tab[0].read) 3667 str = 0; 3668 else if (agc < stv090x_rf_tab[ARRAY_SIZE(stv090x_rf_tab) - 1].read) 3669 str = -100; 3670 *strength = (str + 100) * 0xFFFF / 100; 3671 3672 return 0; 3673 } 3674 3675 static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr) 3676 { 3677 struct stv090x_state *state = fe->demodulator_priv; 3678 u32 reg_0, reg_1, reg, i; 3679 s32 val_0, val_1, val = 0; 3680 u8 lock_f; 3681 s32 div; 3682 u32 last; 3683 3684 switch (state->delsys) { 3685 case STV090x_DVBS2: 3686 reg = STV090x_READ_DEMOD(state, DSTATUS); 3687 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD); 3688 if (lock_f) { 3689 msleep(5); 3690 for (i = 0; i < 16; i++) { 3691 reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1); 3692 val_1 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD); 3693 reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0); 3694 val_0 = STV090x_GETFIELD_Px(reg_0, NOSPLHT_NORMED_FIELD); 3695 val += MAKEWORD16(val_1, val_0); 3696 msleep(1); 3697 } 3698 val /= 16; 3699 last = ARRAY_SIZE(stv090x_s2cn_tab) - 1; 3700 div = stv090x_s2cn_tab[last].real - 3701 stv090x_s2cn_tab[3].real; 3702 val = stv090x_table_lookup(stv090x_s2cn_tab, last, val); 3703 if (val < 0) 3704 val = 0; 3705 *cnr = val * 0xFFFF / div; 3706 } 3707 break; 3708 3709 case STV090x_DVBS1: 3710 case STV090x_DSS: 3711 reg = STV090x_READ_DEMOD(state, DSTATUS); 3712 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD); 3713 if (lock_f) { 3714 msleep(5); 3715 for (i = 0; i < 16; i++) { 3716 reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1); 3717 val_1 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD); 3718 reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0); 3719 val_0 = STV090x_GETFIELD_Px(reg_0, NOSDATAT_UNNORMED_FIELD); 3720 val += MAKEWORD16(val_1, val_0); 3721 msleep(1); 3722 } 3723 val /= 16; 3724 last = ARRAY_SIZE(stv090x_s1cn_tab) - 1; 3725 div = stv090x_s1cn_tab[last].real - 3726 stv090x_s1cn_tab[0].real; 3727 val = stv090x_table_lookup(stv090x_s1cn_tab, last, val); 3728 *cnr = val * 0xFFFF / div; 3729 } 3730 break; 3731 default: 3732 break; 3733 } 3734 3735 return 0; 3736 } 3737 3738 static int stv090x_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone) 3739 { 3740 struct stv090x_state *state = fe->demodulator_priv; 3741 u32 reg; 3742 3743 reg = STV090x_READ_DEMOD(state, DISTXCTL); 3744 switch (tone) { 3745 case SEC_TONE_ON: 3746 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0); 3747 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1); 3748 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3749 goto err; 3750 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0); 3751 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3752 goto err; 3753 break; 3754 3755 case SEC_TONE_OFF: 3756 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0); 3757 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1); 3758 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3759 goto err; 3760 break; 3761 default: 3762 return -EINVAL; 3763 } 3764 3765 return 0; 3766 err: 3767 dprintk(FE_ERROR, 1, "I/O error"); 3768 return -1; 3769 } 3770 3771 3772 static enum dvbfe_algo stv090x_frontend_algo(struct dvb_frontend *fe) 3773 { 3774 return DVBFE_ALGO_CUSTOM; 3775 } 3776 3777 static int stv090x_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd) 3778 { 3779 struct stv090x_state *state = fe->demodulator_priv; 3780 u32 reg, idle = 0, fifo_full = 1; 3781 int i; 3782 3783 reg = STV090x_READ_DEMOD(state, DISTXCTL); 3784 3785 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 3786 (state->config->diseqc_envelope_mode) ? 4 : 2); 3787 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1); 3788 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3789 goto err; 3790 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0); 3791 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3792 goto err; 3793 3794 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1); 3795 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3796 goto err; 3797 3798 for (i = 0; i < cmd->msg_len; i++) { 3799 3800 while (fifo_full) { 3801 reg = STV090x_READ_DEMOD(state, DISTXSTATUS); 3802 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD); 3803 } 3804 3805 if (STV090x_WRITE_DEMOD(state, DISTXDATA, cmd->msg[i]) < 0) 3806 goto err; 3807 } 3808 reg = STV090x_READ_DEMOD(state, DISTXCTL); 3809 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0); 3810 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3811 goto err; 3812 3813 i = 0; 3814 3815 while ((!idle) && (i < 10)) { 3816 reg = STV090x_READ_DEMOD(state, DISTXSTATUS); 3817 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD); 3818 msleep(10); 3819 i++; 3820 } 3821 3822 return 0; 3823 err: 3824 dprintk(FE_ERROR, 1, "I/O error"); 3825 return -1; 3826 } 3827 3828 static int stv090x_send_diseqc_burst(struct dvb_frontend *fe, 3829 enum fe_sec_mini_cmd burst) 3830 { 3831 struct stv090x_state *state = fe->demodulator_priv; 3832 u32 reg, idle = 0, fifo_full = 1; 3833 u8 mode, value; 3834 int i; 3835 3836 reg = STV090x_READ_DEMOD(state, DISTXCTL); 3837 3838 if (burst == SEC_MINI_A) { 3839 mode = (state->config->diseqc_envelope_mode) ? 5 : 3; 3840 value = 0x00; 3841 } else { 3842 mode = (state->config->diseqc_envelope_mode) ? 4 : 2; 3843 value = 0xFF; 3844 } 3845 3846 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, mode); 3847 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1); 3848 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3849 goto err; 3850 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0); 3851 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3852 goto err; 3853 3854 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1); 3855 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3856 goto err; 3857 3858 while (fifo_full) { 3859 reg = STV090x_READ_DEMOD(state, DISTXSTATUS); 3860 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD); 3861 } 3862 3863 if (STV090x_WRITE_DEMOD(state, DISTXDATA, value) < 0) 3864 goto err; 3865 3866 reg = STV090x_READ_DEMOD(state, DISTXCTL); 3867 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0); 3868 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3869 goto err; 3870 3871 i = 0; 3872 3873 while ((!idle) && (i < 10)) { 3874 reg = STV090x_READ_DEMOD(state, DISTXSTATUS); 3875 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD); 3876 msleep(10); 3877 i++; 3878 } 3879 3880 return 0; 3881 err: 3882 dprintk(FE_ERROR, 1, "I/O error"); 3883 return -1; 3884 } 3885 3886 static int stv090x_recv_slave_reply(struct dvb_frontend *fe, struct dvb_diseqc_slave_reply *reply) 3887 { 3888 struct stv090x_state *state = fe->demodulator_priv; 3889 u32 reg = 0, i = 0, rx_end = 0; 3890 3891 while ((rx_end != 1) && (i < 10)) { 3892 msleep(10); 3893 i++; 3894 reg = STV090x_READ_DEMOD(state, DISRX_ST0); 3895 rx_end = STV090x_GETFIELD_Px(reg, RX_END_FIELD); 3896 } 3897 3898 if (rx_end) { 3899 reply->msg_len = STV090x_GETFIELD_Px(reg, FIFO_BYTENBR_FIELD); 3900 for (i = 0; i < reply->msg_len; i++) 3901 reply->msg[i] = STV090x_READ_DEMOD(state, DISRXDATA); 3902 } 3903 3904 return 0; 3905 } 3906 3907 static int stv090x_sleep(struct dvb_frontend *fe) 3908 { 3909 struct stv090x_state *state = fe->demodulator_priv; 3910 u32 reg; 3911 u8 full_standby = 0; 3912 3913 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 3914 goto err; 3915 3916 if (state->config->tuner_sleep) { 3917 if (state->config->tuner_sleep(fe) < 0) 3918 goto err_gateoff; 3919 } 3920 3921 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 3922 goto err; 3923 3924 dprintk(FE_DEBUG, 1, "Set %s(%d) to sleep", 3925 state->device == STV0900 ? "STV0900" : "STV0903", 3926 state->demod); 3927 3928 mutex_lock(&state->internal->demod_lock); 3929 3930 switch (state->demod) { 3931 case STV090x_DEMODULATOR_0: 3932 /* power off ADC 1 */ 3933 reg = stv090x_read_reg(state, STV090x_TSTTNR1); 3934 STV090x_SETFIELD(reg, ADC1_PON_FIELD, 0); 3935 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0) 3936 goto err_unlock; 3937 /* power off DiSEqC 1 */ 3938 reg = stv090x_read_reg(state, STV090x_TSTTNR2); 3939 STV090x_SETFIELD(reg, DISEQC1_PON_FIELD, 0); 3940 if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0) 3941 goto err_unlock; 3942 3943 /* check whether path 2 is already sleeping, that is when 3944 ADC2 is off */ 3945 reg = stv090x_read_reg(state, STV090x_TSTTNR3); 3946 if (STV090x_GETFIELD(reg, ADC2_PON_FIELD) == 0) 3947 full_standby = 1; 3948 3949 /* stop clocks */ 3950 reg = stv090x_read_reg(state, STV090x_STOPCLK1); 3951 /* packet delineator 1 clock */ 3952 STV090x_SETFIELD(reg, STOP_CLKPKDT1_FIELD, 1); 3953 /* ADC 1 clock */ 3954 STV090x_SETFIELD(reg, STOP_CLKADCI1_FIELD, 1); 3955 /* FEC clock is shared between the two paths, only stop it 3956 when full standby is possible */ 3957 if (full_standby) 3958 STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 1); 3959 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0) 3960 goto err_unlock; 3961 reg = stv090x_read_reg(state, STV090x_STOPCLK2); 3962 /* sampling 1 clock */ 3963 STV090x_SETFIELD(reg, STOP_CLKSAMP1_FIELD, 1); 3964 /* viterbi 1 clock */ 3965 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, 1); 3966 /* TS clock is shared between the two paths, only stop it 3967 when full standby is possible */ 3968 if (full_standby) 3969 STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 1); 3970 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) 3971 goto err_unlock; 3972 break; 3973 3974 case STV090x_DEMODULATOR_1: 3975 /* power off ADC 2 */ 3976 reg = stv090x_read_reg(state, STV090x_TSTTNR3); 3977 STV090x_SETFIELD(reg, ADC2_PON_FIELD, 0); 3978 if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0) 3979 goto err_unlock; 3980 /* power off DiSEqC 2 */ 3981 reg = stv090x_read_reg(state, STV090x_TSTTNR4); 3982 STV090x_SETFIELD(reg, DISEQC2_PON_FIELD, 0); 3983 if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0) 3984 goto err_unlock; 3985 3986 /* check whether path 1 is already sleeping, that is when 3987 ADC1 is off */ 3988 reg = stv090x_read_reg(state, STV090x_TSTTNR1); 3989 if (STV090x_GETFIELD(reg, ADC1_PON_FIELD) == 0) 3990 full_standby = 1; 3991 3992 /* stop clocks */ 3993 reg = stv090x_read_reg(state, STV090x_STOPCLK1); 3994 /* packet delineator 2 clock */ 3995 STV090x_SETFIELD(reg, STOP_CLKPKDT2_FIELD, 1); 3996 /* ADC 2 clock */ 3997 STV090x_SETFIELD(reg, STOP_CLKADCI2_FIELD, 1); 3998 /* FEC clock is shared between the two paths, only stop it 3999 when full standby is possible */ 4000 if (full_standby) 4001 STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 1); 4002 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0) 4003 goto err_unlock; 4004 reg = stv090x_read_reg(state, STV090x_STOPCLK2); 4005 /* sampling 2 clock */ 4006 STV090x_SETFIELD(reg, STOP_CLKSAMP2_FIELD, 1); 4007 /* viterbi 2 clock */ 4008 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, 1); 4009 /* TS clock is shared between the two paths, only stop it 4010 when full standby is possible */ 4011 if (full_standby) 4012 STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 1); 4013 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) 4014 goto err_unlock; 4015 break; 4016 4017 default: 4018 dprintk(FE_ERROR, 1, "Wrong demodulator!"); 4019 break; 4020 } 4021 4022 if (full_standby) { 4023 /* general power off */ 4024 reg = stv090x_read_reg(state, STV090x_SYNTCTRL); 4025 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01); 4026 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0) 4027 goto err_unlock; 4028 } 4029 4030 mutex_unlock(&state->internal->demod_lock); 4031 return 0; 4032 4033 err_gateoff: 4034 stv090x_i2c_gate_ctrl(state, 0); 4035 goto err; 4036 err_unlock: 4037 mutex_unlock(&state->internal->demod_lock); 4038 err: 4039 dprintk(FE_ERROR, 1, "I/O error"); 4040 return -1; 4041 } 4042 4043 static int stv090x_wakeup(struct dvb_frontend *fe) 4044 { 4045 struct stv090x_state *state = fe->demodulator_priv; 4046 u32 reg; 4047 4048 dprintk(FE_DEBUG, 1, "Wake %s(%d) from standby", 4049 state->device == STV0900 ? "STV0900" : "STV0903", 4050 state->demod); 4051 4052 mutex_lock(&state->internal->demod_lock); 4053 4054 /* general power on */ 4055 reg = stv090x_read_reg(state, STV090x_SYNTCTRL); 4056 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00); 4057 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0) 4058 goto err; 4059 4060 switch (state->demod) { 4061 case STV090x_DEMODULATOR_0: 4062 /* power on ADC 1 */ 4063 reg = stv090x_read_reg(state, STV090x_TSTTNR1); 4064 STV090x_SETFIELD(reg, ADC1_PON_FIELD, 1); 4065 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0) 4066 goto err; 4067 /* power on DiSEqC 1 */ 4068 reg = stv090x_read_reg(state, STV090x_TSTTNR2); 4069 STV090x_SETFIELD(reg, DISEQC1_PON_FIELD, 1); 4070 if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0) 4071 goto err; 4072 4073 /* activate clocks */ 4074 reg = stv090x_read_reg(state, STV090x_STOPCLK1); 4075 /* packet delineator 1 clock */ 4076 STV090x_SETFIELD(reg, STOP_CLKPKDT1_FIELD, 0); 4077 /* ADC 1 clock */ 4078 STV090x_SETFIELD(reg, STOP_CLKADCI1_FIELD, 0); 4079 /* FEC clock */ 4080 STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 0); 4081 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0) 4082 goto err; 4083 reg = stv090x_read_reg(state, STV090x_STOPCLK2); 4084 /* sampling 1 clock */ 4085 STV090x_SETFIELD(reg, STOP_CLKSAMP1_FIELD, 0); 4086 /* viterbi 1 clock */ 4087 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, 0); 4088 /* TS clock */ 4089 STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 0); 4090 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) 4091 goto err; 4092 break; 4093 4094 case STV090x_DEMODULATOR_1: 4095 /* power on ADC 2 */ 4096 reg = stv090x_read_reg(state, STV090x_TSTTNR3); 4097 STV090x_SETFIELD(reg, ADC2_PON_FIELD, 1); 4098 if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0) 4099 goto err; 4100 /* power on DiSEqC 2 */ 4101 reg = stv090x_read_reg(state, STV090x_TSTTNR4); 4102 STV090x_SETFIELD(reg, DISEQC2_PON_FIELD, 1); 4103 if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0) 4104 goto err; 4105 4106 /* activate clocks */ 4107 reg = stv090x_read_reg(state, STV090x_STOPCLK1); 4108 /* packet delineator 2 clock */ 4109 STV090x_SETFIELD(reg, STOP_CLKPKDT2_FIELD, 0); 4110 /* ADC 2 clock */ 4111 STV090x_SETFIELD(reg, STOP_CLKADCI2_FIELD, 0); 4112 /* FEC clock */ 4113 STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 0); 4114 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0) 4115 goto err; 4116 reg = stv090x_read_reg(state, STV090x_STOPCLK2); 4117 /* sampling 2 clock */ 4118 STV090x_SETFIELD(reg, STOP_CLKSAMP2_FIELD, 0); 4119 /* viterbi 2 clock */ 4120 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, 0); 4121 /* TS clock */ 4122 STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 0); 4123 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) 4124 goto err; 4125 break; 4126 4127 default: 4128 dprintk(FE_ERROR, 1, "Wrong demodulator!"); 4129 break; 4130 } 4131 4132 mutex_unlock(&state->internal->demod_lock); 4133 return 0; 4134 err: 4135 mutex_unlock(&state->internal->demod_lock); 4136 dprintk(FE_ERROR, 1, "I/O error"); 4137 return -1; 4138 } 4139 4140 static void stv090x_release(struct dvb_frontend *fe) 4141 { 4142 struct stv090x_state *state = fe->demodulator_priv; 4143 4144 state->internal->num_used--; 4145 if (state->internal->num_used <= 0) { 4146 4147 dprintk(FE_ERROR, 1, "Actually removing"); 4148 4149 remove_dev(state->internal); 4150 kfree(state->internal); 4151 } 4152 4153 kfree(state); 4154 } 4155 4156 static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc_mode) 4157 { 4158 u32 reg = 0; 4159 4160 reg = stv090x_read_reg(state, STV090x_GENCFG); 4161 4162 switch (ldpc_mode) { 4163 case STV090x_DUAL: 4164 default: 4165 if ((state->demod_mode != STV090x_DUAL) || (STV090x_GETFIELD(reg, DDEMOD_FIELD) != 1)) { 4166 /* set LDPC to dual mode */ 4167 if (stv090x_write_reg(state, STV090x_GENCFG, 0x1d) < 0) 4168 goto err; 4169 4170 state->demod_mode = STV090x_DUAL; 4171 4172 reg = stv090x_read_reg(state, STV090x_TSTRES0); 4173 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1); 4174 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0) 4175 goto err; 4176 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0); 4177 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0) 4178 goto err; 4179 4180 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0) 4181 goto err; 4182 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0) 4183 goto err; 4184 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0) 4185 goto err; 4186 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0) 4187 goto err; 4188 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0) 4189 goto err; 4190 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0) 4191 goto err; 4192 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0) 4193 goto err; 4194 4195 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0) 4196 goto err; 4197 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0) 4198 goto err; 4199 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0) 4200 goto err; 4201 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0) 4202 goto err; 4203 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0) 4204 goto err; 4205 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0) 4206 goto err; 4207 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0) 4208 goto err; 4209 4210 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0) 4211 goto err; 4212 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0) 4213 goto err; 4214 } 4215 break; 4216 4217 case STV090x_SINGLE: 4218 if (stv090x_stop_modcod(state) < 0) 4219 goto err; 4220 if (stv090x_activate_modcod_single(state) < 0) 4221 goto err; 4222 4223 if (state->demod == STV090x_DEMODULATOR_1) { 4224 if (stv090x_write_reg(state, STV090x_GENCFG, 0x06) < 0) /* path 2 */ 4225 goto err; 4226 } else { 4227 if (stv090x_write_reg(state, STV090x_GENCFG, 0x04) < 0) /* path 1 */ 4228 goto err; 4229 } 4230 4231 reg = stv090x_read_reg(state, STV090x_TSTRES0); 4232 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1); 4233 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0) 4234 goto err; 4235 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0); 4236 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0) 4237 goto err; 4238 4239 reg = STV090x_READ_DEMOD(state, PDELCTRL1); 4240 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x01); 4241 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) 4242 goto err; 4243 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x00); 4244 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) 4245 goto err; 4246 break; 4247 } 4248 4249 return 0; 4250 err: 4251 dprintk(FE_ERROR, 1, "I/O error"); 4252 return -1; 4253 } 4254 4255 /* return (Hz), clk in Hz*/ 4256 static u32 stv090x_get_mclk(struct stv090x_state *state) 4257 { 4258 const struct stv090x_config *config = state->config; 4259 u32 div, reg; 4260 u8 ratio; 4261 4262 div = stv090x_read_reg(state, STV090x_NCOARSE); 4263 reg = stv090x_read_reg(state, STV090x_SYNTCTRL); 4264 ratio = STV090x_GETFIELD(reg, SELX1RATIO_FIELD) ? 4 : 6; 4265 4266 return (div + 1) * config->xtal / ratio; /* kHz */ 4267 } 4268 4269 static int stv090x_set_mclk(struct stv090x_state *state, u32 mclk, u32 clk) 4270 { 4271 const struct stv090x_config *config = state->config; 4272 u32 reg, div, clk_sel; 4273 4274 reg = stv090x_read_reg(state, STV090x_SYNTCTRL); 4275 clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6); 4276 4277 div = ((clk_sel * mclk) / config->xtal) - 1; 4278 4279 reg = stv090x_read_reg(state, STV090x_NCOARSE); 4280 STV090x_SETFIELD(reg, M_DIV_FIELD, div); 4281 if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0) 4282 goto err; 4283 4284 state->internal->mclk = stv090x_get_mclk(state); 4285 4286 /*Set the DiseqC frequency to 22KHz */ 4287 div = state->internal->mclk / 704000; 4288 if (STV090x_WRITE_DEMOD(state, F22TX, div) < 0) 4289 goto err; 4290 if (STV090x_WRITE_DEMOD(state, F22RX, div) < 0) 4291 goto err; 4292 4293 return 0; 4294 err: 4295 dprintk(FE_ERROR, 1, "I/O error"); 4296 return -1; 4297 } 4298 4299 static int stv0900_set_tspath(struct stv090x_state *state) 4300 { 4301 u32 reg; 4302 4303 if (state->internal->dev_ver >= 0x20) { 4304 switch (state->config->ts1_mode) { 4305 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4306 case STV090x_TSMODE_DVBCI: 4307 switch (state->config->ts2_mode) { 4308 case STV090x_TSMODE_SERIAL_PUNCTURED: 4309 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4310 default: 4311 stv090x_write_reg(state, STV090x_TSGENERAL, 0x00); 4312 break; 4313 4314 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4315 case STV090x_TSMODE_DVBCI: 4316 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x06) < 0) /* Mux'd stream mode */ 4317 goto err; 4318 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); 4319 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); 4320 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) 4321 goto err; 4322 reg = stv090x_read_reg(state, STV090x_P2_TSCFGM); 4323 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); 4324 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0) 4325 goto err; 4326 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0) 4327 goto err; 4328 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0) 4329 goto err; 4330 break; 4331 } 4332 break; 4333 4334 case STV090x_TSMODE_SERIAL_PUNCTURED: 4335 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4336 default: 4337 switch (state->config->ts2_mode) { 4338 case STV090x_TSMODE_SERIAL_PUNCTURED: 4339 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4340 default: 4341 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0) 4342 goto err; 4343 break; 4344 4345 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4346 case STV090x_TSMODE_DVBCI: 4347 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0a) < 0) 4348 goto err; 4349 break; 4350 } 4351 break; 4352 } 4353 } else { 4354 switch (state->config->ts1_mode) { 4355 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4356 case STV090x_TSMODE_DVBCI: 4357 switch (state->config->ts2_mode) { 4358 case STV090x_TSMODE_SERIAL_PUNCTURED: 4359 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4360 default: 4361 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10); 4362 break; 4363 4364 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4365 case STV090x_TSMODE_DVBCI: 4366 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x16); 4367 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); 4368 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); 4369 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) 4370 goto err; 4371 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); 4372 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 0); 4373 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) 4374 goto err; 4375 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0) 4376 goto err; 4377 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0) 4378 goto err; 4379 break; 4380 } 4381 break; 4382 4383 case STV090x_TSMODE_SERIAL_PUNCTURED: 4384 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4385 default: 4386 switch (state->config->ts2_mode) { 4387 case STV090x_TSMODE_SERIAL_PUNCTURED: 4388 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4389 default: 4390 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14); 4391 break; 4392 4393 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4394 case STV090x_TSMODE_DVBCI: 4395 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x12); 4396 break; 4397 } 4398 break; 4399 } 4400 } 4401 4402 switch (state->config->ts1_mode) { 4403 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4404 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4405 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei); 4406 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); 4407 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); 4408 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4409 goto err; 4410 break; 4411 4412 case STV090x_TSMODE_DVBCI: 4413 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4414 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei); 4415 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); 4416 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); 4417 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4418 goto err; 4419 break; 4420 4421 case STV090x_TSMODE_SERIAL_PUNCTURED: 4422 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4423 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei); 4424 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); 4425 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); 4426 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4427 goto err; 4428 break; 4429 4430 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4431 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4432 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei); 4433 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); 4434 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); 4435 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4436 goto err; 4437 break; 4438 4439 default: 4440 break; 4441 } 4442 4443 switch (state->config->ts2_mode) { 4444 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4445 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); 4446 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei); 4447 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); 4448 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); 4449 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) 4450 goto err; 4451 break; 4452 4453 case STV090x_TSMODE_DVBCI: 4454 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); 4455 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei); 4456 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); 4457 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); 4458 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) 4459 goto err; 4460 break; 4461 4462 case STV090x_TSMODE_SERIAL_PUNCTURED: 4463 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); 4464 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei); 4465 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); 4466 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); 4467 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) 4468 goto err; 4469 break; 4470 4471 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4472 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); 4473 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei); 4474 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); 4475 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); 4476 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) 4477 goto err; 4478 break; 4479 4480 default: 4481 break; 4482 } 4483 4484 if (state->config->ts1_clk > 0) { 4485 u32 speed; 4486 4487 switch (state->config->ts1_mode) { 4488 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4489 case STV090x_TSMODE_DVBCI: 4490 default: 4491 speed = state->internal->mclk / 4492 (state->config->ts1_clk / 4); 4493 if (speed < 0x08) 4494 speed = 0x08; 4495 if (speed > 0xFF) 4496 speed = 0xFF; 4497 break; 4498 case STV090x_TSMODE_SERIAL_PUNCTURED: 4499 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4500 speed = state->internal->mclk / 4501 (state->config->ts1_clk / 32); 4502 if (speed < 0x20) 4503 speed = 0x20; 4504 if (speed > 0xFF) 4505 speed = 0xFF; 4506 break; 4507 } 4508 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); 4509 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); 4510 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) 4511 goto err; 4512 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0) 4513 goto err; 4514 } 4515 4516 if (state->config->ts2_clk > 0) { 4517 u32 speed; 4518 4519 switch (state->config->ts2_mode) { 4520 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4521 case STV090x_TSMODE_DVBCI: 4522 default: 4523 speed = state->internal->mclk / 4524 (state->config->ts2_clk / 4); 4525 if (speed < 0x08) 4526 speed = 0x08; 4527 if (speed > 0xFF) 4528 speed = 0xFF; 4529 break; 4530 case STV090x_TSMODE_SERIAL_PUNCTURED: 4531 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4532 speed = state->internal->mclk / 4533 (state->config->ts2_clk / 32); 4534 if (speed < 0x20) 4535 speed = 0x20; 4536 if (speed > 0xFF) 4537 speed = 0xFF; 4538 break; 4539 } 4540 reg = stv090x_read_reg(state, STV090x_P2_TSCFGM); 4541 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); 4542 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0) 4543 goto err; 4544 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, speed) < 0) 4545 goto err; 4546 } 4547 4548 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); 4549 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01); 4550 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) 4551 goto err; 4552 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00); 4553 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) 4554 goto err; 4555 4556 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4557 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01); 4558 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4559 goto err; 4560 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00); 4561 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4562 goto err; 4563 4564 return 0; 4565 err: 4566 dprintk(FE_ERROR, 1, "I/O error"); 4567 return -1; 4568 } 4569 4570 static int stv0903_set_tspath(struct stv090x_state *state) 4571 { 4572 u32 reg; 4573 4574 if (state->internal->dev_ver >= 0x20) { 4575 switch (state->config->ts1_mode) { 4576 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4577 case STV090x_TSMODE_DVBCI: 4578 stv090x_write_reg(state, STV090x_TSGENERAL, 0x00); 4579 break; 4580 4581 case STV090x_TSMODE_SERIAL_PUNCTURED: 4582 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4583 default: 4584 stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c); 4585 break; 4586 } 4587 } else { 4588 switch (state->config->ts1_mode) { 4589 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4590 case STV090x_TSMODE_DVBCI: 4591 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10); 4592 break; 4593 4594 case STV090x_TSMODE_SERIAL_PUNCTURED: 4595 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4596 default: 4597 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14); 4598 break; 4599 } 4600 } 4601 4602 switch (state->config->ts1_mode) { 4603 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4604 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4605 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); 4606 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); 4607 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4608 goto err; 4609 break; 4610 4611 case STV090x_TSMODE_DVBCI: 4612 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4613 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); 4614 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); 4615 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4616 goto err; 4617 break; 4618 4619 case STV090x_TSMODE_SERIAL_PUNCTURED: 4620 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4621 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); 4622 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); 4623 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4624 goto err; 4625 break; 4626 4627 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4628 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4629 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); 4630 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); 4631 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4632 goto err; 4633 break; 4634 4635 default: 4636 break; 4637 } 4638 4639 if (state->config->ts1_clk > 0) { 4640 u32 speed; 4641 4642 switch (state->config->ts1_mode) { 4643 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4644 case STV090x_TSMODE_DVBCI: 4645 default: 4646 speed = state->internal->mclk / 4647 (state->config->ts1_clk / 4); 4648 if (speed < 0x08) 4649 speed = 0x08; 4650 if (speed > 0xFF) 4651 speed = 0xFF; 4652 break; 4653 case STV090x_TSMODE_SERIAL_PUNCTURED: 4654 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4655 speed = state->internal->mclk / 4656 (state->config->ts1_clk / 32); 4657 if (speed < 0x20) 4658 speed = 0x20; 4659 if (speed > 0xFF) 4660 speed = 0xFF; 4661 break; 4662 } 4663 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); 4664 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); 4665 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) 4666 goto err; 4667 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0) 4668 goto err; 4669 } 4670 4671 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4672 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01); 4673 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4674 goto err; 4675 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00); 4676 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4677 goto err; 4678 4679 return 0; 4680 err: 4681 dprintk(FE_ERROR, 1, "I/O error"); 4682 return -1; 4683 } 4684 4685 static int stv090x_init(struct dvb_frontend *fe) 4686 { 4687 struct stv090x_state *state = fe->demodulator_priv; 4688 const struct stv090x_config *config = state->config; 4689 u32 reg; 4690 4691 if (state->internal->mclk == 0) { 4692 /* call tuner init to configure the tuner's clock output 4693 divider directly before setting up the master clock of 4694 the stv090x. */ 4695 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 4696 goto err; 4697 4698 if (config->tuner_init) { 4699 if (config->tuner_init(fe) < 0) 4700 goto err_gateoff; 4701 } 4702 4703 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 4704 goto err; 4705 4706 stv090x_set_mclk(state, 135000000, config->xtal); /* 135 Mhz */ 4707 msleep(5); 4708 if (stv090x_write_reg(state, STV090x_SYNTCTRL, 4709 0x20 | config->clk_mode) < 0) 4710 goto err; 4711 stv090x_get_mclk(state); 4712 } 4713 4714 if (stv090x_wakeup(fe) < 0) { 4715 dprintk(FE_ERROR, 1, "Error waking device"); 4716 goto err; 4717 } 4718 4719 if (stv090x_ldpc_mode(state, state->demod_mode) < 0) 4720 goto err; 4721 4722 reg = STV090x_READ_DEMOD(state, TNRCFG2); 4723 STV090x_SETFIELD_Px(reg, TUN_IQSWAP_FIELD, state->inversion); 4724 if (STV090x_WRITE_DEMOD(state, TNRCFG2, reg) < 0) 4725 goto err; 4726 reg = STV090x_READ_DEMOD(state, DEMOD); 4727 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff); 4728 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) 4729 goto err; 4730 4731 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 4732 goto err; 4733 4734 if (config->tuner_set_mode) { 4735 if (config->tuner_set_mode(fe, TUNER_WAKE) < 0) 4736 goto err_gateoff; 4737 } 4738 4739 if (config->tuner_init) { 4740 if (config->tuner_init(fe) < 0) 4741 goto err_gateoff; 4742 } 4743 4744 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 4745 goto err; 4746 4747 if (state->device == STV0900) { 4748 if (stv0900_set_tspath(state) < 0) 4749 goto err; 4750 } else { 4751 if (stv0903_set_tspath(state) < 0) 4752 goto err; 4753 } 4754 4755 return 0; 4756 4757 err_gateoff: 4758 stv090x_i2c_gate_ctrl(state, 0); 4759 err: 4760 dprintk(FE_ERROR, 1, "I/O error"); 4761 return -1; 4762 } 4763 4764 static int stv090x_setup(struct dvb_frontend *fe) 4765 { 4766 struct stv090x_state *state = fe->demodulator_priv; 4767 const struct stv090x_config *config = state->config; 4768 const struct stv090x_reg *stv090x_initval = NULL; 4769 const struct stv090x_reg *stv090x_cut20_val = NULL; 4770 unsigned long t1_size = 0, t2_size = 0; 4771 u32 reg = 0; 4772 4773 int i; 4774 4775 if (state->device == STV0900) { 4776 dprintk(FE_DEBUG, 1, "Initializing STV0900"); 4777 stv090x_initval = stv0900_initval; 4778 t1_size = ARRAY_SIZE(stv0900_initval); 4779 stv090x_cut20_val = stv0900_cut20_val; 4780 t2_size = ARRAY_SIZE(stv0900_cut20_val); 4781 } else if (state->device == STV0903) { 4782 dprintk(FE_DEBUG, 1, "Initializing STV0903"); 4783 stv090x_initval = stv0903_initval; 4784 t1_size = ARRAY_SIZE(stv0903_initval); 4785 stv090x_cut20_val = stv0903_cut20_val; 4786 t2_size = ARRAY_SIZE(stv0903_cut20_val); 4787 } 4788 4789 /* STV090x init */ 4790 4791 /* Stop Demod */ 4792 if (stv090x_write_reg(state, STV090x_P1_DMDISTATE, 0x5c) < 0) 4793 goto err; 4794 if (state->device == STV0900) 4795 if (stv090x_write_reg(state, STV090x_P2_DMDISTATE, 0x5c) < 0) 4796 goto err; 4797 4798 msleep(5); 4799 4800 /* Set No Tuner Mode */ 4801 if (stv090x_write_reg(state, STV090x_P1_TNRCFG, 0x6c) < 0) 4802 goto err; 4803 if (state->device == STV0900) 4804 if (stv090x_write_reg(state, STV090x_P2_TNRCFG, 0x6c) < 0) 4805 goto err; 4806 4807 /* I2C repeater OFF */ 4808 STV090x_SETFIELD_Px(reg, ENARPT_LEVEL_FIELD, config->repeater_level); 4809 if (stv090x_write_reg(state, STV090x_P1_I2CRPT, reg) < 0) 4810 goto err; 4811 if (state->device == STV0900) 4812 if (stv090x_write_reg(state, STV090x_P2_I2CRPT, reg) < 0) 4813 goto err; 4814 4815 if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */ 4816 goto err; 4817 msleep(5); 4818 if (stv090x_write_reg(state, STV090x_I2CCFG, 0x08) < 0) /* 1/41 oversampling */ 4819 goto err; 4820 if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0) /* enable PLL */ 4821 goto err; 4822 msleep(5); 4823 4824 /* write initval */ 4825 dprintk(FE_DEBUG, 1, "Setting up initial values"); 4826 for (i = 0; i < t1_size; i++) { 4827 if (stv090x_write_reg(state, stv090x_initval[i].addr, stv090x_initval[i].data) < 0) 4828 goto err; 4829 } 4830 4831 state->internal->dev_ver = stv090x_read_reg(state, STV090x_MID); 4832 if (state->internal->dev_ver >= 0x20) { 4833 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0) 4834 goto err; 4835 4836 /* write cut20_val*/ 4837 dprintk(FE_DEBUG, 1, "Setting up Cut 2.0 initial values"); 4838 for (i = 0; i < t2_size; i++) { 4839 if (stv090x_write_reg(state, stv090x_cut20_val[i].addr, stv090x_cut20_val[i].data) < 0) 4840 goto err; 4841 } 4842 4843 } else if (state->internal->dev_ver < 0x20) { 4844 dprintk(FE_ERROR, 1, "ERROR: Unsupported Cut: 0x%02x!", 4845 state->internal->dev_ver); 4846 4847 goto err; 4848 } else if (state->internal->dev_ver > 0x30) { 4849 /* we shouldn't bail out from here */ 4850 dprintk(FE_ERROR, 1, "INFO: Cut: 0x%02x probably incomplete support!", 4851 state->internal->dev_ver); 4852 } 4853 4854 /* ADC1 range */ 4855 reg = stv090x_read_reg(state, STV090x_TSTTNR1); 4856 STV090x_SETFIELD(reg, ADC1_INMODE_FIELD, 4857 (config->adc1_range == STV090x_ADC_1Vpp) ? 0 : 1); 4858 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0) 4859 goto err; 4860 4861 /* ADC2 range */ 4862 reg = stv090x_read_reg(state, STV090x_TSTTNR3); 4863 STV090x_SETFIELD(reg, ADC2_INMODE_FIELD, 4864 (config->adc2_range == STV090x_ADC_1Vpp) ? 0 : 1); 4865 if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0) 4866 goto err; 4867 4868 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x80) < 0) 4869 goto err; 4870 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0) 4871 goto err; 4872 4873 return 0; 4874 err: 4875 dprintk(FE_ERROR, 1, "I/O error"); 4876 return -1; 4877 } 4878 4879 static int stv090x_set_gpio(struct dvb_frontend *fe, u8 gpio, u8 dir, 4880 u8 value, u8 xor_value) 4881 { 4882 struct stv090x_state *state = fe->demodulator_priv; 4883 u8 reg = 0; 4884 4885 STV090x_SETFIELD(reg, GPIOx_OPD_FIELD, dir); 4886 STV090x_SETFIELD(reg, GPIOx_CONFIG_FIELD, value); 4887 STV090x_SETFIELD(reg, GPIOx_XOR_FIELD, xor_value); 4888 4889 return stv090x_write_reg(state, STV090x_GPIOxCFG(gpio), reg); 4890 } 4891 4892 static int stv090x_setup_compound(struct stv090x_state *state) 4893 { 4894 struct stv090x_dev *temp_int; 4895 4896 temp_int = find_dev(state->i2c, 4897 state->config->address); 4898 4899 if (temp_int && state->demod_mode == STV090x_DUAL) { 4900 state->internal = temp_int->internal; 4901 state->internal->num_used++; 4902 dprintk(FE_INFO, 1, "Found Internal Structure!"); 4903 } else { 4904 state->internal = kmalloc(sizeof(*state->internal), GFP_KERNEL); 4905 if (!state->internal) 4906 goto error; 4907 temp_int = append_internal(state->internal); 4908 if (!temp_int) { 4909 kfree(state->internal); 4910 goto error; 4911 } 4912 state->internal->num_used = 1; 4913 state->internal->mclk = 0; 4914 state->internal->dev_ver = 0; 4915 state->internal->i2c_adap = state->i2c; 4916 state->internal->i2c_addr = state->config->address; 4917 dprintk(FE_INFO, 1, "Create New Internal Structure!"); 4918 4919 mutex_init(&state->internal->demod_lock); 4920 mutex_init(&state->internal->tuner_lock); 4921 4922 if (stv090x_setup(&state->frontend) < 0) { 4923 dprintk(FE_ERROR, 1, "Error setting up device"); 4924 goto err_remove; 4925 } 4926 } 4927 4928 if (state->internal->dev_ver >= 0x30) 4929 state->frontend.ops.info.caps |= FE_CAN_MULTISTREAM; 4930 4931 /* workaround for stuck DiSEqC output */ 4932 if (state->config->diseqc_envelope_mode) 4933 stv090x_send_diseqc_burst(&state->frontend, SEC_MINI_A); 4934 4935 state->config->set_gpio = stv090x_set_gpio; 4936 4937 dprintk(FE_ERROR, 1, "Probing %s demodulator(%d) Cut=0x%02x", 4938 state->device == STV0900 ? "STV0900" : "STV0903", 4939 state->config->demod, 4940 state->internal->dev_ver); 4941 4942 return 0; 4943 4944 error: 4945 return -ENOMEM; 4946 err_remove: 4947 remove_dev(state->internal); 4948 kfree(state->internal); 4949 return -ENODEV; 4950 } 4951 4952 static const struct dvb_frontend_ops stv090x_ops = { 4953 .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS }, 4954 .info = { 4955 .name = "STV090x Multistandard", 4956 .frequency_min_hz = 950 * MHz, 4957 .frequency_max_hz = 2150 * MHz, 4958 .symbol_rate_min = 1000000, 4959 .symbol_rate_max = 45000000, 4960 .caps = FE_CAN_INVERSION_AUTO | 4961 FE_CAN_FEC_AUTO | 4962 FE_CAN_QPSK | 4963 FE_CAN_2G_MODULATION 4964 }, 4965 4966 .release = stv090x_release, 4967 .init = stv090x_init, 4968 4969 .sleep = stv090x_sleep, 4970 .get_frontend_algo = stv090x_frontend_algo, 4971 4972 .diseqc_send_master_cmd = stv090x_send_diseqc_msg, 4973 .diseqc_send_burst = stv090x_send_diseqc_burst, 4974 .diseqc_recv_slave_reply = stv090x_recv_slave_reply, 4975 .set_tone = stv090x_set_tone, 4976 4977 .search = stv090x_search, 4978 .read_status = stv090x_read_status, 4979 .read_ber = stv090x_read_per, 4980 .read_signal_strength = stv090x_read_signal_strength, 4981 .read_snr = stv090x_read_cnr, 4982 }; 4983 4984 static struct dvb_frontend *stv090x_get_dvb_frontend(struct i2c_client *client) 4985 { 4986 struct stv090x_state *state = i2c_get_clientdata(client); 4987 4988 dev_dbg(&client->dev, "\n"); 4989 4990 return &state->frontend; 4991 } 4992 4993 static int stv090x_probe(struct i2c_client *client) 4994 { 4995 int ret = 0; 4996 struct stv090x_config *config = client->dev.platform_data; 4997 4998 struct stv090x_state *state = NULL; 4999 5000 state = kzalloc(sizeof(*state), GFP_KERNEL); 5001 if (!state) { 5002 ret = -ENOMEM; 5003 goto error; 5004 } 5005 5006 state->verbose = &verbose; 5007 state->config = config; 5008 state->i2c = client->adapter; 5009 state->frontend.ops = stv090x_ops; 5010 state->frontend.demodulator_priv = state; 5011 state->demod = config->demod; 5012 /* Single or Dual mode */ 5013 state->demod_mode = config->demod_mode; 5014 state->device = config->device; 5015 /* default */ 5016 state->rolloff = STV090x_RO_35; 5017 5018 ret = stv090x_setup_compound(state); 5019 if (ret) 5020 goto error; 5021 5022 i2c_set_clientdata(client, state); 5023 5024 /* setup callbacks */ 5025 config->get_dvb_frontend = stv090x_get_dvb_frontend; 5026 5027 return 0; 5028 5029 error: 5030 kfree(state); 5031 return ret; 5032 } 5033 5034 static void stv090x_remove(struct i2c_client *client) 5035 { 5036 struct stv090x_state *state = i2c_get_clientdata(client); 5037 5038 stv090x_release(&state->frontend); 5039 } 5040 5041 struct dvb_frontend *stv090x_attach(struct stv090x_config *config, 5042 struct i2c_adapter *i2c, 5043 enum stv090x_demodulator demod) 5044 { 5045 int ret = 0; 5046 struct stv090x_state *state = NULL; 5047 5048 state = kzalloc(sizeof(*state), GFP_KERNEL); 5049 if (!state) 5050 goto error; 5051 5052 state->verbose = &verbose; 5053 state->config = config; 5054 state->i2c = i2c; 5055 state->frontend.ops = stv090x_ops; 5056 state->frontend.demodulator_priv = state; 5057 state->demod = demod; 5058 /* Single or Dual mode */ 5059 state->demod_mode = config->demod_mode; 5060 state->device = config->device; 5061 /* default */ 5062 state->rolloff = STV090x_RO_35; 5063 5064 ret = stv090x_setup_compound(state); 5065 if (ret) 5066 goto error; 5067 5068 return &state->frontend; 5069 5070 error: 5071 kfree(state); 5072 return NULL; 5073 } 5074 EXPORT_SYMBOL_GPL(stv090x_attach); 5075 5076 static const struct i2c_device_id stv090x_id_table[] = { 5077 {"stv090x", 0}, 5078 {} 5079 }; 5080 MODULE_DEVICE_TABLE(i2c, stv090x_id_table); 5081 5082 static struct i2c_driver stv090x_driver = { 5083 .driver = { 5084 .name = "stv090x", 5085 .suppress_bind_attrs = true, 5086 }, 5087 .probe = stv090x_probe, 5088 .remove = stv090x_remove, 5089 .id_table = stv090x_id_table, 5090 }; 5091 5092 module_i2c_driver(stv090x_driver); 5093 5094 MODULE_PARM_DESC(verbose, "Set Verbosity level"); 5095 MODULE_AUTHOR("Manu Abraham"); 5096 MODULE_DESCRIPTION("STV090x Multi-Std Broadcast frontend"); 5097 MODULE_LICENSE("GPL"); 5098