1 /* 2 * stv0900_sw.c 3 * 4 * Driver for ST STV0900 satellite demodulator IC. 5 * 6 * Copyright (C) ST Microelectronics. 7 * Copyright (C) 2009 NetUP Inc. 8 * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * 19 * GNU General Public License for more details. 20 */ 21 22 #include "stv0900.h" 23 #include "stv0900_reg.h" 24 #include "stv0900_priv.h" 25 26 s32 shiftx(s32 x, int demod, s32 shift) 27 { 28 if (demod == 1) 29 return x - shift; 30 31 return x; 32 } 33 34 int stv0900_check_signal_presence(struct stv0900_internal *intp, 35 enum fe_stv0900_demod_num demod) 36 { 37 s32 carr_offset, 38 agc2_integr, 39 max_carrier; 40 41 int no_signal = FALSE; 42 43 carr_offset = (stv0900_read_reg(intp, CFR2) << 8) 44 | stv0900_read_reg(intp, CFR1); 45 carr_offset = ge2comp(carr_offset, 16); 46 agc2_integr = (stv0900_read_reg(intp, AGC2I1) << 8) 47 | stv0900_read_reg(intp, AGC2I0); 48 max_carrier = intp->srch_range[demod] / 1000; 49 50 max_carrier += (max_carrier / 10); 51 max_carrier = 65536 * (max_carrier / 2); 52 max_carrier /= intp->mclk / 1000; 53 if (max_carrier > 0x4000) 54 max_carrier = 0x4000; 55 56 if ((agc2_integr > 0x2000) 57 || (carr_offset > (2 * max_carrier)) 58 || (carr_offset < (-2 * max_carrier))) 59 no_signal = TRUE; 60 61 return no_signal; 62 } 63 64 static void stv0900_get_sw_loop_params(struct stv0900_internal *intp, 65 s32 *frequency_inc, s32 *sw_timeout, 66 s32 *steps, 67 enum fe_stv0900_demod_num demod) 68 { 69 s32 timeout, freq_inc, max_steps, srate, max_carrier; 70 71 enum fe_stv0900_search_standard standard; 72 73 srate = intp->symbol_rate[demod]; 74 max_carrier = intp->srch_range[demod] / 1000; 75 max_carrier += max_carrier / 10; 76 standard = intp->srch_standard[demod]; 77 78 max_carrier = 65536 * (max_carrier / 2); 79 max_carrier /= intp->mclk / 1000; 80 81 if (max_carrier > 0x4000) 82 max_carrier = 0x4000; 83 84 freq_inc = srate; 85 freq_inc /= intp->mclk >> 10; 86 freq_inc = freq_inc << 6; 87 88 switch (standard) { 89 case STV0900_SEARCH_DVBS1: 90 case STV0900_SEARCH_DSS: 91 freq_inc *= 3; 92 timeout = 20; 93 break; 94 case STV0900_SEARCH_DVBS2: 95 freq_inc *= 4; 96 timeout = 25; 97 break; 98 case STV0900_AUTO_SEARCH: 99 default: 100 freq_inc *= 3; 101 timeout = 25; 102 break; 103 } 104 105 freq_inc /= 100; 106 107 if ((freq_inc > max_carrier) || (freq_inc < 0)) 108 freq_inc = max_carrier / 2; 109 110 timeout *= 27500; 111 112 if (srate > 0) 113 timeout /= srate / 1000; 114 115 if ((timeout > 100) || (timeout < 0)) 116 timeout = 100; 117 118 max_steps = (max_carrier / freq_inc) + 1; 119 120 if ((max_steps > 100) || (max_steps < 0)) { 121 max_steps = 100; 122 freq_inc = max_carrier / max_steps; 123 } 124 125 *frequency_inc = freq_inc; 126 *sw_timeout = timeout; 127 *steps = max_steps; 128 129 } 130 131 static int stv0900_search_carr_sw_loop(struct stv0900_internal *intp, 132 s32 FreqIncr, s32 Timeout, int zigzag, 133 s32 MaxStep, enum fe_stv0900_demod_num demod) 134 { 135 int no_signal, 136 lock = FALSE; 137 s32 stepCpt, 138 freqOffset, 139 max_carrier; 140 141 max_carrier = intp->srch_range[demod] / 1000; 142 max_carrier += (max_carrier / 10); 143 144 max_carrier = 65536 * (max_carrier / 2); 145 max_carrier /= intp->mclk / 1000; 146 147 if (max_carrier > 0x4000) 148 max_carrier = 0x4000; 149 150 if (zigzag == TRUE) 151 freqOffset = 0; 152 else 153 freqOffset = -max_carrier + FreqIncr; 154 155 stepCpt = 0; 156 157 do { 158 stv0900_write_reg(intp, DMDISTATE, 0x1c); 159 stv0900_write_reg(intp, CFRINIT1, (freqOffset / 256) & 0xff); 160 stv0900_write_reg(intp, CFRINIT0, freqOffset & 0xff); 161 stv0900_write_reg(intp, DMDISTATE, 0x18); 162 stv0900_write_bits(intp, ALGOSWRST, 1); 163 164 if (intp->chip_id == 0x12) { 165 stv0900_write_bits(intp, RST_HWARE, 1); 166 stv0900_write_bits(intp, RST_HWARE, 0); 167 } 168 169 if (zigzag == TRUE) { 170 if (freqOffset >= 0) 171 freqOffset = -freqOffset - 2 * FreqIncr; 172 else 173 freqOffset = -freqOffset; 174 } else 175 freqOffset += + 2 * FreqIncr; 176 177 stepCpt++; 178 lock = stv0900_get_demod_lock(intp, demod, Timeout); 179 no_signal = stv0900_check_signal_presence(intp, demod); 180 181 } while ((lock == FALSE) 182 && (no_signal == FALSE) 183 && ((freqOffset - FreqIncr) < max_carrier) 184 && ((freqOffset + FreqIncr) > -max_carrier) 185 && (stepCpt < MaxStep)); 186 187 stv0900_write_bits(intp, ALGOSWRST, 0); 188 189 return lock; 190 } 191 192 static int stv0900_sw_algo(struct stv0900_internal *intp, 193 enum fe_stv0900_demod_num demod) 194 { 195 int lock = FALSE, 196 no_signal, 197 zigzag; 198 s32 s2fw, 199 fqc_inc, 200 sft_stp_tout, 201 trial_cntr, 202 max_steps; 203 204 stv0900_get_sw_loop_params(intp, &fqc_inc, &sft_stp_tout, 205 &max_steps, demod); 206 switch (intp->srch_standard[demod]) { 207 case STV0900_SEARCH_DVBS1: 208 case STV0900_SEARCH_DSS: 209 if (intp->chip_id >= 0x20) 210 stv0900_write_reg(intp, CARFREQ, 0x3b); 211 else 212 stv0900_write_reg(intp, CARFREQ, 0xef); 213 214 stv0900_write_reg(intp, DMDCFGMD, 0x49); 215 zigzag = FALSE; 216 break; 217 case STV0900_SEARCH_DVBS2: 218 if (intp->chip_id >= 0x20) 219 stv0900_write_reg(intp, CORRELABS, 0x79); 220 else 221 stv0900_write_reg(intp, CORRELABS, 0x68); 222 223 stv0900_write_reg(intp, DMDCFGMD, 0x89); 224 225 zigzag = TRUE; 226 break; 227 case STV0900_AUTO_SEARCH: 228 default: 229 if (intp->chip_id >= 0x20) { 230 stv0900_write_reg(intp, CARFREQ, 0x3b); 231 stv0900_write_reg(intp, CORRELABS, 0x79); 232 } else { 233 stv0900_write_reg(intp, CARFREQ, 0xef); 234 stv0900_write_reg(intp, CORRELABS, 0x68); 235 } 236 237 stv0900_write_reg(intp, DMDCFGMD, 0xc9); 238 zigzag = FALSE; 239 break; 240 } 241 242 trial_cntr = 0; 243 do { 244 lock = stv0900_search_carr_sw_loop(intp, 245 fqc_inc, 246 sft_stp_tout, 247 zigzag, 248 max_steps, 249 demod); 250 no_signal = stv0900_check_signal_presence(intp, demod); 251 trial_cntr++; 252 if ((lock == TRUE) 253 || (no_signal == TRUE) 254 || (trial_cntr == 2)) { 255 256 if (intp->chip_id >= 0x20) { 257 stv0900_write_reg(intp, CARFREQ, 0x49); 258 stv0900_write_reg(intp, CORRELABS, 0x9e); 259 } else { 260 stv0900_write_reg(intp, CARFREQ, 0xed); 261 stv0900_write_reg(intp, CORRELABS, 0x88); 262 } 263 264 if ((stv0900_get_bits(intp, HEADER_MODE) == 265 STV0900_DVBS2_FOUND) && 266 (lock == TRUE)) { 267 msleep(sft_stp_tout); 268 s2fw = stv0900_get_bits(intp, FLYWHEEL_CPT); 269 270 if (s2fw < 0xd) { 271 msleep(sft_stp_tout); 272 s2fw = stv0900_get_bits(intp, 273 FLYWHEEL_CPT); 274 } 275 276 if (s2fw < 0xd) { 277 lock = FALSE; 278 279 if (trial_cntr < 2) { 280 if (intp->chip_id >= 0x20) 281 stv0900_write_reg(intp, 282 CORRELABS, 283 0x79); 284 else 285 stv0900_write_reg(intp, 286 CORRELABS, 287 0x68); 288 289 stv0900_write_reg(intp, 290 DMDCFGMD, 291 0x89); 292 } 293 } 294 } 295 } 296 297 } while ((lock == FALSE) 298 && (trial_cntr < 2) 299 && (no_signal == FALSE)); 300 301 return lock; 302 } 303 304 static u32 stv0900_get_symbol_rate(struct stv0900_internal *intp, 305 u32 mclk, 306 enum fe_stv0900_demod_num demod) 307 { 308 s32 rem1, rem2, intval1, intval2, srate; 309 310 srate = (stv0900_get_bits(intp, SYMB_FREQ3) << 24) + 311 (stv0900_get_bits(intp, SYMB_FREQ2) << 16) + 312 (stv0900_get_bits(intp, SYMB_FREQ1) << 8) + 313 (stv0900_get_bits(intp, SYMB_FREQ0)); 314 dprintk("lock: srate=%d r0=0x%x r1=0x%x r2=0x%x r3=0x%x \n", 315 srate, stv0900_get_bits(intp, SYMB_FREQ0), 316 stv0900_get_bits(intp, SYMB_FREQ1), 317 stv0900_get_bits(intp, SYMB_FREQ2), 318 stv0900_get_bits(intp, SYMB_FREQ3)); 319 320 intval1 = (mclk) >> 16; 321 intval2 = (srate) >> 16; 322 323 rem1 = (mclk) % 0x10000; 324 rem2 = (srate) % 0x10000; 325 srate = (intval1 * intval2) + 326 ((intval1 * rem2) >> 16) + 327 ((intval2 * rem1) >> 16); 328 329 return srate; 330 } 331 332 static void stv0900_set_symbol_rate(struct stv0900_internal *intp, 333 u32 mclk, u32 srate, 334 enum fe_stv0900_demod_num demod) 335 { 336 u32 symb; 337 338 dprintk("%s: Mclk %d, SR %d, Dmd %d\n", __func__, mclk, 339 srate, demod); 340 341 if (srate > 60000000) { 342 symb = srate << 4; 343 symb /= (mclk >> 12); 344 } else if (srate > 6000000) { 345 symb = srate << 6; 346 symb /= (mclk >> 10); 347 } else { 348 symb = srate << 9; 349 symb /= (mclk >> 7); 350 } 351 352 stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0x7f); 353 stv0900_write_reg(intp, SFRINIT1 + 1, (symb & 0xff)); 354 } 355 356 static void stv0900_set_max_symbol_rate(struct stv0900_internal *intp, 357 u32 mclk, u32 srate, 358 enum fe_stv0900_demod_num demod) 359 { 360 u32 symb; 361 362 srate = 105 * (srate / 100); 363 364 if (srate > 60000000) { 365 symb = srate << 4; 366 symb /= (mclk >> 12); 367 } else if (srate > 6000000) { 368 symb = srate << 6; 369 symb /= (mclk >> 10); 370 } else { 371 symb = srate << 9; 372 symb /= (mclk >> 7); 373 } 374 375 if (symb < 0x7fff) { 376 stv0900_write_reg(intp, SFRUP1, (symb >> 8) & 0x7f); 377 stv0900_write_reg(intp, SFRUP1 + 1, (symb & 0xff)); 378 } else { 379 stv0900_write_reg(intp, SFRUP1, 0x7f); 380 stv0900_write_reg(intp, SFRUP1 + 1, 0xff); 381 } 382 } 383 384 static void stv0900_set_min_symbol_rate(struct stv0900_internal *intp, 385 u32 mclk, u32 srate, 386 enum fe_stv0900_demod_num demod) 387 { 388 u32 symb; 389 390 srate = 95 * (srate / 100); 391 if (srate > 60000000) { 392 symb = srate << 4; 393 symb /= (mclk >> 12); 394 395 } else if (srate > 6000000) { 396 symb = srate << 6; 397 symb /= (mclk >> 10); 398 399 } else { 400 symb = srate << 9; 401 symb /= (mclk >> 7); 402 } 403 404 stv0900_write_reg(intp, SFRLOW1, (symb >> 8) & 0xff); 405 stv0900_write_reg(intp, SFRLOW1 + 1, (symb & 0xff)); 406 } 407 408 static s32 stv0900_get_timing_offst(struct stv0900_internal *intp, 409 u32 srate, 410 enum fe_stv0900_demod_num demod) 411 { 412 s32 timingoffset; 413 414 415 timingoffset = (stv0900_read_reg(intp, TMGREG2) << 16) + 416 (stv0900_read_reg(intp, TMGREG2 + 1) << 8) + 417 (stv0900_read_reg(intp, TMGREG2 + 2)); 418 419 timingoffset = ge2comp(timingoffset, 24); 420 421 422 if (timingoffset == 0) 423 timingoffset = 1; 424 425 timingoffset = ((s32)srate * 10) / ((s32)0x1000000 / timingoffset); 426 timingoffset /= 320; 427 428 return timingoffset; 429 } 430 431 static void stv0900_set_dvbs2_rolloff(struct stv0900_internal *intp, 432 enum fe_stv0900_demod_num demod) 433 { 434 s32 rolloff; 435 436 if (intp->chip_id == 0x10) { 437 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1); 438 rolloff = stv0900_read_reg(intp, MATSTR1) & 0x03; 439 stv0900_write_bits(intp, ROLLOFF_CONTROL, rolloff); 440 } else if (intp->chip_id <= 0x20) 441 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 0); 442 else /* cut 3.0 */ 443 stv0900_write_bits(intp, MANUALS2_ROLLOFF, 0); 444 } 445 446 static u32 stv0900_carrier_width(u32 srate, enum fe_stv0900_rolloff ro) 447 { 448 u32 rolloff; 449 450 switch (ro) { 451 case STV0900_20: 452 rolloff = 20; 453 break; 454 case STV0900_25: 455 rolloff = 25; 456 break; 457 case STV0900_35: 458 default: 459 rolloff = 35; 460 break; 461 } 462 463 return srate + (srate * rolloff) / 100; 464 } 465 466 static int stv0900_check_timing_lock(struct stv0900_internal *intp, 467 enum fe_stv0900_demod_num demod) 468 { 469 int timingLock = FALSE; 470 s32 i, 471 timingcpt = 0; 472 u8 car_freq, 473 tmg_th_high, 474 tmg_th_low; 475 476 car_freq = stv0900_read_reg(intp, CARFREQ); 477 tmg_th_high = stv0900_read_reg(intp, TMGTHRISE); 478 tmg_th_low = stv0900_read_reg(intp, TMGTHFALL); 479 stv0900_write_reg(intp, TMGTHRISE, 0x20); 480 stv0900_write_reg(intp, TMGTHFALL, 0x0); 481 stv0900_write_bits(intp, CFR_AUTOSCAN, 0); 482 stv0900_write_reg(intp, RTC, 0x80); 483 stv0900_write_reg(intp, RTCS2, 0x40); 484 stv0900_write_reg(intp, CARFREQ, 0x0); 485 stv0900_write_reg(intp, CFRINIT1, 0x0); 486 stv0900_write_reg(intp, CFRINIT0, 0x0); 487 stv0900_write_reg(intp, AGC2REF, 0x65); 488 stv0900_write_reg(intp, DMDISTATE, 0x18); 489 msleep(7); 490 491 for (i = 0; i < 10; i++) { 492 if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2) 493 timingcpt++; 494 495 msleep(1); 496 } 497 498 if (timingcpt >= 3) 499 timingLock = TRUE; 500 501 stv0900_write_reg(intp, AGC2REF, 0x38); 502 stv0900_write_reg(intp, RTC, 0x88); 503 stv0900_write_reg(intp, RTCS2, 0x68); 504 stv0900_write_reg(intp, CARFREQ, car_freq); 505 stv0900_write_reg(intp, TMGTHRISE, tmg_th_high); 506 stv0900_write_reg(intp, TMGTHFALL, tmg_th_low); 507 508 return timingLock; 509 } 510 511 static int stv0900_get_demod_cold_lock(struct dvb_frontend *fe, 512 s32 demod_timeout) 513 { 514 struct stv0900_state *state = fe->demodulator_priv; 515 struct stv0900_internal *intp = state->internal; 516 enum fe_stv0900_demod_num demod = state->demod; 517 int lock = FALSE, 518 d = demod; 519 s32 srate, 520 search_range, 521 locktimeout, 522 currier_step, 523 nb_steps, 524 current_step, 525 direction, 526 tuner_freq, 527 timeout, 528 freq; 529 530 srate = intp->symbol_rate[d]; 531 search_range = intp->srch_range[d]; 532 533 if (srate >= 10000000) 534 locktimeout = demod_timeout / 3; 535 else 536 locktimeout = demod_timeout / 2; 537 538 lock = stv0900_get_demod_lock(intp, d, locktimeout); 539 540 if (lock != FALSE) 541 return lock; 542 543 if (srate >= 10000000) { 544 if (stv0900_check_timing_lock(intp, d) == TRUE) { 545 stv0900_write_reg(intp, DMDISTATE, 0x1f); 546 stv0900_write_reg(intp, DMDISTATE, 0x15); 547 lock = stv0900_get_demod_lock(intp, d, demod_timeout); 548 } else 549 lock = FALSE; 550 551 return lock; 552 } 553 554 if (intp->chip_id <= 0x20) { 555 if (srate <= 1000000) 556 currier_step = 500; 557 else if (srate <= 4000000) 558 currier_step = 1000; 559 else if (srate <= 7000000) 560 currier_step = 2000; 561 else if (srate <= 10000000) 562 currier_step = 3000; 563 else 564 currier_step = 5000; 565 566 if (srate >= 2000000) { 567 timeout = (demod_timeout / 3); 568 if (timeout > 1000) 569 timeout = 1000; 570 } else 571 timeout = (demod_timeout / 2); 572 } else { 573 /*cut 3.0 */ 574 currier_step = srate / 4000; 575 timeout = (demod_timeout * 3) / 4; 576 } 577 578 nb_steps = ((search_range / 1000) / currier_step); 579 580 if ((nb_steps % 2) != 0) 581 nb_steps += 1; 582 583 if (nb_steps <= 0) 584 nb_steps = 2; 585 else if (nb_steps > 12) 586 nb_steps = 12; 587 588 current_step = 1; 589 direction = 1; 590 591 if (intp->chip_id <= 0x20) { 592 tuner_freq = intp->freq[d]; 593 intp->bw[d] = stv0900_carrier_width(intp->symbol_rate[d], 594 intp->rolloff) + intp->symbol_rate[d]; 595 } else 596 tuner_freq = 0; 597 598 while ((current_step <= nb_steps) && (lock == FALSE)) { 599 if (direction > 0) 600 tuner_freq += (current_step * currier_step); 601 else 602 tuner_freq -= (current_step * currier_step); 603 604 if (intp->chip_id <= 0x20) { 605 if (intp->tuner_type[d] == 3) 606 stv0900_set_tuner_auto(intp, tuner_freq, 607 intp->bw[d], demod); 608 else 609 stv0900_set_tuner(fe, tuner_freq, intp->bw[d]); 610 611 stv0900_write_reg(intp, DMDISTATE, 0x1c); 612 stv0900_write_reg(intp, CFRINIT1, 0); 613 stv0900_write_reg(intp, CFRINIT0, 0); 614 stv0900_write_reg(intp, DMDISTATE, 0x1f); 615 stv0900_write_reg(intp, DMDISTATE, 0x15); 616 } else { 617 stv0900_write_reg(intp, DMDISTATE, 0x1c); 618 freq = (tuner_freq * 65536) / (intp->mclk / 1000); 619 stv0900_write_bits(intp, CFR_INIT1, MSB(freq)); 620 stv0900_write_bits(intp, CFR_INIT0, LSB(freq)); 621 stv0900_write_reg(intp, DMDISTATE, 0x1f); 622 stv0900_write_reg(intp, DMDISTATE, 0x05); 623 } 624 625 lock = stv0900_get_demod_lock(intp, d, timeout); 626 direction *= -1; 627 current_step++; 628 } 629 630 return lock; 631 } 632 633 static void stv0900_get_lock_timeout(s32 *demod_timeout, s32 *fec_timeout, 634 s32 srate, 635 enum fe_stv0900_search_algo algo) 636 { 637 switch (algo) { 638 case STV0900_BLIND_SEARCH: 639 if (srate <= 1500000) { 640 (*demod_timeout) = 1500; 641 (*fec_timeout) = 400; 642 } else if (srate <= 5000000) { 643 (*demod_timeout) = 1000; 644 (*fec_timeout) = 300; 645 } else { 646 (*demod_timeout) = 700; 647 (*fec_timeout) = 100; 648 } 649 650 break; 651 case STV0900_COLD_START: 652 case STV0900_WARM_START: 653 default: 654 if (srate <= 1000000) { 655 (*demod_timeout) = 3000; 656 (*fec_timeout) = 1700; 657 } else if (srate <= 2000000) { 658 (*demod_timeout) = 2500; 659 (*fec_timeout) = 1100; 660 } else if (srate <= 5000000) { 661 (*demod_timeout) = 1000; 662 (*fec_timeout) = 550; 663 } else if (srate <= 10000000) { 664 (*demod_timeout) = 700; 665 (*fec_timeout) = 250; 666 } else if (srate <= 20000000) { 667 (*demod_timeout) = 400; 668 (*fec_timeout) = 130; 669 } else { 670 (*demod_timeout) = 300; 671 (*fec_timeout) = 100; 672 } 673 674 break; 675 676 } 677 678 if (algo == STV0900_WARM_START) 679 (*demod_timeout) /= 2; 680 } 681 682 static void stv0900_set_viterbi_tracq(struct stv0900_internal *intp, 683 enum fe_stv0900_demod_num demod) 684 { 685 686 s32 vth_reg = VTH12; 687 688 dprintk("%s\n", __func__); 689 690 stv0900_write_reg(intp, vth_reg++, 0xd0); 691 stv0900_write_reg(intp, vth_reg++, 0x7d); 692 stv0900_write_reg(intp, vth_reg++, 0x53); 693 stv0900_write_reg(intp, vth_reg++, 0x2f); 694 stv0900_write_reg(intp, vth_reg++, 0x24); 695 stv0900_write_reg(intp, vth_reg++, 0x1f); 696 } 697 698 static void stv0900_set_viterbi_standard(struct stv0900_internal *intp, 699 enum fe_stv0900_search_standard standard, 700 enum fe_stv0900_fec fec, 701 enum fe_stv0900_demod_num demod) 702 { 703 dprintk("%s: ViterbiStandard = ", __func__); 704 705 switch (standard) { 706 case STV0900_AUTO_SEARCH: 707 dprintk("Auto\n"); 708 stv0900_write_reg(intp, FECM, 0x10); 709 stv0900_write_reg(intp, PRVIT, 0x3f); 710 break; 711 case STV0900_SEARCH_DVBS1: 712 dprintk("DVBS1\n"); 713 stv0900_write_reg(intp, FECM, 0x00); 714 switch (fec) { 715 case STV0900_FEC_UNKNOWN: 716 default: 717 stv0900_write_reg(intp, PRVIT, 0x2f); 718 break; 719 case STV0900_FEC_1_2: 720 stv0900_write_reg(intp, PRVIT, 0x01); 721 break; 722 case STV0900_FEC_2_3: 723 stv0900_write_reg(intp, PRVIT, 0x02); 724 break; 725 case STV0900_FEC_3_4: 726 stv0900_write_reg(intp, PRVIT, 0x04); 727 break; 728 case STV0900_FEC_5_6: 729 stv0900_write_reg(intp, PRVIT, 0x08); 730 break; 731 case STV0900_FEC_7_8: 732 stv0900_write_reg(intp, PRVIT, 0x20); 733 break; 734 } 735 736 break; 737 case STV0900_SEARCH_DSS: 738 dprintk("DSS\n"); 739 stv0900_write_reg(intp, FECM, 0x80); 740 switch (fec) { 741 case STV0900_FEC_UNKNOWN: 742 default: 743 stv0900_write_reg(intp, PRVIT, 0x13); 744 break; 745 case STV0900_FEC_1_2: 746 stv0900_write_reg(intp, PRVIT, 0x01); 747 break; 748 case STV0900_FEC_2_3: 749 stv0900_write_reg(intp, PRVIT, 0x02); 750 break; 751 case STV0900_FEC_6_7: 752 stv0900_write_reg(intp, PRVIT, 0x10); 753 break; 754 } 755 break; 756 default: 757 break; 758 } 759 } 760 761 static enum fe_stv0900_fec stv0900_get_vit_fec(struct stv0900_internal *intp, 762 enum fe_stv0900_demod_num demod) 763 { 764 enum fe_stv0900_fec prate; 765 s32 rate_fld = stv0900_get_bits(intp, VIT_CURPUN); 766 767 switch (rate_fld) { 768 case 13: 769 prate = STV0900_FEC_1_2; 770 break; 771 case 18: 772 prate = STV0900_FEC_2_3; 773 break; 774 case 21: 775 prate = STV0900_FEC_3_4; 776 break; 777 case 24: 778 prate = STV0900_FEC_5_6; 779 break; 780 case 25: 781 prate = STV0900_FEC_6_7; 782 break; 783 case 26: 784 prate = STV0900_FEC_7_8; 785 break; 786 default: 787 prate = STV0900_FEC_UNKNOWN; 788 break; 789 } 790 791 return prate; 792 } 793 794 static void stv0900_set_dvbs1_track_car_loop(struct stv0900_internal *intp, 795 enum fe_stv0900_demod_num demod, 796 u32 srate) 797 { 798 if (intp->chip_id >= 0x30) { 799 if (srate >= 15000000) { 800 stv0900_write_reg(intp, ACLC, 0x2b); 801 stv0900_write_reg(intp, BCLC, 0x1a); 802 } else if ((srate >= 7000000) && (15000000 > srate)) { 803 stv0900_write_reg(intp, ACLC, 0x0c); 804 stv0900_write_reg(intp, BCLC, 0x1b); 805 } else if (srate < 7000000) { 806 stv0900_write_reg(intp, ACLC, 0x2c); 807 stv0900_write_reg(intp, BCLC, 0x1c); 808 } 809 810 } else { /*cut 2.0 and 1.x*/ 811 stv0900_write_reg(intp, ACLC, 0x1a); 812 stv0900_write_reg(intp, BCLC, 0x09); 813 } 814 815 } 816 817 static void stv0900_track_optimization(struct dvb_frontend *fe) 818 { 819 struct stv0900_state *state = fe->demodulator_priv; 820 struct stv0900_internal *intp = state->internal; 821 enum fe_stv0900_demod_num demod = state->demod; 822 823 s32 srate, 824 pilots, 825 aclc, 826 freq1, 827 freq0, 828 i = 0, 829 timed, 830 timef, 831 blind_tun_sw = 0, 832 modulation; 833 834 enum fe_stv0900_modcode foundModcod; 835 836 dprintk("%s\n", __func__); 837 838 srate = stv0900_get_symbol_rate(intp, intp->mclk, demod); 839 srate += stv0900_get_timing_offst(intp, srate, demod); 840 841 switch (intp->result[demod].standard) { 842 case STV0900_DVBS1_STANDARD: 843 case STV0900_DSS_STANDARD: 844 dprintk("%s: found DVB-S or DSS\n", __func__); 845 if (intp->srch_standard[demod] == STV0900_AUTO_SEARCH) { 846 stv0900_write_bits(intp, DVBS1_ENABLE, 1); 847 stv0900_write_bits(intp, DVBS2_ENABLE, 0); 848 } 849 850 stv0900_write_bits(intp, ROLLOFF_CONTROL, intp->rolloff); 851 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1); 852 853 if (intp->chip_id < 0x30) { 854 stv0900_write_reg(intp, ERRCTRL1, 0x75); 855 break; 856 } 857 858 if (stv0900_get_vit_fec(intp, demod) == STV0900_FEC_1_2) { 859 stv0900_write_reg(intp, GAUSSR0, 0x98); 860 stv0900_write_reg(intp, CCIR0, 0x18); 861 } else { 862 stv0900_write_reg(intp, GAUSSR0, 0x18); 863 stv0900_write_reg(intp, CCIR0, 0x18); 864 } 865 866 stv0900_write_reg(intp, ERRCTRL1, 0x75); 867 break; 868 case STV0900_DVBS2_STANDARD: 869 dprintk("%s: found DVB-S2\n", __func__); 870 stv0900_write_bits(intp, DVBS1_ENABLE, 0); 871 stv0900_write_bits(intp, DVBS2_ENABLE, 1); 872 stv0900_write_reg(intp, ACLC, 0); 873 stv0900_write_reg(intp, BCLC, 0); 874 if (intp->result[demod].frame_len == STV0900_LONG_FRAME) { 875 foundModcod = stv0900_get_bits(intp, DEMOD_MODCOD); 876 pilots = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01; 877 aclc = stv0900_get_optim_carr_loop(srate, 878 foundModcod, 879 pilots, 880 intp->chip_id); 881 if (foundModcod <= STV0900_QPSK_910) 882 stv0900_write_reg(intp, ACLC2S2Q, aclc); 883 else if (foundModcod <= STV0900_8PSK_910) { 884 stv0900_write_reg(intp, ACLC2S2Q, 0x2a); 885 stv0900_write_reg(intp, ACLC2S28, aclc); 886 } 887 888 if ((intp->demod_mode == STV0900_SINGLE) && 889 (foundModcod > STV0900_8PSK_910)) { 890 if (foundModcod <= STV0900_16APSK_910) { 891 stv0900_write_reg(intp, ACLC2S2Q, 0x2a); 892 stv0900_write_reg(intp, ACLC2S216A, 893 aclc); 894 } else if (foundModcod <= STV0900_32APSK_910) { 895 stv0900_write_reg(intp, ACLC2S2Q, 0x2a); 896 stv0900_write_reg(intp, ACLC2S232A, 897 aclc); 898 } 899 } 900 901 } else { 902 modulation = intp->result[demod].modulation; 903 aclc = stv0900_get_optim_short_carr_loop(srate, 904 modulation, intp->chip_id); 905 if (modulation == STV0900_QPSK) 906 stv0900_write_reg(intp, ACLC2S2Q, aclc); 907 else if (modulation == STV0900_8PSK) { 908 stv0900_write_reg(intp, ACLC2S2Q, 0x2a); 909 stv0900_write_reg(intp, ACLC2S28, aclc); 910 } else if (modulation == STV0900_16APSK) { 911 stv0900_write_reg(intp, ACLC2S2Q, 0x2a); 912 stv0900_write_reg(intp, ACLC2S216A, aclc); 913 } else if (modulation == STV0900_32APSK) { 914 stv0900_write_reg(intp, ACLC2S2Q, 0x2a); 915 stv0900_write_reg(intp, ACLC2S232A, aclc); 916 } 917 918 } 919 920 if (intp->chip_id <= 0x11) { 921 if (intp->demod_mode != STV0900_SINGLE) 922 stv0900_activate_s2_modcod(intp, demod); 923 924 } 925 926 stv0900_write_reg(intp, ERRCTRL1, 0x67); 927 break; 928 case STV0900_UNKNOWN_STANDARD: 929 default: 930 dprintk("%s: found unknown standard\n", __func__); 931 stv0900_write_bits(intp, DVBS1_ENABLE, 1); 932 stv0900_write_bits(intp, DVBS2_ENABLE, 1); 933 break; 934 } 935 936 freq1 = stv0900_read_reg(intp, CFR2); 937 freq0 = stv0900_read_reg(intp, CFR1); 938 if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) { 939 stv0900_write_reg(intp, SFRSTEP, 0x00); 940 stv0900_write_bits(intp, SCAN_ENABLE, 0); 941 stv0900_write_bits(intp, CFR_AUTOSCAN, 0); 942 stv0900_write_reg(intp, TMGCFG2, 0xc1); 943 stv0900_set_symbol_rate(intp, intp->mclk, srate, demod); 944 blind_tun_sw = 1; 945 if (intp->result[demod].standard != STV0900_DVBS2_STANDARD) 946 stv0900_set_dvbs1_track_car_loop(intp, demod, srate); 947 948 } 949 950 if (intp->chip_id >= 0x20) { 951 if ((intp->srch_standard[demod] == STV0900_SEARCH_DVBS1) || 952 (intp->srch_standard[demod] == 953 STV0900_SEARCH_DSS) || 954 (intp->srch_standard[demod] == 955 STV0900_AUTO_SEARCH)) { 956 stv0900_write_reg(intp, VAVSRVIT, 0x0a); 957 stv0900_write_reg(intp, VITSCALE, 0x0); 958 } 959 } 960 961 if (intp->chip_id < 0x20) 962 stv0900_write_reg(intp, CARHDR, 0x08); 963 964 if (intp->chip_id == 0x10) 965 stv0900_write_reg(intp, CORRELEXP, 0x0a); 966 967 stv0900_write_reg(intp, AGC2REF, 0x38); 968 969 if ((intp->chip_id >= 0x20) || 970 (blind_tun_sw == 1) || 971 (intp->symbol_rate[demod] < 10000000)) { 972 stv0900_write_reg(intp, CFRINIT1, freq1); 973 stv0900_write_reg(intp, CFRINIT0, freq0); 974 intp->bw[demod] = stv0900_carrier_width(srate, 975 intp->rolloff) + 10000000; 976 977 if ((intp->chip_id >= 0x20) || (blind_tun_sw == 1)) { 978 if (intp->srch_algo[demod] != STV0900_WARM_START) { 979 if (intp->tuner_type[demod] == 3) 980 stv0900_set_tuner_auto(intp, 981 intp->freq[demod], 982 intp->bw[demod], 983 demod); 984 else 985 stv0900_set_bandwidth(fe, 986 intp->bw[demod]); 987 } 988 } 989 990 if ((intp->srch_algo[demod] == STV0900_BLIND_SEARCH) || 991 (intp->symbol_rate[demod] < 10000000)) 992 msleep(50); 993 else 994 msleep(5); 995 996 stv0900_get_lock_timeout(&timed, &timef, srate, 997 STV0900_WARM_START); 998 999 if (stv0900_get_demod_lock(intp, demod, timed / 2) == FALSE) { 1000 stv0900_write_reg(intp, DMDISTATE, 0x1f); 1001 stv0900_write_reg(intp, CFRINIT1, freq1); 1002 stv0900_write_reg(intp, CFRINIT0, freq0); 1003 stv0900_write_reg(intp, DMDISTATE, 0x18); 1004 i = 0; 1005 while ((stv0900_get_demod_lock(intp, 1006 demod, 1007 timed / 2) == FALSE) && 1008 (i <= 2)) { 1009 stv0900_write_reg(intp, DMDISTATE, 0x1f); 1010 stv0900_write_reg(intp, CFRINIT1, freq1); 1011 stv0900_write_reg(intp, CFRINIT0, freq0); 1012 stv0900_write_reg(intp, DMDISTATE, 0x18); 1013 i++; 1014 } 1015 } 1016 1017 } 1018 1019 if (intp->chip_id >= 0x20) 1020 stv0900_write_reg(intp, CARFREQ, 0x49); 1021 1022 if ((intp->result[demod].standard == STV0900_DVBS1_STANDARD) || 1023 (intp->result[demod].standard == STV0900_DSS_STANDARD)) 1024 stv0900_set_viterbi_tracq(intp, demod); 1025 1026 } 1027 1028 static int stv0900_get_fec_lock(struct stv0900_internal *intp, 1029 enum fe_stv0900_demod_num demod, s32 time_out) 1030 { 1031 s32 timer = 0, lock = 0; 1032 1033 enum fe_stv0900_search_state dmd_state; 1034 1035 dprintk("%s\n", __func__); 1036 1037 dmd_state = stv0900_get_bits(intp, HEADER_MODE); 1038 1039 while ((timer < time_out) && (lock == 0)) { 1040 switch (dmd_state) { 1041 case STV0900_SEARCH: 1042 case STV0900_PLH_DETECTED: 1043 default: 1044 lock = 0; 1045 break; 1046 case STV0900_DVBS2_FOUND: 1047 lock = stv0900_get_bits(intp, PKTDELIN_LOCK); 1048 break; 1049 case STV0900_DVBS_FOUND: 1050 lock = stv0900_get_bits(intp, LOCKEDVIT); 1051 break; 1052 } 1053 1054 if (lock == 0) { 1055 msleep(10); 1056 timer += 10; 1057 } 1058 } 1059 1060 if (lock) 1061 dprintk("%s: DEMOD FEC LOCK OK\n", __func__); 1062 else 1063 dprintk("%s: DEMOD FEC LOCK FAIL\n", __func__); 1064 1065 return lock; 1066 } 1067 1068 static int stv0900_wait_for_lock(struct stv0900_internal *intp, 1069 enum fe_stv0900_demod_num demod, 1070 s32 dmd_timeout, s32 fec_timeout) 1071 { 1072 1073 s32 timer = 0, lock = 0; 1074 1075 dprintk("%s\n", __func__); 1076 1077 lock = stv0900_get_demod_lock(intp, demod, dmd_timeout); 1078 1079 if (lock) 1080 lock = stv0900_get_fec_lock(intp, demod, fec_timeout); 1081 1082 if (lock) { 1083 lock = 0; 1084 1085 dprintk("%s: Timer = %d, time_out = %d\n", 1086 __func__, timer, fec_timeout); 1087 1088 while ((timer < fec_timeout) && (lock == 0)) { 1089 lock = stv0900_get_bits(intp, TSFIFO_LINEOK); 1090 msleep(1); 1091 timer++; 1092 } 1093 } 1094 1095 if (lock) 1096 dprintk("%s: DEMOD LOCK OK\n", __func__); 1097 else 1098 dprintk("%s: DEMOD LOCK FAIL\n", __func__); 1099 1100 if (lock) 1101 return TRUE; 1102 else 1103 return FALSE; 1104 } 1105 1106 enum fe_stv0900_tracking_standard stv0900_get_standard(struct dvb_frontend *fe, 1107 enum fe_stv0900_demod_num demod) 1108 { 1109 struct stv0900_state *state = fe->demodulator_priv; 1110 struct stv0900_internal *intp = state->internal; 1111 enum fe_stv0900_tracking_standard fnd_standard; 1112 1113 int hdr_mode = stv0900_get_bits(intp, HEADER_MODE); 1114 1115 switch (hdr_mode) { 1116 case 2: 1117 fnd_standard = STV0900_DVBS2_STANDARD; 1118 break; 1119 case 3: 1120 if (stv0900_get_bits(intp, DSS_DVB) == 1) 1121 fnd_standard = STV0900_DSS_STANDARD; 1122 else 1123 fnd_standard = STV0900_DVBS1_STANDARD; 1124 1125 break; 1126 default: 1127 fnd_standard = STV0900_UNKNOWN_STANDARD; 1128 } 1129 1130 dprintk("%s: standard %d\n", __func__, fnd_standard); 1131 1132 return fnd_standard; 1133 } 1134 1135 static s32 stv0900_get_carr_freq(struct stv0900_internal *intp, u32 mclk, 1136 enum fe_stv0900_demod_num demod) 1137 { 1138 s32 derot, 1139 rem1, 1140 rem2, 1141 intval1, 1142 intval2; 1143 1144 derot = (stv0900_get_bits(intp, CAR_FREQ2) << 16) + 1145 (stv0900_get_bits(intp, CAR_FREQ1) << 8) + 1146 (stv0900_get_bits(intp, CAR_FREQ0)); 1147 1148 derot = ge2comp(derot, 24); 1149 intval1 = mclk >> 12; 1150 intval2 = derot >> 12; 1151 rem1 = mclk % 0x1000; 1152 rem2 = derot % 0x1000; 1153 derot = (intval1 * intval2) + 1154 ((intval1 * rem2) >> 12) + 1155 ((intval2 * rem1) >> 12); 1156 1157 return derot; 1158 } 1159 1160 static u32 stv0900_get_tuner_freq(struct dvb_frontend *fe) 1161 { 1162 struct dvb_frontend_ops *frontend_ops = NULL; 1163 struct dvb_tuner_ops *tuner_ops = NULL; 1164 u32 freq = 0; 1165 1166 frontend_ops = &fe->ops; 1167 tuner_ops = &frontend_ops->tuner_ops; 1168 1169 if (tuner_ops->get_frequency) { 1170 if ((tuner_ops->get_frequency(fe, &freq)) < 0) 1171 dprintk("%s: Invalid parameter\n", __func__); 1172 else 1173 dprintk("%s: Frequency=%d\n", __func__, freq); 1174 1175 } 1176 1177 return freq; 1178 } 1179 1180 static enum 1181 fe_stv0900_signal_type stv0900_get_signal_params(struct dvb_frontend *fe) 1182 { 1183 struct stv0900_state *state = fe->demodulator_priv; 1184 struct stv0900_internal *intp = state->internal; 1185 enum fe_stv0900_demod_num demod = state->demod; 1186 enum fe_stv0900_signal_type range = STV0900_OUTOFRANGE; 1187 struct stv0900_signal_info *result = &intp->result[demod]; 1188 s32 offsetFreq, 1189 srate_offset; 1190 int i = 0, 1191 d = demod; 1192 1193 u8 timing; 1194 1195 msleep(5); 1196 if (intp->srch_algo[d] == STV0900_BLIND_SEARCH) { 1197 timing = stv0900_read_reg(intp, TMGREG2); 1198 i = 0; 1199 stv0900_write_reg(intp, SFRSTEP, 0x5c); 1200 1201 while ((i <= 50) && (timing != 0) && (timing != 0xff)) { 1202 timing = stv0900_read_reg(intp, TMGREG2); 1203 msleep(5); 1204 i += 5; 1205 } 1206 } 1207 1208 result->standard = stv0900_get_standard(fe, d); 1209 if (intp->tuner_type[demod] == 3) 1210 result->frequency = stv0900_get_freq_auto(intp, d); 1211 else 1212 result->frequency = stv0900_get_tuner_freq(fe); 1213 1214 offsetFreq = stv0900_get_carr_freq(intp, intp->mclk, d) / 1000; 1215 result->frequency += offsetFreq; 1216 result->symbol_rate = stv0900_get_symbol_rate(intp, intp->mclk, d); 1217 srate_offset = stv0900_get_timing_offst(intp, result->symbol_rate, d); 1218 result->symbol_rate += srate_offset; 1219 result->fec = stv0900_get_vit_fec(intp, d); 1220 result->modcode = stv0900_get_bits(intp, DEMOD_MODCOD); 1221 result->pilot = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01; 1222 result->frame_len = ((u32)stv0900_get_bits(intp, DEMOD_TYPE)) >> 1; 1223 result->rolloff = stv0900_get_bits(intp, ROLLOFF_STATUS); 1224 1225 dprintk("%s: modcode=0x%x \n", __func__, result->modcode); 1226 1227 switch (result->standard) { 1228 case STV0900_DVBS2_STANDARD: 1229 result->spectrum = stv0900_get_bits(intp, SPECINV_DEMOD); 1230 if (result->modcode <= STV0900_QPSK_910) 1231 result->modulation = STV0900_QPSK; 1232 else if (result->modcode <= STV0900_8PSK_910) 1233 result->modulation = STV0900_8PSK; 1234 else if (result->modcode <= STV0900_16APSK_910) 1235 result->modulation = STV0900_16APSK; 1236 else if (result->modcode <= STV0900_32APSK_910) 1237 result->modulation = STV0900_32APSK; 1238 else 1239 result->modulation = STV0900_UNKNOWN; 1240 break; 1241 case STV0900_DVBS1_STANDARD: 1242 case STV0900_DSS_STANDARD: 1243 result->spectrum = stv0900_get_bits(intp, IQINV); 1244 result->modulation = STV0900_QPSK; 1245 break; 1246 default: 1247 break; 1248 } 1249 1250 if ((intp->srch_algo[d] == STV0900_BLIND_SEARCH) || 1251 (intp->symbol_rate[d] < 10000000)) { 1252 offsetFreq = result->frequency - intp->freq[d]; 1253 if (intp->tuner_type[demod] == 3) 1254 intp->freq[d] = stv0900_get_freq_auto(intp, d); 1255 else 1256 intp->freq[d] = stv0900_get_tuner_freq(fe); 1257 1258 if (abs(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500)) 1259 range = STV0900_RANGEOK; 1260 else if (abs(offsetFreq) <= 1261 (stv0900_carrier_width(result->symbol_rate, 1262 result->rolloff) / 2000)) 1263 range = STV0900_RANGEOK; 1264 1265 } else if (abs(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500)) 1266 range = STV0900_RANGEOK; 1267 1268 dprintk("%s: range %d\n", __func__, range); 1269 1270 return range; 1271 } 1272 1273 static enum 1274 fe_stv0900_signal_type stv0900_dvbs1_acq_workaround(struct dvb_frontend *fe) 1275 { 1276 struct stv0900_state *state = fe->demodulator_priv; 1277 struct stv0900_internal *intp = state->internal; 1278 enum fe_stv0900_demod_num demod = state->demod; 1279 enum fe_stv0900_signal_type signal_type = STV0900_NODATA; 1280 1281 s32 srate, 1282 demod_timeout, 1283 fec_timeout, 1284 freq1, 1285 freq0; 1286 1287 intp->result[demod].locked = FALSE; 1288 1289 if (stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) { 1290 srate = stv0900_get_symbol_rate(intp, intp->mclk, demod); 1291 srate += stv0900_get_timing_offst(intp, srate, demod); 1292 if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) 1293 stv0900_set_symbol_rate(intp, intp->mclk, srate, demod); 1294 1295 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout, 1296 srate, STV0900_WARM_START); 1297 freq1 = stv0900_read_reg(intp, CFR2); 1298 freq0 = stv0900_read_reg(intp, CFR1); 1299 stv0900_write_bits(intp, CFR_AUTOSCAN, 0); 1300 stv0900_write_bits(intp, SPECINV_CONTROL, 1301 STV0900_IQ_FORCE_SWAPPED); 1302 stv0900_write_reg(intp, DMDISTATE, 0x1c); 1303 stv0900_write_reg(intp, CFRINIT1, freq1); 1304 stv0900_write_reg(intp, CFRINIT0, freq0); 1305 stv0900_write_reg(intp, DMDISTATE, 0x18); 1306 if (stv0900_wait_for_lock(intp, demod, 1307 demod_timeout, fec_timeout) == TRUE) { 1308 intp->result[demod].locked = TRUE; 1309 signal_type = stv0900_get_signal_params(fe); 1310 stv0900_track_optimization(fe); 1311 } else { 1312 stv0900_write_bits(intp, SPECINV_CONTROL, 1313 STV0900_IQ_FORCE_NORMAL); 1314 stv0900_write_reg(intp, DMDISTATE, 0x1c); 1315 stv0900_write_reg(intp, CFRINIT1, freq1); 1316 stv0900_write_reg(intp, CFRINIT0, freq0); 1317 stv0900_write_reg(intp, DMDISTATE, 0x18); 1318 if (stv0900_wait_for_lock(intp, demod, 1319 demod_timeout, fec_timeout) == TRUE) { 1320 intp->result[demod].locked = TRUE; 1321 signal_type = stv0900_get_signal_params(fe); 1322 stv0900_track_optimization(fe); 1323 } 1324 1325 } 1326 1327 } else 1328 intp->result[demod].locked = FALSE; 1329 1330 return signal_type; 1331 } 1332 1333 static u16 stv0900_blind_check_agc2_min_level(struct stv0900_internal *intp, 1334 enum fe_stv0900_demod_num demod) 1335 { 1336 u32 minagc2level = 0xffff, 1337 agc2level, 1338 init_freq, freq_step; 1339 1340 s32 i, j, nb_steps, direction; 1341 1342 dprintk("%s\n", __func__); 1343 1344 stv0900_write_reg(intp, AGC2REF, 0x38); 1345 stv0900_write_bits(intp, SCAN_ENABLE, 0); 1346 stv0900_write_bits(intp, CFR_AUTOSCAN, 0); 1347 1348 stv0900_write_bits(intp, AUTO_GUP, 1); 1349 stv0900_write_bits(intp, AUTO_GLOW, 1); 1350 1351 stv0900_write_reg(intp, DMDT0M, 0x0); 1352 1353 stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod); 1354 nb_steps = -1 + (intp->srch_range[demod] / 1000000); 1355 nb_steps /= 2; 1356 nb_steps = (2 * nb_steps) + 1; 1357 1358 if (nb_steps < 0) 1359 nb_steps = 1; 1360 1361 direction = 1; 1362 1363 freq_step = (1000000 << 8) / (intp->mclk >> 8); 1364 1365 init_freq = 0; 1366 1367 for (i = 0; i < nb_steps; i++) { 1368 if (direction > 0) 1369 init_freq = init_freq + (freq_step * i); 1370 else 1371 init_freq = init_freq - (freq_step * i); 1372 1373 direction *= -1; 1374 stv0900_write_reg(intp, DMDISTATE, 0x5C); 1375 stv0900_write_reg(intp, CFRINIT1, (init_freq >> 8) & 0xff); 1376 stv0900_write_reg(intp, CFRINIT0, init_freq & 0xff); 1377 stv0900_write_reg(intp, DMDISTATE, 0x58); 1378 msleep(10); 1379 agc2level = 0; 1380 1381 for (j = 0; j < 10; j++) 1382 agc2level += (stv0900_read_reg(intp, AGC2I1) << 8) 1383 | stv0900_read_reg(intp, AGC2I0); 1384 1385 agc2level /= 10; 1386 1387 if (agc2level < minagc2level) 1388 minagc2level = agc2level; 1389 1390 } 1391 1392 return (u16)minagc2level; 1393 } 1394 1395 static u32 stv0900_search_srate_coarse(struct dvb_frontend *fe) 1396 { 1397 struct stv0900_state *state = fe->demodulator_priv; 1398 struct stv0900_internal *intp = state->internal; 1399 enum fe_stv0900_demod_num demod = state->demod; 1400 int timing_lck = FALSE; 1401 s32 i, timingcpt = 0, 1402 direction = 1, 1403 nb_steps, 1404 current_step = 0, 1405 tuner_freq; 1406 u32 agc2_th, 1407 coarse_srate = 0, 1408 agc2_integr = 0, 1409 currier_step = 1200; 1410 1411 if (intp->chip_id >= 0x30) 1412 agc2_th = 0x2e00; 1413 else 1414 agc2_th = 0x1f00; 1415 1416 stv0900_write_bits(intp, DEMOD_MODE, 0x1f); 1417 stv0900_write_reg(intp, TMGCFG, 0x12); 1418 stv0900_write_reg(intp, TMGTHRISE, 0xf0); 1419 stv0900_write_reg(intp, TMGTHFALL, 0xe0); 1420 stv0900_write_bits(intp, SCAN_ENABLE, 1); 1421 stv0900_write_bits(intp, CFR_AUTOSCAN, 1); 1422 stv0900_write_reg(intp, SFRUP1, 0x83); 1423 stv0900_write_reg(intp, SFRUP0, 0xc0); 1424 stv0900_write_reg(intp, SFRLOW1, 0x82); 1425 stv0900_write_reg(intp, SFRLOW0, 0xa0); 1426 stv0900_write_reg(intp, DMDT0M, 0x0); 1427 stv0900_write_reg(intp, AGC2REF, 0x50); 1428 1429 if (intp->chip_id >= 0x30) { 1430 stv0900_write_reg(intp, CARFREQ, 0x99); 1431 stv0900_write_reg(intp, SFRSTEP, 0x98); 1432 } else if (intp->chip_id >= 0x20) { 1433 stv0900_write_reg(intp, CARFREQ, 0x6a); 1434 stv0900_write_reg(intp, SFRSTEP, 0x95); 1435 } else { 1436 stv0900_write_reg(intp, CARFREQ, 0xed); 1437 stv0900_write_reg(intp, SFRSTEP, 0x73); 1438 } 1439 1440 if (intp->symbol_rate[demod] <= 2000000) 1441 currier_step = 1000; 1442 else if (intp->symbol_rate[demod] <= 5000000) 1443 currier_step = 2000; 1444 else if (intp->symbol_rate[demod] <= 12000000) 1445 currier_step = 3000; 1446 else 1447 currier_step = 5000; 1448 1449 nb_steps = -1 + ((intp->srch_range[demod] / 1000) / currier_step); 1450 nb_steps /= 2; 1451 nb_steps = (2 * nb_steps) + 1; 1452 1453 if (nb_steps < 0) 1454 nb_steps = 1; 1455 else if (nb_steps > 10) { 1456 nb_steps = 11; 1457 currier_step = (intp->srch_range[demod] / 1000) / 10; 1458 } 1459 1460 current_step = 0; 1461 direction = 1; 1462 1463 tuner_freq = intp->freq[demod]; 1464 1465 while ((timing_lck == FALSE) && (current_step < nb_steps)) { 1466 stv0900_write_reg(intp, DMDISTATE, 0x5f); 1467 stv0900_write_bits(intp, DEMOD_MODE, 0); 1468 1469 msleep(50); 1470 1471 for (i = 0; i < 10; i++) { 1472 if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2) 1473 timingcpt++; 1474 1475 agc2_integr += (stv0900_read_reg(intp, AGC2I1) << 8) | 1476 stv0900_read_reg(intp, AGC2I0); 1477 } 1478 1479 agc2_integr /= 10; 1480 coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod); 1481 current_step++; 1482 direction *= -1; 1483 1484 dprintk("lock: I2C_DEMOD_MODE_FIELD =0. Search started. tuner freq=%d agc2=0x%x srate_coarse=%d tmg_cpt=%d\n", 1485 tuner_freq, agc2_integr, coarse_srate, timingcpt); 1486 1487 if ((timingcpt >= 5) && 1488 (agc2_integr < agc2_th) && 1489 (coarse_srate < 55000000) && 1490 (coarse_srate > 850000)) 1491 timing_lck = TRUE; 1492 else if (current_step < nb_steps) { 1493 if (direction > 0) 1494 tuner_freq += (current_step * currier_step); 1495 else 1496 tuner_freq -= (current_step * currier_step); 1497 1498 if (intp->tuner_type[demod] == 3) 1499 stv0900_set_tuner_auto(intp, tuner_freq, 1500 intp->bw[demod], demod); 1501 else 1502 stv0900_set_tuner(fe, tuner_freq, 1503 intp->bw[demod]); 1504 } 1505 } 1506 1507 if (timing_lck == FALSE) 1508 coarse_srate = 0; 1509 else 1510 coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod); 1511 1512 return coarse_srate; 1513 } 1514 1515 static u32 stv0900_search_srate_fine(struct dvb_frontend *fe) 1516 { 1517 struct stv0900_state *state = fe->demodulator_priv; 1518 struct stv0900_internal *intp = state->internal; 1519 enum fe_stv0900_demod_num demod = state->demod; 1520 u32 coarse_srate, 1521 coarse_freq, 1522 symb, 1523 symbmax, 1524 symbmin, 1525 symbcomp; 1526 1527 coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod); 1528 1529 if (coarse_srate > 3000000) { 1530 symbmax = 13 * (coarse_srate / 10); 1531 symbmax = (symbmax / 1000) * 65536; 1532 symbmax /= (intp->mclk / 1000); 1533 1534 symbmin = 10 * (coarse_srate / 13); 1535 symbmin = (symbmin / 1000)*65536; 1536 symbmin /= (intp->mclk / 1000); 1537 1538 symb = (coarse_srate / 1000) * 65536; 1539 symb /= (intp->mclk / 1000); 1540 } else { 1541 symbmax = 13 * (coarse_srate / 10); 1542 symbmax = (symbmax / 100) * 65536; 1543 symbmax /= (intp->mclk / 100); 1544 1545 symbmin = 10 * (coarse_srate / 14); 1546 symbmin = (symbmin / 100) * 65536; 1547 symbmin /= (intp->mclk / 100); 1548 1549 symb = (coarse_srate / 100) * 65536; 1550 symb /= (intp->mclk / 100); 1551 } 1552 1553 symbcomp = 13 * (coarse_srate / 10); 1554 coarse_freq = (stv0900_read_reg(intp, CFR2) << 8) 1555 | stv0900_read_reg(intp, CFR1); 1556 1557 if (symbcomp < intp->symbol_rate[demod]) 1558 coarse_srate = 0; 1559 else { 1560 stv0900_write_reg(intp, DMDISTATE, 0x1f); 1561 stv0900_write_reg(intp, TMGCFG2, 0xc1); 1562 stv0900_write_reg(intp, TMGTHRISE, 0x20); 1563 stv0900_write_reg(intp, TMGTHFALL, 0x00); 1564 stv0900_write_reg(intp, TMGCFG, 0xd2); 1565 stv0900_write_bits(intp, CFR_AUTOSCAN, 0); 1566 stv0900_write_reg(intp, AGC2REF, 0x38); 1567 1568 if (intp->chip_id >= 0x30) 1569 stv0900_write_reg(intp, CARFREQ, 0x79); 1570 else if (intp->chip_id >= 0x20) 1571 stv0900_write_reg(intp, CARFREQ, 0x49); 1572 else 1573 stv0900_write_reg(intp, CARFREQ, 0xed); 1574 1575 stv0900_write_reg(intp, SFRUP1, (symbmax >> 8) & 0x7f); 1576 stv0900_write_reg(intp, SFRUP0, (symbmax & 0xff)); 1577 1578 stv0900_write_reg(intp, SFRLOW1, (symbmin >> 8) & 0x7f); 1579 stv0900_write_reg(intp, SFRLOW0, (symbmin & 0xff)); 1580 1581 stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0xff); 1582 stv0900_write_reg(intp, SFRINIT0, (symb & 0xff)); 1583 1584 stv0900_write_reg(intp, DMDT0M, 0x20); 1585 stv0900_write_reg(intp, CFRINIT1, (coarse_freq >> 8) & 0xff); 1586 stv0900_write_reg(intp, CFRINIT0, coarse_freq & 0xff); 1587 stv0900_write_reg(intp, DMDISTATE, 0x15); 1588 } 1589 1590 return coarse_srate; 1591 } 1592 1593 static int stv0900_blind_search_algo(struct dvb_frontend *fe) 1594 { 1595 struct stv0900_state *state = fe->demodulator_priv; 1596 struct stv0900_internal *intp = state->internal; 1597 enum fe_stv0900_demod_num demod = state->demod; 1598 u8 k_ref_tmg, 1599 k_ref_tmg_max, 1600 k_ref_tmg_min; 1601 u32 coarse_srate, 1602 agc2_th; 1603 int lock = FALSE, 1604 coarse_fail = FALSE; 1605 s32 demod_timeout = 500, 1606 fec_timeout = 50, 1607 fail_cpt, 1608 i, 1609 agc2_overflow; 1610 u16 agc2_int; 1611 u8 dstatus2; 1612 1613 dprintk("%s\n", __func__); 1614 1615 if (intp->chip_id < 0x20) { 1616 k_ref_tmg_max = 233; 1617 k_ref_tmg_min = 143; 1618 } else { 1619 k_ref_tmg_max = 110; 1620 k_ref_tmg_min = 10; 1621 } 1622 1623 if (intp->chip_id <= 0x20) 1624 agc2_th = STV0900_BLIND_SEARCH_AGC2_TH; 1625 else 1626 agc2_th = STV0900_BLIND_SEARCH_AGC2_TH_CUT30; 1627 1628 agc2_int = stv0900_blind_check_agc2_min_level(intp, demod); 1629 1630 dprintk("%s agc2_int=%d agc2_th=%d \n", __func__, agc2_int, agc2_th); 1631 if (agc2_int > agc2_th) 1632 return FALSE; 1633 1634 if (intp->chip_id == 0x10) 1635 stv0900_write_reg(intp, CORRELEXP, 0xaa); 1636 1637 if (intp->chip_id < 0x20) 1638 stv0900_write_reg(intp, CARHDR, 0x55); 1639 else 1640 stv0900_write_reg(intp, CARHDR, 0x20); 1641 1642 if (intp->chip_id <= 0x20) 1643 stv0900_write_reg(intp, CARCFG, 0xc4); 1644 else 1645 stv0900_write_reg(intp, CARCFG, 0x6); 1646 1647 stv0900_write_reg(intp, RTCS2, 0x44); 1648 1649 if (intp->chip_id >= 0x20) { 1650 stv0900_write_reg(intp, EQUALCFG, 0x41); 1651 stv0900_write_reg(intp, FFECFG, 0x41); 1652 stv0900_write_reg(intp, VITSCALE, 0x82); 1653 stv0900_write_reg(intp, VAVSRVIT, 0x0); 1654 } 1655 1656 k_ref_tmg = k_ref_tmg_max; 1657 1658 do { 1659 stv0900_write_reg(intp, KREFTMG, k_ref_tmg); 1660 if (stv0900_search_srate_coarse(fe) != 0) { 1661 coarse_srate = stv0900_search_srate_fine(fe); 1662 1663 if (coarse_srate != 0) { 1664 stv0900_get_lock_timeout(&demod_timeout, 1665 &fec_timeout, 1666 coarse_srate, 1667 STV0900_BLIND_SEARCH); 1668 lock = stv0900_get_demod_lock(intp, 1669 demod, 1670 demod_timeout); 1671 } else 1672 lock = FALSE; 1673 } else { 1674 fail_cpt = 0; 1675 agc2_overflow = 0; 1676 1677 for (i = 0; i < 10; i++) { 1678 agc2_int = (stv0900_read_reg(intp, AGC2I1) << 8) 1679 | stv0900_read_reg(intp, AGC2I0); 1680 1681 if (agc2_int >= 0xff00) 1682 agc2_overflow++; 1683 1684 dstatus2 = stv0900_read_reg(intp, DSTATUS2); 1685 1686 if (((dstatus2 & 0x1) == 0x1) && 1687 ((dstatus2 >> 7) == 1)) 1688 fail_cpt++; 1689 } 1690 1691 if ((fail_cpt > 7) || (agc2_overflow > 7)) 1692 coarse_fail = TRUE; 1693 1694 lock = FALSE; 1695 } 1696 k_ref_tmg -= 30; 1697 } while ((k_ref_tmg >= k_ref_tmg_min) && 1698 (lock == FALSE) && 1699 (coarse_fail == FALSE)); 1700 1701 return lock; 1702 } 1703 1704 static void stv0900_set_viterbi_acq(struct stv0900_internal *intp, 1705 enum fe_stv0900_demod_num demod) 1706 { 1707 s32 vth_reg = VTH12; 1708 1709 dprintk("%s\n", __func__); 1710 1711 stv0900_write_reg(intp, vth_reg++, 0x96); 1712 stv0900_write_reg(intp, vth_reg++, 0x64); 1713 stv0900_write_reg(intp, vth_reg++, 0x36); 1714 stv0900_write_reg(intp, vth_reg++, 0x23); 1715 stv0900_write_reg(intp, vth_reg++, 0x1e); 1716 stv0900_write_reg(intp, vth_reg++, 0x19); 1717 } 1718 1719 static void stv0900_set_search_standard(struct stv0900_internal *intp, 1720 enum fe_stv0900_demod_num demod) 1721 { 1722 1723 dprintk("%s\n", __func__); 1724 1725 switch (intp->srch_standard[demod]) { 1726 case STV0900_SEARCH_DVBS1: 1727 dprintk("Search Standard = DVBS1\n"); 1728 break; 1729 case STV0900_SEARCH_DSS: 1730 dprintk("Search Standard = DSS\n"); 1731 break; 1732 case STV0900_SEARCH_DVBS2: 1733 dprintk("Search Standard = DVBS2\n"); 1734 break; 1735 case STV0900_AUTO_SEARCH: 1736 default: 1737 dprintk("Search Standard = AUTO\n"); 1738 break; 1739 } 1740 1741 switch (intp->srch_standard[demod]) { 1742 case STV0900_SEARCH_DVBS1: 1743 case STV0900_SEARCH_DSS: 1744 stv0900_write_bits(intp, DVBS1_ENABLE, 1); 1745 stv0900_write_bits(intp, DVBS2_ENABLE, 0); 1746 stv0900_write_bits(intp, STOP_CLKVIT, 0); 1747 stv0900_set_dvbs1_track_car_loop(intp, 1748 demod, 1749 intp->symbol_rate[demod]); 1750 stv0900_write_reg(intp, CAR2CFG, 0x22); 1751 1752 stv0900_set_viterbi_acq(intp, demod); 1753 stv0900_set_viterbi_standard(intp, 1754 intp->srch_standard[demod], 1755 intp->fec[demod], demod); 1756 1757 break; 1758 case STV0900_SEARCH_DVBS2: 1759 stv0900_write_bits(intp, DVBS1_ENABLE, 0); 1760 stv0900_write_bits(intp, DVBS2_ENABLE, 1); 1761 stv0900_write_bits(intp, STOP_CLKVIT, 1); 1762 stv0900_write_reg(intp, ACLC, 0x1a); 1763 stv0900_write_reg(intp, BCLC, 0x09); 1764 if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/ 1765 stv0900_write_reg(intp, CAR2CFG, 0x26); 1766 else 1767 stv0900_write_reg(intp, CAR2CFG, 0x66); 1768 1769 if (intp->demod_mode != STV0900_SINGLE) { 1770 if (intp->chip_id <= 0x11) 1771 stv0900_stop_all_s2_modcod(intp, demod); 1772 else 1773 stv0900_activate_s2_modcod(intp, demod); 1774 1775 } else 1776 stv0900_activate_s2_modcod_single(intp, demod); 1777 1778 stv0900_set_viterbi_tracq(intp, demod); 1779 1780 break; 1781 case STV0900_AUTO_SEARCH: 1782 default: 1783 stv0900_write_bits(intp, DVBS1_ENABLE, 1); 1784 stv0900_write_bits(intp, DVBS2_ENABLE, 1); 1785 stv0900_write_bits(intp, STOP_CLKVIT, 0); 1786 stv0900_write_reg(intp, ACLC, 0x1a); 1787 stv0900_write_reg(intp, BCLC, 0x09); 1788 stv0900_set_dvbs1_track_car_loop(intp, 1789 demod, 1790 intp->symbol_rate[demod]); 1791 if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/ 1792 stv0900_write_reg(intp, CAR2CFG, 0x26); 1793 else 1794 stv0900_write_reg(intp, CAR2CFG, 0x66); 1795 1796 if (intp->demod_mode != STV0900_SINGLE) { 1797 if (intp->chip_id <= 0x11) 1798 stv0900_stop_all_s2_modcod(intp, demod); 1799 else 1800 stv0900_activate_s2_modcod(intp, demod); 1801 1802 } else 1803 stv0900_activate_s2_modcod_single(intp, demod); 1804 1805 stv0900_set_viterbi_tracq(intp, demod); 1806 stv0900_set_viterbi_standard(intp, 1807 intp->srch_standard[demod], 1808 intp->fec[demod], demod); 1809 1810 break; 1811 } 1812 } 1813 1814 enum fe_stv0900_signal_type stv0900_algo(struct dvb_frontend *fe) 1815 { 1816 struct stv0900_state *state = fe->demodulator_priv; 1817 struct stv0900_internal *intp = state->internal; 1818 enum fe_stv0900_demod_num demod = state->demod; 1819 1820 s32 demod_timeout = 500, fec_timeout = 50; 1821 s32 aq_power, agc1_power, i; 1822 1823 int lock = FALSE, low_sr = FALSE; 1824 1825 enum fe_stv0900_signal_type signal_type = STV0900_NOCARRIER; 1826 enum fe_stv0900_search_algo algo; 1827 int no_signal = FALSE; 1828 1829 dprintk("%s\n", __func__); 1830 1831 algo = intp->srch_algo[demod]; 1832 stv0900_write_bits(intp, RST_HWARE, 1); 1833 stv0900_write_reg(intp, DMDISTATE, 0x5c); 1834 if (intp->chip_id >= 0x20) { 1835 if (intp->symbol_rate[demod] > 5000000) 1836 stv0900_write_reg(intp, CORRELABS, 0x9e); 1837 else 1838 stv0900_write_reg(intp, CORRELABS, 0x82); 1839 } else 1840 stv0900_write_reg(intp, CORRELABS, 0x88); 1841 1842 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout, 1843 intp->symbol_rate[demod], 1844 intp->srch_algo[demod]); 1845 1846 if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) { 1847 intp->bw[demod] = 2 * 36000000; 1848 1849 stv0900_write_reg(intp, TMGCFG2, 0xc0); 1850 stv0900_write_reg(intp, CORRELMANT, 0x70); 1851 1852 stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod); 1853 } else { 1854 stv0900_write_reg(intp, DMDT0M, 0x20); 1855 stv0900_write_reg(intp, TMGCFG, 0xd2); 1856 1857 if (intp->symbol_rate[demod] < 2000000) 1858 stv0900_write_reg(intp, CORRELMANT, 0x63); 1859 else 1860 stv0900_write_reg(intp, CORRELMANT, 0x70); 1861 1862 stv0900_write_reg(intp, AGC2REF, 0x38); 1863 1864 intp->bw[demod] = 1865 stv0900_carrier_width(intp->symbol_rate[demod], 1866 intp->rolloff); 1867 if (intp->chip_id >= 0x20) { 1868 stv0900_write_reg(intp, KREFTMG, 0x5a); 1869 1870 if (intp->srch_algo[demod] == STV0900_COLD_START) { 1871 intp->bw[demod] += 10000000; 1872 intp->bw[demod] *= 15; 1873 intp->bw[demod] /= 10; 1874 } else if (intp->srch_algo[demod] == STV0900_WARM_START) 1875 intp->bw[demod] += 10000000; 1876 1877 } else { 1878 stv0900_write_reg(intp, KREFTMG, 0xc1); 1879 intp->bw[demod] += 10000000; 1880 intp->bw[demod] *= 15; 1881 intp->bw[demod] /= 10; 1882 } 1883 1884 stv0900_write_reg(intp, TMGCFG2, 0xc1); 1885 1886 stv0900_set_symbol_rate(intp, intp->mclk, 1887 intp->symbol_rate[demod], demod); 1888 stv0900_set_max_symbol_rate(intp, intp->mclk, 1889 intp->symbol_rate[demod], demod); 1890 stv0900_set_min_symbol_rate(intp, intp->mclk, 1891 intp->symbol_rate[demod], demod); 1892 if (intp->symbol_rate[demod] >= 10000000) 1893 low_sr = FALSE; 1894 else 1895 low_sr = TRUE; 1896 1897 } 1898 1899 if (intp->tuner_type[demod] == 3) 1900 stv0900_set_tuner_auto(intp, intp->freq[demod], 1901 intp->bw[demod], demod); 1902 else 1903 stv0900_set_tuner(fe, intp->freq[demod], intp->bw[demod]); 1904 1905 agc1_power = MAKEWORD(stv0900_get_bits(intp, AGCIQ_VALUE1), 1906 stv0900_get_bits(intp, AGCIQ_VALUE0)); 1907 1908 aq_power = 0; 1909 1910 if (agc1_power == 0) { 1911 for (i = 0; i < 5; i++) 1912 aq_power += (stv0900_get_bits(intp, POWER_I) + 1913 stv0900_get_bits(intp, POWER_Q)) / 2; 1914 1915 aq_power /= 5; 1916 } 1917 1918 if ((agc1_power == 0) && (aq_power < IQPOWER_THRESHOLD)) { 1919 intp->result[demod].locked = FALSE; 1920 signal_type = STV0900_NOAGC1; 1921 dprintk("%s: NO AGC1, POWERI, POWERQ\n", __func__); 1922 } else { 1923 stv0900_write_bits(intp, SPECINV_CONTROL, 1924 intp->srch_iq_inv[demod]); 1925 if (intp->chip_id <= 0x20) /*cut 2.0*/ 1926 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1); 1927 else /*cut 3.0*/ 1928 stv0900_write_bits(intp, MANUALS2_ROLLOFF, 1); 1929 1930 stv0900_set_search_standard(intp, demod); 1931 1932 if (intp->srch_algo[demod] != STV0900_BLIND_SEARCH) 1933 stv0900_start_search(intp, demod); 1934 } 1935 1936 if (signal_type == STV0900_NOAGC1) 1937 return signal_type; 1938 1939 if (intp->chip_id == 0x12) { 1940 stv0900_write_bits(intp, RST_HWARE, 0); 1941 msleep(3); 1942 stv0900_write_bits(intp, RST_HWARE, 1); 1943 stv0900_write_bits(intp, RST_HWARE, 0); 1944 } 1945 1946 if (algo == STV0900_BLIND_SEARCH) 1947 lock = stv0900_blind_search_algo(fe); 1948 else if (algo == STV0900_COLD_START) 1949 lock = stv0900_get_demod_cold_lock(fe, demod_timeout); 1950 else if (algo == STV0900_WARM_START) 1951 lock = stv0900_get_demod_lock(intp, demod, demod_timeout); 1952 1953 if ((lock == FALSE) && (algo == STV0900_COLD_START)) { 1954 if (low_sr == FALSE) { 1955 if (stv0900_check_timing_lock(intp, demod) == TRUE) 1956 lock = stv0900_sw_algo(intp, demod); 1957 } 1958 } 1959 1960 if (lock == TRUE) 1961 signal_type = stv0900_get_signal_params(fe); 1962 1963 if ((lock == TRUE) && (signal_type == STV0900_RANGEOK)) { 1964 stv0900_track_optimization(fe); 1965 if (intp->chip_id <= 0x11) { 1966 if ((stv0900_get_standard(fe, 0) == 1967 STV0900_DVBS1_STANDARD) && 1968 (stv0900_get_standard(fe, 1) == 1969 STV0900_DVBS1_STANDARD)) { 1970 msleep(20); 1971 stv0900_write_bits(intp, RST_HWARE, 0); 1972 } else { 1973 stv0900_write_bits(intp, RST_HWARE, 0); 1974 msleep(3); 1975 stv0900_write_bits(intp, RST_HWARE, 1); 1976 stv0900_write_bits(intp, RST_HWARE, 0); 1977 } 1978 1979 } else if (intp->chip_id >= 0x20) { 1980 stv0900_write_bits(intp, RST_HWARE, 0); 1981 msleep(3); 1982 stv0900_write_bits(intp, RST_HWARE, 1); 1983 stv0900_write_bits(intp, RST_HWARE, 0); 1984 } 1985 1986 if (stv0900_wait_for_lock(intp, demod, 1987 fec_timeout, fec_timeout) == TRUE) { 1988 lock = TRUE; 1989 intp->result[demod].locked = TRUE; 1990 if (intp->result[demod].standard == 1991 STV0900_DVBS2_STANDARD) { 1992 stv0900_set_dvbs2_rolloff(intp, demod); 1993 stv0900_write_bits(intp, RESET_UPKO_COUNT, 1); 1994 stv0900_write_bits(intp, RESET_UPKO_COUNT, 0); 1995 stv0900_write_reg(intp, ERRCTRL1, 0x67); 1996 } else { 1997 stv0900_write_reg(intp, ERRCTRL1, 0x75); 1998 } 1999 2000 stv0900_write_reg(intp, FBERCPT4, 0); 2001 stv0900_write_reg(intp, ERRCTRL2, 0xc1); 2002 } else { 2003 lock = FALSE; 2004 signal_type = STV0900_NODATA; 2005 no_signal = stv0900_check_signal_presence(intp, demod); 2006 2007 intp->result[demod].locked = FALSE; 2008 } 2009 } 2010 2011 if ((signal_type != STV0900_NODATA) || (no_signal != FALSE)) 2012 return signal_type; 2013 2014 if (intp->chip_id > 0x11) { 2015 intp->result[demod].locked = FALSE; 2016 return signal_type; 2017 } 2018 2019 if ((stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) && 2020 (intp->srch_iq_inv[demod] <= STV0900_IQ_AUTO_NORMAL_FIRST)) 2021 signal_type = stv0900_dvbs1_acq_workaround(fe); 2022 2023 return signal_type; 2024 } 2025 2026