1 /* 2 * stv0367_regs.h 3 * 4 * Driver for ST STV0367 DVB-T & DVB-C demodulator IC. 5 * 6 * Copyright (C) ST Microelectronics. 7 * Copyright (C) 2010,2011 NetUP Inc. 8 * Copyright (C) 2010,2011 Igor M. Liplianin <liplianin@netup.ru> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * 19 * GNU General Public License for more details. 20 */ 21 22 #ifndef STV0367_REGS_H 23 #define STV0367_REGS_H 24 25 /* ID */ 26 #define R367TER_ID 0xf000 27 #define F367TER_IDENTIFICATIONREG 0xf00000ff 28 29 /* I2CRPT */ 30 #define R367TER_I2CRPT 0xf001 31 #define F367TER_I2CT_ON 0xf0010080 32 #define F367TER_ENARPT_LEVEL 0xf0010070 33 #define F367TER_SCLT_DELAY 0xf0010008 34 #define F367TER_SCLT_NOD 0xf0010004 35 #define F367TER_STOP_ENABLE 0xf0010002 36 #define F367TER_SDAT_NOD 0xf0010001 37 38 /* TOPCTRL */ 39 #define R367TER_TOPCTRL 0xf002 40 #define F367TER_STDBY 0xf0020080 41 #define F367TER_STDBY_FEC 0xf0020040 42 #define F367TER_STDBY_CORE 0xf0020020 43 #define F367TER_QAM_COFDM 0xf0020010 44 #define F367TER_TS_DIS 0xf0020008 45 #define F367TER_DIR_CLK_216 0xf0020004 46 #define F367TER_TUNER_BB 0xf0020002 47 #define F367TER_DVBT_H 0xf0020001 48 49 /* IOCFG0 */ 50 #define R367TER_IOCFG0 0xf003 51 #define F367TER_OP0_SD 0xf0030080 52 #define F367TER_OP0_VAL 0xf0030040 53 #define F367TER_OP0_OD 0xf0030020 54 #define F367TER_OP0_INV 0xf0030010 55 #define F367TER_OP0_DACVALUE_HI 0xf003000f 56 57 /* DAc0R */ 58 #define R367TER_DAC0R 0xf004 59 #define F367TER_OP0_DACVALUE_LO 0xf00400ff 60 61 /* IOCFG1 */ 62 #define R367TER_IOCFG1 0xf005 63 #define F367TER_IP0 0xf0050040 64 #define F367TER_OP1_OD 0xf0050020 65 #define F367TER_OP1_INV 0xf0050010 66 #define F367TER_OP1_DACVALUE_HI 0xf005000f 67 68 /* DAC1R */ 69 #define R367TER_DAC1R 0xf006 70 #define F367TER_OP1_DACVALUE_LO 0xf00600ff 71 72 /* IOCFG2 */ 73 #define R367TER_IOCFG2 0xf007 74 #define F367TER_OP2_LOCK_CONF 0xf00700e0 75 #define F367TER_OP2_OD 0xf0070010 76 #define F367TER_OP2_VAL 0xf0070008 77 #define F367TER_OP1_LOCK_CONF 0xf0070007 78 79 /* SDFR */ 80 #define R367TER_SDFR 0xf008 81 #define F367TER_OP0_FREQ 0xf00800f0 82 #define F367TER_OP1_FREQ 0xf008000f 83 84 /* STATUS */ 85 #define R367TER_STATUS 0xf009 86 #define F367TER_TPS_LOCK 0xf0090080 87 #define F367TER_SYR_LOCK 0xf0090040 88 #define F367TER_AGC_LOCK 0xf0090020 89 #define F367TER_PRF 0xf0090010 90 #define F367TER_LK 0xf0090008 91 #define F367TER_PR 0xf0090007 92 93 /* AUX_CLK */ 94 #define R367TER_AUX_CLK 0xf00a 95 #define F367TER_AUXFEC_CTL 0xf00a00c0 96 #define F367TER_DIS_CKX4 0xf00a0020 97 #define F367TER_CKSEL 0xf00a0018 98 #define F367TER_CKDIV_PROG 0xf00a0006 99 #define F367TER_AUXCLK_ENA 0xf00a0001 100 101 /* FREESYS1 */ 102 #define R367TER_FREESYS1 0xf00b 103 #define F367TER_FREE_SYS1 0xf00b00ff 104 105 /* FREESYS2 */ 106 #define R367TER_FREESYS2 0xf00c 107 #define F367TER_FREE_SYS2 0xf00c00ff 108 109 /* FREESYS3 */ 110 #define R367TER_FREESYS3 0xf00d 111 #define F367TER_FREE_SYS3 0xf00d00ff 112 113 /* GPIO_CFG */ 114 #define R367TER_GPIO_CFG 0xf00e 115 #define F367TER_GPIO7_NOD 0xf00e0080 116 #define F367TER_GPIO7_CFG 0xf00e0040 117 #define F367TER_GPIO6_NOD 0xf00e0020 118 #define F367TER_GPIO6_CFG 0xf00e0010 119 #define F367TER_GPIO5_NOD 0xf00e0008 120 #define F367TER_GPIO5_CFG 0xf00e0004 121 #define F367TER_GPIO4_NOD 0xf00e0002 122 #define F367TER_GPIO4_CFG 0xf00e0001 123 124 /* GPIO_CMD */ 125 #define R367TER_GPIO_CMD 0xf00f 126 #define F367TER_GPIO7_VAL 0xf00f0008 127 #define F367TER_GPIO6_VAL 0xf00f0004 128 #define F367TER_GPIO5_VAL 0xf00f0002 129 #define F367TER_GPIO4_VAL 0xf00f0001 130 131 /* AGC2MAX */ 132 #define R367TER_AGC2MAX 0xf010 133 #define F367TER_AGC2_MAX 0xf01000ff 134 135 /* AGC2MIN */ 136 #define R367TER_AGC2MIN 0xf011 137 #define F367TER_AGC2_MIN 0xf01100ff 138 139 /* AGC1MAX */ 140 #define R367TER_AGC1MAX 0xf012 141 #define F367TER_AGC1_MAX 0xf01200ff 142 143 /* AGC1MIN */ 144 #define R367TER_AGC1MIN 0xf013 145 #define F367TER_AGC1_MIN 0xf01300ff 146 147 /* AGCR */ 148 #define R367TER_AGCR 0xf014 149 #define F367TER_RATIO_A 0xf01400e0 150 #define F367TER_RATIO_B 0xf0140018 151 #define F367TER_RATIO_C 0xf0140007 152 153 /* AGC2TH */ 154 #define R367TER_AGC2TH 0xf015 155 #define F367TER_AGC2_THRES 0xf01500ff 156 157 /* AGC12c */ 158 #define R367TER_AGC12C 0xf016 159 #define F367TER_AGC1_IV 0xf0160080 160 #define F367TER_AGC1_OD 0xf0160040 161 #define F367TER_AGC1_LOAD 0xf0160020 162 #define F367TER_AGC2_IV 0xf0160010 163 #define F367TER_AGC2_OD 0xf0160008 164 #define F367TER_AGC2_LOAD 0xf0160004 165 #define F367TER_AGC12_MODE 0xf0160003 166 167 /* AGCCTRL1 */ 168 #define R367TER_AGCCTRL1 0xf017 169 #define F367TER_DAGC_ON 0xf0170080 170 #define F367TER_INVERT_AGC12 0xf0170040 171 #define F367TER_AGC1_MODE 0xf0170008 172 #define F367TER_AGC2_MODE 0xf0170007 173 174 /* AGCCTRL2 */ 175 #define R367TER_AGCCTRL2 0xf018 176 #define F367TER_FRZ2_CTRL 0xf0180060 177 #define F367TER_FRZ1_CTRL 0xf0180018 178 #define F367TER_TIME_CST 0xf0180007 179 180 /* AGC1VAL1 */ 181 #define R367TER_AGC1VAL1 0xf019 182 #define F367TER_AGC1_VAL_LO 0xf01900ff 183 184 /* AGC1VAL2 */ 185 #define R367TER_AGC1VAL2 0xf01a 186 #define F367TER_AGC1_VAL_HI 0xf01a000f 187 188 /* AGC2VAL1 */ 189 #define R367TER_AGC2VAL1 0xf01b 190 #define F367TER_AGC2_VAL_LO 0xf01b00ff 191 192 /* AGC2VAL2 */ 193 #define R367TER_AGC2VAL2 0xf01c 194 #define F367TER_AGC2_VAL_HI 0xf01c000f 195 196 /* AGC2PGA */ 197 #define R367TER_AGC2PGA 0xf01d 198 #define F367TER_AGC2_PGA 0xf01d00ff 199 200 /* OVF_RATE1 */ 201 #define R367TER_OVF_RATE1 0xf01e 202 #define F367TER_OVF_RATE_HI 0xf01e000f 203 204 /* OVF_RATE2 */ 205 #define R367TER_OVF_RATE2 0xf01f 206 #define F367TER_OVF_RATE_LO 0xf01f00ff 207 208 /* GAIN_SRC1 */ 209 #define R367TER_GAIN_SRC1 0xf020 210 #define F367TER_INV_SPECTR 0xf0200080 211 #define F367TER_IQ_INVERT 0xf0200040 212 #define F367TER_INR_BYPASS 0xf0200020 213 #define F367TER_STATUS_INV_SPECRUM 0xf0200010 214 #define F367TER_GAIN_SRC_HI 0xf020000f 215 216 /* GAIN_SRC2 */ 217 #define R367TER_GAIN_SRC2 0xf021 218 #define F367TER_GAIN_SRC_LO 0xf02100ff 219 220 /* INC_DEROT1 */ 221 #define R367TER_INC_DEROT1 0xf022 222 #define F367TER_INC_DEROT_HI 0xf02200ff 223 224 /* INC_DEROT2 */ 225 #define R367TER_INC_DEROT2 0xf023 226 #define F367TER_INC_DEROT_LO 0xf02300ff 227 228 /* PPM_CPAMP_DIR */ 229 #define R367TER_PPM_CPAMP_DIR 0xf024 230 #define F367TER_PPM_CPAMP_DIRECT 0xf02400ff 231 232 /* PPM_CPAMP_INV */ 233 #define R367TER_PPM_CPAMP_INV 0xf025 234 #define F367TER_PPM_CPAMP_INVER 0xf02500ff 235 236 /* FREESTFE_1 */ 237 #define R367TER_FREESTFE_1 0xf026 238 #define F367TER_SYMBOL_NUMBER_INC 0xf02600c0 239 #define F367TER_SEL_LSB 0xf0260004 240 #define F367TER_AVERAGE_ON 0xf0260002 241 #define F367TER_DC_ADJ 0xf0260001 242 243 /* FREESTFE_2 */ 244 #define R367TER_FREESTFE_2 0xf027 245 #define F367TER_SEL_SRCOUT 0xf02700c0 246 #define F367TER_SEL_SYRTHR 0xf027001f 247 248 /* DCOFFSET */ 249 #define R367TER_DCOFFSET 0xf028 250 #define F367TER_SELECT_I_Q 0xf0280080 251 #define F367TER_DC_OFFSET 0xf028007f 252 253 /* EN_PROCESS */ 254 #define R367TER_EN_PROCESS 0xf029 255 #define F367TER_FREE 0xf02900f0 256 #define F367TER_ENAB_MANUAL 0xf0290001 257 258 /* SDI_SMOOTHER */ 259 #define R367TER_SDI_SMOOTHER 0xf02a 260 #define F367TER_DIS_SMOOTH 0xf02a0080 261 #define F367TER_SDI_INC_SMOOTHER 0xf02a007f 262 263 /* FE_LOOP_OPEN */ 264 #define R367TER_FE_LOOP_OPEN 0xf02b 265 #define F367TER_TRL_LOOP_OP 0xf02b0002 266 #define F367TER_CRL_LOOP_OP 0xf02b0001 267 268 /* FREQOFF1 */ 269 #define R367TER_FREQOFF1 0xf02c 270 #define F367TER_FREQ_OFFSET_LOOP_OPEN_VHI 0xf02c00ff 271 272 /* FREQOFF2 */ 273 #define R367TER_FREQOFF2 0xf02d 274 #define F367TER_FREQ_OFFSET_LOOP_OPEN_HI 0xf02d00ff 275 276 /* FREQOFF3 */ 277 #define R367TER_FREQOFF3 0xf02e 278 #define F367TER_FREQ_OFFSET_LOOP_OPEN_LO 0xf02e00ff 279 280 /* TIMOFF1 */ 281 #define R367TER_TIMOFF1 0xf02f 282 #define F367TER_TIM_OFFSET_LOOP_OPEN_HI 0xf02f00ff 283 284 /* TIMOFF2 */ 285 #define R367TER_TIMOFF2 0xf030 286 #define F367TER_TIM_OFFSET_LOOP_OPEN_LO 0xf03000ff 287 288 /* EPQ */ 289 #define R367TER_EPQ 0xf031 290 #define F367TER_EPQ1 0xf03100ff 291 292 /* EPQAUTO */ 293 #define R367TER_EPQAUTO 0xf032 294 #define F367TER_EPQ2 0xf03200ff 295 296 /* SYR_UPDATE */ 297 #define R367TER_SYR_UPDATE 0xf033 298 #define F367TER_SYR_PROTV 0xf0330080 299 #define F367TER_SYR_PROTV_GAIN 0xf0330060 300 #define F367TER_SYR_FILTER 0xf0330010 301 #define F367TER_SYR_TRACK_THRES 0xf033000c 302 303 /* CHPFREE */ 304 #define R367TER_CHPFREE 0xf034 305 #define F367TER_CHP_FREE 0xf03400ff 306 307 /* PPM_STATE_MAC */ 308 #define R367TER_PPM_STATE_MAC 0xf035 309 #define F367TER_PPM_STATE_MACHINE_DECODER 0xf035003f 310 311 /* INR_THRESHOLD */ 312 #define R367TER_INR_THRESHOLD 0xf036 313 #define F367TER_INR_THRESH 0xf03600ff 314 315 /* EPQ_TPS_ID_CELL */ 316 #define R367TER_EPQ_TPS_ID_CELL 0xf037 317 #define F367TER_ENABLE_LGTH_TO_CF 0xf0370080 318 #define F367TER_DIS_TPS_RSVD 0xf0370040 319 #define F367TER_DIS_BCH 0xf0370020 320 #define F367TER_DIS_ID_CEL 0xf0370010 321 #define F367TER_TPS_ADJUST_SYM 0xf037000f 322 323 /* EPQ_CFG */ 324 #define R367TER_EPQ_CFG 0xf038 325 #define F367TER_EPQ_RANGE 0xf0380002 326 #define F367TER_EPQ_SOFT 0xf0380001 327 328 /* EPQ_STATUS */ 329 #define R367TER_EPQ_STATUS 0xf039 330 #define F367TER_SLOPE_INC 0xf03900fc 331 #define F367TER_TPS_FIELD 0xf0390003 332 333 /* AUTORELOCK */ 334 #define R367TER_AUTORELOCK 0xf03a 335 #define F367TER_BYPASS_BER_TEMPO 0xf03a0080 336 #define F367TER_BER_TEMPO 0xf03a0070 337 #define F367TER_BYPASS_COFDM_TEMPO 0xf03a0008 338 #define F367TER_COFDM_TEMPO 0xf03a0007 339 340 /* BER_THR_VMSB */ 341 #define R367TER_BER_THR_VMSB 0xf03b 342 #define F367TER_BER_THRESHOLD_HI 0xf03b00ff 343 344 /* BER_THR_MSB */ 345 #define R367TER_BER_THR_MSB 0xf03c 346 #define F367TER_BER_THRESHOLD_MID 0xf03c00ff 347 348 /* BER_THR_LSB */ 349 #define R367TER_BER_THR_LSB 0xf03d 350 #define F367TER_BER_THRESHOLD_LO 0xf03d00ff 351 352 /* CCD */ 353 #define R367TER_CCD 0xf03e 354 #define F367TER_CCD_DETECTED 0xf03e0080 355 #define F367TER_CCD_RESET 0xf03e0040 356 #define F367TER_CCD_THRESHOLD 0xf03e000f 357 358 /* SPECTR_CFG */ 359 #define R367TER_SPECTR_CFG 0xf03f 360 #define F367TER_SPECT_CFG 0xf03f0003 361 362 /* CONSTMU_MSB */ 363 #define R367TER_CONSTMU_MSB 0xf040 364 #define F367TER_CONSTMU_FREEZE 0xf0400080 365 #define F367TER_CONSTNU_FORCE_EN 0xf0400040 366 #define F367TER_CONST_MU_MSB 0xf040003f 367 368 /* CONSTMU_LSB */ 369 #define R367TER_CONSTMU_LSB 0xf041 370 #define F367TER_CONST_MU_LSB 0xf04100ff 371 372 /* CONSTMU_MAX_MSB */ 373 #define R367TER_CONSTMU_MAX_MSB 0xf042 374 #define F367TER_CONST_MU_MAX_MSB 0xf042003f 375 376 /* CONSTMU_MAX_LSB */ 377 #define R367TER_CONSTMU_MAX_LSB 0xf043 378 #define F367TER_CONST_MU_MAX_LSB 0xf04300ff 379 380 /* ALPHANOISE */ 381 #define R367TER_ALPHANOISE 0xf044 382 #define F367TER_USE_ALLFILTER 0xf0440080 383 #define F367TER_INTER_ON 0xf0440040 384 #define F367TER_ALPHA_NOISE 0xf044001f 385 386 /* MAXGP_MSB */ 387 #define R367TER_MAXGP_MSB 0xf045 388 #define F367TER_MUFILTER_LENGTH 0xf04500f0 389 #define F367TER_MAX_GP_MSB 0xf045000f 390 391 /* MAXGP_LSB */ 392 #define R367TER_MAXGP_LSB 0xf046 393 #define F367TER_MAX_GP_LSB 0xf04600ff 394 395 /* ALPHAMSB */ 396 #define R367TER_ALPHAMSB 0xf047 397 #define F367TER_CHC_DATARATE 0xf04700c0 398 #define F367TER_ALPHA_MSB 0xf047003f 399 400 /* ALPHALSB */ 401 #define R367TER_ALPHALSB 0xf048 402 #define F367TER_ALPHA_LSB 0xf04800ff 403 404 /* PILOT_ACCU */ 405 #define R367TER_PILOT_ACCU 0xf049 406 #define F367TER_USE_SCAT4ADDAPT 0xf0490080 407 #define F367TER_PILOT_ACC 0xf049001f 408 409 /* PILOTMU_ACCU */ 410 #define R367TER_PILOTMU_ACCU 0xf04a 411 #define F367TER_DISCARD_BAD_SP 0xf04a0080 412 #define F367TER_DISCARD_BAD_CP 0xf04a0040 413 #define F367TER_PILOT_MU_ACCU 0xf04a001f 414 415 /* FILT_CHANNEL_EST */ 416 #define R367TER_FILT_CHANNEL_EST 0xf04b 417 #define F367TER_USE_FILT_PILOT 0xf04b0080 418 #define F367TER_FILT_CHANNEL 0xf04b007f 419 420 /* ALPHA_NOPISE_FREQ */ 421 #define R367TER_ALPHA_NOPISE_FREQ 0xf04c 422 #define F367TER_NOISE_FREQ_FILT 0xf04c0040 423 #define F367TER_ALPHA_NOISE_FREQ 0xf04c003f 424 425 /* RATIO_PILOT */ 426 #define R367TER_RATIO_PILOT 0xf04d 427 #define F367TER_RATIO_MEAN_SP 0xf04d00f0 428 #define F367TER_RATIO_MEAN_CP 0xf04d000f 429 430 /* CHC_CTL */ 431 #define R367TER_CHC_CTL 0xf04e 432 #define F367TER_TRACK_EN 0xf04e0080 433 #define F367TER_NOISE_NORM_EN 0xf04e0040 434 #define F367TER_FORCE_CHC_RESET 0xf04e0020 435 #define F367TER_SHORT_TIME 0xf04e0010 436 #define F367TER_FORCE_STATE_EN 0xf04e0008 437 #define F367TER_FORCE_STATE 0xf04e0007 438 439 /* EPQ_ADJUST */ 440 #define R367TER_EPQ_ADJUST 0xf04f 441 #define F367TER_ADJUST_SCAT_IND 0xf04f00c0 442 #define F367TER_ONE_SYMBOL 0xf04f0010 443 #define F367TER_EPQ_DECAY 0xf04f000e 444 #define F367TER_HOLD_SLOPE 0xf04f0001 445 446 /* EPQ_THRES */ 447 #define R367TER_EPQ_THRES 0xf050 448 #define F367TER_EPQ_THR 0xf05000ff 449 450 /* OMEGA_CTL */ 451 #define R367TER_OMEGA_CTL 0xf051 452 #define F367TER_OMEGA_RST 0xf0510080 453 #define F367TER_FREEZE_OMEGA 0xf0510040 454 #define F367TER_OMEGA_SEL 0xf051003f 455 456 /* GP_CTL */ 457 #define R367TER_GP_CTL 0xf052 458 #define F367TER_CHC_STATE 0xf05200e0 459 #define F367TER_FREEZE_GP 0xf0520010 460 #define F367TER_GP_SEL 0xf052000f 461 462 /* MUMSB */ 463 #define R367TER_MUMSB 0xf053 464 #define F367TER_MU_MSB 0xf053007f 465 466 /* MULSB */ 467 #define R367TER_MULSB 0xf054 468 #define F367TER_MU_LSB 0xf05400ff 469 470 /* GPMSB */ 471 #define R367TER_GPMSB 0xf055 472 #define F367TER_CSI_THRESHOLD 0xf05500e0 473 #define F367TER_GP_MSB 0xf055000f 474 475 /* GPLSB */ 476 #define R367TER_GPLSB 0xf056 477 #define F367TER_GP_LSB 0xf05600ff 478 479 /* OMEGAMSB */ 480 #define R367TER_OMEGAMSB 0xf057 481 #define F367TER_OMEGA_MSB 0xf057007f 482 483 /* OMEGALSB */ 484 #define R367TER_OMEGALSB 0xf058 485 #define F367TER_OMEGA_LSB 0xf05800ff 486 487 /* SCAT_NB */ 488 #define R367TER_SCAT_NB 0xf059 489 #define F367TER_CHC_TEST 0xf05900f8 490 #define F367TER_SCAT_NUMB 0xf0590003 491 492 /* CHC_DUMMY */ 493 #define R367TER_CHC_DUMMY 0xf05a 494 #define F367TER_CHC_DUM 0xf05a00ff 495 496 /* INC_CTL */ 497 #define R367TER_INC_CTL 0xf05b 498 #define F367TER_INC_BYPASS 0xf05b0080 499 #define F367TER_INC_NDEPTH 0xf05b000c 500 #define F367TER_INC_MADEPTH 0xf05b0003 501 502 /* INCTHRES_COR1 */ 503 #define R367TER_INCTHRES_COR1 0xf05c 504 #define F367TER_INC_THRES_COR1 0xf05c00ff 505 506 /* INCTHRES_COR2 */ 507 #define R367TER_INCTHRES_COR2 0xf05d 508 #define F367TER_INC_THRES_COR2 0xf05d00ff 509 510 /* INCTHRES_DET1 */ 511 #define R367TER_INCTHRES_DET1 0xf05e 512 #define F367TER_INC_THRES_DET1 0xf05e003f 513 514 /* INCTHRES_DET2 */ 515 #define R367TER_INCTHRES_DET2 0xf05f 516 #define F367TER_INC_THRES_DET2 0xf05f003f 517 518 /* IIR_CELLNB */ 519 #define R367TER_IIR_CELLNB 0xf060 520 #define F367TER_NRST_IIR 0xf0600080 521 #define F367TER_IIR_CELL_NB 0xf0600007 522 523 /* IIRCX_COEFF1_MSB */ 524 #define R367TER_IIRCX_COEFF1_MSB 0xf061 525 #define F367TER_IIR_CX_COEFF1_MSB 0xf06100ff 526 527 /* IIRCX_COEFF1_LSB */ 528 #define R367TER_IIRCX_COEFF1_LSB 0xf062 529 #define F367TER_IIR_CX_COEFF1_LSB 0xf06200ff 530 531 /* IIRCX_COEFF2_MSB */ 532 #define R367TER_IIRCX_COEFF2_MSB 0xf063 533 #define F367TER_IIR_CX_COEFF2_MSB 0xf06300ff 534 535 /* IIRCX_COEFF2_LSB */ 536 #define R367TER_IIRCX_COEFF2_LSB 0xf064 537 #define F367TER_IIR_CX_COEFF2_LSB 0xf06400ff 538 539 /* IIRCX_COEFF3_MSB */ 540 #define R367TER_IIRCX_COEFF3_MSB 0xf065 541 #define F367TER_IIR_CX_COEFF3_MSB 0xf06500ff 542 543 /* IIRCX_COEFF3_LSB */ 544 #define R367TER_IIRCX_COEFF3_LSB 0xf066 545 #define F367TER_IIR_CX_COEFF3_LSB 0xf06600ff 546 547 /* IIRCX_COEFF4_MSB */ 548 #define R367TER_IIRCX_COEFF4_MSB 0xf067 549 #define F367TER_IIR_CX_COEFF4_MSB 0xf06700ff 550 551 /* IIRCX_COEFF4_LSB */ 552 #define R367TER_IIRCX_COEFF4_LSB 0xf068 553 #define F367TER_IIR_CX_COEFF4_LSB 0xf06800ff 554 555 /* IIRCX_COEFF5_MSB */ 556 #define R367TER_IIRCX_COEFF5_MSB 0xf069 557 #define F367TER_IIR_CX_COEFF5_MSB 0xf06900ff 558 559 /* IIRCX_COEFF5_LSB */ 560 #define R367TER_IIRCX_COEFF5_LSB 0xf06a 561 #define F367TER_IIR_CX_COEFF5_LSB 0xf06a00ff 562 563 /* FEPATH_CFG */ 564 #define R367TER_FEPATH_CFG 0xf06b 565 #define F367TER_DEMUX_SWAP 0xf06b0004 566 #define F367TER_DIGAGC_SWAP 0xf06b0002 567 #define F367TER_LONGPATH_IF 0xf06b0001 568 569 /* PMC1_FUNC */ 570 #define R367TER_PMC1_FUNC 0xf06c 571 #define F367TER_SOFT_RSTN 0xf06c0080 572 #define F367TER_PMC1_AVERAGE_TIME 0xf06c0078 573 #define F367TER_PMC1_WAIT_TIME 0xf06c0006 574 #define F367TER_PMC1_2N_SEL 0xf06c0001 575 576 /* PMC1_FOR */ 577 #define R367TER_PMC1_FOR 0xf06d 578 #define F367TER_PMC1_FORCE 0xf06d0080 579 #define F367TER_PMC1_FORCE_VALUE 0xf06d007c 580 581 /* PMC2_FUNC */ 582 #define R367TER_PMC2_FUNC 0xf06e 583 #define F367TER_PMC2_SOFT_STN 0xf06e0080 584 #define F367TER_PMC2_ACCU_TIME 0xf06e0070 585 #define F367TER_PMC2_CMDP_MN 0xf06e0008 586 #define F367TER_PMC2_SWAP 0xf06e0004 587 588 /* STATUS_ERR_DA */ 589 #define R367TER_STATUS_ERR_DA 0xf06f 590 #define F367TER_COM_USEGAINTRK 0xf06f0080 591 #define F367TER_COM_AGCLOCK 0xf06f0040 592 #define F367TER_AUT_AGCLOCK 0xf06f0020 593 #define F367TER_MIN_ERR_X_LSB 0xf06f000f 594 595 /* DIG_AGC_R */ 596 #define R367TER_DIG_AGC_R 0xf070 597 #define F367TER_COM_SOFT_RSTN 0xf0700080 598 #define F367TER_COM_AGC_ON 0xf0700040 599 #define F367TER_COM_EARLY 0xf0700020 600 #define F367TER_AUT_SOFT_RESETN 0xf0700010 601 #define F367TER_AUT_AGC_ON 0xf0700008 602 #define F367TER_AUT_EARLY 0xf0700004 603 #define F367TER_AUT_ROT_EN 0xf0700002 604 #define F367TER_LOCK_SOFT_RESETN 0xf0700001 605 606 /* COMAGC_TARMSB */ 607 #define R367TER_COMAGC_TARMSB 0xf071 608 #define F367TER_COM_AGC_TARGET_MSB 0xf07100ff 609 610 /* COM_AGC_TAR_ENMODE */ 611 #define R367TER_COM_AGC_TAR_ENMODE 0xf072 612 #define F367TER_COM_AGC_TARGET_LSB 0xf07200f0 613 #define F367TER_COM_ENMODE 0xf072000f 614 615 /* COM_AGC_CFG */ 616 #define R367TER_COM_AGC_CFG 0xf073 617 #define F367TER_COM_N 0xf07300f8 618 #define F367TER_COM_STABMODE 0xf0730006 619 #define F367TER_ERR_SEL 0xf0730001 620 621 /* COM_AGC_GAIN1 */ 622 #define R367TER_COM_AGC_GAIN1 0xf074 623 #define F367TER_COM_GAIN1aCK 0xf07400f0 624 #define F367TER_COM_GAIN1TRK 0xf074000f 625 626 /* AUT_AGC_TARGETMSB */ 627 #define R367TER_AUT_AGC_TARGETMSB 0xf075 628 #define F367TER_AUT_AGC_TARGET_MSB 0xf07500ff 629 630 /* LOCK_DET_MSB */ 631 #define R367TER_LOCK_DET_MSB 0xf076 632 #define F367TER_LOCK_DETECT_MSB 0xf07600ff 633 634 /* AGCTAR_LOCK_LSBS */ 635 #define R367TER_AGCTAR_LOCK_LSBS 0xf077 636 #define F367TER_AUT_AGC_TARGET_LSB 0xf07700f0 637 #define F367TER_LOCK_DETECT_LSB 0xf077000f 638 639 /* AUT_GAIN_EN */ 640 #define R367TER_AUT_GAIN_EN 0xf078 641 #define F367TER_AUT_ENMODE 0xf07800f0 642 #define F367TER_AUT_GAIN2 0xf078000f 643 644 /* AUT_CFG */ 645 #define R367TER_AUT_CFG 0xf079 646 #define F367TER_AUT_N 0xf07900f8 647 #define F367TER_INT_CHOICE 0xf0790006 648 #define F367TER_INT_LOAD 0xf0790001 649 650 /* LOCKN */ 651 #define R367TER_LOCKN 0xf07a 652 #define F367TER_LOCK_N 0xf07a00f8 653 #define F367TER_SEL_IQNTAR 0xf07a0004 654 #define F367TER_LOCK_DETECT_CHOICE 0xf07a0003 655 656 /* INT_X_3 */ 657 #define R367TER_INT_X_3 0xf07b 658 #define F367TER_INT_X3 0xf07b00ff 659 660 /* INT_X_2 */ 661 #define R367TER_INT_X_2 0xf07c 662 #define F367TER_INT_X2 0xf07c00ff 663 664 /* INT_X_1 */ 665 #define R367TER_INT_X_1 0xf07d 666 #define F367TER_INT_X1 0xf07d00ff 667 668 /* INT_X_0 */ 669 #define R367TER_INT_X_0 0xf07e 670 #define F367TER_INT_X0 0xf07e00ff 671 672 /* MIN_ERRX_MSB */ 673 #define R367TER_MIN_ERRX_MSB 0xf07f 674 #define F367TER_MIN_ERR_X_MSB 0xf07f00ff 675 676 /* COR_CTL */ 677 #define R367TER_COR_CTL 0xf080 678 #define F367TER_CORE_ACTIVE 0xf0800020 679 #define F367TER_HOLD 0xf0800010 680 #define F367TER_CORE_STATE_CTL 0xf080000f 681 682 /* COR_STAT */ 683 #define R367TER_COR_STAT 0xf081 684 #define F367TER_SCATT_LOCKED 0xf0810080 685 #define F367TER_TPS_LOCKED 0xf0810040 686 #define F367TER_SYR_LOCKED_COR 0xf0810020 687 #define F367TER_AGC_LOCKED_STAT 0xf0810010 688 #define F367TER_CORE_STATE_STAT 0xf081000f 689 690 /* COR_INTEN */ 691 #define R367TER_COR_INTEN 0xf082 692 #define F367TER_INTEN 0xf0820080 693 #define F367TER_INTEN_SYR 0xf0820020 694 #define F367TER_INTEN_FFT 0xf0820010 695 #define F367TER_INTEN_AGC 0xf0820008 696 #define F367TER_INTEN_TPS1 0xf0820004 697 #define F367TER_INTEN_TPS2 0xf0820002 698 #define F367TER_INTEN_TPS3 0xf0820001 699 700 /* COR_INTSTAT */ 701 #define R367TER_COR_INTSTAT 0xf083 702 #define F367TER_INTSTAT_SYR 0xf0830020 703 #define F367TER_INTSTAT_FFT 0xf0830010 704 #define F367TER_INTSAT_AGC 0xf0830008 705 #define F367TER_INTSTAT_TPS1 0xf0830004 706 #define F367TER_INTSTAT_TPS2 0xf0830002 707 #define F367TER_INTSTAT_TPS3 0xf0830001 708 709 /* COR_MODEGUARD */ 710 #define R367TER_COR_MODEGUARD 0xf084 711 #define F367TER_FORCE 0xf0840010 712 #define F367TER_MODE 0xf084000c 713 #define F367TER_GUARD 0xf0840003 714 715 /* AGC_CTL */ 716 #define R367TER_AGC_CTL 0xf085 717 #define F367TER_AGC_TIMING_FACTOR 0xf08500e0 718 #define F367TER_AGC_LAST 0xf0850010 719 #define F367TER_AGC_GAIN 0xf085000c 720 #define F367TER_AGC_NEG 0xf0850002 721 #define F367TER_AGC_SET 0xf0850001 722 723 /* AGC_MANUAL1 */ 724 #define R367TER_AGC_MANUAL1 0xf086 725 #define F367TER_AGC_VAL_LO 0xf08600ff 726 727 /* AGC_MANUAL2 */ 728 #define R367TER_AGC_MANUAL2 0xf087 729 #define F367TER_AGC_VAL_HI 0xf087000f 730 731 /* AGC_TARG */ 732 #define R367TER_AGC_TARG 0xf088 733 #define F367TER_AGC_TARGET 0xf08800ff 734 735 /* AGC_GAIN1 */ 736 #define R367TER_AGC_GAIN1 0xf089 737 #define F367TER_AGC_GAIN_LO 0xf08900ff 738 739 /* AGC_GAIN2 */ 740 #define R367TER_AGC_GAIN2 0xf08a 741 #define F367TER_AGC_LOCKED_GAIN2 0xf08a0010 742 #define F367TER_AGC_GAIN_HI 0xf08a000f 743 744 /* RESERVED_1 */ 745 #define R367TER_RESERVED_1 0xf08b 746 #define F367TER_RESERVED1 0xf08b00ff 747 748 /* RESERVED_2 */ 749 #define R367TER_RESERVED_2 0xf08c 750 #define F367TER_RESERVED2 0xf08c00ff 751 752 /* RESERVED_3 */ 753 #define R367TER_RESERVED_3 0xf08d 754 #define F367TER_RESERVED3 0xf08d00ff 755 756 /* CAS_CTL */ 757 #define R367TER_CAS_CTL 0xf08e 758 #define F367TER_CCS_ENABLE 0xf08e0080 759 #define F367TER_ACS_DISABLE 0xf08e0040 760 #define F367TER_DAGC_DIS 0xf08e0020 761 #define F367TER_DAGC_GAIN 0xf08e0018 762 #define F367TER_CCSMU 0xf08e0007 763 764 /* CAS_FREQ */ 765 #define R367TER_CAS_FREQ 0xf08f 766 #define F367TER_CCS_FREQ 0xf08f00ff 767 768 /* CAS_DAGCGAIN */ 769 #define R367TER_CAS_DAGCGAIN 0xf090 770 #define F367TER_CAS_DAGC_GAIN 0xf09000ff 771 772 /* SYR_CTL */ 773 #define R367TER_SYR_CTL 0xf091 774 #define F367TER_SICTH_ENABLE 0xf0910080 775 #define F367TER_LONG_ECHO 0xf0910078 776 #define F367TER_AUTO_LE_EN 0xf0910004 777 #define F367TER_SYR_BYPASS 0xf0910002 778 #define F367TER_SYR_TR_DIS 0xf0910001 779 780 /* SYR_STAT */ 781 #define R367TER_SYR_STAT 0xf092 782 #define F367TER_SYR_LOCKED_STAT 0xf0920010 783 #define F367TER_SYR_MODE 0xf092000c 784 #define F367TER_SYR_GUARD 0xf0920003 785 786 /* SYR_NCO1 */ 787 #define R367TER_SYR_NCO1 0xf093 788 #define F367TER_SYR_NCO_LO 0xf09300ff 789 790 /* SYR_NCO2 */ 791 #define R367TER_SYR_NCO2 0xf094 792 #define F367TER_SYR_NCO_HI 0xf094003f 793 794 /* SYR_OFFSET1 */ 795 #define R367TER_SYR_OFFSET1 0xf095 796 #define F367TER_SYR_OFFSET_LO 0xf09500ff 797 798 /* SYR_OFFSET2 */ 799 #define R367TER_SYR_OFFSET2 0xf096 800 #define F367TER_SYR_OFFSET_HI 0xf096003f 801 802 /* FFT_CTL */ 803 #define R367TER_FFT_CTL 0xf097 804 #define F367TER_SHIFT_FFT_TRIG 0xf0970018 805 #define F367TER_FFT_TRIGGER 0xf0970004 806 #define F367TER_FFT_MANUAL 0xf0970002 807 #define F367TER_IFFT_MODE 0xf0970001 808 809 /* SCR_CTL */ 810 #define R367TER_SCR_CTL 0xf098 811 #define F367TER_SYRADJDECAY 0xf0980070 812 #define F367TER_SCR_CPEDIS 0xf0980002 813 #define F367TER_SCR_DIS 0xf0980001 814 815 /* PPM_CTL1 */ 816 #define R367TER_PPM_CTL1 0xf099 817 #define F367TER_PPM_MAXFREQ 0xf0990030 818 #define F367TER_PPM_MAXTIM 0xf0990008 819 #define F367TER_PPM_INVSEL 0xf0990004 820 #define F367TER_PPM_SCATDIS 0xf0990002 821 #define F367TER_PPM_BYP 0xf0990001 822 823 /* TRL_CTL */ 824 #define R367TER_TRL_CTL 0xf09a 825 #define F367TER_TRL_NOMRATE_LSB 0xf09a0080 826 #define F367TER_TRL_GAIN_FACTOR 0xf09a0078 827 #define F367TER_TRL_LOOPGAIN 0xf09a0007 828 829 /* TRL_NOMRATE1 */ 830 #define R367TER_TRL_NOMRATE1 0xf09b 831 #define F367TER_TRL_NOMRATE_LO 0xf09b00ff 832 833 /* TRL_NOMRATE2 */ 834 #define R367TER_TRL_NOMRATE2 0xf09c 835 #define F367TER_TRL_NOMRATE_HI 0xf09c00ff 836 837 /* TRL_TIME1 */ 838 #define R367TER_TRL_TIME1 0xf09d 839 #define F367TER_TRL_TOFFSET_LO 0xf09d00ff 840 841 /* TRL_TIME2 */ 842 #define R367TER_TRL_TIME2 0xf09e 843 #define F367TER_TRL_TOFFSET_HI 0xf09e00ff 844 845 /* CRL_CTL */ 846 #define R367TER_CRL_CTL 0xf09f 847 #define F367TER_CRL_DIS 0xf09f0080 848 #define F367TER_CRL_GAIN_FACTOR 0xf09f0078 849 #define F367TER_CRL_LOOPGAIN 0xf09f0007 850 851 /* CRL_FREQ1 */ 852 #define R367TER_CRL_FREQ1 0xf0a0 853 #define F367TER_CRL_FOFFSET_LO 0xf0a000ff 854 855 /* CRL_FREQ2 */ 856 #define R367TER_CRL_FREQ2 0xf0a1 857 #define F367TER_CRL_FOFFSET_HI 0xf0a100ff 858 859 /* CRL_FREQ3 */ 860 #define R367TER_CRL_FREQ3 0xf0a2 861 #define F367TER_CRL_FOFFSET_VHI 0xf0a200ff 862 863 /* TPS_SFRAME_CTL */ 864 #define R367TER_TPS_SFRAME_CTL 0xf0a3 865 #define F367TER_TPS_SFRAME_SYNC 0xf0a30001 866 867 /* CHC_SNR */ 868 #define R367TER_CHC_SNR 0xf0a4 869 #define F367TER_CHCSNR 0xf0a400ff 870 871 /* BDI_CTL */ 872 #define R367TER_BDI_CTL 0xf0a5 873 #define F367TER_BDI_LPSEL 0xf0a50002 874 #define F367TER_BDI_SERIAL 0xf0a50001 875 876 /* DMP_CTL */ 877 #define R367TER_DMP_CTL 0xf0a6 878 #define F367TER_DMP_SCALING_FACTOR 0xf0a6001e 879 #define F367TER_DMP_SDDIS 0xf0a60001 880 881 /* TPS_RCVD1 */ 882 #define R367TER_TPS_RCVD1 0xf0a7 883 #define F367TER_TPS_CHANGE 0xf0a70040 884 #define F367TER_BCH_OK 0xf0a70020 885 #define F367TER_TPS_SYNC 0xf0a70010 886 #define F367TER_TPS_FRAME 0xf0a70003 887 888 /* TPS_RCVD2 */ 889 #define R367TER_TPS_RCVD2 0xf0a8 890 #define F367TER_TPS_HIERMODE 0xf0a80070 891 #define F367TER_TPS_CONST 0xf0a80003 892 893 /* TPS_RCVD3 */ 894 #define R367TER_TPS_RCVD3 0xf0a9 895 #define F367TER_TPS_LPCODE 0xf0a90070 896 #define F367TER_TPS_HPCODE 0xf0a90007 897 898 /* TPS_RCVD4 */ 899 #define R367TER_TPS_RCVD4 0xf0aa 900 #define F367TER_TPS_GUARD 0xf0aa0030 901 #define F367TER_TPS_MODE 0xf0aa0003 902 903 /* TPS_ID_CELL1 */ 904 #define R367TER_TPS_ID_CELL1 0xf0ab 905 #define F367TER_TPS_ID_CELL_LO 0xf0ab00ff 906 907 /* TPS_ID_CELL2 */ 908 #define R367TER_TPS_ID_CELL2 0xf0ac 909 #define F367TER_TPS_ID_CELL_HI 0xf0ac00ff 910 911 /* TPS_RCVD5_SET1 */ 912 #define R367TER_TPS_RCVD5_SET1 0xf0ad 913 #define F367TER_TPS_NA 0xf0ad00fC 914 #define F367TER_TPS_SETFRAME 0xf0ad0003 915 916 /* TPS_SET2 */ 917 #define R367TER_TPS_SET2 0xf0ae 918 #define F367TER_TPS_SETHIERMODE 0xf0ae0070 919 #define F367TER_TPS_SETCONST 0xf0ae0003 920 921 /* TPS_SET3 */ 922 #define R367TER_TPS_SET3 0xf0af 923 #define F367TER_TPS_SETLPCODE 0xf0af0070 924 #define F367TER_TPS_SETHPCODE 0xf0af0007 925 926 /* TPS_CTL */ 927 #define R367TER_TPS_CTL 0xf0b0 928 #define F367TER_TPS_IMM 0xf0b00004 929 #define F367TER_TPS_BCHDIS 0xf0b00002 930 #define F367TER_TPS_UPDDIS 0xf0b00001 931 932 /* CTL_FFTOSNUM */ 933 #define R367TER_CTL_FFTOSNUM 0xf0b1 934 #define F367TER_SYMBOL_NUMBER 0xf0b1007f 935 936 /* TESTSELECT */ 937 #define R367TER_TESTSELECT 0xf0b2 938 #define F367TER_TEST_SELECT 0xf0b2001f 939 940 /* MSC_REV */ 941 #define R367TER_MSC_REV 0xf0b3 942 #define F367TER_REV_NUMBER 0xf0b300ff 943 944 /* PIR_CTL */ 945 #define R367TER_PIR_CTL 0xf0b4 946 #define F367TER_FREEZE 0xf0b40001 947 948 /* SNR_CARRIER1 */ 949 #define R367TER_SNR_CARRIER1 0xf0b5 950 #define F367TER_SNR_CARRIER_LO 0xf0b500ff 951 952 /* SNR_CARRIER2 */ 953 #define R367TER_SNR_CARRIER2 0xf0b6 954 #define F367TER_MEAN 0xf0b600c0 955 #define F367TER_SNR_CARRIER_HI 0xf0b6001f 956 957 /* PPM_CPAMP */ 958 #define R367TER_PPM_CPAMP 0xf0b7 959 #define F367TER_PPM_CPC 0xf0b700ff 960 961 /* TSM_AP0 */ 962 #define R367TER_TSM_AP0 0xf0b8 963 #define F367TER_ADDRESS_BYTE_0 0xf0b800ff 964 965 /* TSM_AP1 */ 966 #define R367TER_TSM_AP1 0xf0b9 967 #define F367TER_ADDRESS_BYTE_1 0xf0b900ff 968 969 /* TSM_AP2 */ 970 #define R367TER_TSM_AP2 0xf0bA 971 #define F367TER_DATA_BYTE_0 0xf0ba00ff 972 973 /* TSM_AP3 */ 974 #define R367TER_TSM_AP3 0xf0bB 975 #define F367TER_DATA_BYTE_1 0xf0bb00ff 976 977 /* TSM_AP4 */ 978 #define R367TER_TSM_AP4 0xf0bC 979 #define F367TER_DATA_BYTE_2 0xf0bc00ff 980 981 /* TSM_AP5 */ 982 #define R367TER_TSM_AP5 0xf0bD 983 #define F367TER_DATA_BYTE_3 0xf0bd00ff 984 985 /* TSM_AP6 */ 986 #define R367TER_TSM_AP6 0xf0bE 987 #define F367TER_TSM_AP_6 0xf0be00ff 988 989 /* TSM_AP7 */ 990 #define R367TER_TSM_AP7 0xf0bF 991 #define F367TER_MEM_SELECT_BYTE 0xf0bf00ff 992 993 /* TSTRES */ 994 #define R367TER_TSTRES 0xf0c0 995 #define F367TER_FRES_DISPLAY 0xf0c00080 996 #define F367TER_FRES_FIFO_AD 0xf0c00020 997 #define F367TER_FRESRS 0xf0c00010 998 #define F367TER_FRESACS 0xf0c00008 999 #define F367TER_FRESFEC 0xf0c00004 1000 #define F367TER_FRES_PRIF 0xf0c00002 1001 #define F367TER_FRESCORE 0xf0c00001 1002 1003 /* ANACTRL */ 1004 #define R367TER_ANACTRL 0xf0c1 1005 #define F367TER_BYPASS_XTAL 0xf0c10040 1006 #define F367TER_BYPASS_PLLXN 0xf0c1000c 1007 #define F367TER_DIS_PAD_OSC 0xf0c10002 1008 #define F367TER_STDBY_PLLXN 0xf0c10001 1009 1010 /* TSTBUS */ 1011 #define R367TER_TSTBUS 0xf0c2 1012 #define F367TER_TS_BYTE_CLK_INV 0xf0c20080 1013 #define F367TER_CFG_IP 0xf0c20070 1014 #define F367TER_CFG_TST 0xf0c2000f 1015 1016 /* TSTRATE */ 1017 #define R367TER_TSTRATE 0xf0c6 1018 #define F367TER_FORCEPHA 0xf0c60080 1019 #define F367TER_FNEWPHA 0xf0c60010 1020 #define F367TER_FROT90 0xf0c60008 1021 #define F367TER_FR 0xf0c60007 1022 1023 /* CONSTMODE */ 1024 #define R367TER_CONSTMODE 0xf0cb 1025 #define F367TER_TST_PRIF 0xf0cb00e0 1026 #define F367TER_CAR_TYPE 0xf0cb0018 1027 #define F367TER_CONST_MODE 0xf0cb0003 1028 1029 /* CONSTCARR1 */ 1030 #define R367TER_CONSTCARR1 0xf0cc 1031 #define F367TER_CONST_CARR_LO 0xf0cc00ff 1032 1033 /* CONSTCARR2 */ 1034 #define R367TER_CONSTCARR2 0xf0cd 1035 #define F367TER_CONST_CARR_HI 0xf0cd001f 1036 1037 /* ICONSTEL */ 1038 #define R367TER_ICONSTEL 0xf0ce 1039 #define F367TER_PICONSTEL 0xf0ce00ff 1040 1041 /* QCONSTEL */ 1042 #define R367TER_QCONSTEL 0xf0cf 1043 #define F367TER_PQCONSTEL 0xf0cf00ff 1044 1045 /* TSTBISTRES0 */ 1046 #define R367TER_TSTBISTRES0 0xf0d0 1047 #define F367TER_BEND_PPM 0xf0d00080 1048 #define F367TER_BBAD_PPM 0xf0d00040 1049 #define F367TER_BEND_FFTW 0xf0d00020 1050 #define F367TER_BBAD_FFTW 0xf0d00010 1051 #define F367TER_BEND_FFT_BUF 0xf0d00008 1052 #define F367TER_BBAD_FFT_BUF 0xf0d00004 1053 #define F367TER_BEND_SYR 0xf0d00002 1054 #define F367TER_BBAD_SYR 0xf0d00001 1055 1056 /* TSTBISTRES1 */ 1057 #define R367TER_TSTBISTRES1 0xf0d1 1058 #define F367TER_BEND_CHC_CP 0xf0d10080 1059 #define F367TER_BBAD_CHC_CP 0xf0d10040 1060 #define F367TER_BEND_CHCI 0xf0d10020 1061 #define F367TER_BBAD_CHCI 0xf0d10010 1062 #define F367TER_BEND_BDI 0xf0d10008 1063 #define F367TER_BBAD_BDI 0xf0d10004 1064 #define F367TER_BEND_SDI 0xf0d10002 1065 #define F367TER_BBAD_SDI 0xf0d10001 1066 1067 /* TSTBISTRES2 */ 1068 #define R367TER_TSTBISTRES2 0xf0d2 1069 #define F367TER_BEND_CHC_INC 0xf0d20080 1070 #define F367TER_BBAD_CHC_INC 0xf0d20040 1071 #define F367TER_BEND_CHC_SPP 0xf0d20020 1072 #define F367TER_BBAD_CHC_SPP 0xf0d20010 1073 #define F367TER_BEND_CHC_CPP 0xf0d20008 1074 #define F367TER_BBAD_CHC_CPP 0xf0d20004 1075 #define F367TER_BEND_CHC_SP 0xf0d20002 1076 #define F367TER_BBAD_CHC_SP 0xf0d20001 1077 1078 /* TSTBISTRES3 */ 1079 #define R367TER_TSTBISTRES3 0xf0d3 1080 #define F367TER_BEND_QAM 0xf0d30080 1081 #define F367TER_BBAD_QAM 0xf0d30040 1082 #define F367TER_BEND_SFEC_VIT 0xf0d30020 1083 #define F367TER_BBAD_SFEC_VIT 0xf0d30010 1084 #define F367TER_BEND_SFEC_DLINE 0xf0d30008 1085 #define F367TER_BBAD_SFEC_DLINE 0xf0d30004 1086 #define F367TER_BEND_SFEC_HW 0xf0d30002 1087 #define F367TER_BBAD_SFEC_HW 0xf0d30001 1088 1089 /* RF_AGC1 */ 1090 #define R367TER_RF_AGC1 0xf0d4 1091 #define F367TER_RF_AGC1_LEVEL_HI 0xf0d400ff 1092 1093 /* RF_AGC2 */ 1094 #define R367TER_RF_AGC2 0xf0d5 1095 #define F367TER_REF_ADGP 0xf0d50080 1096 #define F367TER_STDBY_ADCGP 0xf0d50020 1097 #define F367TER_CHANNEL_SEL 0xf0d5001c 1098 #define F367TER_RF_AGC1_LEVEL_LO 0xf0d50003 1099 1100 /* ANADIGCTRL */ 1101 #define R367TER_ANADIGCTRL 0xf0d7 1102 #define F367TER_SEL_CLKDEM 0xf0d70020 1103 #define F367TER_EN_BUFFER_Q 0xf0d70010 1104 #define F367TER_EN_BUFFER_I 0xf0d70008 1105 #define F367TER_ADC_RIS_EGDE 0xf0d70004 1106 #define F367TER_SGN_ADC 0xf0d70002 1107 #define F367TER_SEL_AD12_SYNC 0xf0d70001 1108 1109 /* PLLMDIV */ 1110 #define R367TER_PLLMDIV 0xf0d8 1111 #define F367TER_PLL_MDIV 0xf0d800ff 1112 1113 /* PLLNDIV */ 1114 #define R367TER_PLLNDIV 0xf0d9 1115 #define F367TER_PLL_NDIV 0xf0d900ff 1116 1117 /* PLLSETUP */ 1118 #define R367TER_PLLSETUP 0xf0dA 1119 #define F367TER_PLL_PDIV 0xf0da0070 1120 #define F367TER_PLL_KDIV 0xf0da000f 1121 1122 /* DUAL_AD12 */ 1123 #define R367TER_DUAL_AD12 0xf0dB 1124 #define F367TER_FS20M 0xf0db0020 1125 #define F367TER_FS50M 0xf0db0010 1126 #define F367TER_INMODe0 0xf0db0008 1127 #define F367TER_POFFQ 0xf0db0004 1128 #define F367TER_POFFI 0xf0db0002 1129 #define F367TER_INMODE1 0xf0db0001 1130 1131 /* TSTBIST */ 1132 #define R367TER_TSTBIST 0xf0dC 1133 #define F367TER_TST_BYP_CLK 0xf0dc0080 1134 #define F367TER_TST_GCLKENA_STD 0xf0dc0040 1135 #define F367TER_TST_GCLKENA 0xf0dc0020 1136 #define F367TER_TST_MEMBIST 0xf0dc001f 1137 1138 /* PAD_COMP_CTRL */ 1139 #define R367TER_PAD_COMP_CTRL 0xf0dD 1140 #define F367TER_COMPTQ 0xf0dd0010 1141 #define F367TER_COMPEN 0xf0dd0008 1142 #define F367TER_FREEZE2 0xf0dd0004 1143 #define F367TER_SLEEP_INHBT 0xf0dd0002 1144 #define F367TER_CHIP_SLEEP 0xf0dd0001 1145 1146 /* PAD_COMP_WR */ 1147 #define R367TER_PAD_COMP_WR 0xf0de 1148 #define F367TER_WR_ASRC 0xf0de007f 1149 1150 /* PAD_COMP_RD */ 1151 #define R367TER_PAD_COMP_RD 0xf0df 1152 #define F367TER_COMPOK 0xf0df0080 1153 #define F367TER_RD_ASRC 0xf0df007f 1154 1155 /* SYR_TARGET_FFTADJT_MSB */ 1156 #define R367TER_SYR_TARGET_FFTADJT_MSB 0xf100 1157 #define F367TER_SYR_START 0xf1000080 1158 #define F367TER_SYR_TARGET_FFTADJ_HI 0xf100000f 1159 1160 /* SYR_TARGET_FFTADJT_LSB */ 1161 #define R367TER_SYR_TARGET_FFTADJT_LSB 0xf101 1162 #define F367TER_SYR_TARGET_FFTADJ_LO 0xf10100ff 1163 1164 /* SYR_TARGET_CHCADJT_MSB */ 1165 #define R367TER_SYR_TARGET_CHCADJT_MSB 0xf102 1166 #define F367TER_SYR_TARGET_CHCADJ_HI 0xf102000f 1167 1168 /* SYR_TARGET_CHCADJT_LSB */ 1169 #define R367TER_SYR_TARGET_CHCADJT_LSB 0xf103 1170 #define F367TER_SYR_TARGET_CHCADJ_LO 0xf10300ff 1171 1172 /* SYR_FLAG */ 1173 #define R367TER_SYR_FLAG 0xf104 1174 #define F367TER_TRIG_FLG1 0xf1040080 1175 #define F367TER_TRIG_FLG0 0xf1040040 1176 #define F367TER_FFT_FLG1 0xf1040008 1177 #define F367TER_FFT_FLG0 0xf1040004 1178 #define F367TER_CHC_FLG1 0xf1040002 1179 #define F367TER_CHC_FLG0 0xf1040001 1180 1181 /* CRL_TARGET1 */ 1182 #define R367TER_CRL_TARGET1 0xf105 1183 #define F367TER_CRL_START 0xf1050080 1184 #define F367TER_CRL_TARGET_VHI 0xf105000f 1185 1186 /* CRL_TARGET2 */ 1187 #define R367TER_CRL_TARGET2 0xf106 1188 #define F367TER_CRL_TARGET_HI 0xf10600ff 1189 1190 /* CRL_TARGET3 */ 1191 #define R367TER_CRL_TARGET3 0xf107 1192 #define F367TER_CRL_TARGET_LO 0xf10700ff 1193 1194 /* CRL_TARGET4 */ 1195 #define R367TER_CRL_TARGET4 0xf108 1196 #define F367TER_CRL_TARGET_VLO 0xf10800ff 1197 1198 /* CRL_FLAG */ 1199 #define R367TER_CRL_FLAG 0xf109 1200 #define F367TER_CRL_FLAG1 0xf1090002 1201 #define F367TER_CRL_FLAG0 0xf1090001 1202 1203 /* TRL_TARGET1 */ 1204 #define R367TER_TRL_TARGET1 0xf10a 1205 #define F367TER_TRL_TARGET_HI 0xf10a00ff 1206 1207 /* TRL_TARGET2 */ 1208 #define R367TER_TRL_TARGET2 0xf10b 1209 #define F367TER_TRL_TARGET_LO 0xf10b00ff 1210 1211 /* TRL_CHC */ 1212 #define R367TER_TRL_CHC 0xf10c 1213 #define F367TER_TRL_START 0xf10c0080 1214 #define F367TER_CHC_START 0xf10c0040 1215 #define F367TER_TRL_FLAG1 0xf10c0002 1216 #define F367TER_TRL_FLAG0 0xf10c0001 1217 1218 /* CHC_SNR_TARG */ 1219 #define R367TER_CHC_SNR_TARG 0xf10d 1220 #define F367TER_CHC_SNR_TARGET 0xf10d00ff 1221 1222 /* TOP_TRACK */ 1223 #define R367TER_TOP_TRACK 0xf10e 1224 #define F367TER_TOP_START 0xf10e0080 1225 #define F367TER_FIRST_FLAG 0xf10e0070 1226 #define F367TER_TOP_FLAG1 0xf10e0008 1227 #define F367TER_TOP_FLAG0 0xf10e0004 1228 #define F367TER_CHC_FLAG1 0xf10e0002 1229 #define F367TER_CHC_FLAG0 0xf10e0001 1230 1231 /* TRACKER_FREE1 */ 1232 #define R367TER_TRACKER_FREE1 0xf10f 1233 #define F367TER_TRACKER_FREE_1 0xf10f00ff 1234 1235 /* ERROR_CRL1 */ 1236 #define R367TER_ERROR_CRL1 0xf110 1237 #define F367TER_ERROR_CRL_VHI 0xf11000ff 1238 1239 /* ERROR_CRL2 */ 1240 #define R367TER_ERROR_CRL2 0xf111 1241 #define F367TER_ERROR_CRL_HI 0xf11100ff 1242 1243 /* ERROR_CRL3 */ 1244 #define R367TER_ERROR_CRL3 0xf112 1245 #define F367TER_ERROR_CRL_LOI 0xf11200ff 1246 1247 /* ERROR_CRL4 */ 1248 #define R367TER_ERROR_CRL4 0xf113 1249 #define F367TER_ERROR_CRL_VLO 0xf11300ff 1250 1251 /* DEC_NCO1 */ 1252 #define R367TER_DEC_NCO1 0xf114 1253 #define F367TER_DEC_NCO_VHI 0xf11400ff 1254 1255 /* DEC_NCO2 */ 1256 #define R367TER_DEC_NCO2 0xf115 1257 #define F367TER_DEC_NCO_HI 0xf11500ff 1258 1259 /* DEC_NCO3 */ 1260 #define R367TER_DEC_NCO3 0xf116 1261 #define F367TER_DEC_NCO_LO 0xf11600ff 1262 1263 /* SNR */ 1264 #define R367TER_SNR 0xf117 1265 #define F367TER_SNRATIO 0xf11700ff 1266 1267 /* SYR_FFTADJ1 */ 1268 #define R367TER_SYR_FFTADJ1 0xf118 1269 #define F367TER_SYR_FFTADJ_HI 0xf11800ff 1270 1271 /* SYR_FFTADJ2 */ 1272 #define R367TER_SYR_FFTADJ2 0xf119 1273 #define F367TER_SYR_FFTADJ_LO 0xf11900ff 1274 1275 /* SYR_CHCADJ1 */ 1276 #define R367TER_SYR_CHCADJ1 0xf11a 1277 #define F367TER_SYR_CHCADJ_HI 0xf11a00ff 1278 1279 /* SYR_CHCADJ2 */ 1280 #define R367TER_SYR_CHCADJ2 0xf11b 1281 #define F367TER_SYR_CHCADJ_LO 0xf11b00ff 1282 1283 /* SYR_OFF */ 1284 #define R367TER_SYR_OFF 0xf11c 1285 #define F367TER_SYR_OFFSET 0xf11c00ff 1286 1287 /* PPM_OFFSET1 */ 1288 #define R367TER_PPM_OFFSET1 0xf11d 1289 #define F367TER_PPM_OFFSET_HI 0xf11d00ff 1290 1291 /* PPM_OFFSET2 */ 1292 #define R367TER_PPM_OFFSET2 0xf11e 1293 #define F367TER_PPM_OFFSET_LO 0xf11e00ff 1294 1295 /* TRACKER_FREE2 */ 1296 #define R367TER_TRACKER_FREE2 0xf11f 1297 #define F367TER_TRACKER_FREE_2 0xf11f00ff 1298 1299 /* DEBG_LT10 */ 1300 #define R367TER_DEBG_LT10 0xf120 1301 #define F367TER_DEBUG_LT10 0xf12000ff 1302 1303 /* DEBG_LT11 */ 1304 #define R367TER_DEBG_LT11 0xf121 1305 #define F367TER_DEBUG_LT11 0xf12100ff 1306 1307 /* DEBG_LT12 */ 1308 #define R367TER_DEBG_LT12 0xf122 1309 #define F367TER_DEBUG_LT12 0xf12200ff 1310 1311 /* DEBG_LT13 */ 1312 #define R367TER_DEBG_LT13 0xf123 1313 #define F367TER_DEBUG_LT13 0xf12300ff 1314 1315 /* DEBG_LT14 */ 1316 #define R367TER_DEBG_LT14 0xf124 1317 #define F367TER_DEBUG_LT14 0xf12400ff 1318 1319 /* DEBG_LT15 */ 1320 #define R367TER_DEBG_LT15 0xf125 1321 #define F367TER_DEBUG_LT15 0xf12500ff 1322 1323 /* DEBG_LT16 */ 1324 #define R367TER_DEBG_LT16 0xf126 1325 #define F367TER_DEBUG_LT16 0xf12600ff 1326 1327 /* DEBG_LT17 */ 1328 #define R367TER_DEBG_LT17 0xf127 1329 #define F367TER_DEBUG_LT17 0xf12700ff 1330 1331 /* DEBG_LT18 */ 1332 #define R367TER_DEBG_LT18 0xf128 1333 #define F367TER_DEBUG_LT18 0xf12800ff 1334 1335 /* DEBG_LT19 */ 1336 #define R367TER_DEBG_LT19 0xf129 1337 #define F367TER_DEBUG_LT19 0xf12900ff 1338 1339 /* DEBG_LT1a */ 1340 #define R367TER_DEBG_LT1A 0xf12a 1341 #define F367TER_DEBUG_LT1A 0xf12a00ff 1342 1343 /* DEBG_LT1b */ 1344 #define R367TER_DEBG_LT1B 0xf12b 1345 #define F367TER_DEBUG_LT1B 0xf12b00ff 1346 1347 /* DEBG_LT1c */ 1348 #define R367TER_DEBG_LT1C 0xf12c 1349 #define F367TER_DEBUG_LT1C 0xf12c00ff 1350 1351 /* DEBG_LT1D */ 1352 #define R367TER_DEBG_LT1D 0xf12d 1353 #define F367TER_DEBUG_LT1D 0xf12d00ff 1354 1355 /* DEBG_LT1E */ 1356 #define R367TER_DEBG_LT1E 0xf12e 1357 #define F367TER_DEBUG_LT1E 0xf12e00ff 1358 1359 /* DEBG_LT1F */ 1360 #define R367TER_DEBG_LT1F 0xf12f 1361 #define F367TER_DEBUG_LT1F 0xf12f00ff 1362 1363 /* RCCFGH */ 1364 #define R367TER_RCCFGH 0xf200 1365 #define F367TER_TSRCFIFO_DVBCI 0xf2000080 1366 #define F367TER_TSRCFIFO_SERIAL 0xf2000040 1367 #define F367TER_TSRCFIFO_DISABLE 0xf2000020 1368 #define F367TER_TSFIFO_2TORC 0xf2000010 1369 #define F367TER_TSRCFIFO_HSGNLOUT 0xf2000008 1370 #define F367TER_TSRCFIFO_ERRMODE 0xf2000006 1371 #define F367TER_RCCFGH_0 0xf2000001 1372 1373 /* RCCFGM */ 1374 #define R367TER_RCCFGM 0xf201 1375 #define F367TER_TSRCFIFO_MANSPEED 0xf20100c0 1376 #define F367TER_TSRCFIFO_PERMDATA 0xf2010020 1377 #define F367TER_TSRCFIFO_NONEWSGNL 0xf2010010 1378 #define F367TER_RCBYTE_OVERSAMPLING 0xf201000e 1379 #define F367TER_TSRCFIFO_INVDATA 0xf2010001 1380 1381 /* RCCFGL */ 1382 #define R367TER_RCCFGL 0xf202 1383 #define F367TER_TSRCFIFO_BCLKDEL1cK 0xf20200c0 1384 #define F367TER_RCCFGL_5 0xf2020020 1385 #define F367TER_TSRCFIFO_DUTY50 0xf2020010 1386 #define F367TER_TSRCFIFO_NSGNL2dATA 0xf2020008 1387 #define F367TER_TSRCFIFO_DISSERMUX 0xf2020004 1388 #define F367TER_RCCFGL_1 0xf2020002 1389 #define F367TER_TSRCFIFO_STOPCKDIS 0xf2020001 1390 1391 /* RCINSDELH */ 1392 #define R367TER_RCINSDELH 0xf203 1393 #define F367TER_TSRCDEL_SYNCBYTE 0xf2030080 1394 #define F367TER_TSRCDEL_XXHEADER 0xf2030040 1395 #define F367TER_TSRCDEL_BBHEADER 0xf2030020 1396 #define F367TER_TSRCDEL_DATAFIELD 0xf2030010 1397 #define F367TER_TSRCINSDEL_ISCR 0xf2030008 1398 #define F367TER_TSRCINSDEL_NPD 0xf2030004 1399 #define F367TER_TSRCINSDEL_RSPARITY 0xf2030002 1400 #define F367TER_TSRCINSDEL_CRC8 0xf2030001 1401 1402 /* RCINSDELM */ 1403 #define R367TER_RCINSDELM 0xf204 1404 #define F367TER_TSRCINS_BBPADDING 0xf2040080 1405 #define F367TER_TSRCINS_BCHFEC 0xf2040040 1406 #define F367TER_TSRCINS_LDPCFEC 0xf2040020 1407 #define F367TER_TSRCINS_EMODCOD 0xf2040010 1408 #define F367TER_TSRCINS_TOKEN 0xf2040008 1409 #define F367TER_TSRCINS_XXXERR 0xf2040004 1410 #define F367TER_TSRCINS_MATYPE 0xf2040002 1411 #define F367TER_TSRCINS_UPL 0xf2040001 1412 1413 /* RCINSDELL */ 1414 #define R367TER_RCINSDELL 0xf205 1415 #define F367TER_TSRCINS_DFL 0xf2050080 1416 #define F367TER_TSRCINS_SYNCD 0xf2050040 1417 #define F367TER_TSRCINS_BLOCLEN 0xf2050020 1418 #define F367TER_TSRCINS_SIGPCOUNT 0xf2050010 1419 #define F367TER_TSRCINS_FIFO 0xf2050008 1420 #define F367TER_TSRCINS_REALPACK 0xf2050004 1421 #define F367TER_TSRCINS_TSCONFIG 0xf2050002 1422 #define F367TER_TSRCINS_LATENCY 0xf2050001 1423 1424 /* RCSTATUS */ 1425 #define R367TER_RCSTATUS 0xf206 1426 #define F367TER_TSRCFIFO_LINEOK 0xf2060080 1427 #define F367TER_TSRCFIFO_ERROR 0xf2060040 1428 #define F367TER_TSRCFIFO_DATA7 0xf2060020 1429 #define F367TER_RCSTATUS_4 0xf2060010 1430 #define F367TER_TSRCFIFO_DEMODSEL 0xf2060008 1431 #define F367TER_TSRC1FIFOSPEED_STORE 0xf2060004 1432 #define F367TER_RCSTATUS_1 0xf2060002 1433 #define F367TER_TSRCSERIAL_IMPOSSIBLE 0xf2060001 1434 1435 /* RCSPEED */ 1436 #define R367TER_RCSPEED 0xf207 1437 #define F367TER_TSRCFIFO_OUTSPEED 0xf20700ff 1438 1439 /* RCDEBUGM */ 1440 #define R367TER_RCDEBUGM 0xf208 1441 #define F367TER_SD_UNSYNC 0xf2080080 1442 #define F367TER_ULFLOCK_DETECTM 0xf2080040 1443 #define F367TER_SUL_SELECTOS 0xf2080020 1444 #define F367TER_DILUL_NOSCRBLE 0xf2080010 1445 #define F367TER_NUL_SCRB 0xf2080008 1446 #define F367TER_UL_SCRB 0xf2080004 1447 #define F367TER_SCRAULBAD 0xf2080002 1448 #define F367TER_SCRAUL_UNSYNC 0xf2080001 1449 1450 /* RCDEBUGL */ 1451 #define R367TER_RCDEBUGL 0xf209 1452 #define F367TER_RS_ERR 0xf2090080 1453 #define F367TER_LLFLOCK_DETECTM 0xf2090040 1454 #define F367TER_NOT_SUL_SELECTOS 0xf2090020 1455 #define F367TER_DILLL_NOSCRBLE 0xf2090010 1456 #define F367TER_NLL_SCRB 0xf2090008 1457 #define F367TER_LL_SCRB 0xf2090004 1458 #define F367TER_SCRALLBAD 0xf2090002 1459 #define F367TER_SCRALL_UNSYNC 0xf2090001 1460 1461 /* RCOBSCFG */ 1462 #define R367TER_RCOBSCFG 0xf20a 1463 #define F367TER_TSRCFIFO_OBSCFG 0xf20a00ff 1464 1465 /* RCOBSM */ 1466 #define R367TER_RCOBSM 0xf20b 1467 #define F367TER_TSRCFIFO_OBSDATA_HI 0xf20b00ff 1468 1469 /* RCOBSL */ 1470 #define R367TER_RCOBSL 0xf20c 1471 #define F367TER_TSRCFIFO_OBSDATA_LO 0xf20c00ff 1472 1473 /* RCFECSPY */ 1474 #define R367TER_RCFECSPY 0xf210 1475 #define F367TER_SPYRC_ENABLE 0xf2100080 1476 #define F367TER_RCNO_SYNCBYTE 0xf2100040 1477 #define F367TER_RCSERIAL_MODE 0xf2100020 1478 #define F367TER_RCUNUSUAL_PACKET 0xf2100010 1479 #define F367TER_BERRCMETER_DATAMODE 0xf210000c 1480 #define F367TER_BERRCMETER_LMODE 0xf2100002 1481 #define F367TER_BERRCMETER_RESET 0xf2100001 1482 1483 /* RCFSPYCFG */ 1484 #define R367TER_RCFSPYCFG 0xf211 1485 #define F367TER_FECSPYRC_INPUT 0xf21100c0 1486 #define F367TER_RCRST_ON_ERROR 0xf2110020 1487 #define F367TER_RCONE_SHOT 0xf2110010 1488 #define F367TER_RCI2C_MODE 0xf211000c 1489 #define F367TER_SPYRC_HSTERESIS 0xf2110003 1490 1491 /* RCFSPYDATA */ 1492 #define R367TER_RCFSPYDATA 0xf212 1493 #define F367TER_SPYRC_STUFFING 0xf2120080 1494 #define F367TER_RCNOERR_PKTJITTER 0xf2120040 1495 #define F367TER_SPYRC_CNULLPKT 0xf2120020 1496 #define F367TER_SPYRC_OUTDATA_MODE 0xf212001f 1497 1498 /* RCFSPYOUT */ 1499 #define R367TER_RCFSPYOUT 0xf213 1500 #define F367TER_FSPYRC_DIRECT 0xf2130080 1501 #define F367TER_RCFSPYOUT_6 0xf2130040 1502 #define F367TER_SPYRC_OUTDATA_BUS 0xf2130038 1503 #define F367TER_RCSTUFF_MODE 0xf2130007 1504 1505 /* RCFSTATUS */ 1506 #define R367TER_RCFSTATUS 0xf214 1507 #define F367TER_SPYRC_ENDSIM 0xf2140080 1508 #define F367TER_RCVALID_SIM 0xf2140040 1509 #define F367TER_RCFOUND_SIGNAL 0xf2140020 1510 #define F367TER_RCDSS_SYNCBYTE 0xf2140010 1511 #define F367TER_RCRESULT_STATE 0xf214000f 1512 1513 /* RCFGOODPACK */ 1514 #define R367TER_RCFGOODPACK 0xf215 1515 #define F367TER_RCGOOD_PACKET 0xf21500ff 1516 1517 /* RCFPACKCNT */ 1518 #define R367TER_RCFPACKCNT 0xf216 1519 #define F367TER_RCPACKET_COUNTER 0xf21600ff 1520 1521 /* RCFSPYMISC */ 1522 #define R367TER_RCFSPYMISC 0xf217 1523 #define F367TER_RCLABEL_COUNTER 0xf21700ff 1524 1525 /* RCFBERCPT4 */ 1526 #define R367TER_RCFBERCPT4 0xf218 1527 #define F367TER_FBERRCMETER_CPT_MMMMSB 0xf21800ff 1528 1529 /* RCFBERCPT3 */ 1530 #define R367TER_RCFBERCPT3 0xf219 1531 #define F367TER_FBERRCMETER_CPT_MMMSB 0xf21900ff 1532 1533 /* RCFBERCPT2 */ 1534 #define R367TER_RCFBERCPT2 0xf21a 1535 #define F367TER_FBERRCMETER_CPT_MMSB 0xf21a00ff 1536 1537 /* RCFBERCPT1 */ 1538 #define R367TER_RCFBERCPT1 0xf21b 1539 #define F367TER_FBERRCMETER_CPT_MSB 0xf21b00ff 1540 1541 /* RCFBERCPT0 */ 1542 #define R367TER_RCFBERCPT0 0xf21c 1543 #define F367TER_FBERRCMETER_CPT_LSB 0xf21c00ff 1544 1545 /* RCFBERERR2 */ 1546 #define R367TER_RCFBERERR2 0xf21d 1547 #define F367TER_FBERRCMETER_ERR_HI 0xf21d00ff 1548 1549 /* RCFBERERR1 */ 1550 #define R367TER_RCFBERERR1 0xf21e 1551 #define F367TER_FBERRCMETER_ERR 0xf21e00ff 1552 1553 /* RCFBERERR0 */ 1554 #define R367TER_RCFBERERR0 0xf21f 1555 #define F367TER_FBERRCMETER_ERR_LO 0xf21f00ff 1556 1557 /* RCFSTATESM */ 1558 #define R367TER_RCFSTATESM 0xf220 1559 #define F367TER_RCRSTATE_F 0xf2200080 1560 #define F367TER_RCRSTATE_E 0xf2200040 1561 #define F367TER_RCRSTATE_D 0xf2200020 1562 #define F367TER_RCRSTATE_C 0xf2200010 1563 #define F367TER_RCRSTATE_B 0xf2200008 1564 #define F367TER_RCRSTATE_A 0xf2200004 1565 #define F367TER_RCRSTATE_9 0xf2200002 1566 #define F367TER_RCRSTATE_8 0xf2200001 1567 1568 /* RCFSTATESL */ 1569 #define R367TER_RCFSTATESL 0xf221 1570 #define F367TER_RCRSTATE_7 0xf2210080 1571 #define F367TER_RCRSTATE_6 0xf2210040 1572 #define F367TER_RCRSTATE_5 0xf2210020 1573 #define F367TER_RCRSTATE_4 0xf2210010 1574 #define F367TER_RCRSTATE_3 0xf2210008 1575 #define F367TER_RCRSTATE_2 0xf2210004 1576 #define F367TER_RCRSTATE_1 0xf2210002 1577 #define F367TER_RCRSTATE_0 0xf2210001 1578 1579 /* RCFSPYBER */ 1580 #define R367TER_RCFSPYBER 0xf222 1581 #define F367TER_RCFSPYBER_7 0xf2220080 1582 #define F367TER_SPYRCOBS_XORREAD 0xf2220040 1583 #define F367TER_FSPYRCBER_OBSMODE 0xf2220020 1584 #define F367TER_FSPYRCBER_SYNCBYT 0xf2220010 1585 #define F367TER_FSPYRCBER_UNSYNC 0xf2220008 1586 #define F367TER_FSPYRCBER_CTIME 0xf2220007 1587 1588 /* RCFSPYDISTM */ 1589 #define R367TER_RCFSPYDISTM 0xf223 1590 #define F367TER_RCPKTTIME_DISTANCE_HI 0xf22300ff 1591 1592 /* RCFSPYDISTL */ 1593 #define R367TER_RCFSPYDISTL 0xf224 1594 #define F367TER_RCPKTTIME_DISTANCE_LO 0xf22400ff 1595 1596 /* RCFSPYOBS7 */ 1597 #define R367TER_RCFSPYOBS7 0xf228 1598 #define F367TER_RCSPYOBS_SPYFAIL 0xf2280080 1599 #define F367TER_RCSPYOBS_SPYFAIL1 0xf2280040 1600 #define F367TER_RCSPYOBS_ERROR 0xf2280020 1601 #define F367TER_RCSPYOBS_STROUT 0xf2280010 1602 #define F367TER_RCSPYOBS_RESULTSTATE1 0xf228000f 1603 1604 /* RCFSPYOBS6 */ 1605 #define R367TER_RCFSPYOBS6 0xf229 1606 #define F367TER_RCSPYOBS_RESULTSTATe0 0xf22900f0 1607 #define F367TER_RCSPYOBS_RESULTSTATEM1 0xf229000f 1608 1609 /* RCFSPYOBS5 */ 1610 #define R367TER_RCFSPYOBS5 0xf22a 1611 #define F367TER_RCSPYOBS_BYTEOFPACKET1 0xf22a00ff 1612 1613 /* RCFSPYOBS4 */ 1614 #define R367TER_RCFSPYOBS4 0xf22b 1615 #define F367TER_RCSPYOBS_BYTEVALUE1 0xf22b00ff 1616 1617 /* RCFSPYOBS3 */ 1618 #define R367TER_RCFSPYOBS3 0xf22c 1619 #define F367TER_RCSPYOBS_DATA1 0xf22c00ff 1620 1621 /* RCFSPYOBS2 */ 1622 #define R367TER_RCFSPYOBS2 0xf22d 1623 #define F367TER_RCSPYOBS_DATa0 0xf22d00ff 1624 1625 /* RCFSPYOBS1 */ 1626 #define R367TER_RCFSPYOBS1 0xf22e 1627 #define F367TER_RCSPYOBS_DATAM1 0xf22e00ff 1628 1629 /* RCFSPYOBS0 */ 1630 #define R367TER_RCFSPYOBS0 0xf22f 1631 #define F367TER_RCSPYOBS_DATAM2 0xf22f00ff 1632 1633 /* TSGENERAL */ 1634 #define R367TER_TSGENERAL 0xf230 1635 #define F367TER_TSGENERAL_7 0xf2300080 1636 #define F367TER_TSGENERAL_6 0xf2300040 1637 #define F367TER_TSFIFO_BCLK1aLL 0xf2300020 1638 #define F367TER_TSGENERAL_4 0xf2300010 1639 #define F367TER_MUXSTREAM_OUTMODE 0xf2300008 1640 #define F367TER_TSFIFO_PERMPARAL 0xf2300006 1641 #define F367TER_RST_REEDSOLO 0xf2300001 1642 1643 /* RC1SPEED */ 1644 #define R367TER_RC1SPEED 0xf231 1645 #define F367TER_TSRCFIFO1_OUTSPEED 0xf23100ff 1646 1647 /* TSGSTATUS */ 1648 #define R367TER_TSGSTATUS 0xf232 1649 #define F367TER_TSGSTATUS_7 0xf2320080 1650 #define F367TER_TSGSTATUS_6 0xf2320040 1651 #define F367TER_RSMEM_FULL 0xf2320020 1652 #define F367TER_RS_MULTCALC 0xf2320010 1653 #define F367TER_RSIN_OVERTIME 0xf2320008 1654 #define F367TER_TSFIFO3_DEMODSEL 0xf2320004 1655 #define F367TER_TSFIFO2_DEMODSEL 0xf2320002 1656 #define F367TER_TSFIFO1_DEMODSEL 0xf2320001 1657 1658 1659 /* FECM */ 1660 #define R367TER_FECM 0xf233 1661 #define F367TER_DSS_DVB 0xf2330080 1662 #define F367TER_DEMOD_BYPASS 0xf2330040 1663 #define F367TER_CMP_SLOWMODE 0xf2330020 1664 #define F367TER_DSS_SRCH 0xf2330010 1665 #define F367TER_FECM_3 0xf2330008 1666 #define F367TER_DIFF_MODEVIT 0xf2330004 1667 #define F367TER_SYNCVIT 0xf2330002 1668 #define F367TER_I2CSYM 0xf2330001 1669 1670 /* VTH12 */ 1671 #define R367TER_VTH12 0xf234 1672 #define F367TER_VTH_12 0xf23400ff 1673 1674 /* VTH23 */ 1675 #define R367TER_VTH23 0xf235 1676 #define F367TER_VTH_23 0xf23500ff 1677 1678 /* VTH34 */ 1679 #define R367TER_VTH34 0xf236 1680 #define F367TER_VTH_34 0xf23600ff 1681 1682 /* VTH56 */ 1683 #define R367TER_VTH56 0xf237 1684 #define F367TER_VTH_56 0xf23700ff 1685 1686 /* VTH67 */ 1687 #define R367TER_VTH67 0xf238 1688 #define F367TER_VTH_67 0xf23800ff 1689 1690 /* VTH78 */ 1691 #define R367TER_VTH78 0xf239 1692 #define F367TER_VTH_78 0xf23900ff 1693 1694 /* VITCURPUN */ 1695 #define R367TER_VITCURPUN 0xf23a 1696 #define F367TER_VIT_MAPPING 0xf23a00e0 1697 #define F367TER_VIT_CURPUN 0xf23a001f 1698 1699 /* VERROR */ 1700 #define R367TER_VERROR 0xf23b 1701 #define F367TER_REGERR_VIT 0xf23b00ff 1702 1703 /* PRVIT */ 1704 #define R367TER_PRVIT 0xf23c 1705 #define F367TER_PRVIT_7 0xf23c0080 1706 #define F367TER_DIS_VTHLOCK 0xf23c0040 1707 #define F367TER_E7_8VIT 0xf23c0020 1708 #define F367TER_E6_7VIT 0xf23c0010 1709 #define F367TER_E5_6VIT 0xf23c0008 1710 #define F367TER_E3_4VIT 0xf23c0004 1711 #define F367TER_E2_3VIT 0xf23c0002 1712 #define F367TER_E1_2VIT 0xf23c0001 1713 1714 /* VAVSRVIT */ 1715 #define R367TER_VAVSRVIT 0xf23d 1716 #define F367TER_AMVIT 0xf23d0080 1717 #define F367TER_FROZENVIT 0xf23d0040 1718 #define F367TER_SNVIT 0xf23d0030 1719 #define F367TER_TOVVIT 0xf23d000c 1720 #define F367TER_HYPVIT 0xf23d0003 1721 1722 /* VSTATUSVIT */ 1723 #define R367TER_VSTATUSVIT 0xf23e 1724 #define F367TER_VITERBI_ON 0xf23e0080 1725 #define F367TER_END_LOOPVIT 0xf23e0040 1726 #define F367TER_VITERBI_DEPRF 0xf23e0020 1727 #define F367TER_PRFVIT 0xf23e0010 1728 #define F367TER_LOCKEDVIT 0xf23e0008 1729 #define F367TER_VITERBI_DELOCK 0xf23e0004 1730 #define F367TER_VIT_DEMODSEL 0xf23e0002 1731 #define F367TER_VITERBI_COMPOUT 0xf23e0001 1732 1733 /* VTHINUSE */ 1734 #define R367TER_VTHINUSE 0xf23f 1735 #define F367TER_VIT_INUSE 0xf23f00ff 1736 1737 /* KDIV12 */ 1738 #define R367TER_KDIV12 0xf240 1739 #define F367TER_KDIV12_MANUAL 0xf2400080 1740 #define F367TER_K_DIVIDER_12 0xf240007f 1741 1742 /* KDIV23 */ 1743 #define R367TER_KDIV23 0xf241 1744 #define F367TER_KDIV23_MANUAL 0xf2410080 1745 #define F367TER_K_DIVIDER_23 0xf241007f 1746 1747 /* KDIV34 */ 1748 #define R367TER_KDIV34 0xf242 1749 #define F367TER_KDIV34_MANUAL 0xf2420080 1750 #define F367TER_K_DIVIDER_34 0xf242007f 1751 1752 /* KDIV56 */ 1753 #define R367TER_KDIV56 0xf243 1754 #define F367TER_KDIV56_MANUAL 0xf2430080 1755 #define F367TER_K_DIVIDER_56 0xf243007f 1756 1757 /* KDIV67 */ 1758 #define R367TER_KDIV67 0xf244 1759 #define F367TER_KDIV67_MANUAL 0xf2440080 1760 #define F367TER_K_DIVIDER_67 0xf244007f 1761 1762 /* KDIV78 */ 1763 #define R367TER_KDIV78 0xf245 1764 #define F367TER_KDIV78_MANUAL 0xf2450080 1765 #define F367TER_K_DIVIDER_78 0xf245007f 1766 1767 /* SIGPOWER */ 1768 #define R367TER_SIGPOWER 0xf246 1769 #define F367TER_SIGPOWER_MANUAL 0xf2460080 1770 #define F367TER_SIG_POWER 0xf246007f 1771 1772 /* DEMAPVIT */ 1773 #define R367TER_DEMAPVIT 0xf247 1774 #define F367TER_DEMAPVIT_7 0xf2470080 1775 #define F367TER_K_DIVIDER_VIT 0xf247007f 1776 1777 /* VITSCALE */ 1778 #define R367TER_VITSCALE 0xf248 1779 #define F367TER_NVTH_NOSRANGE 0xf2480080 1780 #define F367TER_VERROR_MAXMODE 0xf2480040 1781 #define F367TER_KDIV_MODE 0xf2480030 1782 #define F367TER_NSLOWSN_LOCKED 0xf2480008 1783 #define F367TER_DELOCK_PRFLOSS 0xf2480004 1784 #define F367TER_DIS_RSFLOCK 0xf2480002 1785 #define F367TER_VITSCALE_0 0xf2480001 1786 1787 /* FFEC1PRG */ 1788 #define R367TER_FFEC1PRG 0xf249 1789 #define F367TER_FDSS_DVB 0xf2490080 1790 #define F367TER_FDSS_SRCH 0xf2490040 1791 #define F367TER_FFECPROG_5 0xf2490020 1792 #define F367TER_FFECPROG_4 0xf2490010 1793 #define F367TER_FFECPROG_3 0xf2490008 1794 #define F367TER_FFECPROG_2 0xf2490004 1795 #define F367TER_FTS1_DISABLE 0xf2490002 1796 #define F367TER_FTS2_DISABLE 0xf2490001 1797 1798 /* FVITCURPUN */ 1799 #define R367TER_FVITCURPUN 0xf24a 1800 #define F367TER_FVIT_MAPPING 0xf24a00e0 1801 #define F367TER_FVIT_CURPUN 0xf24a001f 1802 1803 /* FVERROR */ 1804 #define R367TER_FVERROR 0xf24b 1805 #define F367TER_FREGERR_VIT 0xf24b00ff 1806 1807 /* FVSTATUSVIT */ 1808 #define R367TER_FVSTATUSVIT 0xf24c 1809 #define F367TER_FVITERBI_ON 0xf24c0080 1810 #define F367TER_F1END_LOOPVIT 0xf24c0040 1811 #define F367TER_FVITERBI_DEPRF 0xf24c0020 1812 #define F367TER_FPRFVIT 0xf24c0010 1813 #define F367TER_FLOCKEDVIT 0xf24c0008 1814 #define F367TER_FVITERBI_DELOCK 0xf24c0004 1815 #define F367TER_FVIT_DEMODSEL 0xf24c0002 1816 #define F367TER_FVITERBI_COMPOUT 0xf24c0001 1817 1818 /* DEBUG_LT1 */ 1819 #define R367TER_DEBUG_LT1 0xf24d 1820 #define F367TER_DBG_LT1 0xf24d00ff 1821 1822 /* DEBUG_LT2 */ 1823 #define R367TER_DEBUG_LT2 0xf24e 1824 #define F367TER_DBG_LT2 0xf24e00ff 1825 1826 /* DEBUG_LT3 */ 1827 #define R367TER_DEBUG_LT3 0xf24f 1828 #define F367TER_DBG_LT3 0xf24f00ff 1829 1830 /* TSTSFMET */ 1831 #define R367TER_TSTSFMET 0xf250 1832 #define F367TER_TSTSFEC_METRIQUES 0xf25000ff 1833 1834 /* SELOUT */ 1835 #define R367TER_SELOUT 0xf252 1836 #define F367TER_EN_SYNC 0xf2520080 1837 #define F367TER_EN_TBUSDEMAP 0xf2520040 1838 #define F367TER_SELOUT_5 0xf2520020 1839 #define F367TER_SELOUT_4 0xf2520010 1840 #define F367TER_TSTSYNCHRO_MODE 0xf2520002 1841 1842 /* TSYNC */ 1843 #define R367TER_TSYNC 0xf253 1844 #define F367TER_CURPUN_INCMODE 0xf2530080 1845 #define F367TER_CERR_TSTMODE 0xf2530040 1846 #define F367TER_SHIFTSOF_MODE 0xf2530030 1847 #define F367TER_SLOWPHA_MODE 0xf2530008 1848 #define F367TER_PXX_BYPALL 0xf2530004 1849 #define F367TER_FROTA45_FIRST 0xf2530002 1850 #define F367TER_TST_BCHERROR 0xf2530001 1851 1852 /* TSTERR */ 1853 #define R367TER_TSTERR 0xf254 1854 #define F367TER_TST_LONGPKT 0xf2540080 1855 #define F367TER_TST_ISSYION 0xf2540040 1856 #define F367TER_TST_NPDON 0xf2540020 1857 #define F367TER_TSTERR_4 0xf2540010 1858 #define F367TER_TRACEBACK_MODE 0xf2540008 1859 #define F367TER_TST_RSPARITY 0xf2540004 1860 #define F367TER_METRIQUE_MODE 0xf2540003 1861 1862 /* TSFSYNC */ 1863 #define R367TER_TSFSYNC 0xf255 1864 #define F367TER_EN_SFECSYNC 0xf2550080 1865 #define F367TER_EN_SFECDEMAP 0xf2550040 1866 #define F367TER_SFCERR_TSTMODE 0xf2550020 1867 #define F367TER_SFECPXX_BYPALL 0xf2550010 1868 #define F367TER_SFECTSTSYNCHRO_MODE 0xf255000f 1869 1870 /* TSTSFERR */ 1871 #define R367TER_TSTSFERR 0xf256 1872 #define F367TER_TSTSTERR_7 0xf2560080 1873 #define F367TER_TSTSTERR_6 0xf2560040 1874 #define F367TER_TSTSTERR_5 0xf2560020 1875 #define F367TER_TSTSTERR_4 0xf2560010 1876 #define F367TER_SFECTRACEBACK_MODE 0xf2560008 1877 #define F367TER_SFEC_NCONVPROG 0xf2560004 1878 #define F367TER_SFECMETRIQUE_MODE 0xf2560003 1879 1880 /* TSTTSSF1 */ 1881 #define R367TER_TSTTSSF1 0xf258 1882 #define F367TER_TSTERSSF 0xf2580080 1883 #define F367TER_TSTTSSFEN 0xf2580040 1884 #define F367TER_SFEC_OUTMODE 0xf2580030 1885 #define F367TER_XLSF_NOFTHRESHOLD 0xf2580008 1886 #define F367TER_TSTTSSF_STACKSEL 0xf2580007 1887 1888 /* TSTTSSF2 */ 1889 #define R367TER_TSTTSSF2 0xf259 1890 #define F367TER_DILSF_DBBHEADER 0xf2590080 1891 #define F367TER_TSTTSSF_DISBUG 0xf2590040 1892 #define F367TER_TSTTSSF_NOBADSTART 0xf2590020 1893 #define F367TER_TSTTSSF_SELECT 0xf259001f 1894 1895 /* TSTTSSF3 */ 1896 #define R367TER_TSTTSSF3 0xf25a 1897 #define F367TER_TSTTSSF3_7 0xf25a0080 1898 #define F367TER_TSTTSSF3_6 0xf25a0040 1899 #define F367TER_TSTTSSF3_5 0xf25a0020 1900 #define F367TER_TSTTSSF3_4 0xf25a0010 1901 #define F367TER_TSTTSSF3_3 0xf25a0008 1902 #define F367TER_TSTTSSF3_2 0xf25a0004 1903 #define F367TER_TSTTSSF3_1 0xf25a0002 1904 #define F367TER_DISSF_CLKENABLE 0xf25a0001 1905 1906 /* TSTTS1 */ 1907 #define R367TER_TSTTS1 0xf25c 1908 #define F367TER_TSTERS 0xf25c0080 1909 #define F367TER_TSFIFO_DSSSYNCB 0xf25c0040 1910 #define F367TER_TSTTS_FSPYBEFRS 0xf25c0020 1911 #define F367TER_NFORCE_SYNCBYTE 0xf25c0010 1912 #define F367TER_XL_NOFTHRESHOLD 0xf25c0008 1913 #define F367TER_TSTTS_FRFORCEPKT 0xf25c0004 1914 #define F367TER_DESCR_NOTAUTO 0xf25c0002 1915 #define F367TER_TSTTSEN 0xf25c0001 1916 1917 /* TSTTS2 */ 1918 #define R367TER_TSTTS2 0xf25d 1919 #define F367TER_DIL_DBBHEADER 0xf25d0080 1920 #define F367TER_TSTTS_NOBADXXX 0xf25d0040 1921 #define F367TER_TSFIFO_DELSPEEDUP 0xf25d0020 1922 #define F367TER_TSTTS_SELECT 0xf25d001f 1923 1924 /* TSTTS3 */ 1925 #define R367TER_TSTTS3 0xf25e 1926 #define F367TER_TSTTS_NOPKTGAIN 0xf25e0080 1927 #define F367TER_TSTTS_NOPKTENE 0xf25e0040 1928 #define F367TER_TSTTS_ISOLATION 0xf25e0020 1929 #define F367TER_TSTTS_DISBUG 0xf25e0010 1930 #define F367TER_TSTTS_NOBADSTART 0xf25e0008 1931 #define F367TER_TSTTS_STACKSEL 0xf25e0007 1932 1933 /* TSTTS4 */ 1934 #define R367TER_TSTTS4 0xf25f 1935 #define F367TER_TSTTS4_7 0xf25f0080 1936 #define F367TER_TSTTS4_6 0xf25f0040 1937 #define F367TER_TSTTS4_5 0xf25f0020 1938 #define F367TER_TSTTS_DISDSTATE 0xf25f0010 1939 #define F367TER_TSTTS_FASTNOSYNC 0xf25f0008 1940 #define F367TER_EXT_FECSPYIN 0xf25f0004 1941 #define F367TER_TSTTS_NODPZERO 0xf25f0002 1942 #define F367TER_TSTTS_NODIV3 0xf25f0001 1943 1944 /* TSTTSRC */ 1945 #define R367TER_TSTTSRC 0xf26c 1946 #define F367TER_TSTTSRC_7 0xf26c0080 1947 #define F367TER_TSRCFIFO_DSSSYNCB 0xf26c0040 1948 #define F367TER_TSRCFIFO_DPUNACTIVE 0xf26c0020 1949 #define F367TER_TSRCFIFO_DELSPEEDUP 0xf26c0010 1950 #define F367TER_TSTTSRC_NODIV3 0xf26c0008 1951 #define F367TER_TSTTSRC_FRFORCEPKT 0xf26c0004 1952 #define F367TER_SAT25_SDDORIGINE 0xf26c0002 1953 #define F367TER_TSTTSRC_INACTIVE 0xf26c0001 1954 1955 /* TSTTSRS */ 1956 #define R367TER_TSTTSRS 0xf26d 1957 #define F367TER_TSTTSRS_7 0xf26d0080 1958 #define F367TER_TSTTSRS_6 0xf26d0040 1959 #define F367TER_TSTTSRS_5 0xf26d0020 1960 #define F367TER_TSTTSRS_4 0xf26d0010 1961 #define F367TER_TSTTSRS_3 0xf26d0008 1962 #define F367TER_TSTTSRS_2 0xf26d0004 1963 #define F367TER_TSTRS_DISRS2 0xf26d0002 1964 #define F367TER_TSTRS_DISRS1 0xf26d0001 1965 1966 /* TSSTATEM */ 1967 #define R367TER_TSSTATEM 0xf270 1968 #define F367TER_TSDIL_ON 0xf2700080 1969 #define F367TER_TSSKIPRS_ON 0xf2700040 1970 #define F367TER_TSRS_ON 0xf2700020 1971 #define F367TER_TSDESCRAMB_ON 0xf2700010 1972 #define F367TER_TSFRAME_MODE 0xf2700008 1973 #define F367TER_TS_DISABLE 0xf2700004 1974 #define F367TER_TSACM_MODE 0xf2700002 1975 #define F367TER_TSOUT_NOSYNC 0xf2700001 1976 1977 /* TSSTATEL */ 1978 #define R367TER_TSSTATEL 0xf271 1979 #define F367TER_TSNOSYNCBYTE 0xf2710080 1980 #define F367TER_TSPARITY_ON 0xf2710040 1981 #define F367TER_TSSYNCOUTRS_ON 0xf2710020 1982 #define F367TER_TSDVBS2_MODE 0xf2710010 1983 #define F367TER_TSISSYI_ON 0xf2710008 1984 #define F367TER_TSNPD_ON 0xf2710004 1985 #define F367TER_TSCRC8_ON 0xf2710002 1986 #define F367TER_TSDSS_PACKET 0xf2710001 1987 1988 /* TSCFGH */ 1989 #define R367TER_TSCFGH 0xf272 1990 #define F367TER_TSFIFO_DVBCI 0xf2720080 1991 #define F367TER_TSFIFO_SERIAL 0xf2720040 1992 #define F367TER_TSFIFO_TEIUPDATE 0xf2720020 1993 #define F367TER_TSFIFO_DUTY50 0xf2720010 1994 #define F367TER_TSFIFO_HSGNLOUT 0xf2720008 1995 #define F367TER_TSFIFO_ERRMODE 0xf2720006 1996 #define F367TER_RST_HWARE 0xf2720001 1997 1998 /* TSCFGM */ 1999 #define R367TER_TSCFGM 0xf273 2000 #define F367TER_TSFIFO_MANSPEED 0xf27300c0 2001 #define F367TER_TSFIFO_PERMDATA 0xf2730020 2002 #define F367TER_TSFIFO_NONEWSGNL 0xf2730010 2003 #define F367TER_TSFIFO_BITSPEED 0xf2730008 2004 #define F367TER_NPD_SPECDVBS2 0xf2730004 2005 #define F367TER_TSFIFO_STOPCKDIS 0xf2730002 2006 #define F367TER_TSFIFO_INVDATA 0xf2730001 2007 2008 /* TSCFGL */ 2009 #define R367TER_TSCFGL 0xf274 2010 #define F367TER_TSFIFO_BCLKDEL1cK 0xf27400c0 2011 #define F367TER_BCHERROR_MODE 0xf2740030 2012 #define F367TER_TSFIFO_NSGNL2dATA 0xf2740008 2013 #define F367TER_TSFIFO_EMBINDVB 0xf2740004 2014 #define F367TER_TSFIFO_DPUNACT 0xf2740002 2015 #define F367TER_TSFIFO_NPDOFF 0xf2740001 2016 2017 /* TSSYNC */ 2018 #define R367TER_TSSYNC 0xf275 2019 #define F367TER_TSFIFO_PERMUTE 0xf2750080 2020 #define F367TER_TSFIFO_FISCR3B 0xf2750060 2021 #define F367TER_TSFIFO_SYNCMODE 0xf2750018 2022 #define F367TER_TSFIFO_SYNCSEL 0xf2750007 2023 2024 /* TSINSDELH */ 2025 #define R367TER_TSINSDELH 0xf276 2026 #define F367TER_TSDEL_SYNCBYTE 0xf2760080 2027 #define F367TER_TSDEL_XXHEADER 0xf2760040 2028 #define F367TER_TSDEL_BBHEADER 0xf2760020 2029 #define F367TER_TSDEL_DATAFIELD 0xf2760010 2030 #define F367TER_TSINSDEL_ISCR 0xf2760008 2031 #define F367TER_TSINSDEL_NPD 0xf2760004 2032 #define F367TER_TSINSDEL_RSPARITY 0xf2760002 2033 #define F367TER_TSINSDEL_CRC8 0xf2760001 2034 2035 /* TSINSDELM */ 2036 #define R367TER_TSINSDELM 0xf277 2037 #define F367TER_TSINS_BBPADDING 0xf2770080 2038 #define F367TER_TSINS_BCHFEC 0xf2770040 2039 #define F367TER_TSINS_LDPCFEC 0xf2770020 2040 #define F367TER_TSINS_EMODCOD 0xf2770010 2041 #define F367TER_TSINS_TOKEN 0xf2770008 2042 #define F367TER_TSINS_XXXERR 0xf2770004 2043 #define F367TER_TSINS_MATYPE 0xf2770002 2044 #define F367TER_TSINS_UPL 0xf2770001 2045 2046 /* TSINSDELL */ 2047 #define R367TER_TSINSDELL 0xf278 2048 #define F367TER_TSINS_DFL 0xf2780080 2049 #define F367TER_TSINS_SYNCD 0xf2780040 2050 #define F367TER_TSINS_BLOCLEN 0xf2780020 2051 #define F367TER_TSINS_SIGPCOUNT 0xf2780010 2052 #define F367TER_TSINS_FIFO 0xf2780008 2053 #define F367TER_TSINS_REALPACK 0xf2780004 2054 #define F367TER_TSINS_TSCONFIG 0xf2780002 2055 #define F367TER_TSINS_LATENCY 0xf2780001 2056 2057 /* TSDIVN */ 2058 #define R367TER_TSDIVN 0xf279 2059 #define F367TER_TSFIFO_LOWSPEED 0xf2790080 2060 #define F367TER_BYTE_OVERSAMPLING 0xf2790070 2061 #define F367TER_TSMANUAL_PACKETNBR 0xf279000f 2062 2063 /* TSDIVPM */ 2064 #define R367TER_TSDIVPM 0xf27a 2065 #define F367TER_TSMANUAL_P_HI 0xf27a00ff 2066 2067 /* TSDIVPL */ 2068 #define R367TER_TSDIVPL 0xf27b 2069 #define F367TER_TSMANUAL_P_LO 0xf27b00ff 2070 2071 /* TSDIVQM */ 2072 #define R367TER_TSDIVQM 0xf27c 2073 #define F367TER_TSMANUAL_Q_HI 0xf27c00ff 2074 2075 /* TSDIVQL */ 2076 #define R367TER_TSDIVQL 0xf27d 2077 #define F367TER_TSMANUAL_Q_LO 0xf27d00ff 2078 2079 /* TSDILSTKM */ 2080 #define R367TER_TSDILSTKM 0xf27e 2081 #define F367TER_TSFIFO_DILSTK_HI 0xf27e00ff 2082 2083 /* TSDILSTKL */ 2084 #define R367TER_TSDILSTKL 0xf27f 2085 #define F367TER_TSFIFO_DILSTK_LO 0xf27f00ff 2086 2087 /* TSSPEED */ 2088 #define R367TER_TSSPEED 0xf280 2089 #define F367TER_TSFIFO_OUTSPEED 0xf28000ff 2090 2091 /* TSSTATUS */ 2092 #define R367TER_TSSTATUS 0xf281 2093 #define F367TER_TSFIFO_LINEOK 0xf2810080 2094 #define F367TER_TSFIFO_ERROR 0xf2810040 2095 #define F367TER_TSFIFO_DATA7 0xf2810020 2096 #define F367TER_TSFIFO_NOSYNC 0xf2810010 2097 #define F367TER_ISCR_INITIALIZED 0xf2810008 2098 #define F367TER_ISCR_UPDATED 0xf2810004 2099 #define F367TER_SOFFIFO_UNREGUL 0xf2810002 2100 #define F367TER_DIL_READY 0xf2810001 2101 2102 /* TSSTATUS2 */ 2103 #define R367TER_TSSTATUS2 0xf282 2104 #define F367TER_TSFIFO_DEMODSEL 0xf2820080 2105 #define F367TER_TSFIFOSPEED_STORE 0xf2820040 2106 #define F367TER_DILXX_RESET 0xf2820020 2107 #define F367TER_TSSERIAL_IMPOSSIBLE 0xf2820010 2108 #define F367TER_TSFIFO_UNDERSPEED 0xf2820008 2109 #define F367TER_BITSPEED_EVENT 0xf2820004 2110 #define F367TER_UL_SCRAMBDETECT 0xf2820002 2111 #define F367TER_ULDTV67_FALSELOCK 0xf2820001 2112 2113 /* TSBITRATEM */ 2114 #define R367TER_TSBITRATEM 0xf283 2115 #define F367TER_TSFIFO_BITRATE_HI 0xf28300ff 2116 2117 /* TSBITRATEL */ 2118 #define R367TER_TSBITRATEL 0xf284 2119 #define F367TER_TSFIFO_BITRATE_LO 0xf28400ff 2120 2121 /* TSPACKLENM */ 2122 #define R367TER_TSPACKLENM 0xf285 2123 #define F367TER_TSFIFO_PACKCPT 0xf28500e0 2124 #define F367TER_DIL_RPLEN_HI 0xf285001f 2125 2126 /* TSPACKLENL */ 2127 #define R367TER_TSPACKLENL 0xf286 2128 #define F367TER_DIL_RPLEN_LO 0xf28600ff 2129 2130 /* TSBLOCLENM */ 2131 #define R367TER_TSBLOCLENM 0xf287 2132 #define F367TER_TSFIFO_PFLEN_HI 0xf28700ff 2133 2134 /* TSBLOCLENL */ 2135 #define R367TER_TSBLOCLENL 0xf288 2136 #define F367TER_TSFIFO_PFLEN_LO 0xf28800ff 2137 2138 /* TSDLYH */ 2139 #define R367TER_TSDLYH 0xf289 2140 #define F367TER_SOFFIFO_TSTIMEVALID 0xf2890080 2141 #define F367TER_SOFFIFO_SPEEDUP 0xf2890040 2142 #define F367TER_SOFFIFO_STOP 0xf2890020 2143 #define F367TER_SOFFIFO_REGULATED 0xf2890010 2144 #define F367TER_SOFFIFO_REALSBOFF_HI 0xf289000f 2145 2146 /* TSDLYM */ 2147 #define R367TER_TSDLYM 0xf28a 2148 #define F367TER_SOFFIFO_REALSBOFF_MED 0xf28a00ff 2149 2150 /* TSDLYL */ 2151 #define R367TER_TSDLYL 0xf28b 2152 #define F367TER_SOFFIFO_REALSBOFF_LO 0xf28b00ff 2153 2154 /* TSNPDAV */ 2155 #define R367TER_TSNPDAV 0xf28c 2156 #define F367TER_TSNPD_AVERAGE 0xf28c00ff 2157 2158 /* TSBUFSTATH */ 2159 #define R367TER_TSBUFSTATH 0xf28d 2160 #define F367TER_TSISCR_3BYTES 0xf28d0080 2161 #define F367TER_TSISCR_NEWDATA 0xf28d0040 2162 #define F367TER_TSISCR_BUFSTAT_HI 0xf28d003f 2163 2164 /* TSBUFSTATM */ 2165 #define R367TER_TSBUFSTATM 0xf28e 2166 #define F367TER_TSISCR_BUFSTAT_MED 0xf28e00ff 2167 2168 /* TSBUFSTATL */ 2169 #define R367TER_TSBUFSTATL 0xf28f 2170 #define F367TER_TSISCR_BUFSTAT_LO 0xf28f00ff 2171 2172 /* TSDEBUGM */ 2173 #define R367TER_TSDEBUGM 0xf290 2174 #define F367TER_TSFIFO_ILLPACKET 0xf2900080 2175 #define F367TER_DIL_NOSYNC 0xf2900040 2176 #define F367TER_DIL_ISCR 0xf2900020 2177 #define F367TER_DILOUT_BSYNCB 0xf2900010 2178 #define F367TER_TSFIFO_EMPTYPKT 0xf2900008 2179 #define F367TER_TSFIFO_EMPTYRD 0xf2900004 2180 #define F367TER_SOFFIFO_STOPM 0xf2900002 2181 #define F367TER_SOFFIFO_SPEEDUPM 0xf2900001 2182 2183 /* TSDEBUGL */ 2184 #define R367TER_TSDEBUGL 0xf291 2185 #define F367TER_TSFIFO_PACKLENFAIL 0xf2910080 2186 #define F367TER_TSFIFO_SYNCBFAIL 0xf2910040 2187 #define F367TER_TSFIFO_VITLIBRE 0xf2910020 2188 #define F367TER_TSFIFO_BOOSTSPEEDM 0xf2910010 2189 #define F367TER_TSFIFO_UNDERSPEEDM 0xf2910008 2190 #define F367TER_TSFIFO_ERROR_EVNT 0xf2910004 2191 #define F367TER_TSFIFO_FULL 0xf2910002 2192 #define F367TER_TSFIFO_OVERFLOWM 0xf2910001 2193 2194 /* TSDLYSETH */ 2195 #define R367TER_TSDLYSETH 0xf292 2196 #define F367TER_SOFFIFO_OFFSET 0xf29200e0 2197 #define F367TER_SOFFIFO_SYMBOFFSET_HI 0xf292001f 2198 2199 /* TSDLYSETM */ 2200 #define R367TER_TSDLYSETM 0xf293 2201 #define F367TER_SOFFIFO_SYMBOFFSET_MED 0xf29300ff 2202 2203 /* TSDLYSETL */ 2204 #define R367TER_TSDLYSETL 0xf294 2205 #define F367TER_SOFFIFO_SYMBOFFSET_LO 0xf29400ff 2206 2207 /* TSOBSCFG */ 2208 #define R367TER_TSOBSCFG 0xf295 2209 #define F367TER_TSFIFO_OBSCFG 0xf29500ff 2210 2211 /* TSOBSM */ 2212 #define R367TER_TSOBSM 0xf296 2213 #define F367TER_TSFIFO_OBSDATA_HI 0xf29600ff 2214 2215 /* TSOBSL */ 2216 #define R367TER_TSOBSL 0xf297 2217 #define F367TER_TSFIFO_OBSDATA_LO 0xf29700ff 2218 2219 /* ERRCTRL1 */ 2220 #define R367TER_ERRCTRL1 0xf298 2221 #define F367TER_ERR_SRC1 0xf29800f0 2222 #define F367TER_ERRCTRL1_3 0xf2980008 2223 #define F367TER_NUM_EVT1 0xf2980007 2224 2225 /* ERRCNT1H */ 2226 #define R367TER_ERRCNT1H 0xf299 2227 #define F367TER_ERRCNT1_OLDVALUE 0xf2990080 2228 #define F367TER_ERR_CNT1 0xf299007f 2229 2230 /* ERRCNT1M */ 2231 #define R367TER_ERRCNT1M 0xf29a 2232 #define F367TER_ERR_CNT1_HI 0xf29a00ff 2233 2234 /* ERRCNT1L */ 2235 #define R367TER_ERRCNT1L 0xf29b 2236 #define F367TER_ERR_CNT1_LO 0xf29b00ff 2237 2238 /* ERRCTRL2 */ 2239 #define R367TER_ERRCTRL2 0xf29c 2240 #define F367TER_ERR_SRC2 0xf29c00f0 2241 #define F367TER_ERRCTRL2_3 0xf29c0008 2242 #define F367TER_NUM_EVT2 0xf29c0007 2243 2244 /* ERRCNT2H */ 2245 #define R367TER_ERRCNT2H 0xf29d 2246 #define F367TER_ERRCNT2_OLDVALUE 0xf29d0080 2247 #define F367TER_ERR_CNT2_HI 0xf29d007f 2248 2249 /* ERRCNT2M */ 2250 #define R367TER_ERRCNT2M 0xf29e 2251 #define F367TER_ERR_CNT2_MED 0xf29e00ff 2252 2253 /* ERRCNT2L */ 2254 #define R367TER_ERRCNT2L 0xf29f 2255 #define F367TER_ERR_CNT2_LO 0xf29f00ff 2256 2257 /* FECSPY */ 2258 #define R367TER_FECSPY 0xf2a0 2259 #define F367TER_SPY_ENABLE 0xf2a00080 2260 #define F367TER_NO_SYNCBYTE 0xf2a00040 2261 #define F367TER_SERIAL_MODE 0xf2a00020 2262 #define F367TER_UNUSUAL_PACKET 0xf2a00010 2263 #define F367TER_BERMETER_DATAMODE 0xf2a0000c 2264 #define F367TER_BERMETER_LMODE 0xf2a00002 2265 #define F367TER_BERMETER_RESET 0xf2a00001 2266 2267 /* FSPYCFG */ 2268 #define R367TER_FSPYCFG 0xf2a1 2269 #define F367TER_FECSPY_INPUT 0xf2a100c0 2270 #define F367TER_RST_ON_ERROR 0xf2a10020 2271 #define F367TER_ONE_SHOT 0xf2a10010 2272 #define F367TER_I2C_MOD 0xf2a1000c 2273 #define F367TER_SPY_HYSTERESIS 0xf2a10003 2274 2275 /* FSPYDATA */ 2276 #define R367TER_FSPYDATA 0xf2a2 2277 #define F367TER_SPY_STUFFING 0xf2a20080 2278 #define F367TER_NOERROR_PKTJITTER 0xf2a20040 2279 #define F367TER_SPY_CNULLPKT 0xf2a20020 2280 #define F367TER_SPY_OUTDATA_MODE 0xf2a2001f 2281 2282 /* FSPYOUT */ 2283 #define R367TER_FSPYOUT 0xf2a3 2284 #define F367TER_FSPY_DIRECT 0xf2a30080 2285 #define F367TER_FSPYOUT_6 0xf2a30040 2286 #define F367TER_SPY_OUTDATA_BUS 0xf2a30038 2287 #define F367TER_STUFF_MODE 0xf2a30007 2288 2289 /* FSTATUS */ 2290 #define R367TER_FSTATUS 0xf2a4 2291 #define F367TER_SPY_ENDSIM 0xf2a40080 2292 #define F367TER_VALID_SIM 0xf2a40040 2293 #define F367TER_FOUND_SIGNAL 0xf2a40020 2294 #define F367TER_DSS_SYNCBYTE 0xf2a40010 2295 #define F367TER_RESULT_STATE 0xf2a4000f 2296 2297 /* FGOODPACK */ 2298 #define R367TER_FGOODPACK 0xf2a5 2299 #define F367TER_FGOOD_PACKET 0xf2a500ff 2300 2301 /* FPACKCNT */ 2302 #define R367TER_FPACKCNT 0xf2a6 2303 #define F367TER_FPACKET_COUNTER 0xf2a600ff 2304 2305 /* FSPYMISC */ 2306 #define R367TER_FSPYMISC 0xf2a7 2307 #define F367TER_FLABEL_COUNTER 0xf2a700ff 2308 2309 /* FBERCPT4 */ 2310 #define R367TER_FBERCPT4 0xf2a8 2311 #define F367TER_FBERMETER_CPT5 0xf2a800ff 2312 2313 /* FBERCPT3 */ 2314 #define R367TER_FBERCPT3 0xf2a9 2315 #define F367TER_FBERMETER_CPT4 0xf2a900ff 2316 2317 /* FBERCPT2 */ 2318 #define R367TER_FBERCPT2 0xf2aa 2319 #define F367TER_FBERMETER_CPT3 0xf2aa00ff 2320 2321 /* FBERCPT1 */ 2322 #define R367TER_FBERCPT1 0xf2ab 2323 #define F367TER_FBERMETER_CPT2 0xf2ab00ff 2324 2325 /* FBERCPT0 */ 2326 #define R367TER_FBERCPT0 0xf2ac 2327 #define F367TER_FBERMETER_CPT1 0xf2ac00ff 2328 2329 /* FBERERR2 */ 2330 #define R367TER_FBERERR2 0xf2ad 2331 #define F367TER_FBERMETER_ERR_HI 0xf2ad00ff 2332 2333 /* FBERERR1 */ 2334 #define R367TER_FBERERR1 0xf2ae 2335 #define F367TER_FBERMETER_ERR_MED 0xf2ae00ff 2336 2337 /* FBERERR0 */ 2338 #define R367TER_FBERERR0 0xf2af 2339 #define F367TER_FBERMETER_ERR_LO 0xf2af00ff 2340 2341 /* FSTATESM */ 2342 #define R367TER_FSTATESM 0xf2b0 2343 #define F367TER_RSTATE_F 0xf2b00080 2344 #define F367TER_RSTATE_E 0xf2b00040 2345 #define F367TER_RSTATE_D 0xf2b00020 2346 #define F367TER_RSTATE_C 0xf2b00010 2347 #define F367TER_RSTATE_B 0xf2b00008 2348 #define F367TER_RSTATE_A 0xf2b00004 2349 #define F367TER_RSTATE_9 0xf2b00002 2350 #define F367TER_RSTATE_8 0xf2b00001 2351 2352 /* FSTATESL */ 2353 #define R367TER_FSTATESL 0xf2b1 2354 #define F367TER_RSTATE_7 0xf2b10080 2355 #define F367TER_RSTATE_6 0xf2b10040 2356 #define F367TER_RSTATE_5 0xf2b10020 2357 #define F367TER_RSTATE_4 0xf2b10010 2358 #define F367TER_RSTATE_3 0xf2b10008 2359 #define F367TER_RSTATE_2 0xf2b10004 2360 #define F367TER_RSTATE_1 0xf2b10002 2361 #define F367TER_RSTATE_0 0xf2b10001 2362 2363 /* FSPYBER */ 2364 #define R367TER_FSPYBER 0xf2b2 2365 #define F367TER_FSPYBER_7 0xf2b20080 2366 #define F367TER_FSPYOBS_XORREAD 0xf2b20040 2367 #define F367TER_FSPYBER_OBSMODE 0xf2b20020 2368 #define F367TER_FSPYBER_SYNCBYTE 0xf2b20010 2369 #define F367TER_FSPYBER_UNSYNC 0xf2b20008 2370 #define F367TER_FSPYBER_CTIME 0xf2b20007 2371 2372 /* FSPYDISTM */ 2373 #define R367TER_FSPYDISTM 0xf2b3 2374 #define F367TER_PKTTIME_DISTANCE_HI 0xf2b300ff 2375 2376 /* FSPYDISTL */ 2377 #define R367TER_FSPYDISTL 0xf2b4 2378 #define F367TER_PKTTIME_DISTANCE_LO 0xf2b400ff 2379 2380 /* FSPYOBS7 */ 2381 #define R367TER_FSPYOBS7 0xf2b8 2382 #define F367TER_FSPYOBS_SPYFAIL 0xf2b80080 2383 #define F367TER_FSPYOBS_SPYFAIL1 0xf2b80040 2384 #define F367TER_FSPYOBS_ERROR 0xf2b80020 2385 #define F367TER_FSPYOBS_STROUT 0xf2b80010 2386 #define F367TER_FSPYOBS_RESULTSTATE1 0xf2b8000f 2387 2388 /* FSPYOBS6 */ 2389 #define R367TER_FSPYOBS6 0xf2b9 2390 #define F367TER_FSPYOBS_RESULTSTATe0 0xf2b900f0 2391 #define F367TER_FSPYOBS_RESULTSTATEM1 0xf2b9000f 2392 2393 /* FSPYOBS5 */ 2394 #define R367TER_FSPYOBS5 0xf2ba 2395 #define F367TER_FSPYOBS_BYTEOFPACKET1 0xf2ba00ff 2396 2397 /* FSPYOBS4 */ 2398 #define R367TER_FSPYOBS4 0xf2bb 2399 #define F367TER_FSPYOBS_BYTEVALUE1 0xf2bb00ff 2400 2401 /* FSPYOBS3 */ 2402 #define R367TER_FSPYOBS3 0xf2bc 2403 #define F367TER_FSPYOBS_DATA1 0xf2bc00ff 2404 2405 /* FSPYOBS2 */ 2406 #define R367TER_FSPYOBS2 0xf2bd 2407 #define F367TER_FSPYOBS_DATa0 0xf2bd00ff 2408 2409 /* FSPYOBS1 */ 2410 #define R367TER_FSPYOBS1 0xf2be 2411 #define F367TER_FSPYOBS_DATAM1 0xf2be00ff 2412 2413 /* FSPYOBS0 */ 2414 #define R367TER_FSPYOBS0 0xf2bf 2415 #define F367TER_FSPYOBS_DATAM2 0xf2bf00ff 2416 2417 /* SFDEMAP */ 2418 #define R367TER_SFDEMAP 0xf2c0 2419 #define F367TER_SFDEMAP_7 0xf2c00080 2420 #define F367TER_SFEC_K_DIVIDER_VIT 0xf2c0007f 2421 2422 /* SFERROR */ 2423 #define R367TER_SFERROR 0xf2c1 2424 #define F367TER_SFEC_REGERR_VIT 0xf2c100ff 2425 2426 /* SFAVSR */ 2427 #define R367TER_SFAVSR 0xf2c2 2428 #define F367TER_SFEC_SUMERRORS 0xf2c20080 2429 #define F367TER_SERROR_MAXMODE 0xf2c20040 2430 #define F367TER_SN_SFEC 0xf2c20030 2431 #define F367TER_KDIV_MODE_SFEC 0xf2c2000c 2432 #define F367TER_SFAVSR_1 0xf2c20002 2433 #define F367TER_SFAVSR_0 0xf2c20001 2434 2435 /* SFECSTATUS */ 2436 #define R367TER_SFECSTATUS 0xf2c3 2437 #define F367TER_SFEC_ON 0xf2c30080 2438 #define F367TER_SFSTATUS_6 0xf2c30040 2439 #define F367TER_SFSTATUS_5 0xf2c30020 2440 #define F367TER_SFSTATUS_4 0xf2c30010 2441 #define F367TER_LOCKEDSFEC 0xf2c30008 2442 #define F367TER_SFEC_DELOCK 0xf2c30004 2443 #define F367TER_SFEC_DEMODSEL1 0xf2c30002 2444 #define F367TER_SFEC_OVFON 0xf2c30001 2445 2446 /* SFKDIV12 */ 2447 #define R367TER_SFKDIV12 0xf2c4 2448 #define F367TER_SFECKDIV12_MAN 0xf2c40080 2449 #define F367TER_SFEC_K_DIVIDER_12 0xf2c4007f 2450 2451 /* SFKDIV23 */ 2452 #define R367TER_SFKDIV23 0xf2c5 2453 #define F367TER_SFECKDIV23_MAN 0xf2c50080 2454 #define F367TER_SFEC_K_DIVIDER_23 0xf2c5007f 2455 2456 /* SFKDIV34 */ 2457 #define R367TER_SFKDIV34 0xf2c6 2458 #define F367TER_SFECKDIV34_MAN 0xf2c60080 2459 #define F367TER_SFEC_K_DIVIDER_34 0xf2c6007f 2460 2461 /* SFKDIV56 */ 2462 #define R367TER_SFKDIV56 0xf2c7 2463 #define F367TER_SFECKDIV56_MAN 0xf2c70080 2464 #define F367TER_SFEC_K_DIVIDER_56 0xf2c7007f 2465 2466 /* SFKDIV67 */ 2467 #define R367TER_SFKDIV67 0xf2c8 2468 #define F367TER_SFECKDIV67_MAN 0xf2c80080 2469 #define F367TER_SFEC_K_DIVIDER_67 0xf2c8007f 2470 2471 /* SFKDIV78 */ 2472 #define R367TER_SFKDIV78 0xf2c9 2473 #define F367TER_SFECKDIV78_MAN 0xf2c90080 2474 #define F367TER_SFEC_K_DIVIDER_78 0xf2c9007f 2475 2476 /* SFDILSTKM */ 2477 #define R367TER_SFDILSTKM 0xf2ca 2478 #define F367TER_SFEC_PACKCPT 0xf2ca00e0 2479 #define F367TER_SFEC_DILSTK_HI 0xf2ca001f 2480 2481 /* SFDILSTKL */ 2482 #define R367TER_SFDILSTKL 0xf2cb 2483 #define F367TER_SFEC_DILSTK_LO 0xf2cb00ff 2484 2485 /* SFSTATUS */ 2486 #define R367TER_SFSTATUS 0xf2cc 2487 #define F367TER_SFEC_LINEOK 0xf2cc0080 2488 #define F367TER_SFEC_ERROR 0xf2cc0040 2489 #define F367TER_SFEC_DATA7 0xf2cc0020 2490 #define F367TER_SFEC_OVERFLOW 0xf2cc0010 2491 #define F367TER_SFEC_DEMODSEL2 0xf2cc0008 2492 #define F367TER_SFEC_NOSYNC 0xf2cc0004 2493 #define F367TER_SFEC_UNREGULA 0xf2cc0002 2494 #define F367TER_SFEC_READY 0xf2cc0001 2495 2496 /* SFDLYH */ 2497 #define R367TER_SFDLYH 0xf2cd 2498 #define F367TER_SFEC_TSTIMEVALID 0xf2cd0080 2499 #define F367TER_SFEC_SPEEDUP 0xf2cd0040 2500 #define F367TER_SFEC_STOP 0xf2cd0020 2501 #define F367TER_SFEC_REGULATED 0xf2cd0010 2502 #define F367TER_SFEC_REALSYMBOFFSET 0xf2cd000f 2503 2504 /* SFDLYM */ 2505 #define R367TER_SFDLYM 0xf2ce 2506 #define F367TER_SFEC_REALSYMBOFFSET_HI 0xf2ce00ff 2507 2508 /* SFDLYL */ 2509 #define R367TER_SFDLYL 0xf2cf 2510 #define F367TER_SFEC_REALSYMBOFFSET_LO 0xf2cf00ff 2511 2512 /* SFDLYSETH */ 2513 #define R367TER_SFDLYSETH 0xf2d0 2514 #define F367TER_SFEC_OFFSET 0xf2d000e0 2515 #define F367TER_SFECDLYSETH_4 0xf2d00010 2516 #define F367TER_RST_SFEC 0xf2d00008 2517 #define F367TER_SFECDLYSETH_2 0xf2d00004 2518 #define F367TER_SFEC_DISABLE 0xf2d00002 2519 #define F367TER_SFEC_UNREGUL 0xf2d00001 2520 2521 /* SFDLYSETM */ 2522 #define R367TER_SFDLYSETM 0xf2d1 2523 #define F367TER_SFECDLYSETM_7 0xf2d10080 2524 #define F367TER_SFEC_SYMBOFFSET_HI 0xf2d1007f 2525 2526 /* SFDLYSETL */ 2527 #define R367TER_SFDLYSETL 0xf2d2 2528 #define F367TER_SFEC_SYMBOFFSET_LO 0xf2d200ff 2529 2530 /* SFOBSCFG */ 2531 #define R367TER_SFOBSCFG 0xf2d3 2532 #define F367TER_SFEC_OBSCFG 0xf2d300ff 2533 2534 /* SFOBSM */ 2535 #define R367TER_SFOBSM 0xf2d4 2536 #define F367TER_SFEC_OBSDATA_HI 0xf2d400ff 2537 2538 /* SFOBSL */ 2539 #define R367TER_SFOBSL 0xf2d5 2540 #define F367TER_SFEC_OBSDATA_LO 0xf2d500ff 2541 2542 /* SFECINFO */ 2543 #define R367TER_SFECINFO 0xf2d6 2544 #define F367TER_SFECINFO_7 0xf2d60080 2545 #define F367TER_SFEC_SYNCDLSB 0xf2d60070 2546 #define F367TER_SFCE_S1cPHASE 0xf2d6000f 2547 2548 /* SFERRCTRL */ 2549 #define R367TER_SFERRCTRL 0xf2d8 2550 #define F367TER_SFEC_ERR_SOURCE 0xf2d800f0 2551 #define F367TER_SFERRCTRL_3 0xf2d80008 2552 #define F367TER_SFEC_NUM_EVENT 0xf2d80007 2553 2554 /* SFERRCNTH */ 2555 #define R367TER_SFERRCNTH 0xf2d9 2556 #define F367TER_SFERRC_OLDVALUE 0xf2d90080 2557 #define F367TER_SFEC_ERR_CNT 0xf2d9007f 2558 2559 /* SFERRCNTM */ 2560 #define R367TER_SFERRCNTM 0xf2da 2561 #define F367TER_SFEC_ERR_CNT_HI 0xf2da00ff 2562 2563 /* SFERRCNTL */ 2564 #define R367TER_SFERRCNTL 0xf2db 2565 #define F367TER_SFEC_ERR_CNT_LO 0xf2db00ff 2566 2567 /* SYMBRATEM */ 2568 #define R367TER_SYMBRATEM 0xf2e0 2569 #define F367TER_DEFGEN_SYMBRATE_HI 0xf2e000ff 2570 2571 /* SYMBRATEL */ 2572 #define R367TER_SYMBRATEL 0xf2e1 2573 #define F367TER_DEFGEN_SYMBRATE_LO 0xf2e100ff 2574 2575 /* SYMBSTATUS */ 2576 #define R367TER_SYMBSTATUS 0xf2e2 2577 #define F367TER_SYMBDLINE2_OFF 0xf2e20080 2578 #define F367TER_SDDL_REINIT1 0xf2e20040 2579 #define F367TER_SDD_REINIT1 0xf2e20020 2580 #define F367TER_TOKENID_ERROR 0xf2e20010 2581 #define F367TER_SYMBRATE_OVERFLOW 0xf2e20008 2582 #define F367TER_SYMBRATE_UNDERFLOW 0xf2e20004 2583 #define F367TER_TOKENID_RSTEVENT 0xf2e20002 2584 #define F367TER_TOKENID_RESET1 0xf2e20001 2585 2586 /* SYMBCFG */ 2587 #define R367TER_SYMBCFG 0xf2e3 2588 #define F367TER_SYMBCFG_7 0xf2e30080 2589 #define F367TER_SYMBCFG_6 0xf2e30040 2590 #define F367TER_SYMBCFG_5 0xf2e30020 2591 #define F367TER_SYMBCFG_4 0xf2e30010 2592 #define F367TER_SYMRATE_FSPEED 0xf2e3000c 2593 #define F367TER_SYMRATE_SSPEED 0xf2e30003 2594 2595 /* SYMBFIFOM */ 2596 #define R367TER_SYMBFIFOM 0xf2e4 2597 #define F367TER_SYMBFIFOM_7 0xf2e40080 2598 #define F367TER_SYMBFIFOM_6 0xf2e40040 2599 #define F367TER_DEFGEN_SYMFIFO_HI 0xf2e4003f 2600 2601 /* SYMBFIFOL */ 2602 #define R367TER_SYMBFIFOL 0xf2e5 2603 #define F367TER_DEFGEN_SYMFIFO_LO 0xf2e500ff 2604 2605 /* SYMBOFFSM */ 2606 #define R367TER_SYMBOFFSM 0xf2e6 2607 #define F367TER_TOKENID_RESET2 0xf2e60080 2608 #define F367TER_SDDL_REINIT2 0xf2e60040 2609 #define F367TER_SDD_REINIT2 0xf2e60020 2610 #define F367TER_SYMBOFFSM_4 0xf2e60010 2611 #define F367TER_SYMBOFFSM_3 0xf2e60008 2612 #define F367TER_DEFGEN_SYMBOFFSET_HI 0xf2e60007 2613 2614 /* SYMBOFFSL */ 2615 #define R367TER_SYMBOFFSL 0xf2e7 2616 #define F367TER_DEFGEN_SYMBOFFSET_LO 0xf2e700ff 2617 2618 /* DEBUG_LT4 */ 2619 #define R367TER_DEBUG_LT4 0xf400 2620 #define F367TER_F_DEBUG_LT4 0xf40000ff 2621 2622 /* DEBUG_LT5 */ 2623 #define R367TER_DEBUG_LT5 0xf401 2624 #define F367TER_F_DEBUG_LT5 0xf40100ff 2625 2626 /* DEBUG_LT6 */ 2627 #define R367TER_DEBUG_LT6 0xf402 2628 #define F367TER_F_DEBUG_LT6 0xf40200ff 2629 2630 /* DEBUG_LT7 */ 2631 #define R367TER_DEBUG_LT7 0xf403 2632 #define F367TER_F_DEBUG_LT7 0xf40300ff 2633 2634 /* DEBUG_LT8 */ 2635 #define R367TER_DEBUG_LT8 0xf404 2636 #define F367TER_F_DEBUG_LT8 0xf40400ff 2637 2638 /* DEBUG_LT9 */ 2639 #define R367TER_DEBUG_LT9 0xf405 2640 #define F367TER_F_DEBUG_LT9 0xf40500ff 2641 2642 #define STV0367TER_NBREGS 445 2643 2644 /* ID */ 2645 #define R367CAB_ID 0xf000 2646 #define F367CAB_IDENTIFICATIONREGISTER 0xf00000ff 2647 2648 /* I2CRPT */ 2649 #define R367CAB_I2CRPT 0xf001 2650 #define F367CAB_I2CT_ON 0xf0010080 2651 #define F367CAB_ENARPT_LEVEL 0xf0010070 2652 #define F367CAB_SCLT_DELAY 0xf0010008 2653 #define F367CAB_SCLT_NOD 0xf0010004 2654 #define F367CAB_STOP_ENABLE 0xf0010002 2655 #define F367CAB_SDAT_NOD 0xf0010001 2656 2657 /* TOPCTRL */ 2658 #define R367CAB_TOPCTRL 0xf002 2659 #define F367CAB_STDBY 0xf0020080 2660 #define F367CAB_STDBY_CORE 0xf0020020 2661 #define F367CAB_QAM_COFDM 0xf0020010 2662 #define F367CAB_TS_DIS 0xf0020008 2663 #define F367CAB_DIR_CLK_216 0xf0020004 2664 2665 /* IOCFG0 */ 2666 #define R367CAB_IOCFG0 0xf003 2667 #define F367CAB_OP0_SD 0xf0030080 2668 #define F367CAB_OP0_VAL 0xf0030040 2669 #define F367CAB_OP0_OD 0xf0030020 2670 #define F367CAB_OP0_INV 0xf0030010 2671 #define F367CAB_OP0_DACVALUE_HI 0xf003000f 2672 2673 /* DAc0R */ 2674 #define R367CAB_DAC0R 0xf004 2675 #define F367CAB_OP0_DACVALUE_LO 0xf00400ff 2676 2677 /* IOCFG1 */ 2678 #define R367CAB_IOCFG1 0xf005 2679 #define F367CAB_IP0 0xf0050040 2680 #define F367CAB_OP1_OD 0xf0050020 2681 #define F367CAB_OP1_INV 0xf0050010 2682 #define F367CAB_OP1_DACVALUE_HI 0xf005000f 2683 2684 /* DAC1R */ 2685 #define R367CAB_DAC1R 0xf006 2686 #define F367CAB_OP1_DACVALUE_LO 0xf00600ff 2687 2688 /* IOCFG2 */ 2689 #define R367CAB_IOCFG2 0xf007 2690 #define F367CAB_OP2_LOCK_CONF 0xf00700e0 2691 #define F367CAB_OP2_OD 0xf0070010 2692 #define F367CAB_OP2_VAL 0xf0070008 2693 #define F367CAB_OP1_LOCK_CONF 0xf0070007 2694 2695 /* SDFR */ 2696 #define R367CAB_SDFR 0xf008 2697 #define F367CAB_OP0_FREQ 0xf00800f0 2698 #define F367CAB_OP1_FREQ 0xf008000f 2699 2700 /* AUX_CLK */ 2701 #define R367CAB_AUX_CLK 0xf00a 2702 #define F367CAB_AUXFEC_CTL 0xf00a00c0 2703 #define F367CAB_DIS_CKX4 0xf00a0020 2704 #define F367CAB_CKSEL 0xf00a0018 2705 #define F367CAB_CKDIV_PROG 0xf00a0006 2706 #define F367CAB_AUXCLK_ENA 0xf00a0001 2707 2708 /* FREESYS1 */ 2709 #define R367CAB_FREESYS1 0xf00b 2710 #define F367CAB_FREESYS_1 0xf00b00ff 2711 2712 /* FREESYS2 */ 2713 #define R367CAB_FREESYS2 0xf00c 2714 #define F367CAB_FREESYS_2 0xf00c00ff 2715 2716 /* FREESYS3 */ 2717 #define R367CAB_FREESYS3 0xf00d 2718 #define F367CAB_FREESYS_3 0xf00d00ff 2719 2720 /* GPIO_CFG */ 2721 #define R367CAB_GPIO_CFG 0xf00e 2722 #define F367CAB_GPIO7_OD 0xf00e0080 2723 #define F367CAB_GPIO7_CFG 0xf00e0040 2724 #define F367CAB_GPIO6_OD 0xf00e0020 2725 #define F367CAB_GPIO6_CFG 0xf00e0010 2726 #define F367CAB_GPIO5_OD 0xf00e0008 2727 #define F367CAB_GPIO5_CFG 0xf00e0004 2728 #define F367CAB_GPIO4_OD 0xf00e0002 2729 #define F367CAB_GPIO4_CFG 0xf00e0001 2730 2731 /* GPIO_CMD */ 2732 #define R367CAB_GPIO_CMD 0xf00f 2733 #define F367CAB_GPIO7_VAL 0xf00f0008 2734 #define F367CAB_GPIO6_VAL 0xf00f0004 2735 #define F367CAB_GPIO5_VAL 0xf00f0002 2736 #define F367CAB_GPIO4_VAL 0xf00f0001 2737 2738 /* TSTRES */ 2739 #define R367CAB_TSTRES 0xf0c0 2740 #define F367CAB_FRES_DISPLAY 0xf0c00080 2741 #define F367CAB_FRES_FIFO_AD 0xf0c00020 2742 #define F367CAB_FRESRS 0xf0c00010 2743 #define F367CAB_FRESACS 0xf0c00008 2744 #define F367CAB_FRESFEC 0xf0c00004 2745 #define F367CAB_FRES_PRIF 0xf0c00002 2746 #define F367CAB_FRESCORE 0xf0c00001 2747 2748 /* ANACTRL */ 2749 #define R367CAB_ANACTRL 0xf0c1 2750 #define F367CAB_BYPASS_XTAL 0xf0c10040 2751 #define F367CAB_BYPASS_PLLXN 0xf0c1000c 2752 #define F367CAB_DIS_PAD_OSC 0xf0c10002 2753 #define F367CAB_STDBY_PLLXN 0xf0c10001 2754 2755 /* TSTBUS */ 2756 #define R367CAB_TSTBUS 0xf0c2 2757 #define F367CAB_TS_BYTE_CLK_INV 0xf0c20080 2758 #define F367CAB_CFG_IP 0xf0c20070 2759 #define F367CAB_CFG_TST 0xf0c2000f 2760 2761 /* RF_AGC1 */ 2762 #define R367CAB_RF_AGC1 0xf0d4 2763 #define F367CAB_RF_AGC1_LEVEL_HI 0xf0d400ff 2764 2765 /* RF_AGC2 */ 2766 #define R367CAB_RF_AGC2 0xf0d5 2767 #define F367CAB_REF_ADGP 0xf0d50080 2768 #define F367CAB_STDBY_ADCGP 0xf0d50020 2769 #define F367CAB_RF_AGC1_LEVEL_LO 0xf0d50003 2770 2771 /* ANADIGCTRL */ 2772 #define R367CAB_ANADIGCTRL 0xf0d7 2773 #define F367CAB_SEL_CLKDEM 0xf0d70020 2774 #define F367CAB_EN_BUFFER_Q 0xf0d70010 2775 #define F367CAB_EN_BUFFER_I 0xf0d70008 2776 #define F367CAB_ADC_RIS_EGDE 0xf0d70004 2777 #define F367CAB_SGN_ADC 0xf0d70002 2778 #define F367CAB_SEL_AD12_SYNC 0xf0d70001 2779 2780 /* PLLMDIV */ 2781 #define R367CAB_PLLMDIV 0xf0d8 2782 #define F367CAB_PLL_MDIV 0xf0d800ff 2783 2784 /* PLLNDIV */ 2785 #define R367CAB_PLLNDIV 0xf0d9 2786 #define F367CAB_PLL_NDIV 0xf0d900ff 2787 2788 /* PLLSETUP */ 2789 #define R367CAB_PLLSETUP 0xf0da 2790 #define F367CAB_PLL_PDIV 0xf0da0070 2791 #define F367CAB_PLL_KDIV 0xf0da000f 2792 2793 /* DUAL_AD12 */ 2794 #define R367CAB_DUAL_AD12 0xf0db 2795 #define F367CAB_FS20M 0xf0db0020 2796 #define F367CAB_FS50M 0xf0db0010 2797 #define F367CAB_INMODe0 0xf0db0008 2798 #define F367CAB_POFFQ 0xf0db0004 2799 #define F367CAB_POFFI 0xf0db0002 2800 #define F367CAB_INMODE1 0xf0db0001 2801 2802 /* TSTBIST */ 2803 #define R367CAB_TSTBIST 0xf0dc 2804 #define F367CAB_TST_BYP_CLK 0xf0dc0080 2805 #define F367CAB_TST_GCLKENA_STD 0xf0dc0040 2806 #define F367CAB_TST_GCLKENA 0xf0dc0020 2807 #define F367CAB_TST_MEMBIST 0xf0dc001f 2808 2809 /* CTRL_1 */ 2810 #define R367CAB_CTRL_1 0xf402 2811 #define F367CAB_SOFT_RST 0xf4020080 2812 #define F367CAB_EQU_RST 0xf4020008 2813 #define F367CAB_CRL_RST 0xf4020004 2814 #define F367CAB_TRL_RST 0xf4020002 2815 #define F367CAB_AGC_RST 0xf4020001 2816 2817 /* CTRL_2 */ 2818 #define R367CAB_CTRL_2 0xf403 2819 #define F367CAB_DEINT_RST 0xf4030008 2820 #define F367CAB_RS_RST 0xf4030004 2821 2822 /* IT_STATUS1 */ 2823 #define R367CAB_IT_STATUS1 0xf408 2824 #define F367CAB_SWEEP_OUT 0xf4080080 2825 #define F367CAB_FSM_CRL 0xf4080040 2826 #define F367CAB_CRL_LOCK 0xf4080020 2827 #define F367CAB_MFSM 0xf4080010 2828 #define F367CAB_TRL_LOCK 0xf4080008 2829 #define F367CAB_TRL_AGC_LIMIT 0xf4080004 2830 #define F367CAB_ADJ_AGC_LOCK 0xf4080002 2831 #define F367CAB_AGC_QAM_LOCK 0xf4080001 2832 2833 /* IT_STATUS2 */ 2834 #define R367CAB_IT_STATUS2 0xf409 2835 #define F367CAB_TSMF_CNT 0xf4090080 2836 #define F367CAB_TSMF_EOF 0xf4090040 2837 #define F367CAB_TSMF_RDY 0xf4090020 2838 #define F367CAB_FEC_NOCORR 0xf4090010 2839 #define F367CAB_SYNCSTATE 0xf4090008 2840 #define F367CAB_DEINT_LOCK 0xf4090004 2841 #define F367CAB_FADDING_FRZ 0xf4090002 2842 #define F367CAB_TAPMON_ALARM 0xf4090001 2843 2844 /* IT_EN1 */ 2845 #define R367CAB_IT_EN1 0xf40a 2846 #define F367CAB_SWEEP_OUTE 0xf40a0080 2847 #define F367CAB_FSM_CRLE 0xf40a0040 2848 #define F367CAB_CRL_LOCKE 0xf40a0020 2849 #define F367CAB_MFSME 0xf40a0010 2850 #define F367CAB_TRL_LOCKE 0xf40a0008 2851 #define F367CAB_TRL_AGC_LIMITE 0xf40a0004 2852 #define F367CAB_ADJ_AGC_LOCKE 0xf40a0002 2853 #define F367CAB_AGC_LOCKE 0xf40a0001 2854 2855 /* IT_EN2 */ 2856 #define R367CAB_IT_EN2 0xf40b 2857 #define F367CAB_TSMF_CNTE 0xf40b0080 2858 #define F367CAB_TSMF_EOFE 0xf40b0040 2859 #define F367CAB_TSMF_RDYE 0xf40b0020 2860 #define F367CAB_FEC_NOCORRE 0xf40b0010 2861 #define F367CAB_SYNCSTATEE 0xf40b0008 2862 #define F367CAB_DEINT_LOCKE 0xf40b0004 2863 #define F367CAB_FADDING_FRZE 0xf40b0002 2864 #define F367CAB_TAPMON_ALARME 0xf40b0001 2865 2866 /* CTRL_STATUS */ 2867 #define R367CAB_CTRL_STATUS 0xf40c 2868 #define F367CAB_QAMFEC_LOCK 0xf40c0004 2869 #define F367CAB_TSMF_LOCK 0xf40c0002 2870 #define F367CAB_TSMF_ERROR 0xf40c0001 2871 2872 /* TEST_CTL */ 2873 #define R367CAB_TEST_CTL 0xf40f 2874 #define F367CAB_TST_BLK_SEL 0xf40f0060 2875 #define F367CAB_TST_BUS_SEL 0xf40f001f 2876 2877 /* AGC_CTL */ 2878 #define R367CAB_AGC_CTL 0xf410 2879 #define F367CAB_AGC_LCK_TH 0xf41000f0 2880 #define F367CAB_AGC_ACCUMRSTSEL 0xf4100007 2881 2882 /* AGC_IF_CFG */ 2883 #define R367CAB_AGC_IF_CFG 0xf411 2884 #define F367CAB_AGC_IF_BWSEL 0xf41100f0 2885 #define F367CAB_AGC_IF_FREEZE 0xf4110002 2886 2887 /* AGC_RF_CFG */ 2888 #define R367CAB_AGC_RF_CFG 0xf412 2889 #define F367CAB_AGC_RF_BWSEL 0xf4120070 2890 #define F367CAB_AGC_RF_FREEZE 0xf4120002 2891 2892 /* AGC_PWM_CFG */ 2893 #define R367CAB_AGC_PWM_CFG 0xf413 2894 #define F367CAB_AGC_RF_PWM_TST 0xf4130080 2895 #define F367CAB_AGC_RF_PWM_INV 0xf4130040 2896 #define F367CAB_AGC_IF_PWM_TST 0xf4130008 2897 #define F367CAB_AGC_IF_PWM_INV 0xf4130004 2898 #define F367CAB_AGC_PWM_CLKDIV 0xf4130003 2899 2900 /* AGC_PWR_REF_L */ 2901 #define R367CAB_AGC_PWR_REF_L 0xf414 2902 #define F367CAB_AGC_PWRREF_LO 0xf41400ff 2903 2904 /* AGC_PWR_REF_H */ 2905 #define R367CAB_AGC_PWR_REF_H 0xf415 2906 #define F367CAB_AGC_PWRREF_HI 0xf4150003 2907 2908 /* AGC_RF_TH_L */ 2909 #define R367CAB_AGC_RF_TH_L 0xf416 2910 #define F367CAB_AGC_RF_TH_LO 0xf41600ff 2911 2912 /* AGC_RF_TH_H */ 2913 #define R367CAB_AGC_RF_TH_H 0xf417 2914 #define F367CAB_AGC_RF_TH_HI 0xf417000f 2915 2916 /* AGC_IF_LTH_L */ 2917 #define R367CAB_AGC_IF_LTH_L 0xf418 2918 #define F367CAB_AGC_IF_THLO_LO 0xf41800ff 2919 2920 /* AGC_IF_LTH_H */ 2921 #define R367CAB_AGC_IF_LTH_H 0xf419 2922 #define F367CAB_AGC_IF_THLO_HI 0xf419000f 2923 2924 /* AGC_IF_HTH_L */ 2925 #define R367CAB_AGC_IF_HTH_L 0xf41a 2926 #define F367CAB_AGC_IF_THHI_LO 0xf41a00ff 2927 2928 /* AGC_IF_HTH_H */ 2929 #define R367CAB_AGC_IF_HTH_H 0xf41b 2930 #define F367CAB_AGC_IF_THHI_HI 0xf41b000f 2931 2932 /* AGC_PWR_RD_L */ 2933 #define R367CAB_AGC_PWR_RD_L 0xf41c 2934 #define F367CAB_AGC_PWR_WORD_LO 0xf41c00ff 2935 2936 /* AGC_PWR_RD_M */ 2937 #define R367CAB_AGC_PWR_RD_M 0xf41d 2938 #define F367CAB_AGC_PWR_WORD_ME 0xf41d00ff 2939 2940 /* AGC_PWR_RD_H */ 2941 #define R367CAB_AGC_PWR_RD_H 0xf41e 2942 #define F367CAB_AGC_PWR_WORD_HI 0xf41e0003 2943 2944 /* AGC_PWM_IFCMD_L */ 2945 #define R367CAB_AGC_PWM_IFCMD_L 0xf420 2946 #define F367CAB_AGC_IF_PWMCMD_LO 0xf42000ff 2947 2948 /* AGC_PWM_IFCMD_H */ 2949 #define R367CAB_AGC_PWM_IFCMD_H 0xf421 2950 #define F367CAB_AGC_IF_PWMCMD_HI 0xf421000f 2951 2952 /* AGC_PWM_RFCMD_L */ 2953 #define R367CAB_AGC_PWM_RFCMD_L 0xf422 2954 #define F367CAB_AGC_RF_PWMCMD_LO 0xf42200ff 2955 2956 /* AGC_PWM_RFCMD_H */ 2957 #define R367CAB_AGC_PWM_RFCMD_H 0xf423 2958 #define F367CAB_AGC_RF_PWMCMD_HI 0xf423000f 2959 2960 /* IQDEM_CFG */ 2961 #define R367CAB_IQDEM_CFG 0xf424 2962 #define F367CAB_IQDEM_CLK_SEL 0xf4240004 2963 #define F367CAB_IQDEM_INVIQ 0xf4240002 2964 #define F367CAB_IQDEM_A2dTYPE 0xf4240001 2965 2966 /* MIX_NCO_LL */ 2967 #define R367CAB_MIX_NCO_LL 0xf425 2968 #define F367CAB_MIX_NCO_INC_LL 0xf42500ff 2969 2970 /* MIX_NCO_HL */ 2971 #define R367CAB_MIX_NCO_HL 0xf426 2972 #define F367CAB_MIX_NCO_INC_HL 0xf42600ff 2973 2974 /* MIX_NCO_HH */ 2975 #define R367CAB_MIX_NCO_HH 0xf427 2976 #define F367CAB_MIX_NCO_INVCNST 0xf4270080 2977 #define F367CAB_MIX_NCO_INC_HH 0xf427007f 2978 2979 /* SRC_NCO_LL */ 2980 #define R367CAB_SRC_NCO_LL 0xf428 2981 #define F367CAB_SRC_NCO_INC_LL 0xf42800ff 2982 2983 /* SRC_NCO_LH */ 2984 #define R367CAB_SRC_NCO_LH 0xf429 2985 #define F367CAB_SRC_NCO_INC_LH 0xf42900ff 2986 2987 /* SRC_NCO_HL */ 2988 #define R367CAB_SRC_NCO_HL 0xf42a 2989 #define F367CAB_SRC_NCO_INC_HL 0xf42a00ff 2990 2991 /* SRC_NCO_HH */ 2992 #define R367CAB_SRC_NCO_HH 0xf42b 2993 #define F367CAB_SRC_NCO_INC_HH 0xf42b007f 2994 2995 /* IQDEM_GAIN_SRC_L */ 2996 #define R367CAB_IQDEM_GAIN_SRC_L 0xf42c 2997 #define F367CAB_GAIN_SRC_LO 0xf42c00ff 2998 2999 /* IQDEM_GAIN_SRC_H */ 3000 #define R367CAB_IQDEM_GAIN_SRC_H 0xf42d 3001 #define F367CAB_GAIN_SRC_HI 0xf42d0003 3002 3003 /* IQDEM_DCRM_CFG_LL */ 3004 #define R367CAB_IQDEM_DCRM_CFG_LL 0xf430 3005 #define F367CAB_DCRM0_DCIN_L 0xf43000ff 3006 3007 /* IQDEM_DCRM_CFG_LH */ 3008 #define R367CAB_IQDEM_DCRM_CFG_LH 0xf431 3009 #define F367CAB_DCRM1_I_DCIN_L 0xf43100fc 3010 #define F367CAB_DCRM0_DCIN_H 0xf4310003 3011 3012 /* IQDEM_DCRM_CFG_HL */ 3013 #define R367CAB_IQDEM_DCRM_CFG_HL 0xf432 3014 #define F367CAB_DCRM1_Q_DCIN_L 0xf43200f0 3015 #define F367CAB_DCRM1_I_DCIN_H 0xf432000f 3016 3017 /* IQDEM_DCRM_CFG_HH */ 3018 #define R367CAB_IQDEM_DCRM_CFG_HH 0xf433 3019 #define F367CAB_DCRM1_FRZ 0xf4330080 3020 #define F367CAB_DCRM0_FRZ 0xf4330040 3021 #define F367CAB_DCRM1_Q_DCIN_H 0xf433003f 3022 3023 /* IQDEM_ADJ_COEFf0 */ 3024 #define R367CAB_IQDEM_ADJ_COEFF0 0xf434 3025 #define F367CAB_ADJIIR_COEFF10_L 0xf43400ff 3026 3027 /* IQDEM_ADJ_COEFF1 */ 3028 #define R367CAB_IQDEM_ADJ_COEFF1 0xf435 3029 #define F367CAB_ADJIIR_COEFF11_L 0xf43500fc 3030 #define F367CAB_ADJIIR_COEFF10_H 0xf4350003 3031 3032 /* IQDEM_ADJ_COEFF2 */ 3033 #define R367CAB_IQDEM_ADJ_COEFF2 0xf436 3034 #define F367CAB_ADJIIR_COEFF12_L 0xf43600f0 3035 #define F367CAB_ADJIIR_COEFF11_H 0xf436000f 3036 3037 /* IQDEM_ADJ_COEFF3 */ 3038 #define R367CAB_IQDEM_ADJ_COEFF3 0xf437 3039 #define F367CAB_ADJIIR_COEFF20_L 0xf43700c0 3040 #define F367CAB_ADJIIR_COEFF12_H 0xf437003f 3041 3042 /* IQDEM_ADJ_COEFF4 */ 3043 #define R367CAB_IQDEM_ADJ_COEFF4 0xf438 3044 #define F367CAB_ADJIIR_COEFF20_H 0xf43800ff 3045 3046 /* IQDEM_ADJ_COEFF5 */ 3047 #define R367CAB_IQDEM_ADJ_COEFF5 0xf439 3048 #define F367CAB_ADJIIR_COEFF21_L 0xf43900ff 3049 3050 /* IQDEM_ADJ_COEFF6 */ 3051 #define R367CAB_IQDEM_ADJ_COEFF6 0xf43a 3052 #define F367CAB_ADJIIR_COEFF22_L 0xf43a00fc 3053 #define F367CAB_ADJIIR_COEFF21_H 0xf43a0003 3054 3055 /* IQDEM_ADJ_COEFF7 */ 3056 #define R367CAB_IQDEM_ADJ_COEFF7 0xf43b 3057 #define F367CAB_ADJIIR_COEFF22_H 0xf43b000f 3058 3059 /* IQDEM_ADJ_EN */ 3060 #define R367CAB_IQDEM_ADJ_EN 0xf43c 3061 #define F367CAB_ALLPASSFILT_EN 0xf43c0008 3062 #define F367CAB_ADJ_AGC_EN 0xf43c0004 3063 #define F367CAB_ADJ_COEFF_FRZ 0xf43c0002 3064 #define F367CAB_ADJ_EN 0xf43c0001 3065 3066 /* IQDEM_ADJ_AGC_REF */ 3067 #define R367CAB_IQDEM_ADJ_AGC_REF 0xf43d 3068 #define F367CAB_ADJ_AGC_REF 0xf43d00ff 3069 3070 /* ALLPASSFILT1 */ 3071 #define R367CAB_ALLPASSFILT1 0xf440 3072 #define F367CAB_ALLPASSFILT_COEFF1_LO 0xf44000ff 3073 3074 /* ALLPASSFILT2 */ 3075 #define R367CAB_ALLPASSFILT2 0xf441 3076 #define F367CAB_ALLPASSFILT_COEFF1_ME 0xf44100ff 3077 3078 /* ALLPASSFILT3 */ 3079 #define R367CAB_ALLPASSFILT3 0xf442 3080 #define F367CAB_ALLPASSFILT_COEFF2_LO 0xf44200c0 3081 #define F367CAB_ALLPASSFILT_COEFF1_HI 0xf442003f 3082 3083 /* ALLPASSFILT4 */ 3084 #define R367CAB_ALLPASSFILT4 0xf443 3085 #define F367CAB_ALLPASSFILT_COEFF2_MEL 0xf44300ff 3086 3087 /* ALLPASSFILT5 */ 3088 #define R367CAB_ALLPASSFILT5 0xf444 3089 #define F367CAB_ALLPASSFILT_COEFF2_MEH 0xf44400ff 3090 3091 /* ALLPASSFILT6 */ 3092 #define R367CAB_ALLPASSFILT6 0xf445 3093 #define F367CAB_ALLPASSFILT_COEFF3_LO 0xf44500f0 3094 #define F367CAB_ALLPASSFILT_COEFF2_HI 0xf445000f 3095 3096 /* ALLPASSFILT7 */ 3097 #define R367CAB_ALLPASSFILT7 0xf446 3098 #define F367CAB_ALLPASSFILT_COEFF3_MEL 0xf44600ff 3099 3100 /* ALLPASSFILT8 */ 3101 #define R367CAB_ALLPASSFILT8 0xf447 3102 #define F367CAB_ALLPASSFILT_COEFF3_MEH 0xf44700ff 3103 3104 /* ALLPASSFILT9 */ 3105 #define R367CAB_ALLPASSFILT9 0xf448 3106 #define F367CAB_ALLPASSFILT_COEFF4_LO 0xf44800fc 3107 #define F367CAB_ALLPASSFILT_COEFF3_HI 0xf4480003 3108 3109 /* ALLPASSFILT10 */ 3110 #define R367CAB_ALLPASSFILT10 0xf449 3111 #define F367CAB_ALLPASSFILT_COEFF4_ME 0xf44900ff 3112 3113 /* ALLPASSFILT11 */ 3114 #define R367CAB_ALLPASSFILT11 0xf44a 3115 #define F367CAB_ALLPASSFILT_COEFF4_HI 0xf44a00ff 3116 3117 /* TRL_AGC_CFG */ 3118 #define R367CAB_TRL_AGC_CFG 0xf450 3119 #define F367CAB_TRL_AGC_FREEZE 0xf4500080 3120 #define F367CAB_TRL_AGC_REF 0xf450007f 3121 3122 /* TRL_LPF_CFG */ 3123 #define R367CAB_TRL_LPF_CFG 0xf454 3124 #define F367CAB_NYQPOINT_INV 0xf4540040 3125 #define F367CAB_TRL_SHIFT 0xf4540030 3126 #define F367CAB_NYQ_COEFF_SEL 0xf454000c 3127 #define F367CAB_TRL_LPF_FREEZE 0xf4540002 3128 #define F367CAB_TRL_LPF_CRT 0xf4540001 3129 3130 /* TRL_LPF_ACQ_GAIN */ 3131 #define R367CAB_TRL_LPF_ACQ_GAIN 0xf455 3132 #define F367CAB_TRL_GDIR_ACQ 0xf4550070 3133 #define F367CAB_TRL_GINT_ACQ 0xf4550007 3134 3135 /* TRL_LPF_TRK_GAIN */ 3136 #define R367CAB_TRL_LPF_TRK_GAIN 0xf456 3137 #define F367CAB_TRL_GDIR_TRK 0xf4560070 3138 #define F367CAB_TRL_GINT_TRK 0xf4560007 3139 3140 /* TRL_LPF_OUT_GAIN */ 3141 #define R367CAB_TRL_LPF_OUT_GAIN 0xf457 3142 #define F367CAB_TRL_GAIN_OUT 0xf4570007 3143 3144 /* TRL_LOCKDET_LTH */ 3145 #define R367CAB_TRL_LOCKDET_LTH 0xf458 3146 #define F367CAB_TRL_LCK_THLO 0xf4580007 3147 3148 /* TRL_LOCKDET_HTH */ 3149 #define R367CAB_TRL_LOCKDET_HTH 0xf459 3150 #define F367CAB_TRL_LCK_THHI 0xf45900ff 3151 3152 /* TRL_LOCKDET_TRGVAL */ 3153 #define R367CAB_TRL_LOCKDET_TRGVAL 0xf45a 3154 #define F367CAB_TRL_LCK_TRG 0xf45a00ff 3155 3156 /* IQ_QAM */ 3157 #define R367CAB_IQ_QAM 0xf45c 3158 #define F367CAB_IQ_INPUT 0xf45c0008 3159 #define F367CAB_DETECT_MODE 0xf45c0007 3160 3161 /* FSM_STATE */ 3162 #define R367CAB_FSM_STATE 0xf460 3163 #define F367CAB_CRL_DFE 0xf4600080 3164 #define F367CAB_DFE_START 0xf4600040 3165 #define F367CAB_CTRLG_START 0xf4600030 3166 #define F367CAB_FSM_FORCESTATE 0xf460000f 3167 3168 /* FSM_CTL */ 3169 #define R367CAB_FSM_CTL 0xf461 3170 #define F367CAB_FEC2_EN 0xf4610040 3171 #define F367CAB_SIT_EN 0xf4610020 3172 #define F367CAB_TRL_AHEAD 0xf4610010 3173 #define F367CAB_TRL2_EN 0xf4610008 3174 #define F367CAB_FSM_EQA1_EN 0xf4610004 3175 #define F367CAB_FSM_BKP_DIS 0xf4610002 3176 #define F367CAB_FSM_FORCE_EN 0xf4610001 3177 3178 /* FSM_STS */ 3179 #define R367CAB_FSM_STS 0xf462 3180 #define F367CAB_FSM_STATUS 0xf462000f 3181 3182 /* FSM_SNR0_HTH */ 3183 #define R367CAB_FSM_SNR0_HTH 0xf463 3184 #define F367CAB_SNR0_HTH 0xf46300ff 3185 3186 /* FSM_SNR1_HTH */ 3187 #define R367CAB_FSM_SNR1_HTH 0xf464 3188 #define F367CAB_SNR1_HTH 0xf46400ff 3189 3190 /* FSM_SNR2_HTH */ 3191 #define R367CAB_FSM_SNR2_HTH 0xf465 3192 #define F367CAB_SNR2_HTH 0xf46500ff 3193 3194 /* FSM_SNR0_LTH */ 3195 #define R367CAB_FSM_SNR0_LTH 0xf466 3196 #define F367CAB_SNR0_LTH 0xf46600ff 3197 3198 /* FSM_SNR1_LTH */ 3199 #define R367CAB_FSM_SNR1_LTH 0xf467 3200 #define F367CAB_SNR1_LTH 0xf46700ff 3201 3202 /* FSM_EQA1_HTH */ 3203 #define R367CAB_FSM_EQA1_HTH 0xf468 3204 #define F367CAB_SNR3_HTH_LO 0xf46800f0 3205 #define F367CAB_EQA1_HTH 0xf468000f 3206 3207 /* FSM_TEMPO */ 3208 #define R367CAB_FSM_TEMPO 0xf469 3209 #define F367CAB_SIT 0xf46900c0 3210 #define F367CAB_WST 0xf4690038 3211 #define F367CAB_ELT 0xf4690006 3212 #define F367CAB_SNR3_HTH_HI 0xf4690001 3213 3214 /* FSM_CONFIG */ 3215 #define R367CAB_FSM_CONFIG 0xf46a 3216 #define F367CAB_FEC2_DFEOFF 0xf46a0004 3217 #define F367CAB_PRIT_STATE 0xf46a0002 3218 #define F367CAB_MODMAP_STATE 0xf46a0001 3219 3220 /* EQU_I_TESTTAP_L */ 3221 #define R367CAB_EQU_I_TESTTAP_L 0xf474 3222 #define F367CAB_I_TEST_TAP_L 0xf47400ff 3223 3224 /* EQU_I_TESTTAP_M */ 3225 #define R367CAB_EQU_I_TESTTAP_M 0xf475 3226 #define F367CAB_I_TEST_TAP_M 0xf47500ff 3227 3228 /* EQU_I_TESTTAP_H */ 3229 #define R367CAB_EQU_I_TESTTAP_H 0xf476 3230 #define F367CAB_I_TEST_TAP_H 0xf476001f 3231 3232 /* EQU_TESTAP_CFG */ 3233 #define R367CAB_EQU_TESTAP_CFG 0xf477 3234 #define F367CAB_TEST_FFE_DFE_SEL 0xf4770040 3235 #define F367CAB_TEST_TAP_SELECT 0xf477003f 3236 3237 /* EQU_Q_TESTTAP_L */ 3238 #define R367CAB_EQU_Q_TESTTAP_L 0xf478 3239 #define F367CAB_Q_TEST_TAP_L 0xf47800ff 3240 3241 /* EQU_Q_TESTTAP_M */ 3242 #define R367CAB_EQU_Q_TESTTAP_M 0xf479 3243 #define F367CAB_Q_TEST_TAP_M 0xf47900ff 3244 3245 /* EQU_Q_TESTTAP_H */ 3246 #define R367CAB_EQU_Q_TESTTAP_H 0xf47a 3247 #define F367CAB_Q_TEST_TAP_H 0xf47a001f 3248 3249 /* EQU_TAP_CTRL */ 3250 #define R367CAB_EQU_TAP_CTRL 0xf47b 3251 #define F367CAB_MTAP_FRZ 0xf47b0010 3252 #define F367CAB_PRE_FREEZE 0xf47b0008 3253 #define F367CAB_DFE_TAPMON_EN 0xf47b0004 3254 #define F367CAB_FFE_TAPMON_EN 0xf47b0002 3255 #define F367CAB_MTAP_ONLY 0xf47b0001 3256 3257 /* EQU_CTR_CRL_CONTROL_L */ 3258 #define R367CAB_EQU_CTR_CRL_CONTROL_L 0xf47c 3259 #define F367CAB_EQU_CTR_CRL_CONTROL_LO 0xf47c00ff 3260 3261 /* EQU_CTR_CRL_CONTROL_H */ 3262 #define R367CAB_EQU_CTR_CRL_CONTROL_H 0xf47d 3263 #define F367CAB_EQU_CTR_CRL_CONTROL_HI 0xf47d00ff 3264 3265 /* EQU_CTR_HIPOW_L */ 3266 #define R367CAB_EQU_CTR_HIPOW_L 0xf47e 3267 #define F367CAB_CTR_HIPOW_L 0xf47e00ff 3268 3269 /* EQU_CTR_HIPOW_H */ 3270 #define R367CAB_EQU_CTR_HIPOW_H 0xf47f 3271 #define F367CAB_CTR_HIPOW_H 0xf47f00ff 3272 3273 /* EQU_I_EQU_LO */ 3274 #define R367CAB_EQU_I_EQU_LO 0xf480 3275 #define F367CAB_EQU_I_EQU_L 0xf48000ff 3276 3277 /* EQU_I_EQU_HI */ 3278 #define R367CAB_EQU_I_EQU_HI 0xf481 3279 #define F367CAB_EQU_I_EQU_H 0xf4810003 3280 3281 /* EQU_Q_EQU_LO */ 3282 #define R367CAB_EQU_Q_EQU_LO 0xf482 3283 #define F367CAB_EQU_Q_EQU_L 0xf48200ff 3284 3285 /* EQU_Q_EQU_HI */ 3286 #define R367CAB_EQU_Q_EQU_HI 0xf483 3287 #define F367CAB_EQU_Q_EQU_H 0xf4830003 3288 3289 /* EQU_MAPPER */ 3290 #define R367CAB_EQU_MAPPER 0xf484 3291 #define F367CAB_QUAD_AUTO 0xf4840080 3292 #define F367CAB_QUAD_INV 0xf4840040 3293 #define F367CAB_QAM_MODE 0xf4840007 3294 3295 /* EQU_SWEEP_RATE */ 3296 #define R367CAB_EQU_SWEEP_RATE 0xf485 3297 #define F367CAB_SNR_PER 0xf48500c0 3298 #define F367CAB_SWEEP_RATE 0xf485003f 3299 3300 /* EQU_SNR_LO */ 3301 #define R367CAB_EQU_SNR_LO 0xf486 3302 #define F367CAB_SNR_LO 0xf48600ff 3303 3304 /* EQU_SNR_HI */ 3305 #define R367CAB_EQU_SNR_HI 0xf487 3306 #define F367CAB_SNR_HI 0xf48700ff 3307 3308 /* EQU_GAMMA_LO */ 3309 #define R367CAB_EQU_GAMMA_LO 0xf488 3310 #define F367CAB_GAMMA_LO 0xf48800ff 3311 3312 /* EQU_GAMMA_HI */ 3313 #define R367CAB_EQU_GAMMA_HI 0xf489 3314 #define F367CAB_GAMMA_ME 0xf48900ff 3315 3316 /* EQU_ERR_GAIN */ 3317 #define R367CAB_EQU_ERR_GAIN 0xf48a 3318 #define F367CAB_EQA1MU 0xf48a0070 3319 #define F367CAB_CRL2MU 0xf48a000e 3320 #define F367CAB_GAMMA_HI 0xf48a0001 3321 3322 /* EQU_RADIUS */ 3323 #define R367CAB_EQU_RADIUS 0xf48b 3324 #define F367CAB_RADIUS 0xf48b00ff 3325 3326 /* EQU_FFE_MAINTAP */ 3327 #define R367CAB_EQU_FFE_MAINTAP 0xf48c 3328 #define F367CAB_FFE_MAINTAP_INIT 0xf48c00ff 3329 3330 /* EQU_FFE_LEAKAGE */ 3331 #define R367CAB_EQU_FFE_LEAKAGE 0xf48e 3332 #define F367CAB_LEAK_PER 0xf48e00f0 3333 #define F367CAB_EQU_OUTSEL 0xf48e0002 3334 #define F367CAB_PNT2dFE 0xf48e0001 3335 3336 /* EQU_FFE_MAINTAP_POS */ 3337 #define R367CAB_EQU_FFE_MAINTAP_POS 0xf48f 3338 #define F367CAB_FFE_LEAK_EN 0xf48f0080 3339 #define F367CAB_DFE_LEAK_EN 0xf48f0040 3340 #define F367CAB_FFE_MAINTAP_POS 0xf48f003f 3341 3342 /* EQU_GAIN_WIDE */ 3343 #define R367CAB_EQU_GAIN_WIDE 0xf490 3344 #define F367CAB_DFE_GAIN_WIDE 0xf49000f0 3345 #define F367CAB_FFE_GAIN_WIDE 0xf490000f 3346 3347 /* EQU_GAIN_NARROW */ 3348 #define R367CAB_EQU_GAIN_NARROW 0xf491 3349 #define F367CAB_DFE_GAIN_NARROW 0xf49100f0 3350 #define F367CAB_FFE_GAIN_NARROW 0xf491000f 3351 3352 /* EQU_CTR_LPF_GAIN */ 3353 #define R367CAB_EQU_CTR_LPF_GAIN 0xf492 3354 #define F367CAB_CTR_GTO 0xf4920080 3355 #define F367CAB_CTR_GDIR 0xf4920070 3356 #define F367CAB_SWEEP_EN 0xf4920008 3357 #define F367CAB_CTR_GINT 0xf4920007 3358 3359 /* EQU_CRL_LPF_GAIN */ 3360 #define R367CAB_EQU_CRL_LPF_GAIN 0xf493 3361 #define F367CAB_CRL_GTO 0xf4930080 3362 #define F367CAB_CRL_GDIR 0xf4930070 3363 #define F367CAB_SWEEP_DIR 0xf4930008 3364 #define F367CAB_CRL_GINT 0xf4930007 3365 3366 /* EQU_GLOBAL_GAIN */ 3367 #define R367CAB_EQU_GLOBAL_GAIN 0xf494 3368 #define F367CAB_CRL_GAIN 0xf49400f8 3369 #define F367CAB_CTR_INC_GAIN 0xf4940004 3370 #define F367CAB_CTR_FRAC 0xf4940003 3371 3372 /* EQU_CRL_LD_SEN */ 3373 #define R367CAB_EQU_CRL_LD_SEN 0xf495 3374 #define F367CAB_CTR_BADPOINT_EN 0xf4950080 3375 #define F367CAB_CTR_GAIN 0xf4950070 3376 #define F367CAB_LIMANEN 0xf4950008 3377 #define F367CAB_CRL_LD_SEN 0xf4950007 3378 3379 /* EQU_CRL_LD_VAL */ 3380 #define R367CAB_EQU_CRL_LD_VAL 0xf496 3381 #define F367CAB_CRL_BISTH_LIMIT 0xf4960080 3382 #define F367CAB_CARE_EN 0xf4960040 3383 #define F367CAB_CRL_LD_PER 0xf4960030 3384 #define F367CAB_CRL_LD_WST 0xf496000c 3385 #define F367CAB_CRL_LD_TFS 0xf4960003 3386 3387 /* EQU_CRL_TFR */ 3388 #define R367CAB_EQU_CRL_TFR 0xf497 3389 #define F367CAB_CRL_LD_TFR 0xf49700ff 3390 3391 /* EQU_CRL_BISTH_LO */ 3392 #define R367CAB_EQU_CRL_BISTH_LO 0xf498 3393 #define F367CAB_CRL_BISTH_LO 0xf49800ff 3394 3395 /* EQU_CRL_BISTH_HI */ 3396 #define R367CAB_EQU_CRL_BISTH_HI 0xf499 3397 #define F367CAB_CRL_BISTH_HI 0xf49900ff 3398 3399 /* EQU_SWEEP_RANGE_LO */ 3400 #define R367CAB_EQU_SWEEP_RANGE_LO 0xf49a 3401 #define F367CAB_SWEEP_RANGE_LO 0xf49a00ff 3402 3403 /* EQU_SWEEP_RANGE_HI */ 3404 #define R367CAB_EQU_SWEEP_RANGE_HI 0xf49b 3405 #define F367CAB_SWEEP_RANGE_HI 0xf49b00ff 3406 3407 /* EQU_CRL_LIMITER */ 3408 #define R367CAB_EQU_CRL_LIMITER 0xf49c 3409 #define F367CAB_BISECTOR_EN 0xf49c0080 3410 #define F367CAB_PHEST128_EN 0xf49c0040 3411 #define F367CAB_CRL_LIM 0xf49c003f 3412 3413 /* EQU_MODULUS_MAP */ 3414 #define R367CAB_EQU_MODULUS_MAP 0xf49d 3415 #define F367CAB_PNT_DEPTH 0xf49d00e0 3416 #define F367CAB_MODULUS_CMP 0xf49d001f 3417 3418 /* EQU_PNT_GAIN */ 3419 #define R367CAB_EQU_PNT_GAIN 0xf49e 3420 #define F367CAB_PNT_EN 0xf49e0080 3421 #define F367CAB_MODULUSMAP_EN 0xf49e0040 3422 #define F367CAB_PNT_GAIN 0xf49e003f 3423 3424 /* FEC_AC_CTR_0 */ 3425 #define R367CAB_FEC_AC_CTR_0 0xf4a8 3426 #define F367CAB_BE_BYPASS 0xf4a80020 3427 #define F367CAB_REFRESH47 0xf4a80010 3428 #define F367CAB_CT_NBST 0xf4a80008 3429 #define F367CAB_TEI_ENA 0xf4a80004 3430 #define F367CAB_DS_ENA 0xf4a80002 3431 #define F367CAB_TSMF_EN 0xf4a80001 3432 3433 /* FEC_AC_CTR_1 */ 3434 #define R367CAB_FEC_AC_CTR_1 0xf4a9 3435 #define F367CAB_DEINT_DEPTH 0xf4a900ff 3436 3437 /* FEC_AC_CTR_2 */ 3438 #define R367CAB_FEC_AC_CTR_2 0xf4aa 3439 #define F367CAB_DEINT_M 0xf4aa00f8 3440 #define F367CAB_DIS_UNLOCK 0xf4aa0004 3441 #define F367CAB_DESCR_MODE 0xf4aa0003 3442 3443 /* FEC_AC_CTR_3 */ 3444 #define R367CAB_FEC_AC_CTR_3 0xf4ab 3445 #define F367CAB_DI_UNLOCK 0xf4ab0080 3446 #define F367CAB_DI_FREEZE 0xf4ab0040 3447 #define F367CAB_MISMATCH 0xf4ab0030 3448 #define F367CAB_ACQ_MODE 0xf4ab000c 3449 #define F367CAB_TRK_MODE 0xf4ab0003 3450 3451 /* FEC_STATUS */ 3452 #define R367CAB_FEC_STATUS 0xf4ac 3453 #define F367CAB_DEINT_SMCNTR 0xf4ac00e0 3454 #define F367CAB_DEINT_SYNCSTATE 0xf4ac0018 3455 #define F367CAB_DEINT_SYNLOST 0xf4ac0004 3456 #define F367CAB_DESCR_SYNCSTATE 0xf4ac0002 3457 3458 /* RS_COUNTER_0 */ 3459 #define R367CAB_RS_COUNTER_0 0xf4ae 3460 #define F367CAB_BK_CT_L 0xf4ae00ff 3461 3462 /* RS_COUNTER_1 */ 3463 #define R367CAB_RS_COUNTER_1 0xf4af 3464 #define F367CAB_BK_CT_H 0xf4af00ff 3465 3466 /* RS_COUNTER_2 */ 3467 #define R367CAB_RS_COUNTER_2 0xf4b0 3468 #define F367CAB_CORR_CT_L 0xf4b000ff 3469 3470 /* RS_COUNTER_3 */ 3471 #define R367CAB_RS_COUNTER_3 0xf4b1 3472 #define F367CAB_CORR_CT_H 0xf4b100ff 3473 3474 /* RS_COUNTER_4 */ 3475 #define R367CAB_RS_COUNTER_4 0xf4b2 3476 #define F367CAB_UNCORR_CT_L 0xf4b200ff 3477 3478 /* RS_COUNTER_5 */ 3479 #define R367CAB_RS_COUNTER_5 0xf4b3 3480 #define F367CAB_UNCORR_CT_H 0xf4b300ff 3481 3482 /* BERT_0 */ 3483 #define R367CAB_BERT_0 0xf4b4 3484 #define F367CAB_RS_NOCORR 0xf4b40004 3485 #define F367CAB_CT_HOLD 0xf4b40002 3486 #define F367CAB_CT_CLEAR 0xf4b40001 3487 3488 /* BERT_1 */ 3489 #define R367CAB_BERT_1 0xf4b5 3490 #define F367CAB_BERT_ON 0xf4b50020 3491 #define F367CAB_BERT_ERR_SRC 0xf4b50010 3492 #define F367CAB_BERT_ERR_MODE 0xf4b50008 3493 #define F367CAB_BERT_NBYTE 0xf4b50007 3494 3495 /* BERT_2 */ 3496 #define R367CAB_BERT_2 0xf4b6 3497 #define F367CAB_BERT_ERRCOUNT_L 0xf4b600ff 3498 3499 /* BERT_3 */ 3500 #define R367CAB_BERT_3 0xf4b7 3501 #define F367CAB_BERT_ERRCOUNT_H 0xf4b700ff 3502 3503 /* OUTFORMAT_0 */ 3504 #define R367CAB_OUTFORMAT_0 0xf4b8 3505 #define F367CAB_CLK_POLARITY 0xf4b80080 3506 #define F367CAB_FEC_TYPE 0xf4b80040 3507 #define F367CAB_SYNC_STRIP 0xf4b80008 3508 #define F367CAB_TS_SWAP 0xf4b80004 3509 #define F367CAB_OUTFORMAT 0xf4b80003 3510 3511 /* OUTFORMAT_1 */ 3512 #define R367CAB_OUTFORMAT_1 0xf4b9 3513 #define F367CAB_CI_DIVRANGE 0xf4b900ff 3514 3515 /* SMOOTHER_2 */ 3516 #define R367CAB_SMOOTHER_2 0xf4be 3517 #define F367CAB_FIFO_BYPASS 0xf4be0020 3518 3519 /* TSMF_CTRL_0 */ 3520 #define R367CAB_TSMF_CTRL_0 0xf4c0 3521 #define F367CAB_TS_NUMBER 0xf4c0001e 3522 #define F367CAB_SEL_MODE 0xf4c00001 3523 3524 /* TSMF_CTRL_1 */ 3525 #define R367CAB_TSMF_CTRL_1 0xf4c1 3526 #define F367CAB_CHECK_ERROR_BIT 0xf4c10080 3527 #define F367CAB_CHCK_F_SYNC 0xf4c10040 3528 #define F367CAB_H_MODE 0xf4c10008 3529 #define F367CAB_D_V_MODE 0xf4c10004 3530 #define F367CAB_MODE 0xf4c10003 3531 3532 /* TSMF_CTRL_3 */ 3533 #define R367CAB_TSMF_CTRL_3 0xf4c3 3534 #define F367CAB_SYNC_IN_COUNT 0xf4c300f0 3535 #define F367CAB_SYNC_OUT_COUNT 0xf4c3000f 3536 3537 /* TS_ON_ID_0 */ 3538 #define R367CAB_TS_ON_ID_0 0xf4c4 3539 #define F367CAB_TS_ID_L 0xf4c400ff 3540 3541 /* TS_ON_ID_1 */ 3542 #define R367CAB_TS_ON_ID_1 0xf4c5 3543 #define F367CAB_TS_ID_H 0xf4c500ff 3544 3545 /* TS_ON_ID_2 */ 3546 #define R367CAB_TS_ON_ID_2 0xf4c6 3547 #define F367CAB_ON_ID_L 0xf4c600ff 3548 3549 /* TS_ON_ID_3 */ 3550 #define R367CAB_TS_ON_ID_3 0xf4c7 3551 #define F367CAB_ON_ID_H 0xf4c700ff 3552 3553 /* RE_STATUS_0 */ 3554 #define R367CAB_RE_STATUS_0 0xf4c8 3555 #define F367CAB_RECEIVE_STATUS_L 0xf4c800ff 3556 3557 /* RE_STATUS_1 */ 3558 #define R367CAB_RE_STATUS_1 0xf4c9 3559 #define F367CAB_RECEIVE_STATUS_LH 0xf4c900ff 3560 3561 /* RE_STATUS_2 */ 3562 #define R367CAB_RE_STATUS_2 0xf4ca 3563 #define F367CAB_RECEIVE_STATUS_HL 0xf4ca00ff 3564 3565 /* RE_STATUS_3 */ 3566 #define R367CAB_RE_STATUS_3 0xf4cb 3567 #define F367CAB_RECEIVE_STATUS_HH 0xf4cb003f 3568 3569 /* TS_STATUS_0 */ 3570 #define R367CAB_TS_STATUS_0 0xf4cc 3571 #define F367CAB_TS_STATUS_L 0xf4cc00ff 3572 3573 /* TS_STATUS_1 */ 3574 #define R367CAB_TS_STATUS_1 0xf4cd 3575 #define F367CAB_TS_STATUS_H 0xf4cd007f 3576 3577 /* TS_STATUS_2 */ 3578 #define R367CAB_TS_STATUS_2 0xf4ce 3579 #define F367CAB_ERROR 0xf4ce0080 3580 #define F367CAB_EMERGENCY 0xf4ce0040 3581 #define F367CAB_CRE_TS 0xf4ce0030 3582 #define F367CAB_VER 0xf4ce000e 3583 #define F367CAB_M_LOCK 0xf4ce0001 3584 3585 /* TS_STATUS_3 */ 3586 #define R367CAB_TS_STATUS_3 0xf4cf 3587 #define F367CAB_UPDATE_READY 0xf4cf0080 3588 #define F367CAB_END_FRAME_HEADER 0xf4cf0040 3589 #define F367CAB_CONTCNT 0xf4cf0020 3590 #define F367CAB_TS_IDENTIFIER_SEL 0xf4cf000f 3591 3592 /* T_O_ID_0 */ 3593 #define R367CAB_T_O_ID_0 0xf4d0 3594 #define F367CAB_ON_ID_I_L 0xf4d000ff 3595 3596 /* T_O_ID_1 */ 3597 #define R367CAB_T_O_ID_1 0xf4d1 3598 #define F367CAB_ON_ID_I_H 0xf4d100ff 3599 3600 /* T_O_ID_2 */ 3601 #define R367CAB_T_O_ID_2 0xf4d2 3602 #define F367CAB_TS_ID_I_L 0xf4d200ff 3603 3604 /* T_O_ID_3 */ 3605 #define R367CAB_T_O_ID_3 0xf4d3 3606 #define F367CAB_TS_ID_I_H 0xf4d300ff 3607 3608 #define STV0367CAB_NBREGS 187 3609 3610 #endif 3611