1 /* 2 * Samsung s5h1432 DVB-T demodulator driver 3 * 4 * Copyright (C) 2009 Bill Liu <Bill.Liu@Conexant.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21 #include <linux/kernel.h> 22 #include <linux/init.h> 23 #include <linux/module.h> 24 #include <linux/string.h> 25 #include <linux/slab.h> 26 #include <linux/delay.h> 27 #include "dvb_frontend.h" 28 #include "s5h1432.h" 29 30 struct s5h1432_state { 31 32 struct i2c_adapter *i2c; 33 34 /* configuration settings */ 35 const struct s5h1432_config *config; 36 37 struct dvb_frontend frontend; 38 39 enum fe_modulation current_modulation; 40 unsigned int first_tune:1; 41 42 u32 current_frequency; 43 int if_freq; 44 45 u8 inversion; 46 }; 47 48 static int debug; 49 50 #define dprintk(arg...) do { \ 51 if (debug) \ 52 printk(arg); \ 53 } while (0) 54 55 static int s5h1432_writereg(struct s5h1432_state *state, 56 u8 addr, u8 reg, u8 data) 57 { 58 int ret; 59 u8 buf[] = { reg, data }; 60 61 struct i2c_msg msg = {.addr = addr, .flags = 0, .buf = buf, .len = 2 }; 62 63 ret = i2c_transfer(state->i2c, &msg, 1); 64 65 if (ret != 1) 66 printk(KERN_ERR "%s: writereg error 0x%02x 0x%02x 0x%04x, " 67 "ret == %i)\n", __func__, addr, reg, data, ret); 68 69 return (ret != 1) ? -1 : 0; 70 } 71 72 static u8 s5h1432_readreg(struct s5h1432_state *state, u8 addr, u8 reg) 73 { 74 int ret; 75 u8 b0[] = { reg }; 76 u8 b1[] = { 0 }; 77 78 struct i2c_msg msg[] = { 79 {.addr = addr, .flags = 0, .buf = b0, .len = 1}, 80 {.addr = addr, .flags = I2C_M_RD, .buf = b1, .len = 1} 81 }; 82 83 ret = i2c_transfer(state->i2c, msg, 2); 84 85 if (ret != 2) 86 printk(KERN_ERR "%s: readreg error (ret == %i)\n", 87 __func__, ret); 88 return b1[0]; 89 } 90 91 static int s5h1432_sleep(struct dvb_frontend *fe) 92 { 93 return 0; 94 } 95 96 static int s5h1432_set_channel_bandwidth(struct dvb_frontend *fe, 97 u32 bandwidth) 98 { 99 struct s5h1432_state *state = fe->demodulator_priv; 100 101 u8 reg = 0; 102 103 /* Register [0x2E] bit 3:2 : 8MHz = 0; 7MHz = 1; 6MHz = 2 */ 104 reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x2E); 105 reg &= ~(0x0C); 106 switch (bandwidth) { 107 case 6: 108 reg |= 0x08; 109 break; 110 case 7: 111 reg |= 0x04; 112 break; 113 case 8: 114 reg |= 0x00; 115 break; 116 default: 117 return 0; 118 } 119 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2E, reg); 120 return 1; 121 } 122 123 static int s5h1432_set_IF(struct dvb_frontend *fe, u32 ifFreqHz) 124 { 125 struct s5h1432_state *state = fe->demodulator_priv; 126 127 switch (ifFreqHz) { 128 case TAIWAN_HI_IF_FREQ_44_MHZ: 129 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x55); 130 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x55); 131 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0x15); 132 break; 133 case EUROPE_HI_IF_FREQ_36_MHZ: 134 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x00); 135 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x00); 136 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0x40); 137 break; 138 case IF_FREQ_6_MHZ: 139 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x00); 140 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x00); 141 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xe0); 142 break; 143 case IF_FREQ_3point3_MHZ: 144 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x66); 145 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x66); 146 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEE); 147 break; 148 case IF_FREQ_3point5_MHZ: 149 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x55); 150 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x55); 151 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xED); 152 break; 153 case IF_FREQ_4_MHZ: 154 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0xAA); 155 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0xAA); 156 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEA); 157 break; 158 default: 159 { 160 u32 value = 0; 161 value = (u32) (((48000 - (ifFreqHz / 1000)) * 512 * 162 (u32) 32768) / (48 * 1000)); 163 printk(KERN_INFO 164 "Default IFFreq %d :reg value = 0x%x\n", 165 ifFreqHz, value); 166 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 167 (u8) value & 0xFF); 168 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 169 (u8) (value >> 8) & 0xFF); 170 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 171 (u8) (value >> 16) & 0xFF); 172 break; 173 } 174 175 } 176 177 return 1; 178 } 179 180 /* Talk to the demod, set the FEC, GUARD, QAM settings etc */ 181 static int s5h1432_set_frontend(struct dvb_frontend *fe) 182 { 183 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 184 u32 dvb_bandwidth = 8; 185 struct s5h1432_state *state = fe->demodulator_priv; 186 187 if (p->frequency == state->current_frequency) { 188 /*current_frequency = p->frequency; */ 189 /*state->current_frequency = p->frequency; */ 190 } else { 191 fe->ops.tuner_ops.set_params(fe); 192 msleep(300); 193 s5h1432_set_channel_bandwidth(fe, dvb_bandwidth); 194 switch (p->bandwidth_hz) { 195 case 6000000: 196 dvb_bandwidth = 6; 197 s5h1432_set_IF(fe, IF_FREQ_4_MHZ); 198 break; 199 case 7000000: 200 dvb_bandwidth = 7; 201 s5h1432_set_IF(fe, IF_FREQ_4_MHZ); 202 break; 203 case 8000000: 204 dvb_bandwidth = 8; 205 s5h1432_set_IF(fe, IF_FREQ_4_MHZ); 206 break; 207 default: 208 return 0; 209 } 210 /*fe->ops.tuner_ops.set_params(fe); */ 211 /*Soft Reset chip*/ 212 msleep(30); 213 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a); 214 msleep(30); 215 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b); 216 217 s5h1432_set_channel_bandwidth(fe, dvb_bandwidth); 218 switch (p->bandwidth_hz) { 219 case 6000000: 220 dvb_bandwidth = 6; 221 s5h1432_set_IF(fe, IF_FREQ_4_MHZ); 222 break; 223 case 7000000: 224 dvb_bandwidth = 7; 225 s5h1432_set_IF(fe, IF_FREQ_4_MHZ); 226 break; 227 case 8000000: 228 dvb_bandwidth = 8; 229 s5h1432_set_IF(fe, IF_FREQ_4_MHZ); 230 break; 231 default: 232 return 0; 233 } 234 /*fe->ops.tuner_ops.set_params(fe); */ 235 /*Soft Reset chip*/ 236 msleep(30); 237 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a); 238 msleep(30); 239 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b); 240 241 } 242 243 state->current_frequency = p->frequency; 244 245 return 0; 246 } 247 248 static int s5h1432_init(struct dvb_frontend *fe) 249 { 250 struct s5h1432_state *state = fe->demodulator_priv; 251 252 u8 reg = 0; 253 state->current_frequency = 0; 254 printk(KERN_INFO " s5h1432_init().\n"); 255 256 /*Set VSB mode as default, this also does a soft reset */ 257 /*Initialize registers */ 258 259 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x04, 0xa8); 260 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x05, 0x01); 261 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x07, 0x70); 262 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x19, 0x80); 263 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1b, 0x9D); 264 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1c, 0x30); 265 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1d, 0x20); 266 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x1B); 267 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2e, 0x40); 268 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, 0x84); 269 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x50, 0x5a); 270 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x5a, 0xd3); 271 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x68, 0x50); 272 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xb8, 0x3c); 273 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xc4, 0x10); 274 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xcc, 0x9c); 275 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xDA, 0x00); 276 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe1, 0x94); 277 /* s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf4, 0xa1); */ 278 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf9, 0x00); 279 280 /*For NXP tuner*/ 281 282 /*Set 3.3MHz as default IF frequency */ 283 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x66); 284 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x66); 285 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEE); 286 /* Set reg 0x1E to get the full dynamic range */ 287 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x31); 288 289 /* Mode setting in demod */ 290 reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x42); 291 reg |= 0x80; 292 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, reg); 293 /* Serial mode */ 294 295 /* Soft Reset chip */ 296 297 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a); 298 msleep(30); 299 s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b); 300 301 302 return 0; 303 } 304 305 static int s5h1432_read_status(struct dvb_frontend *fe, enum fe_status *status) 306 { 307 return 0; 308 } 309 310 static int s5h1432_read_signal_strength(struct dvb_frontend *fe, 311 u16 *signal_strength) 312 { 313 return 0; 314 } 315 316 static int s5h1432_read_snr(struct dvb_frontend *fe, u16 *snr) 317 { 318 return 0; 319 } 320 321 static int s5h1432_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 322 { 323 324 return 0; 325 } 326 327 static int s5h1432_read_ber(struct dvb_frontend *fe, u32 *ber) 328 { 329 return 0; 330 } 331 332 static int s5h1432_get_tune_settings(struct dvb_frontend *fe, 333 struct dvb_frontend_tune_settings *tune) 334 { 335 return 0; 336 } 337 338 static void s5h1432_release(struct dvb_frontend *fe) 339 { 340 struct s5h1432_state *state = fe->demodulator_priv; 341 kfree(state); 342 } 343 344 static struct dvb_frontend_ops s5h1432_ops; 345 346 struct dvb_frontend *s5h1432_attach(const struct s5h1432_config *config, 347 struct i2c_adapter *i2c) 348 { 349 struct s5h1432_state *state = NULL; 350 351 printk(KERN_INFO " Enter s5h1432_attach(). attach success!\n"); 352 /* allocate memory for the internal state */ 353 state = kmalloc(sizeof(struct s5h1432_state), GFP_KERNEL); 354 if (!state) 355 return NULL; 356 357 /* setup the state */ 358 state->config = config; 359 state->i2c = i2c; 360 state->current_modulation = QAM_16; 361 state->inversion = state->config->inversion; 362 363 /* create dvb_frontend */ 364 memcpy(&state->frontend.ops, &s5h1432_ops, 365 sizeof(struct dvb_frontend_ops)); 366 367 state->frontend.demodulator_priv = state; 368 369 return &state->frontend; 370 } 371 EXPORT_SYMBOL(s5h1432_attach); 372 373 static struct dvb_frontend_ops s5h1432_ops = { 374 .delsys = { SYS_DVBT }, 375 .info = { 376 .name = "Samsung s5h1432 DVB-T Frontend", 377 .frequency_min = 177000000, 378 .frequency_max = 858000000, 379 .frequency_stepsize = 166666, 380 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 381 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 382 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | 383 FE_CAN_HIERARCHY_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | 384 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER}, 385 386 .init = s5h1432_init, 387 .sleep = s5h1432_sleep, 388 .set_frontend = s5h1432_set_frontend, 389 .get_tune_settings = s5h1432_get_tune_settings, 390 .read_status = s5h1432_read_status, 391 .read_ber = s5h1432_read_ber, 392 .read_signal_strength = s5h1432_read_signal_strength, 393 .read_snr = s5h1432_read_snr, 394 .read_ucblocks = s5h1432_read_ucblocks, 395 .release = s5h1432_release, 396 }; 397 398 module_param(debug, int, 0644); 399 MODULE_PARM_DESC(debug, "Enable verbose debug messages"); 400 401 MODULE_DESCRIPTION("Samsung s5h1432 DVB-T Demodulator driver"); 402 MODULE_AUTHOR("Bill Liu"); 403 MODULE_LICENSE("GPL"); 404