1*b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 29a0bf528SMauro Carvalho Chehab /* 39a0bf528SMauro Carvalho Chehab * Public Include File for DRV6000 users 49a0bf528SMauro Carvalho Chehab * (ie. NxtWave Communications - NXT6000 demodulator driver) 59a0bf528SMauro Carvalho Chehab * 69a0bf528SMauro Carvalho Chehab * Copyright (C) 2001 NxtWave Communications, Inc. 79a0bf528SMauro Carvalho Chehab * 89a0bf528SMauro Carvalho Chehab */ 99a0bf528SMauro Carvalho Chehab 109a0bf528SMauro Carvalho Chehab /* Nxt6000 Register Addresses and Bit Masks */ 119a0bf528SMauro Carvalho Chehab 129a0bf528SMauro Carvalho Chehab /* Maximum Register Number */ 139a0bf528SMauro Carvalho Chehab #define MAXNXT6000REG (0x9A) 149a0bf528SMauro Carvalho Chehab 159a0bf528SMauro Carvalho Chehab /* 0x1B A_VIT_BER_0 aka 0x3A */ 169a0bf528SMauro Carvalho Chehab #define A_VIT_BER_0 (0x1B) 179a0bf528SMauro Carvalho Chehab 189a0bf528SMauro Carvalho Chehab /* 0x1D A_VIT_BER_TIMER_0 aka 0x38 */ 199a0bf528SMauro Carvalho Chehab #define A_VIT_BER_TIMER_0 (0x1D) 209a0bf528SMauro Carvalho Chehab 219a0bf528SMauro Carvalho Chehab /* 0x21 RS_COR_STAT */ 229a0bf528SMauro Carvalho Chehab #define RS_COR_STAT (0x21) 239a0bf528SMauro Carvalho Chehab #define RSCORESTATUS (0x03) 249a0bf528SMauro Carvalho Chehab 259a0bf528SMauro Carvalho Chehab /* 0x22 RS_COR_INTEN */ 269a0bf528SMauro Carvalho Chehab #define RS_COR_INTEN (0x22) 279a0bf528SMauro Carvalho Chehab 289a0bf528SMauro Carvalho Chehab /* 0x23 RS_COR_INSTAT */ 299a0bf528SMauro Carvalho Chehab #define RS_COR_INSTAT (0x23) 309a0bf528SMauro Carvalho Chehab #define INSTAT_ERROR (0x04) 319a0bf528SMauro Carvalho Chehab #define LOCK_LOSS_BITS (0x03) 329a0bf528SMauro Carvalho Chehab 339a0bf528SMauro Carvalho Chehab /* 0x24 RS_COR_SYNC_PARAM */ 349a0bf528SMauro Carvalho Chehab #define RS_COR_SYNC_PARAM (0x24) 359a0bf528SMauro Carvalho Chehab #define SYNC_PARAM (0x03) 369a0bf528SMauro Carvalho Chehab 379a0bf528SMauro Carvalho Chehab /* 0x25 BER_CTRL */ 389a0bf528SMauro Carvalho Chehab #define BER_CTRL (0x25) 399a0bf528SMauro Carvalho Chehab #define BER_ENABLE (0x02) 409a0bf528SMauro Carvalho Chehab #define BER_RESET (0x01) 419a0bf528SMauro Carvalho Chehab 429a0bf528SMauro Carvalho Chehab /* 0x26 BER_PAY */ 439a0bf528SMauro Carvalho Chehab #define BER_PAY (0x26) 449a0bf528SMauro Carvalho Chehab 459a0bf528SMauro Carvalho Chehab /* 0x27 BER_PKT_L */ 469a0bf528SMauro Carvalho Chehab #define BER_PKT_L (0x27) 479a0bf528SMauro Carvalho Chehab #define BER_PKTOVERFLOW (0x80) 489a0bf528SMauro Carvalho Chehab 499a0bf528SMauro Carvalho Chehab /* 0x30 VIT_COR_CTL */ 509a0bf528SMauro Carvalho Chehab #define VIT_COR_CTL (0x30) 519a0bf528SMauro Carvalho Chehab #define BER_CONTROL (0x02) 529a0bf528SMauro Carvalho Chehab #define VIT_COR_MASK (0x82) 539a0bf528SMauro Carvalho Chehab #define VIT_COR_RESYNC (0x80) 549a0bf528SMauro Carvalho Chehab 559a0bf528SMauro Carvalho Chehab 569a0bf528SMauro Carvalho Chehab /* 0x32 VIT_SYNC_STATUS */ 579a0bf528SMauro Carvalho Chehab #define VIT_SYNC_STATUS (0x32) 589a0bf528SMauro Carvalho Chehab #define VITINSYNC (0x80) 599a0bf528SMauro Carvalho Chehab 609a0bf528SMauro Carvalho Chehab /* 0x33 VIT_COR_INTEN */ 619a0bf528SMauro Carvalho Chehab #define VIT_COR_INTEN (0x33) 629a0bf528SMauro Carvalho Chehab #define GLOBAL_ENABLE (0x80) 639a0bf528SMauro Carvalho Chehab 649a0bf528SMauro Carvalho Chehab /* 0x34 VIT_COR_INTSTAT */ 659a0bf528SMauro Carvalho Chehab #define VIT_COR_INTSTAT (0x34) 669a0bf528SMauro Carvalho Chehab #define BER_DONE (0x08) 679a0bf528SMauro Carvalho Chehab #define BER_OVERFLOW (0x10) 689a0bf528SMauro Carvalho Chehab 699a0bf528SMauro Carvalho Chehab /* 0x38 VIT_BERTIME_2 */ 709a0bf528SMauro Carvalho Chehab #define VIT_BERTIME_2 (0x38) 719a0bf528SMauro Carvalho Chehab 729a0bf528SMauro Carvalho Chehab /* 0x39 VIT_BERTIME_1 */ 739a0bf528SMauro Carvalho Chehab #define VIT_BERTIME_1 (0x39) 749a0bf528SMauro Carvalho Chehab 759a0bf528SMauro Carvalho Chehab /* 0x3A VIT_BERTIME_0 */ 769a0bf528SMauro Carvalho Chehab #define VIT_BERTIME_0 (0x3a) 779a0bf528SMauro Carvalho Chehab 789a0bf528SMauro Carvalho Chehab /* 0x38 OFDM_BERTimer *//* Use the alias registers */ 799a0bf528SMauro Carvalho Chehab #define A_VIT_BER_TIMER_0 (0x1D) 809a0bf528SMauro Carvalho Chehab 819a0bf528SMauro Carvalho Chehab /* 0x3A VIT_BER_TIMER_0 *//* Use the alias registers */ 829a0bf528SMauro Carvalho Chehab #define A_VIT_BER_0 (0x1B) 839a0bf528SMauro Carvalho Chehab 849a0bf528SMauro Carvalho Chehab /* 0x3B VIT_BER_1 */ 859a0bf528SMauro Carvalho Chehab #define VIT_BER_1 (0x3b) 869a0bf528SMauro Carvalho Chehab 879a0bf528SMauro Carvalho Chehab /* 0x3C VIT_BER_0 */ 889a0bf528SMauro Carvalho Chehab #define VIT_BER_0 (0x3c) 899a0bf528SMauro Carvalho Chehab 909a0bf528SMauro Carvalho Chehab /* 0x40 OFDM_COR_CTL */ 919a0bf528SMauro Carvalho Chehab #define OFDM_COR_CTL (0x40) 929a0bf528SMauro Carvalho Chehab #define COREACT (0x20) 939a0bf528SMauro Carvalho Chehab #define HOLDSM (0x10) 949a0bf528SMauro Carvalho Chehab #define WAIT_AGC (0x02) 959a0bf528SMauro Carvalho Chehab #define WAIT_SYR (0x03) 969a0bf528SMauro Carvalho Chehab 979a0bf528SMauro Carvalho Chehab /* 0x41 OFDM_COR_STAT */ 989a0bf528SMauro Carvalho Chehab #define OFDM_COR_STAT (0x41) 999a0bf528SMauro Carvalho Chehab #define COR_STATUS (0x0F) 1009a0bf528SMauro Carvalho Chehab #define MONITOR_TPS (0x06) 1019a0bf528SMauro Carvalho Chehab #define TPSLOCKED (0x40) 1029a0bf528SMauro Carvalho Chehab #define AGCLOCKED (0x10) 1039a0bf528SMauro Carvalho Chehab 1049a0bf528SMauro Carvalho Chehab /* 0x42 OFDM_COR_INTEN */ 1059a0bf528SMauro Carvalho Chehab #define OFDM_COR_INTEN (0x42) 1069a0bf528SMauro Carvalho Chehab #define TPSRCVBAD (0x04) 1079a0bf528SMauro Carvalho Chehab #define TPSRCVCHANGED (0x02) 1089a0bf528SMauro Carvalho Chehab #define TPSRCVUPDATE (0x01) 1099a0bf528SMauro Carvalho Chehab 1109a0bf528SMauro Carvalho Chehab /* 0x43 OFDM_COR_INSTAT */ 1119a0bf528SMauro Carvalho Chehab #define OFDM_COR_INSTAT (0x43) 1129a0bf528SMauro Carvalho Chehab 1139a0bf528SMauro Carvalho Chehab /* 0x44 OFDM_COR_MODEGUARD */ 1149a0bf528SMauro Carvalho Chehab #define OFDM_COR_MODEGUARD (0x44) 1159a0bf528SMauro Carvalho Chehab #define FORCEMODE (0x08) 1169a0bf528SMauro Carvalho Chehab #define FORCEMODE8K (0x04) 1179a0bf528SMauro Carvalho Chehab 1189a0bf528SMauro Carvalho Chehab /* 0x45 OFDM_AGC_CTL */ 1199a0bf528SMauro Carvalho Chehab #define OFDM_AGC_CTL (0x45) 1209a0bf528SMauro Carvalho Chehab #define INITIAL_AGC_BW (0x08) 1219a0bf528SMauro Carvalho Chehab #define AGCNEG (0x02) 1229a0bf528SMauro Carvalho Chehab #define AGCLAST (0x10) 1239a0bf528SMauro Carvalho Chehab 1249a0bf528SMauro Carvalho Chehab /* 0x48 OFDM_AGC_TARGET */ 1259a0bf528SMauro Carvalho Chehab #define OFDM_AGC_TARGET (0x48) 1269a0bf528SMauro Carvalho Chehab #define OFDM_AGC_TARGET_DEFAULT (0x28) 1279a0bf528SMauro Carvalho Chehab #define OFDM_AGC_TARGET_IMPULSE (0x38) 1289a0bf528SMauro Carvalho Chehab 1299a0bf528SMauro Carvalho Chehab /* 0x49 OFDM_AGC_GAIN_1 */ 1309a0bf528SMauro Carvalho Chehab #define OFDM_AGC_GAIN_1 (0x49) 1319a0bf528SMauro Carvalho Chehab 1329a0bf528SMauro Carvalho Chehab /* 0x4B OFDM_ITB_CTL */ 1339a0bf528SMauro Carvalho Chehab #define OFDM_ITB_CTL (0x4B) 1349a0bf528SMauro Carvalho Chehab #define ITBINV (0x01) 1359a0bf528SMauro Carvalho Chehab 1369a0bf528SMauro Carvalho Chehab /* 0x49 AGC_GAIN_1 */ 1379a0bf528SMauro Carvalho Chehab #define AGC_GAIN_1 (0x49) 1389a0bf528SMauro Carvalho Chehab 1399a0bf528SMauro Carvalho Chehab /* 0x4A AGC_GAIN_2 */ 1409a0bf528SMauro Carvalho Chehab #define AGC_GAIN_2 (0x4A) 1419a0bf528SMauro Carvalho Chehab 1429a0bf528SMauro Carvalho Chehab /* 0x4C OFDM_ITB_FREQ_1 */ 1439a0bf528SMauro Carvalho Chehab #define OFDM_ITB_FREQ_1 (0x4C) 1449a0bf528SMauro Carvalho Chehab 1459a0bf528SMauro Carvalho Chehab /* 0x4D OFDM_ITB_FREQ_2 */ 1469a0bf528SMauro Carvalho Chehab #define OFDM_ITB_FREQ_2 (0x4D) 1479a0bf528SMauro Carvalho Chehab 1489a0bf528SMauro Carvalho Chehab /* 0x4E OFDM_CAS_CTL */ 1499a0bf528SMauro Carvalho Chehab #define OFDM_CAS_CTL (0x4E) 1509a0bf528SMauro Carvalho Chehab #define ACSDIS (0x40) 1519a0bf528SMauro Carvalho Chehab #define CCSEN (0x80) 1529a0bf528SMauro Carvalho Chehab 1539a0bf528SMauro Carvalho Chehab /* 0x4F CAS_FREQ */ 1549a0bf528SMauro Carvalho Chehab #define CAS_FREQ (0x4F) 1559a0bf528SMauro Carvalho Chehab 1569a0bf528SMauro Carvalho Chehab /* 0x51 OFDM_SYR_CTL */ 1579a0bf528SMauro Carvalho Chehab #define OFDM_SYR_CTL (0x51) 1589a0bf528SMauro Carvalho Chehab #define SIXTH_ENABLE (0x80) 1599a0bf528SMauro Carvalho Chehab #define SYR_TRACKING_DISABLE (0x01) 1609a0bf528SMauro Carvalho Chehab 1619a0bf528SMauro Carvalho Chehab /* 0x52 OFDM_SYR_STAT */ 1629a0bf528SMauro Carvalho Chehab #define OFDM_SYR_STAT (0x52) 1639a0bf528SMauro Carvalho Chehab #define GI14_2K_SYR_LOCK (0x13) 1649a0bf528SMauro Carvalho Chehab #define GI14_8K_SYR_LOCK (0x17) 1659a0bf528SMauro Carvalho Chehab #define GI14_SYR_LOCK (0x10) 1669a0bf528SMauro Carvalho Chehab 1679a0bf528SMauro Carvalho Chehab /* 0x55 OFDM_SYR_OFFSET_1 */ 1689a0bf528SMauro Carvalho Chehab #define OFDM_SYR_OFFSET_1 (0x55) 1699a0bf528SMauro Carvalho Chehab 1709a0bf528SMauro Carvalho Chehab /* 0x56 OFDM_SYR_OFFSET_2 */ 1719a0bf528SMauro Carvalho Chehab #define OFDM_SYR_OFFSET_2 (0x56) 1729a0bf528SMauro Carvalho Chehab 1739a0bf528SMauro Carvalho Chehab /* 0x58 OFDM_SCR_CTL */ 1749a0bf528SMauro Carvalho Chehab #define OFDM_SCR_CTL (0x58) 1759a0bf528SMauro Carvalho Chehab #define SYR_ADJ_DECAY_MASK (0x70) 1769a0bf528SMauro Carvalho Chehab #define SYR_ADJ_DECAY (0x30) 1779a0bf528SMauro Carvalho Chehab 1789a0bf528SMauro Carvalho Chehab /* 0x59 OFDM_PPM_CTL_1 */ 1799a0bf528SMauro Carvalho Chehab #define OFDM_PPM_CTL_1 (0x59) 1809a0bf528SMauro Carvalho Chehab #define PPMMAX_MASK (0x30) 1819a0bf528SMauro Carvalho Chehab #define PPM256 (0x30) 1829a0bf528SMauro Carvalho Chehab 1839a0bf528SMauro Carvalho Chehab /* 0x5B OFDM_TRL_NOMINALRATE_1 */ 1849a0bf528SMauro Carvalho Chehab #define OFDM_TRL_NOMINALRATE_1 (0x5B) 1859a0bf528SMauro Carvalho Chehab 1869a0bf528SMauro Carvalho Chehab /* 0x5C OFDM_TRL_NOMINALRATE_2 */ 1879a0bf528SMauro Carvalho Chehab #define OFDM_TRL_NOMINALRATE_2 (0x5C) 1889a0bf528SMauro Carvalho Chehab 1899a0bf528SMauro Carvalho Chehab /* 0x5D OFDM_TRL_TIME_1 */ 1909a0bf528SMauro Carvalho Chehab #define OFDM_TRL_TIME_1 (0x5D) 1919a0bf528SMauro Carvalho Chehab 1929a0bf528SMauro Carvalho Chehab /* 0x60 OFDM_CRL_FREQ_1 */ 1939a0bf528SMauro Carvalho Chehab #define OFDM_CRL_FREQ_1 (0x60) 1949a0bf528SMauro Carvalho Chehab 1959a0bf528SMauro Carvalho Chehab /* 0x63 OFDM_CHC_CTL_1 */ 1969a0bf528SMauro Carvalho Chehab #define OFDM_CHC_CTL_1 (0x63) 1979a0bf528SMauro Carvalho Chehab #define MANMEAN1 (0xF0); 1989a0bf528SMauro Carvalho Chehab #define CHCFIR (0x01) 1999a0bf528SMauro Carvalho Chehab 2009a0bf528SMauro Carvalho Chehab /* 0x64 OFDM_CHC_SNR */ 2019a0bf528SMauro Carvalho Chehab #define OFDM_CHC_SNR (0x64) 2029a0bf528SMauro Carvalho Chehab 2039a0bf528SMauro Carvalho Chehab /* 0x65 OFDM_BDI_CTL */ 2049a0bf528SMauro Carvalho Chehab #define OFDM_BDI_CTL (0x65) 2059a0bf528SMauro Carvalho Chehab #define LP_SELECT (0x02) 2069a0bf528SMauro Carvalho Chehab 2079a0bf528SMauro Carvalho Chehab /* 0x67 OFDM_TPS_RCVD_1 */ 2089a0bf528SMauro Carvalho Chehab #define OFDM_TPS_RCVD_1 (0x67) 2099a0bf528SMauro Carvalho Chehab #define TPSFRAME (0x03) 2109a0bf528SMauro Carvalho Chehab 2119a0bf528SMauro Carvalho Chehab /* 0x68 OFDM_TPS_RCVD_2 */ 2129a0bf528SMauro Carvalho Chehab #define OFDM_TPS_RCVD_2 (0x68) 2139a0bf528SMauro Carvalho Chehab 2149a0bf528SMauro Carvalho Chehab /* 0x69 OFDM_TPS_RCVD_3 */ 2159a0bf528SMauro Carvalho Chehab #define OFDM_TPS_RCVD_3 (0x69) 2169a0bf528SMauro Carvalho Chehab 2179a0bf528SMauro Carvalho Chehab /* 0x6A OFDM_TPS_RCVD_4 */ 2189a0bf528SMauro Carvalho Chehab #define OFDM_TPS_RCVD_4 (0x6A) 2199a0bf528SMauro Carvalho Chehab 2209a0bf528SMauro Carvalho Chehab /* 0x6B OFDM_TPS_RESERVED_1 */ 2219a0bf528SMauro Carvalho Chehab #define OFDM_TPS_RESERVED_1 (0x6B) 2229a0bf528SMauro Carvalho Chehab 2239a0bf528SMauro Carvalho Chehab /* 0x6C OFDM_TPS_RESERVED_2 */ 2249a0bf528SMauro Carvalho Chehab #define OFDM_TPS_RESERVED_2 (0x6C) 2259a0bf528SMauro Carvalho Chehab 2269a0bf528SMauro Carvalho Chehab /* 0x73 OFDM_MSC_REV */ 2279a0bf528SMauro Carvalho Chehab #define OFDM_MSC_REV (0x73) 2289a0bf528SMauro Carvalho Chehab 2299a0bf528SMauro Carvalho Chehab /* 0x76 OFDM_SNR_CARRIER_2 */ 2309a0bf528SMauro Carvalho Chehab #define OFDM_SNR_CARRIER_2 (0x76) 2319a0bf528SMauro Carvalho Chehab #define MEAN_MASK (0x80) 2329a0bf528SMauro Carvalho Chehab #define MEANBIT (0x80) 2339a0bf528SMauro Carvalho Chehab 2349a0bf528SMauro Carvalho Chehab /* 0x80 ANALOG_CONTROL_0 */ 2359a0bf528SMauro Carvalho Chehab #define ANALOG_CONTROL_0 (0x80) 2369a0bf528SMauro Carvalho Chehab #define POWER_DOWN_ADC (0x40) 2379a0bf528SMauro Carvalho Chehab 2389a0bf528SMauro Carvalho Chehab /* 0x81 ENABLE_TUNER_IIC */ 2399a0bf528SMauro Carvalho Chehab #define ENABLE_TUNER_IIC (0x81) 2409a0bf528SMauro Carvalho Chehab #define ENABLE_TUNER_BIT (0x01) 2419a0bf528SMauro Carvalho Chehab 2429a0bf528SMauro Carvalho Chehab /* 0x82 EN_DMD_RACQ */ 2439a0bf528SMauro Carvalho Chehab #define EN_DMD_RACQ (0x82) 2449a0bf528SMauro Carvalho Chehab #define EN_DMD_RACQ_REG_VAL (0x81) 2459a0bf528SMauro Carvalho Chehab #define EN_DMD_RACQ_REG_VAL_14 (0x01) 2469a0bf528SMauro Carvalho Chehab 2479a0bf528SMauro Carvalho Chehab /* 0x84 SNR_COMMAND */ 2489a0bf528SMauro Carvalho Chehab #define SNR_COMMAND (0x84) 2499a0bf528SMauro Carvalho Chehab #define SNRStat (0x80) 2509a0bf528SMauro Carvalho Chehab 2519a0bf528SMauro Carvalho Chehab /* 0x85 SNRCARRIERNUMBER_LSB */ 2529a0bf528SMauro Carvalho Chehab #define SNRCARRIERNUMBER_LSB (0x85) 2539a0bf528SMauro Carvalho Chehab 2549a0bf528SMauro Carvalho Chehab /* 0x87 SNRMINTHRESHOLD_LSB */ 2559a0bf528SMauro Carvalho Chehab #define SNRMINTHRESHOLD_LSB (0x87) 2569a0bf528SMauro Carvalho Chehab 2579a0bf528SMauro Carvalho Chehab /* 0x89 SNR_PER_CARRIER_LSB */ 2589a0bf528SMauro Carvalho Chehab #define SNR_PER_CARRIER_LSB (0x89) 2599a0bf528SMauro Carvalho Chehab 2609a0bf528SMauro Carvalho Chehab /* 0x8B SNRBELOWTHRESHOLD_LSB */ 2619a0bf528SMauro Carvalho Chehab #define SNRBELOWTHRESHOLD_LSB (0x8B) 2629a0bf528SMauro Carvalho Chehab 2639a0bf528SMauro Carvalho Chehab /* 0x91 RF_AGC_VAL_1 */ 2649a0bf528SMauro Carvalho Chehab #define RF_AGC_VAL_1 (0x91) 2659a0bf528SMauro Carvalho Chehab 2669a0bf528SMauro Carvalho Chehab /* 0x92 RF_AGC_STATUS */ 2679a0bf528SMauro Carvalho Chehab #define RF_AGC_STATUS (0x92) 2689a0bf528SMauro Carvalho Chehab 2699a0bf528SMauro Carvalho Chehab /* 0x98 DIAG_CONFIG */ 2709a0bf528SMauro Carvalho Chehab #define DIAG_CONFIG (0x98) 2719a0bf528SMauro Carvalho Chehab #define DIAG_MASK (0x70) 2729a0bf528SMauro Carvalho Chehab #define TB_SET (0x10) 2739a0bf528SMauro Carvalho Chehab #define TRAN_SELECT (0x07) 2749a0bf528SMauro Carvalho Chehab #define SERIAL_SELECT (0x01) 2759a0bf528SMauro Carvalho Chehab 2769a0bf528SMauro Carvalho Chehab /* 0x99 SUB_DIAG_MODE_SEL */ 2779a0bf528SMauro Carvalho Chehab #define SUB_DIAG_MODE_SEL (0x99) 2789a0bf528SMauro Carvalho Chehab #define CLKINVERSION (0x01) 2799a0bf528SMauro Carvalho Chehab 2809a0bf528SMauro Carvalho Chehab /* 0x9A TS_FORMAT */ 2819a0bf528SMauro Carvalho Chehab #define TS_FORMAT (0x9A) 2829a0bf528SMauro Carvalho Chehab #define ERROR_SENSE (0x08) 2839a0bf528SMauro Carvalho Chehab #define VALID_SENSE (0x04) 2849a0bf528SMauro Carvalho Chehab #define SYNC_SENSE (0x02) 2859a0bf528SMauro Carvalho Chehab #define GATED_CLOCK (0x01) 2869a0bf528SMauro Carvalho Chehab 2879a0bf528SMauro Carvalho Chehab #define NXT6000ASICDEVICE (0x0b) 288