1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Driver for the MaxLinear MxL69x family of combo tuners/demods 4 * 5 * Copyright (C) 2020 Brad Love <brad@nextdimension.cc> 6 * 7 * based on code: 8 * Copyright (c) 2016 MaxLinear, Inc. All rights reserved 9 * which was released under GPL V2 10 */ 11 12 /***************************************************************************** 13 * Defines 14 ***************************************************************************** 15 */ 16 #define MXL_EAGLE_HOST_MSG_HEADER_SIZE 8 17 #define MXL_EAGLE_FW_MAX_SIZE_IN_KB 76 18 #define MXL_EAGLE_QAM_FFE_TAPS_LENGTH 16 19 #define MXL_EAGLE_QAM_SPUR_TAPS_LENGTH 32 20 #define MXL_EAGLE_QAM_DFE_TAPS_LENGTH 72 21 #define MXL_EAGLE_ATSC_FFE_TAPS_LENGTH 4096 22 #define MXL_EAGLE_ATSC_DFE_TAPS_LENGTH 384 23 #define MXL_EAGLE_VERSION_SIZE 5 /* A.B.C.D-RCx */ 24 #define MXL_EAGLE_FW_LOAD_TIME 50 25 26 #define MXL_EAGLE_FW_MAX_SIZE_IN_KB 76 27 #define MXL_EAGLE_FW_HEADER_SIZE 16 28 #define MXL_EAGLE_FW_SEGMENT_HEADER_SIZE 8 29 #define MXL_EAGLE_MAX_I2C_PACKET_SIZE 58 30 #define MXL_EAGLE_I2C_MHEADER_SIZE 6 31 #define MXL_EAGLE_I2C_PHEADER_SIZE 2 32 33 /* Enum of Eagle family devices */ 34 enum MXL_EAGLE_DEVICE_E { 35 MXL_EAGLE_DEVICE_691 = 1, /* Device Mxl691 */ 36 MXL_EAGLE_DEVICE_248 = 2, /* Device Mxl248 */ 37 MXL_EAGLE_DEVICE_692 = 3, /* Device Mxl692 */ 38 MXL_EAGLE_DEVICE_MAX, /* No such device */ 39 }; 40 41 #define VER_A 1 42 #define VER_B 1 43 #define VER_C 1 44 #define VER_D 3 45 #define VER_E 6 46 47 /* Enum of Host to Eagle I2C protocol opcodes */ 48 enum MXL_EAGLE_OPCODE_E { 49 /* DEVICE */ 50 MXL_EAGLE_OPCODE_DEVICE_DEMODULATOR_TYPE_SET, 51 MXL_EAGLE_OPCODE_DEVICE_MPEG_OUT_PARAMS_SET, 52 MXL_EAGLE_OPCODE_DEVICE_POWERMODE_SET, 53 MXL_EAGLE_OPCODE_DEVICE_GPIO_DIRECTION_SET, 54 MXL_EAGLE_OPCODE_DEVICE_GPO_LEVEL_SET, 55 MXL_EAGLE_OPCODE_DEVICE_INTR_MASK_SET, 56 MXL_EAGLE_OPCODE_DEVICE_IO_MUX_SET, 57 MXL_EAGLE_OPCODE_DEVICE_VERSION_GET, 58 MXL_EAGLE_OPCODE_DEVICE_STATUS_GET, 59 MXL_EAGLE_OPCODE_DEVICE_GPI_LEVEL_GET, 60 61 /* TUNER */ 62 MXL_EAGLE_OPCODE_TUNER_CHANNEL_TUNE_SET, 63 MXL_EAGLE_OPCODE_TUNER_LOCK_STATUS_GET, 64 MXL_EAGLE_OPCODE_TUNER_AGC_STATUS_GET, 65 66 /* ATSC */ 67 MXL_EAGLE_OPCODE_ATSC_INIT_SET, 68 MXL_EAGLE_OPCODE_ATSC_ACQUIRE_CARRIER_SET, 69 MXL_EAGLE_OPCODE_ATSC_STATUS_GET, 70 MXL_EAGLE_OPCODE_ATSC_ERROR_COUNTERS_GET, 71 MXL_EAGLE_OPCODE_ATSC_EQUALIZER_FILTER_DFE_TAPS_GET, 72 MXL_EAGLE_OPCODE_ATSC_EQUALIZER_FILTER_FFE_TAPS_GET, 73 74 /* QAM */ 75 MXL_EAGLE_OPCODE_QAM_PARAMS_SET, 76 MXL_EAGLE_OPCODE_QAM_RESTART_SET, 77 MXL_EAGLE_OPCODE_QAM_STATUS_GET, 78 MXL_EAGLE_OPCODE_QAM_ERROR_COUNTERS_GET, 79 MXL_EAGLE_OPCODE_QAM_CONSTELLATION_VALUE_GET, 80 MXL_EAGLE_OPCODE_QAM_EQUALIZER_FILTER_FFE_GET, 81 MXL_EAGLE_OPCODE_QAM_EQUALIZER_FILTER_SPUR_START_GET, 82 MXL_EAGLE_OPCODE_QAM_EQUALIZER_FILTER_SPUR_END_GET, 83 MXL_EAGLE_OPCODE_QAM_EQUALIZER_FILTER_DFE_TAPS_NUMBER_GET, 84 MXL_EAGLE_OPCODE_QAM_EQUALIZER_FILTER_DFE_START_GET, 85 MXL_EAGLE_OPCODE_QAM_EQUALIZER_FILTER_DFE_MIDDLE_GET, 86 MXL_EAGLE_OPCODE_QAM_EQUALIZER_FILTER_DFE_END_GET, 87 88 /* OOB */ 89 MXL_EAGLE_OPCODE_OOB_PARAMS_SET, 90 MXL_EAGLE_OPCODE_OOB_RESTART_SET, 91 MXL_EAGLE_OPCODE_OOB_ERROR_COUNTERS_GET, 92 MXL_EAGLE_OPCODE_OOB_STATUS_GET, 93 94 /* SMA */ 95 MXL_EAGLE_OPCODE_SMA_INIT_SET, 96 MXL_EAGLE_OPCODE_SMA_PARAMS_SET, 97 MXL_EAGLE_OPCODE_SMA_TRANSMIT_SET, 98 MXL_EAGLE_OPCODE_SMA_RECEIVE_GET, 99 100 /* DEBUG */ 101 MXL_EAGLE_OPCODE_INTERNAL, 102 103 MXL_EAGLE_OPCODE_MAX = 70, 104 }; 105 106 /* Enum of Host to Eagle I2C protocol opcodes */ 107 static const char * const MXL_EAGLE_OPCODE_STRING[] = { 108 /* DEVICE */ 109 "DEVICE_DEMODULATOR_TYPE_SET", 110 "DEVICE_MPEG_OUT_PARAMS_SET", 111 "DEVICE_POWERMODE_SET", 112 "DEVICE_GPIO_DIRECTION_SET", 113 "DEVICE_GPO_LEVEL_SET", 114 "DEVICE_INTR_MASK_SET", 115 "DEVICE_IO_MUX_SET", 116 "DEVICE_VERSION_GET", 117 "DEVICE_STATUS_GET", 118 "DEVICE_GPI_LEVEL_GET", 119 120 /* TUNER */ 121 "TUNER_CHANNEL_TUNE_SET", 122 "TUNER_LOCK_STATUS_GET", 123 "TUNER_AGC_STATUS_GET", 124 125 /* ATSC */ 126 "ATSC_INIT_SET", 127 "ATSC_ACQUIRE_CARRIER_SET", 128 "ATSC_STATUS_GET", 129 "ATSC_ERROR_COUNTERS_GET", 130 "ATSC_EQUALIZER_FILTER_DFE_TAPS_GET", 131 "ATSC_EQUALIZER_FILTER_FFE_TAPS_GET", 132 133 /* QAM */ 134 "QAM_PARAMS_SET", 135 "QAM_RESTART_SET", 136 "QAM_STATUS_GET", 137 "QAM_ERROR_COUNTERS_GET", 138 "QAM_CONSTELLATION_VALUE_GET", 139 "QAM_EQUALIZER_FILTER_FFE_GET", 140 "QAM_EQUALIZER_FILTER_SPUR_START_GET", 141 "QAM_EQUALIZER_FILTER_SPUR_END_GET", 142 "QAM_EQUALIZER_FILTER_DFE_TAPS_NUMBER_GET", 143 "QAM_EQUALIZER_FILTER_DFE_START_GET", 144 "QAM_EQUALIZER_FILTER_DFE_MIDDLE_GET", 145 "QAM_EQUALIZER_FILTER_DFE_END_GET", 146 147 /* OOB */ 148 "OOB_PARAMS_SET", 149 "OOB_RESTART_SET", 150 "OOB_ERROR_COUNTERS_GET", 151 "OOB_STATUS_GET", 152 153 /* SMA */ 154 "SMA_INIT_SET", 155 "SMA_PARAMS_SET", 156 "SMA_TRANSMIT_SET", 157 "SMA_RECEIVE_GET", 158 159 /* DEBUG */ 160 "INTERNAL", 161 }; 162 163 /* Enum of Callabck function types */ 164 enum MXL_EAGLE_CB_TYPE_E { 165 MXL_EAGLE_CB_FW_DOWNLOAD = 0, 166 }; 167 168 /* Enum of power supply types */ 169 enum MXL_EAGLE_POWER_SUPPLY_SOURCE_E { 170 MXL_EAGLE_POWER_SUPPLY_SOURCE_SINGLE, /* Single supply of 3.3V */ 171 MXL_EAGLE_POWER_SUPPLY_SOURCE_DUAL, /* Dual supply, 1.8V & 3.3V */ 172 }; 173 174 /* Enum of I/O pad drive modes */ 175 enum MXL_EAGLE_IO_MUX_DRIVE_MODE_E { 176 MXL_EAGLE_IO_MUX_DRIVE_MODE_1X, 177 MXL_EAGLE_IO_MUX_DRIVE_MODE_2X, 178 MXL_EAGLE_IO_MUX_DRIVE_MODE_3X, 179 MXL_EAGLE_IO_MUX_DRIVE_MODE_4X, 180 MXL_EAGLE_IO_MUX_DRIVE_MODE_5X, 181 MXL_EAGLE_IO_MUX_DRIVE_MODE_6X, 182 MXL_EAGLE_IO_MUX_DRIVE_MODE_7X, 183 MXL_EAGLE_IO_MUX_DRIVE_MODE_8X, 184 }; 185 186 /* Enum of demodulator types. Used for selection of demodulator 187 * type in relevant devices, e.g. ATSC vs. QAM in Mxl691 188 */ 189 enum MXL_EAGLE_DEMOD_TYPE_E { 190 MXL_EAGLE_DEMOD_TYPE_QAM, /* Mxl248 or Mxl692 */ 191 MXL_EAGLE_DEMOD_TYPE_OOB, /* Mxl248 only */ 192 MXL_EAGLE_DEMOD_TYPE_ATSC /* Mxl691 or Mxl692 */ 193 }; 194 195 /* Enum of power modes. Used for initial 196 * activation, or for activating sleep mode 197 */ 198 enum MXL_EAGLE_POWER_MODE_E { 199 MXL_EAGLE_POWER_MODE_SLEEP, 200 MXL_EAGLE_POWER_MODE_ACTIVE 201 }; 202 203 /* Enum of GPIOs, used in device GPIO APIs */ 204 enum MXL_EAGLE_GPIO_NUMBER_E { 205 MXL_EAGLE_GPIO_NUMBER_0, 206 MXL_EAGLE_GPIO_NUMBER_1, 207 MXL_EAGLE_GPIO_NUMBER_2, 208 MXL_EAGLE_GPIO_NUMBER_3, 209 MXL_EAGLE_GPIO_NUMBER_4, 210 MXL_EAGLE_GPIO_NUMBER_5, 211 MXL_EAGLE_GPIO_NUMBER_6 212 }; 213 214 /* Enum of GPIO directions, used in GPIO direction configuration API */ 215 enum MXL_EAGLE_GPIO_DIRECTION_E { 216 MXL_EAGLE_GPIO_DIRECTION_INPUT, 217 MXL_EAGLE_GPIO_DIRECTION_OUTPUT 218 }; 219 220 /* Enum of GPIO level, used in device GPIO APIs */ 221 enum MXL_EAGLE_GPIO_LEVEL_E { 222 MXL_EAGLE_GPIO_LEVEL_LOW, 223 MXL_EAGLE_GPIO_LEVEL_HIGH, 224 }; 225 226 /* Enum of I/O Mux function, used in device I/O mux configuration API */ 227 enum MXL_EAGLE_IOMUX_FUNCTION_E { 228 MXL_EAGLE_IOMUX_FUNC_FEC_LOCK, 229 MXL_EAGLE_IOMUX_FUNC_MERR, 230 }; 231 232 /* Enum of MPEG Data format, used in MPEG and OOB output configuration */ 233 enum MXL_EAGLE_MPEG_DATA_FORMAT_E { 234 MXL_EAGLE_DATA_SERIAL_LSB_1ST = 0, 235 MXL_EAGLE_DATA_SERIAL_MSB_1ST, 236 237 MXL_EAGLE_DATA_SYNC_WIDTH_BIT = 0, 238 MXL_EAGLE_DATA_SYNC_WIDTH_BYTE 239 }; 240 241 /* Enum of MPEG Clock format, used in MPEG and OOB output configuration */ 242 enum MXL_EAGLE_MPEG_CLOCK_FORMAT_E { 243 MXL_EAGLE_CLOCK_ACTIVE_HIGH = 0, 244 MXL_EAGLE_CLOCK_ACTIVE_LOW, 245 246 MXL_EAGLE_CLOCK_POSITIVE = 0, 247 MXL_EAGLE_CLOCK_NEGATIVE, 248 249 MXL_EAGLE_CLOCK_IN_PHASE = 0, 250 MXL_EAGLE_CLOCK_INVERTED, 251 }; 252 253 /* Enum of MPEG Clock speeds, used in MPEG output configuration */ 254 enum MXL_EAGLE_MPEG_CLOCK_RATE_E { 255 MXL_EAGLE_MPEG_CLOCK_54MHZ, 256 MXL_EAGLE_MPEG_CLOCK_40_5MHZ, 257 MXL_EAGLE_MPEG_CLOCK_27MHZ, 258 MXL_EAGLE_MPEG_CLOCK_13_5MHZ, 259 }; 260 261 /* Enum of Interrupt mask bit, used in host interrupt configuration */ 262 enum MXL_EAGLE_INTR_MASK_BITS_E { 263 MXL_EAGLE_INTR_MASK_DEMOD = 0, 264 MXL_EAGLE_INTR_MASK_SMA_RX = 1, 265 MXL_EAGLE_INTR_MASK_WDOG = 31 266 }; 267 268 /* Enum of QAM Demodulator type, used in QAM configuration */ 269 enum MXL_EAGLE_QAM_DEMOD_ANNEX_TYPE_E { 270 MXL_EAGLE_QAM_DEMOD_ANNEX_B, /* J.83B */ 271 MXL_EAGLE_QAM_DEMOD_ANNEX_A, /* DVB-C */ 272 }; 273 274 /* Enum of QAM Demodulator modulation, used in QAM configuration and status */ 275 enum MXL_EAGLE_QAM_DEMOD_QAM_TYPE_E { 276 MXL_EAGLE_QAM_DEMOD_QAM16, 277 MXL_EAGLE_QAM_DEMOD_QAM64, 278 MXL_EAGLE_QAM_DEMOD_QAM256, 279 MXL_EAGLE_QAM_DEMOD_QAM1024, 280 MXL_EAGLE_QAM_DEMOD_QAM32, 281 MXL_EAGLE_QAM_DEMOD_QAM128, 282 MXL_EAGLE_QAM_DEMOD_QPSK, 283 MXL_EAGLE_QAM_DEMOD_AUTO, 284 }; 285 286 /* Enum of Demodulator IQ setup, used in QAM, OOB configuration and status */ 287 enum MXL_EAGLE_IQ_FLIP_E { 288 MXL_EAGLE_DEMOD_IQ_NORMAL, 289 MXL_EAGLE_DEMOD_IQ_FLIPPED, 290 MXL_EAGLE_DEMOD_IQ_AUTO, 291 }; 292 293 /* Enum of OOB Demodulator symbol rates, used in OOB configuration */ 294 enum MXL_EAGLE_OOB_DEMOD_SYMB_RATE_E { 295 MXL_EAGLE_OOB_DEMOD_SYMB_RATE_0_772MHZ, /* ANSI/SCTE 55-2 0.772 MHz */ 296 MXL_EAGLE_OOB_DEMOD_SYMB_RATE_1_024MHZ, /* ANSI/SCTE 55-1 1.024 MHz */ 297 MXL_EAGLE_OOB_DEMOD_SYMB_RATE_1_544MHZ, /* ANSI/SCTE 55-2 1.544 MHz */ 298 }; 299 300 /* Enum of tuner channel tuning mode */ 301 enum MXL_EAGLE_TUNER_CHANNEL_TUNE_MODE_E { 302 MXL_EAGLE_TUNER_CHANNEL_TUNE_MODE_VIEW, /* Normal "view" mode */ 303 MXL_EAGLE_TUNER_CHANNEL_TUNE_MODE_SCAN, /* Fast "scan" mode */ 304 }; 305 306 /* Enum of tuner bandwidth */ 307 enum MXL_EAGLE_TUNER_BW_E { 308 MXL_EAGLE_TUNER_BW_6MHZ, 309 MXL_EAGLE_TUNER_BW_7MHZ, 310 MXL_EAGLE_TUNER_BW_8MHZ, 311 }; 312 313 /* Enum of tuner bandwidth */ 314 enum MXL_EAGLE_JUNCTION_TEMPERATURE_E { 315 MXL_EAGLE_JUNCTION_TEMPERATURE_BELOW_0_CELSIUS = 0, 316 MXL_EAGLE_JUNCTION_TEMPERATURE_BETWEEN_0_TO_14_CELSIUS = 1, 317 MXL_EAGLE_JUNCTION_TEMPERATURE_BETWEEN_14_TO_28_CELSIUS = 3, 318 MXL_EAGLE_JUNCTION_TEMPERATURE_BETWEEN_28_TO_42_CELSIUS = 2, 319 MXL_EAGLE_JUNCTION_TEMPERATURE_BETWEEN_42_TO_57_CELSIUS = 6, 320 MXL_EAGLE_JUNCTION_TEMPERATURE_BETWEEN_57_TO_71_CELSIUS = 7, 321 MXL_EAGLE_JUNCTION_TEMPERATURE_BETWEEN_71_TO_85_CELSIUS = 5, 322 MXL_EAGLE_JUNCTION_TEMPERATURE_ABOVE_85_CELSIUS = 4, 323 }; 324 325 /* Struct passed in optional callback used during FW download */ 326 struct MXL_EAGLE_FW_DOWNLOAD_CB_PAYLOAD_T { 327 u32 total_len; 328 u32 downloaded_len; 329 }; 330 331 /* Struct used of I2C protocol between host and Eagle, internal use only */ 332 struct __packed MXL_EAGLE_HOST_MSG_HEADER_T { 333 u8 opcode; 334 u8 seqnum; 335 u8 payload_size; 336 u8 status; 337 u32 checksum; 338 }; 339 340 /* Device version information struct */ 341 struct __packed MXL_EAGLE_DEV_VER_T { 342 u8 chip_id; 343 u8 firmware_ver[MXL_EAGLE_VERSION_SIZE]; 344 u8 mxlware_ver[MXL_EAGLE_VERSION_SIZE]; 345 }; 346 347 /* Xtal configuration struct */ 348 struct __packed MXL_EAGLE_DEV_XTAL_T { 349 u8 xtal_cap; /* accepted range is 1..31 pF. Default is 26 */ 350 u8 clk_out_enable; 351 u8 clk_out_div_enable; /* clock out freq is xtal freq / 6 */ 352 u8 xtal_sharing_enable; /* if enabled set xtal_cap to 25 pF */ 353 u8 xtal_calibration_enable; /* enable for master, disable for slave */ 354 }; 355 356 /* GPIO direction struct, internally used in GPIO configuration API */ 357 struct __packed MXL_EAGLE_DEV_GPIO_DIRECTION_T { 358 u8 gpio_number; 359 u8 gpio_direction; 360 }; 361 362 /* GPO level struct, internally used in GPIO configuration API */ 363 struct __packed MXL_EAGLE_DEV_GPO_LEVEL_T { 364 u8 gpio_number; 365 u8 gpo_level; 366 }; 367 368 /* Device Status struct */ 369 struct MXL_EAGLE_DEV_STATUS_T { 370 u8 temperature; 371 u8 demod_type; 372 u8 power_mode; 373 u8 cpu_utilization_percent; 374 }; 375 376 /* Device interrupt configuration struct */ 377 struct __packed MXL_EAGLE_DEV_INTR_CFG_T { 378 u32 intr_mask; 379 u8 edge_trigger; 380 u8 positive_trigger; 381 u8 global_enable_interrupt; 382 }; 383 384 /* MPEG pad drive parameters, used on MPEG output configuration */ 385 /* See MXL_EAGLE_IO_MUX_DRIVE_MODE_E */ 386 struct MXL_EAGLE_MPEG_PAD_DRIVE_T { 387 u8 pad_drv_mpeg_syn; 388 u8 pad_drv_mpeg_dat; 389 u8 pad_drv_mpeg_val; 390 u8 pad_drv_mpeg_clk; 391 }; 392 393 /* MPEGOUT parameter struct, used in MPEG output configuration */ 394 struct MXL_EAGLE_MPEGOUT_PARAMS_T { 395 u8 mpeg_parallel; 396 u8 msb_first; 397 u8 mpeg_sync_pulse_width; /* See MXL_EAGLE_MPEG_DATA_FORMAT_E */ 398 u8 mpeg_valid_pol; 399 u8 mpeg_sync_pol; 400 u8 mpeg_clk_pol; 401 u8 mpeg3wire_mode_enable; 402 u8 mpeg_clk_freq; 403 struct MXL_EAGLE_MPEG_PAD_DRIVE_T mpeg_pad_drv; 404 }; 405 406 /* QAM Demodulator parameters struct, used in QAM params configuration */ 407 struct __packed MXL_EAGLE_QAM_DEMOD_PARAMS_T { 408 u8 annex_type; 409 u8 qam_type; 410 u8 iq_flip; 411 u8 search_range_idx; 412 u8 spur_canceller_enable; 413 u32 symbol_rate_hz; 414 u32 symbol_rate_256qam_hz; 415 }; 416 417 /* QAM Demodulator status */ 418 struct MXL_EAGLE_QAM_DEMOD_STATUS_T { 419 u8 annex_type; 420 u8 qam_type; 421 u8 iq_flip; 422 u8 interleaver_depth_i; 423 u8 interleaver_depth_j; 424 u8 qam_locked; 425 u8 fec_locked; 426 u8 mpeg_locked; 427 u16 snr_db_tenths; 428 s16 timing_offset; 429 s32 carrier_offset_hz; 430 }; 431 432 /* QAM Demodulator error counters */ 433 struct MXL_EAGLE_QAM_DEMOD_ERROR_COUNTERS_T { 434 u32 corrected_code_words; 435 u32 uncorrected_code_words; 436 u32 total_code_words_received; 437 u32 corrected_bits; 438 u32 error_mpeg_frames; 439 u32 mpeg_frames_received; 440 u32 erasures; 441 }; 442 443 /* QAM Demodulator constellation point */ 444 struct MXL_EAGLE_QAM_DEMOD_CONSTELLATION_VAL_T { 445 s16 i_value[12]; 446 s16 q_value[12]; 447 }; 448 449 /* QAM Demodulator equalizer filter taps */ 450 struct MXL_EAGLE_QAM_DEMOD_EQU_FILTER_T { 451 s16 ffe_taps[MXL_EAGLE_QAM_FFE_TAPS_LENGTH]; 452 s16 spur_taps[MXL_EAGLE_QAM_SPUR_TAPS_LENGTH]; 453 s16 dfe_taps[MXL_EAGLE_QAM_DFE_TAPS_LENGTH]; 454 u8 ffe_leading_tap_index; 455 u8 dfe_taps_number; 456 }; 457 458 /* OOB Demodulator parameters struct, used in OOB params configuration */ 459 struct __packed MXL_EAGLE_OOB_DEMOD_PARAMS_T { 460 u8 symbol_rate; 461 u8 iq_flip; 462 u8 clk_pol; 463 }; 464 465 /* OOB Demodulator error counters */ 466 struct MXL_EAGLE_OOB_DEMOD_ERROR_COUNTERS_T { 467 u32 corrected_packets; 468 u32 uncorrected_packets; 469 u32 total_packets_received; 470 }; 471 472 /* OOB status */ 473 struct __packed MXL_EAGLE_OOB_DEMOD_STATUS_T { 474 u16 snr_db_tenths; 475 s16 timing_offset; 476 s32 carrier_offsetHz; 477 u8 qam_locked; 478 u8 fec_locked; 479 u8 mpeg_locked; 480 u8 retune_required; 481 u8 iq_flip; 482 }; 483 484 /* ATSC Demodulator status */ 485 struct __packed MXL_EAGLE_ATSC_DEMOD_STATUS_T { 486 s16 snr_db_tenths; 487 s16 timing_offset; 488 s32 carrier_offset_hz; 489 u8 frame_lock; 490 u8 atsc_lock; 491 u8 fec_lock; 492 }; 493 494 /* ATSC Demodulator error counters */ 495 struct MXL_EAGLE_ATSC_DEMOD_ERROR_COUNTERS_T { 496 u32 error_packets; 497 u32 total_packets; 498 u32 error_bytes; 499 }; 500 501 /* ATSC Demodulator equalizers filter taps */ 502 struct __packed MXL_EAGLE_ATSC_DEMOD_EQU_FILTER_T { 503 s16 ffe_taps[MXL_EAGLE_ATSC_FFE_TAPS_LENGTH]; 504 s8 dfe_taps[MXL_EAGLE_ATSC_DFE_TAPS_LENGTH]; 505 }; 506 507 /* Tuner AGC Status */ 508 struct __packed MXL_EAGLE_TUNER_AGC_STATUS_T { 509 u8 locked; 510 u16 raw_agc_gain; /* AGC gain [dB] = rawAgcGain / 2^6 */ 511 s16 rx_power_db_hundredths; 512 }; 513 514 /* Tuner channel tune parameters */ 515 struct __packed MXL_EAGLE_TUNER_CHANNEL_PARAMS_T { 516 u32 freq_hz; 517 u8 tune_mode; 518 u8 bandwidth; 519 }; 520 521 /* Tuner channel lock indications */ 522 struct __packed MXL_EAGLE_TUNER_LOCK_STATUS_T { 523 u8 rf_pll_locked; 524 u8 ref_pll_locked; 525 }; 526 527 /* Smart antenna parameters used in Smart antenna params configuration */ 528 struct __packed MXL_EAGLE_SMA_PARAMS_T { 529 u8 full_duplex_enable; 530 u8 rx_disable; 531 u8 idle_logic_high; 532 }; 533 534 /* Smart antenna message format */ 535 struct __packed MXL_EAGLE_SMA_MESSAGE_T { 536 u32 payload_bits; 537 u8 total_num_bits; 538 }; 539 540