1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2011-2013 MaxLinear, Inc. All rights reserved 4 * 5 * License type: GPLv2 6 * 7 * This program is free software; you can redistribute it and/or modify it under 8 * the terms of the GNU General Public License as published by the Free Software 9 * Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 13 * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. 14 * 15 * This program may alternatively be licensed under a proprietary license from 16 * MaxLinear, Inc. 17 * 18 */ 19 20 #ifndef __MXL58X_REGISTERS_H__ 21 #define __MXL58X_REGISTERS_H__ 22 23 #define HYDRA_INTR_STATUS_REG 0x80030008 24 #define HYDRA_INTR_MASK_REG 0x8003000C 25 26 #define HYDRA_CRYSTAL_SETTING 0x3FFFC5F0 /* 0 - 24 MHz & 1 - 27 MHz */ 27 #define HYDRA_CRYSTAL_CAP 0x3FFFEDA4 /* 0 - 24 MHz & 1 - 27 MHz */ 28 29 #define HYDRA_CPU_RESET_REG 0x8003003C 30 #define HYDRA_CPU_RESET_DATA 0x00000400 31 32 #define HYDRA_RESET_TRANSPORT_FIFO_REG 0x80030028 33 #define HYDRA_RESET_TRANSPORT_FIFO_DATA 0x00000000 34 35 #define HYDRA_RESET_BBAND_REG 0x80030024 36 #define HYDRA_RESET_BBAND_DATA 0x00000000 37 38 #define HYDRA_RESET_XBAR_REG 0x80030020 39 #define HYDRA_RESET_XBAR_DATA 0x00000000 40 41 #define HYDRA_MODULES_CLK_1_REG 0x80030014 42 #define HYDRA_DISABLE_CLK_1 0x00000000 43 44 #define HYDRA_MODULES_CLK_2_REG 0x8003001C 45 #define HYDRA_DISABLE_CLK_2 0x0000000B 46 47 #define HYDRA_PRCM_ROOT_CLK_REG 0x80030018 48 #define HYDRA_PRCM_ROOT_CLK_DISABLE 0x00000000 49 50 #define HYDRA_CPU_RESET_CHECK_REG 0x80030008 51 #define HYDRA_CPU_RESET_CHECK_OFFSET 0x40000000 /* <bit 30> */ 52 53 #define HYDRA_SKU_ID_REG 0x90000190 54 55 #define FW_DL_SIGN_ADDR 0x3FFFEAE0 56 57 /* Register to check if FW is running or not */ 58 #define HYDRA_HEAR_BEAT 0x3FFFEDDC 59 60 /* Firmware version */ 61 #define HYDRA_FIRMWARE_VERSION 0x3FFFEDB8 62 #define HYDRA_FW_RC_VERSION 0x3FFFCFAC 63 64 /* Firmware patch version */ 65 #define HYDRA_FIRMWARE_PATCH_VERSION 0x3FFFEDC2 66 67 /* SOC operating temperature in C */ 68 #define HYDRA_TEMPARATURE 0x3FFFEDB4 69 70 /* Demod & Tuner status registers */ 71 /* Demod 0 status base address */ 72 #define HYDRA_DEMOD_0_BASE_ADDR 0x3FFFC64C 73 74 /* Tuner 0 status base address */ 75 #define HYDRA_TUNER_0_BASE_ADDR 0x3FFFCE4C 76 77 #define POWER_FROM_ADCRSSI_READBACK 0x3FFFEB6C 78 79 /* Macros to determine base address of respective demod or tuner */ 80 #define HYDRA_DMD_STATUS_OFFSET(demodID) ((demodID) * 0x100) 81 #define HYDRA_TUNER_STATUS_OFFSET(tunerID) ((tunerID) * 0x40) 82 83 /* Demod status address offset from respective demod's base address */ 84 #define HYDRA_DMD_AGC_DIG_LEVEL_ADDR_OFFSET 0x3FFFC64C 85 #define HYDRA_DMD_LOCK_STATUS_ADDR_OFFSET 0x3FFFC650 86 #define HYDRA_DMD_ACQ_STATUS_ADDR_OFFSET 0x3FFFC654 87 88 #define HYDRA_DMD_STANDARD_ADDR_OFFSET 0x3FFFC658 89 #define HYDRA_DMD_SPECTRUM_INVERSION_ADDR_OFFSET 0x3FFFC65C 90 #define HYDRA_DMD_SPECTRUM_ROLL_OFF_ADDR_OFFSET 0x3FFFC660 91 #define HYDRA_DMD_SYMBOL_RATE_ADDR_OFFSET 0x3FFFC664 92 #define HYDRA_DMD_MODULATION_SCHEME_ADDR_OFFSET 0x3FFFC668 93 #define HYDRA_DMD_FEC_CODE_RATE_ADDR_OFFSET 0x3FFFC66C 94 95 #define HYDRA_DMD_SNR_ADDR_OFFSET 0x3FFFC670 96 #define HYDRA_DMD_FREQ_OFFSET_ADDR_OFFSET 0x3FFFC674 97 #define HYDRA_DMD_CTL_FREQ_OFFSET_ADDR_OFFSET 0x3FFFC678 98 #define HYDRA_DMD_STR_FREQ_OFFSET_ADDR_OFFSET 0x3FFFC67C 99 #define HYDRA_DMD_FTL_FREQ_OFFSET_ADDR_OFFSET 0x3FFFC680 100 #define HYDRA_DMD_STR_NBC_SYNC_LOCK_ADDR_OFFSET 0x3FFFC684 101 #define HYDRA_DMD_CYCLE_SLIP_COUNT_ADDR_OFFSET 0x3FFFC688 102 103 #define HYDRA_DMD_DISPLAY_I_ADDR_OFFSET 0x3FFFC68C 104 #define HYDRA_DMD_DISPLAY_Q_ADDR_OFFSET 0x3FFFC68E 105 106 #define HYDRA_DMD_DVBS2_CRC_ERRORS_ADDR_OFFSET 0x3FFFC690 107 #define HYDRA_DMD_DVBS2_PER_COUNT_ADDR_OFFSET 0x3FFFC694 108 #define HYDRA_DMD_DVBS2_PER_WINDOW_ADDR_OFFSET 0x3FFFC698 109 110 #define HYDRA_DMD_DVBS_CORR_RS_ERRORS_ADDR_OFFSET 0x3FFFC69C 111 #define HYDRA_DMD_DVBS_UNCORR_RS_ERRORS_ADDR_OFFSET 0x3FFFC6A0 112 #define HYDRA_DMD_DVBS_BER_COUNT_ADDR_OFFSET 0x3FFFC6A4 113 #define HYDRA_DMD_DVBS_BER_WINDOW_ADDR_OFFSET 0x3FFFC6A8 114 115 /* Debug-purpose DVB-S DMD 0 */ 116 #define HYDRA_DMD_DVBS_1ST_CORR_RS_ERRORS_ADDR_OFFSET 0x3FFFC6C8 /* corrected RS Errors: 1st iteration */ 117 #define HYDRA_DMD_DVBS_1ST_UNCORR_RS_ERRORS_ADDR_OFFSET 0x3FFFC6CC /* uncorrected RS Errors: 1st iteration */ 118 #define HYDRA_DMD_DVBS_BER_COUNT_1ST_ADDR_OFFSET 0x3FFFC6D0 119 #define HYDRA_DMD_DVBS_BER_WINDOW_1ST_ADDR_OFFSET 0x3FFFC6D4 120 121 #define HYDRA_DMD_TUNER_ID_ADDR_OFFSET 0x3FFFC6AC 122 #define HYDRA_DMD_DVBS2_PILOT_ON_OFF_ADDR_OFFSET 0x3FFFC6B0 123 #define HYDRA_DMD_FREQ_SEARCH_RANGE_KHZ_ADDR_OFFSET 0x3FFFC6B4 124 #define HYDRA_DMD_STATUS_LOCK_ADDR_OFFSET 0x3FFFC6B8 125 #define HYDRA_DMD_STATUS_CENTER_FREQ_IN_KHZ_ADDR 0x3FFFC704 126 #define HYDRA_DMD_STATUS_INPUT_POWER_ADDR 0x3FFFC708 127 128 /* DVB-S new scaled_BER_count for a new BER API, see HYDRA-1343 "DVB-S post viterbi information" */ 129 #define DMD0_STATUS_DVBS_1ST_SCALED_BER_COUNT_ADDR 0x3FFFC710 /* DMD 0: 1st iteration BER count scaled by HYDRA_BER_COUNT_SCALING_FACTOR */ 130 #define DMD0_STATUS_DVBS_SCALED_BER_COUNT_ADDR 0x3FFFC714 /* DMD 0: 2nd iteration BER count scaled by HYDRA_BER_COUNT_SCALING_FACTOR */ 131 132 #define DMD0_SPECTRUM_MIN_GAIN_STATUS 0x3FFFC73C 133 #define DMD0_SPECTRUM_MIN_GAIN_WB_SAGC_VALUE 0x3FFFC740 134 #define DMD0_SPECTRUM_MIN_GAIN_NB_SAGC_VALUE 0x3FFFC744 135 136 #define HYDRA_DMD_STATUS_END_ADDR_OFFSET 0x3FFFC748 137 138 /* Tuner status address offset from respective tuners's base address */ 139 #define HYDRA_TUNER_DEMOD_ID_ADDR_OFFSET 0x3FFFCE4C 140 #define HYDRA_TUNER_AGC_LOCK_OFFSET 0x3FFFCE50 141 #define HYDRA_TUNER_SPECTRUM_STATUS_OFFSET 0x3FFFCE54 142 #define HYDRA_TUNER_SPECTRUM_BIN_SIZE_OFFSET 0x3FFFCE58 143 #define HYDRA_TUNER_SPECTRUM_ADDRESS_OFFSET 0x3FFFCE5C 144 #define HYDRA_TUNER_ENABLE_COMPLETE 0x3FFFEB78 145 146 #define HYDRA_DEMOD_STATUS_LOCK(devId, demodId) write_register(devId, (HYDRA_DMD_STATUS_LOCK_ADDR_OFFSET + HYDRA_DMD_STATUS_OFFSET(demodId)), MXL_YES) 147 #define HYDRA_DEMOD_STATUS_UNLOCK(devId, demodId) write_register(devId, (HYDRA_DMD_STATUS_LOCK_ADDR_OFFSET + HYDRA_DMD_STATUS_OFFSET(demodId)), MXL_NO) 148 149 #define HYDRA_VERSION 0x3FFFEDB8 150 #define HYDRA_DEMOD0_VERSION 0x3FFFEDBC 151 #define HYDRA_DEMOD1_VERSION 0x3FFFEDC0 152 #define HYDRA_DEMOD2_VERSION 0x3FFFEDC4 153 #define HYDRA_DEMOD3_VERSION 0x3FFFEDC8 154 #define HYDRA_DEMOD4_VERSION 0x3FFFEDCC 155 #define HYDRA_DEMOD5_VERSION 0x3FFFEDD0 156 #define HYDRA_DEMOD6_VERSION 0x3FFFEDD4 157 #define HYDRA_DEMOD7_VERSION 0x3FFFEDD8 158 #define HYDRA_HEAR_BEAT 0x3FFFEDDC 159 #define HYDRA_SKU_MGMT 0x3FFFEBC0 160 161 #define MXL_HYDRA_FPGA_A_ADDRESS 0x91C00000 162 #define MXL_HYDRA_FPGA_B_ADDRESS 0x91D00000 163 164 /* TS control base address */ 165 #define HYDRA_TS_CTRL_BASE_ADDR 0x90700000 166 167 #define MPEG_MUX_MODE_SLICE0_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x08) 168 169 #define MPEG_MUX_MODE_SLICE1_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x08) 170 171 #define PID_BANK_SEL_SLICE0_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x190) 172 #define PID_BANK_SEL_SLICE1_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x1B0) 173 174 #define MPEG_CLK_GATED_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x20) 175 176 #define MPEG_CLK_ALWAYS_ON_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x1D4) 177 178 #define HYDRA_REGULAR_PID_BANK_A_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x190) 179 180 #define HYDRA_FIXED_PID_BANK_A_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x190) 181 182 #define HYDRA_REGULAR_PID_BANK_B_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x1B0) 183 184 #define HYDRA_FIXED_PID_BANK_B_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x1B0) 185 186 #define FIXED_PID_TBL_REG_ADDRESS_0 (HYDRA_TS_CTRL_BASE_ADDR + 0x9000) 187 #define FIXED_PID_TBL_REG_ADDRESS_1 (HYDRA_TS_CTRL_BASE_ADDR + 0x9100) 188 #define FIXED_PID_TBL_REG_ADDRESS_2 (HYDRA_TS_CTRL_BASE_ADDR + 0x9200) 189 #define FIXED_PID_TBL_REG_ADDRESS_3 (HYDRA_TS_CTRL_BASE_ADDR + 0x9300) 190 191 #define FIXED_PID_TBL_REG_ADDRESS_4 (HYDRA_TS_CTRL_BASE_ADDR + 0xB000) 192 #define FIXED_PID_TBL_REG_ADDRESS_5 (HYDRA_TS_CTRL_BASE_ADDR + 0xB100) 193 #define FIXED_PID_TBL_REG_ADDRESS_6 (HYDRA_TS_CTRL_BASE_ADDR + 0xB200) 194 #define FIXED_PID_TBL_REG_ADDRESS_7 (HYDRA_TS_CTRL_BASE_ADDR + 0xB300) 195 196 #define REGULAR_PID_TBL_REG_ADDRESS_0 (HYDRA_TS_CTRL_BASE_ADDR + 0x8000) 197 #define REGULAR_PID_TBL_REG_ADDRESS_1 (HYDRA_TS_CTRL_BASE_ADDR + 0x8200) 198 #define REGULAR_PID_TBL_REG_ADDRESS_2 (HYDRA_TS_CTRL_BASE_ADDR + 0x8400) 199 #define REGULAR_PID_TBL_REG_ADDRESS_3 (HYDRA_TS_CTRL_BASE_ADDR + 0x8600) 200 201 #define REGULAR_PID_TBL_REG_ADDRESS_4 (HYDRA_TS_CTRL_BASE_ADDR + 0xA000) 202 #define REGULAR_PID_TBL_REG_ADDRESS_5 (HYDRA_TS_CTRL_BASE_ADDR + 0xA200) 203 #define REGULAR_PID_TBL_REG_ADDRESS_6 (HYDRA_TS_CTRL_BASE_ADDR + 0xA400) 204 #define REGULAR_PID_TBL_REG_ADDRESS_7 (HYDRA_TS_CTRL_BASE_ADDR + 0xA600) 205 206 /***************************************************************************/ 207 208 #define PAD_MUX_GPIO_00_SYNC_BASEADDR 0x90000188 209 210 211 #define PAD_MUX_UART_RX_C_PINMUX_BASEADDR 0x9000001C 212 213 #define XPT_PACKET_GAP_MIN_BASEADDR 0x90700044 214 #define XPT_NCO_COUNT_BASEADDR 0x90700238 215 216 #define XPT_NCO_COUNT_BASEADDR1 0x9070023C 217 218 /* V2 DigRF status register */ 219 220 #define XPT_PID_BASEADDR 0x90708000 221 222 #define XPT_PID_REMAP_BASEADDR 0x90708004 223 224 #define XPT_KNOWN_PID_BASEADDR 0x90709000 225 226 #define XPT_PID_BASEADDR1 0x9070A000 227 228 #define XPT_PID_REMAP_BASEADDR1 0x9070A004 229 230 #define XPT_KNOWN_PID_BASEADDR1 0x9070B000 231 232 #define XPT_BERT_LOCK_BASEADDR 0x907000B8 233 234 #define XPT_BERT_BASEADDR 0x907000BC 235 236 #define XPT_BERT_INVERT_BASEADDR 0x907000C0 237 238 #define XPT_BERT_HEADER_BASEADDR 0x907000C4 239 240 #define XPT_BERT_BASEADDR1 0x907000C8 241 242 #define XPT_BERT_BIT_COUNT0_BASEADDR 0x907000CC 243 244 #define XPT_BERT_BIT_COUNT0_BASEADDR1 0x907000D0 245 246 #define XPT_BERT_BIT_COUNT1_BASEADDR 0x907000D4 247 248 #define XPT_BERT_BIT_COUNT1_BASEADDR1 0x907000D8 249 250 #define XPT_BERT_BIT_COUNT2_BASEADDR 0x907000DC 251 252 #define XPT_BERT_BIT_COUNT2_BASEADDR1 0x907000E0 253 254 #define XPT_BERT_BIT_COUNT3_BASEADDR 0x907000E4 255 256 #define XPT_BERT_BIT_COUNT3_BASEADDR1 0x907000E8 257 258 #define XPT_BERT_BIT_COUNT4_BASEADDR 0x907000EC 259 260 #define XPT_BERT_BIT_COUNT4_BASEADDR1 0x907000F0 261 262 #define XPT_BERT_BIT_COUNT5_BASEADDR 0x907000F4 263 264 #define XPT_BERT_BIT_COUNT5_BASEADDR1 0x907000F8 265 266 #define XPT_BERT_BIT_COUNT6_BASEADDR 0x907000FC 267 268 #define XPT_BERT_BIT_COUNT6_BASEADDR1 0x90700100 269 270 #define XPT_BERT_BIT_COUNT7_BASEADDR 0x90700104 271 272 #define XPT_BERT_BIT_COUNT7_BASEADDR1 0x90700108 273 274 #define XPT_BERT_ERR_COUNT0_BASEADDR 0x9070010C 275 276 #define XPT_BERT_ERR_COUNT0_BASEADDR1 0x90700110 277 278 #define XPT_BERT_ERR_COUNT1_BASEADDR 0x90700114 279 280 #define XPT_BERT_ERR_COUNT1_BASEADDR1 0x90700118 281 282 #define XPT_BERT_ERR_COUNT2_BASEADDR 0x9070011C 283 284 #define XPT_BERT_ERR_COUNT2_BASEADDR1 0x90700120 285 286 #define XPT_BERT_ERR_COUNT3_BASEADDR 0x90700124 287 288 #define XPT_BERT_ERR_COUNT3_BASEADDR1 0x90700128 289 290 #define XPT_BERT_ERR_COUNT4_BASEADDR 0x9070012C 291 292 #define XPT_BERT_ERR_COUNT4_BASEADDR1 0x90700130 293 294 #define XPT_BERT_ERR_COUNT5_BASEADDR 0x90700134 295 296 #define XPT_BERT_ERR_COUNT5_BASEADDR1 0x90700138 297 298 #define XPT_BERT_ERR_COUNT6_BASEADDR 0x9070013C 299 300 #define XPT_BERT_ERR_COUNT6_BASEADDR1 0x90700140 301 302 #define XPT_BERT_ERR_COUNT7_BASEADDR 0x90700144 303 304 #define XPT_BERT_ERR_COUNT7_BASEADDR1 0x90700148 305 306 #define XPT_BERT_ERROR_BASEADDR 0x9070014C 307 308 #define XPT_BERT_ANALYZER_BASEADDR 0x90700150 309 310 #define XPT_BERT_ANALYZER_BASEADDR1 0x90700154 311 312 #define XPT_BERT_ANALYZER_BASEADDR2 0x90700158 313 314 #define XPT_BERT_ANALYZER_BASEADDR3 0x9070015C 315 316 #define XPT_BERT_ANALYZER_BASEADDR4 0x90700160 317 318 #define XPT_BERT_ANALYZER_BASEADDR5 0x90700164 319 320 #define XPT_BERT_ANALYZER_BASEADDR6 0x90700168 321 322 #define XPT_BERT_ANALYZER_BASEADDR7 0x9070016C 323 324 #define XPT_BERT_ANALYZER_BASEADDR8 0x90700170 325 326 #define XPT_BERT_ANALYZER_BASEADDR9 0x90700174 327 328 #define XPT_DMD0_BASEADDR 0x9070024C 329 330 /* V2 AGC Gain Freeze & step */ 331 #define DBG_ENABLE_DISABLE_AGC (0x3FFFCF60) /* 1: DISABLE, 0:ENABLE */ 332 #define WB_DFE0_DFE_FB_RF1_BASEADDR 0x903004A4 333 334 #define WB_DFE1_DFE_FB_RF1_BASEADDR 0x904004A4 335 336 #define WB_DFE2_DFE_FB_RF1_BASEADDR 0x905004A4 337 338 #define WB_DFE3_DFE_FB_RF1_BASEADDR 0x906004A4 339 340 #define AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR 0x90200104 341 342 #define AFE_REG_AFE_REG_SPARE_BASEADDR 0x902000A0 343 344 #define AFE_REG_AFE_REG_SPARE_BASEADDR1 0x902000B4 345 346 #define AFE_REG_AFE_REG_SPARE_BASEADDR2 0x902000C4 347 348 #define AFE_REG_AFE_REG_SPARE_BASEADDR3 0x902000D4 349 350 #define WB_DFE0_DFE_FB_AGC_BASEADDR 0x90300498 351 352 #define WB_DFE1_DFE_FB_AGC_BASEADDR 0x90400498 353 354 #define WB_DFE2_DFE_FB_AGC_BASEADDR 0x90500498 355 356 #define WB_DFE3_DFE_FB_AGC_BASEADDR 0x90600498 357 358 #define WDT_WD_INT_BASEADDR 0x8002000C 359 360 #define FSK_TX_FTM_BASEADDR 0x80090000 361 362 #define FSK_TX_FTM_TX_CNT_BASEADDR 0x80090018 363 364 #define AFE_REG_D2A_FSK_BIAS_BASEADDR 0x90200040 365 366 #define DMD_TEI_BASEADDR 0x3FFFEBE0 367 368 #endif /* __MXL58X_REGISTERS_H__ */ 369