1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the MaxLinear MxL5xx family of tuners/demods 4 * 5 * Copyright (C) 2014-2015 Ralph Metzler <rjkm@metzlerbros.de> 6 * Marcus Metzler <mocm@metzlerbros.de> 7 * developed for Digital Devices GmbH 8 * 9 * based on code: 10 * Copyright (c) 2011-2013 MaxLinear, Inc. All rights reserved 11 * which was released under GPL V2 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License 15 * version 2, as published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 */ 22 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/moduleparam.h> 26 #include <linux/init.h> 27 #include <linux/delay.h> 28 #include <linux/firmware.h> 29 #include <linux/i2c.h> 30 #include <linux/mutex.h> 31 #include <linux/vmalloc.h> 32 #include <asm/div64.h> 33 #include <asm/unaligned.h> 34 35 #include <media/dvb_frontend.h> 36 #include "mxl5xx.h" 37 #include "mxl5xx_regs.h" 38 #include "mxl5xx_defs.h" 39 40 #define BYTE0(v) ((v >> 0) & 0xff) 41 #define BYTE1(v) ((v >> 8) & 0xff) 42 #define BYTE2(v) ((v >> 16) & 0xff) 43 #define BYTE3(v) ((v >> 24) & 0xff) 44 45 static LIST_HEAD(mxllist); 46 47 struct mxl_base { 48 struct list_head mxllist; 49 struct list_head mxls; 50 51 u8 adr; 52 struct i2c_adapter *i2c; 53 54 u32 count; 55 u32 type; 56 u32 sku_type; 57 u32 chipversion; 58 u32 clock; 59 u32 fwversion; 60 61 u8 *ts_map; 62 u8 can_clkout; 63 u8 chan_bond; 64 u8 demod_num; 65 u8 tuner_num; 66 67 unsigned long next_tune; 68 69 struct mutex i2c_lock; 70 struct mutex status_lock; 71 struct mutex tune_lock; 72 73 u8 buf[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN]; 74 75 u32 cmd_size; 76 u8 cmd_data[MAX_CMD_DATA]; 77 }; 78 79 struct mxl { 80 struct list_head mxl; 81 82 struct mxl_base *base; 83 struct dvb_frontend fe; 84 struct device *i2cdev; 85 u32 demod; 86 u32 tuner; 87 u32 tuner_in_use; 88 u8 xbar[3]; 89 90 unsigned long tune_time; 91 }; 92 93 static void convert_endian(u8 flag, u32 size, u8 *d) 94 { 95 u32 i; 96 97 if (!flag) 98 return; 99 for (i = 0; i < (size & ~3); i += 4) { 100 d[i + 0] ^= d[i + 3]; 101 d[i + 3] ^= d[i + 0]; 102 d[i + 0] ^= d[i + 3]; 103 104 d[i + 1] ^= d[i + 2]; 105 d[i + 2] ^= d[i + 1]; 106 d[i + 1] ^= d[i + 2]; 107 } 108 109 switch (size & 3) { 110 case 0: 111 case 1: 112 /* do nothing */ 113 break; 114 case 2: 115 d[i + 0] ^= d[i + 1]; 116 d[i + 1] ^= d[i + 0]; 117 d[i + 0] ^= d[i + 1]; 118 break; 119 120 case 3: 121 d[i + 0] ^= d[i + 2]; 122 d[i + 2] ^= d[i + 0]; 123 d[i + 0] ^= d[i + 2]; 124 break; 125 } 126 127 } 128 129 static int i2c_write(struct i2c_adapter *adap, u8 adr, 130 u8 *data, u32 len) 131 { 132 struct i2c_msg msg = {.addr = adr, .flags = 0, 133 .buf = data, .len = len}; 134 135 return (i2c_transfer(adap, &msg, 1) == 1) ? 0 : -1; 136 } 137 138 static int i2c_read(struct i2c_adapter *adap, u8 adr, 139 u8 *data, u32 len) 140 { 141 struct i2c_msg msg = {.addr = adr, .flags = I2C_M_RD, 142 .buf = data, .len = len}; 143 144 return (i2c_transfer(adap, &msg, 1) == 1) ? 0 : -1; 145 } 146 147 static int i2cread(struct mxl *state, u8 *data, int len) 148 { 149 return i2c_read(state->base->i2c, state->base->adr, data, len); 150 } 151 152 static int i2cwrite(struct mxl *state, u8 *data, int len) 153 { 154 return i2c_write(state->base->i2c, state->base->adr, data, len); 155 } 156 157 static int read_register_unlocked(struct mxl *state, u32 reg, u32 *val) 158 { 159 int stat; 160 u8 data[MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE] = { 161 MXL_HYDRA_PLID_REG_READ, 0x04, 162 GET_BYTE(reg, 0), GET_BYTE(reg, 1), 163 GET_BYTE(reg, 2), GET_BYTE(reg, 3), 164 }; 165 166 stat = i2cwrite(state, data, 167 MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE); 168 if (stat) 169 dev_err(state->i2cdev, "i2c read error 1\n"); 170 if (!stat) 171 stat = i2cread(state, (u8 *) val, 172 MXL_HYDRA_REG_SIZE_IN_BYTES); 173 le32_to_cpus(val); 174 if (stat) 175 dev_err(state->i2cdev, "i2c read error 2\n"); 176 return stat; 177 } 178 179 #define DMA_I2C_INTERRUPT_ADDR 0x8000011C 180 #define DMA_INTR_PROT_WR_CMP 0x08 181 182 static int send_command(struct mxl *state, u32 size, u8 *buf) 183 { 184 int stat; 185 u32 val, count = 10; 186 187 mutex_lock(&state->base->i2c_lock); 188 if (state->base->fwversion > 0x02010109) { 189 read_register_unlocked(state, DMA_I2C_INTERRUPT_ADDR, &val); 190 if (DMA_INTR_PROT_WR_CMP & val) 191 dev_info(state->i2cdev, "%s busy\n", __func__); 192 while ((DMA_INTR_PROT_WR_CMP & val) && --count) { 193 mutex_unlock(&state->base->i2c_lock); 194 usleep_range(1000, 2000); 195 mutex_lock(&state->base->i2c_lock); 196 read_register_unlocked(state, DMA_I2C_INTERRUPT_ADDR, 197 &val); 198 } 199 if (!count) { 200 dev_info(state->i2cdev, "%s busy\n", __func__); 201 mutex_unlock(&state->base->i2c_lock); 202 return -EBUSY; 203 } 204 } 205 stat = i2cwrite(state, buf, size); 206 mutex_unlock(&state->base->i2c_lock); 207 return stat; 208 } 209 210 static int write_register(struct mxl *state, u32 reg, u32 val) 211 { 212 int stat; 213 u8 data[MXL_HYDRA_REG_WRITE_LEN] = { 214 MXL_HYDRA_PLID_REG_WRITE, 0x08, 215 BYTE0(reg), BYTE1(reg), BYTE2(reg), BYTE3(reg), 216 BYTE0(val), BYTE1(val), BYTE2(val), BYTE3(val), 217 }; 218 mutex_lock(&state->base->i2c_lock); 219 stat = i2cwrite(state, data, sizeof(data)); 220 mutex_unlock(&state->base->i2c_lock); 221 if (stat) 222 dev_err(state->i2cdev, "i2c write error\n"); 223 return stat; 224 } 225 226 static int write_firmware_block(struct mxl *state, 227 u32 reg, u32 size, u8 *reg_data_ptr) 228 { 229 int stat; 230 u8 *buf = state->base->buf; 231 232 mutex_lock(&state->base->i2c_lock); 233 buf[0] = MXL_HYDRA_PLID_REG_WRITE; 234 buf[1] = size + 4; 235 buf[2] = GET_BYTE(reg, 0); 236 buf[3] = GET_BYTE(reg, 1); 237 buf[4] = GET_BYTE(reg, 2); 238 buf[5] = GET_BYTE(reg, 3); 239 memcpy(&buf[6], reg_data_ptr, size); 240 stat = i2cwrite(state, buf, 241 MXL_HYDRA_I2C_HDR_SIZE + 242 MXL_HYDRA_REG_SIZE_IN_BYTES + size); 243 mutex_unlock(&state->base->i2c_lock); 244 if (stat) 245 dev_err(state->i2cdev, "fw block write failed\n"); 246 return stat; 247 } 248 249 static int read_register(struct mxl *state, u32 reg, u32 *val) 250 { 251 int stat; 252 u8 data[MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE] = { 253 MXL_HYDRA_PLID_REG_READ, 0x04, 254 GET_BYTE(reg, 0), GET_BYTE(reg, 1), 255 GET_BYTE(reg, 2), GET_BYTE(reg, 3), 256 }; 257 258 mutex_lock(&state->base->i2c_lock); 259 stat = i2cwrite(state, data, 260 MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE); 261 if (stat) 262 dev_err(state->i2cdev, "i2c read error 1\n"); 263 if (!stat) 264 stat = i2cread(state, (u8 *) val, 265 MXL_HYDRA_REG_SIZE_IN_BYTES); 266 mutex_unlock(&state->base->i2c_lock); 267 le32_to_cpus(val); 268 if (stat) 269 dev_err(state->i2cdev, "i2c read error 2\n"); 270 return stat; 271 } 272 273 static int read_register_block(struct mxl *state, u32 reg, u32 size, u8 *data) 274 { 275 int stat; 276 u8 *buf = state->base->buf; 277 278 mutex_lock(&state->base->i2c_lock); 279 280 buf[0] = MXL_HYDRA_PLID_REG_READ; 281 buf[1] = size + 4; 282 buf[2] = GET_BYTE(reg, 0); 283 buf[3] = GET_BYTE(reg, 1); 284 buf[4] = GET_BYTE(reg, 2); 285 buf[5] = GET_BYTE(reg, 3); 286 stat = i2cwrite(state, buf, 287 MXL_HYDRA_I2C_HDR_SIZE + MXL_HYDRA_REG_SIZE_IN_BYTES); 288 if (!stat) { 289 stat = i2cread(state, data, size); 290 convert_endian(MXL_ENABLE_BIG_ENDIAN, size, data); 291 } 292 mutex_unlock(&state->base->i2c_lock); 293 return stat; 294 } 295 296 static int read_by_mnemonic(struct mxl *state, 297 u32 reg, u8 lsbloc, u8 numofbits, u32 *val) 298 { 299 u32 data = 0, mask = 0; 300 int stat; 301 302 stat = read_register(state, reg, &data); 303 if (stat) 304 return stat; 305 mask = MXL_GET_REG_MASK_32(lsbloc, numofbits); 306 data &= mask; 307 data >>= lsbloc; 308 *val = data; 309 return 0; 310 } 311 312 313 static int update_by_mnemonic(struct mxl *state, 314 u32 reg, u8 lsbloc, u8 numofbits, u32 val) 315 { 316 u32 data, mask; 317 int stat; 318 319 stat = read_register(state, reg, &data); 320 if (stat) 321 return stat; 322 mask = MXL_GET_REG_MASK_32(lsbloc, numofbits); 323 data = (data & ~mask) | ((val << lsbloc) & mask); 324 stat = write_register(state, reg, data); 325 return stat; 326 } 327 328 static int firmware_is_alive(struct mxl *state) 329 { 330 u32 hb0, hb1; 331 332 if (read_register(state, HYDRA_HEAR_BEAT, &hb0)) 333 return 0; 334 msleep(20); 335 if (read_register(state, HYDRA_HEAR_BEAT, &hb1)) 336 return 0; 337 if (hb1 == hb0) 338 return 0; 339 return 1; 340 } 341 342 static int init(struct dvb_frontend *fe) 343 { 344 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 345 346 /* init fe stats */ 347 p->strength.len = 1; 348 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 349 p->cnr.len = 1; 350 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 351 p->pre_bit_error.len = 1; 352 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 353 p->pre_bit_count.len = 1; 354 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 355 p->post_bit_error.len = 1; 356 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 357 p->post_bit_count.len = 1; 358 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 359 360 return 0; 361 } 362 363 static void release(struct dvb_frontend *fe) 364 { 365 struct mxl *state = fe->demodulator_priv; 366 367 list_del(&state->mxl); 368 /* Release one frontend, two more shall take its place! */ 369 state->base->count--; 370 if (state->base->count == 0) { 371 list_del(&state->base->mxllist); 372 kfree(state->base); 373 } 374 kfree(state); 375 } 376 377 static enum dvbfe_algo get_algo(struct dvb_frontend *fe) 378 { 379 return DVBFE_ALGO_HW; 380 } 381 382 static u32 gold2root(u32 gold) 383 { 384 u32 x, g, tmp = gold; 385 386 if (tmp >= 0x3ffff) 387 tmp = 0; 388 for (g = 0, x = 1; g < tmp; g++) 389 x = (((x ^ (x >> 7)) & 1) << 17) | (x >> 1); 390 return x; 391 } 392 393 static int cfg_scrambler(struct mxl *state, u32 gold) 394 { 395 u32 root; 396 u8 buf[26] = { 397 MXL_HYDRA_PLID_CMD_WRITE, 24, 398 0, MXL_HYDRA_DEMOD_SCRAMBLE_CODE_CMD, 0, 0, 399 state->demod, 0, 0, 0, 400 0, 0, 0, 0, 0, 0, 0, 0, 401 0, 0, 0, 0, 1, 0, 0, 0, 402 }; 403 404 root = gold2root(gold); 405 406 buf[25] = (root >> 24) & 0xff; 407 buf[24] = (root >> 16) & 0xff; 408 buf[23] = (root >> 8) & 0xff; 409 buf[22] = root & 0xff; 410 411 return send_command(state, sizeof(buf), buf); 412 } 413 414 static int cfg_demod_abort_tune(struct mxl *state) 415 { 416 struct MXL_HYDRA_DEMOD_ABORT_TUNE_T abort_tune_cmd; 417 u8 cmd_size = sizeof(abort_tune_cmd); 418 u8 cmd_buff[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN]; 419 420 abort_tune_cmd.demod_id = state->demod; 421 BUILD_HYDRA_CMD(MXL_HYDRA_ABORT_TUNE_CMD, MXL_CMD_WRITE, 422 cmd_size, &abort_tune_cmd, cmd_buff); 423 return send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE, 424 &cmd_buff[0]); 425 } 426 427 static int send_master_cmd(struct dvb_frontend *fe, 428 struct dvb_diseqc_master_cmd *cmd) 429 { 430 /*struct mxl *state = fe->demodulator_priv;*/ 431 432 return 0; /*CfgDemodAbortTune(state);*/ 433 } 434 435 static int set_parameters(struct dvb_frontend *fe) 436 { 437 struct mxl *state = fe->demodulator_priv; 438 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 439 struct MXL_HYDRA_DEMOD_PARAM_T demod_chan_cfg; 440 u8 cmd_size = sizeof(demod_chan_cfg); 441 u8 cmd_buff[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN]; 442 u32 srange = 10; 443 int stat; 444 445 if (p->frequency < 950000 || p->frequency > 2150000) 446 return -EINVAL; 447 if (p->symbol_rate < 1000000 || p->symbol_rate > 45000000) 448 return -EINVAL; 449 450 /* CfgDemodAbortTune(state); */ 451 452 switch (p->delivery_system) { 453 case SYS_DSS: 454 demod_chan_cfg.standard = MXL_HYDRA_DSS; 455 demod_chan_cfg.roll_off = MXL_HYDRA_ROLLOFF_AUTO; 456 break; 457 case SYS_DVBS: 458 srange = p->symbol_rate / 1000000; 459 if (srange > 10) 460 srange = 10; 461 demod_chan_cfg.standard = MXL_HYDRA_DVBS; 462 demod_chan_cfg.roll_off = MXL_HYDRA_ROLLOFF_0_35; 463 demod_chan_cfg.modulation_scheme = MXL_HYDRA_MOD_QPSK; 464 demod_chan_cfg.pilots = MXL_HYDRA_PILOTS_OFF; 465 break; 466 case SYS_DVBS2: 467 demod_chan_cfg.standard = MXL_HYDRA_DVBS2; 468 demod_chan_cfg.roll_off = MXL_HYDRA_ROLLOFF_AUTO; 469 demod_chan_cfg.modulation_scheme = MXL_HYDRA_MOD_AUTO; 470 demod_chan_cfg.pilots = MXL_HYDRA_PILOTS_AUTO; 471 cfg_scrambler(state, p->scrambling_sequence_index); 472 break; 473 default: 474 return -EINVAL; 475 } 476 demod_chan_cfg.tuner_index = state->tuner; 477 demod_chan_cfg.demod_index = state->demod; 478 demod_chan_cfg.frequency_in_hz = p->frequency * 1000; 479 demod_chan_cfg.symbol_rate_in_hz = p->symbol_rate; 480 demod_chan_cfg.max_carrier_offset_in_mhz = srange; 481 demod_chan_cfg.spectrum_inversion = MXL_HYDRA_SPECTRUM_AUTO; 482 demod_chan_cfg.fec_code_rate = MXL_HYDRA_FEC_AUTO; 483 484 mutex_lock(&state->base->tune_lock); 485 if (time_after(jiffies + msecs_to_jiffies(200), 486 state->base->next_tune)) 487 while (time_before(jiffies, state->base->next_tune)) 488 usleep_range(10000, 11000); 489 state->base->next_tune = jiffies + msecs_to_jiffies(100); 490 state->tuner_in_use = state->tuner; 491 BUILD_HYDRA_CMD(MXL_HYDRA_DEMOD_SET_PARAM_CMD, MXL_CMD_WRITE, 492 cmd_size, &demod_chan_cfg, cmd_buff); 493 stat = send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE, 494 &cmd_buff[0]); 495 mutex_unlock(&state->base->tune_lock); 496 return stat; 497 } 498 499 static int enable_tuner(struct mxl *state, u32 tuner, u32 enable); 500 501 static int sleep(struct dvb_frontend *fe) 502 { 503 struct mxl *state = fe->demodulator_priv; 504 struct mxl *p; 505 506 cfg_demod_abort_tune(state); 507 if (state->tuner_in_use != 0xffffffff) { 508 mutex_lock(&state->base->tune_lock); 509 state->tuner_in_use = 0xffffffff; 510 list_for_each_entry(p, &state->base->mxls, mxl) { 511 if (p->tuner_in_use == state->tuner) 512 break; 513 } 514 if (&p->mxl == &state->base->mxls) 515 enable_tuner(state, state->tuner, 0); 516 mutex_unlock(&state->base->tune_lock); 517 } 518 return 0; 519 } 520 521 static int read_snr(struct dvb_frontend *fe) 522 { 523 struct mxl *state = fe->demodulator_priv; 524 int stat; 525 u32 reg_data = 0; 526 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 527 528 mutex_lock(&state->base->status_lock); 529 HYDRA_DEMOD_STATUS_LOCK(state, state->demod); 530 stat = read_register(state, (HYDRA_DMD_SNR_ADDR_OFFSET + 531 HYDRA_DMD_STATUS_OFFSET(state->demod)), 532 ®_data); 533 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod); 534 mutex_unlock(&state->base->status_lock); 535 536 p->cnr.stat[0].scale = FE_SCALE_DECIBEL; 537 p->cnr.stat[0].svalue = (s16)reg_data * 10; 538 539 return stat; 540 } 541 542 static int read_ber(struct dvb_frontend *fe) 543 { 544 struct mxl *state = fe->demodulator_priv; 545 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 546 u32 reg[8]; 547 548 mutex_lock(&state->base->status_lock); 549 HYDRA_DEMOD_STATUS_LOCK(state, state->demod); 550 read_register_block(state, 551 (HYDRA_DMD_DVBS_1ST_CORR_RS_ERRORS_ADDR_OFFSET + 552 HYDRA_DMD_STATUS_OFFSET(state->demod)), 553 (4 * sizeof(u32)), 554 (u8 *) ®[0]); 555 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod); 556 557 switch (p->delivery_system) { 558 case SYS_DSS: 559 case SYS_DVBS: 560 p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; 561 p->pre_bit_error.stat[0].uvalue = reg[2]; 562 p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; 563 p->pre_bit_count.stat[0].uvalue = reg[3]; 564 break; 565 default: 566 break; 567 } 568 569 read_register_block(state, 570 (HYDRA_DMD_DVBS2_CRC_ERRORS_ADDR_OFFSET + 571 HYDRA_DMD_STATUS_OFFSET(state->demod)), 572 (7 * sizeof(u32)), 573 (u8 *) ®[0]); 574 575 switch (p->delivery_system) { 576 case SYS_DSS: 577 case SYS_DVBS: 578 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; 579 p->post_bit_error.stat[0].uvalue = reg[5]; 580 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; 581 p->post_bit_count.stat[0].uvalue = reg[6]; 582 break; 583 case SYS_DVBS2: 584 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; 585 p->post_bit_error.stat[0].uvalue = reg[1]; 586 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; 587 p->post_bit_count.stat[0].uvalue = reg[2]; 588 break; 589 default: 590 break; 591 } 592 593 mutex_unlock(&state->base->status_lock); 594 595 return 0; 596 } 597 598 static int read_signal_strength(struct dvb_frontend *fe) 599 { 600 struct mxl *state = fe->demodulator_priv; 601 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 602 int stat; 603 u32 reg_data = 0; 604 605 mutex_lock(&state->base->status_lock); 606 HYDRA_DEMOD_STATUS_LOCK(state, state->demod); 607 stat = read_register(state, (HYDRA_DMD_STATUS_INPUT_POWER_ADDR + 608 HYDRA_DMD_STATUS_OFFSET(state->demod)), 609 ®_data); 610 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod); 611 mutex_unlock(&state->base->status_lock); 612 613 p->strength.stat[0].scale = FE_SCALE_DECIBEL; 614 p->strength.stat[0].svalue = (s16) reg_data * 10; /* fix scale */ 615 616 return stat; 617 } 618 619 static int read_status(struct dvb_frontend *fe, enum fe_status *status) 620 { 621 struct mxl *state = fe->demodulator_priv; 622 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 623 u32 reg_data = 0; 624 625 mutex_lock(&state->base->status_lock); 626 HYDRA_DEMOD_STATUS_LOCK(state, state->demod); 627 read_register(state, (HYDRA_DMD_LOCK_STATUS_ADDR_OFFSET + 628 HYDRA_DMD_STATUS_OFFSET(state->demod)), 629 ®_data); 630 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod); 631 mutex_unlock(&state->base->status_lock); 632 633 *status = (reg_data == 1) ? 0x1f : 0; 634 635 /* signal statistics */ 636 637 /* signal strength is always available */ 638 read_signal_strength(fe); 639 640 if (*status & FE_HAS_CARRIER) 641 read_snr(fe); 642 else 643 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 644 645 if (*status & FE_HAS_SYNC) 646 read_ber(fe); 647 else { 648 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 649 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 650 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 651 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 652 } 653 654 return 0; 655 } 656 657 static int tune(struct dvb_frontend *fe, bool re_tune, 658 unsigned int mode_flags, 659 unsigned int *delay, enum fe_status *status) 660 { 661 struct mxl *state = fe->demodulator_priv; 662 int r = 0; 663 664 *delay = HZ / 2; 665 if (re_tune) { 666 r = set_parameters(fe); 667 if (r) 668 return r; 669 state->tune_time = jiffies; 670 } 671 672 return read_status(fe, status); 673 } 674 675 static enum fe_code_rate conv_fec(enum MXL_HYDRA_FEC_E fec) 676 { 677 enum fe_code_rate fec2fec[11] = { 678 FEC_NONE, FEC_1_2, FEC_3_5, FEC_2_3, 679 FEC_3_4, FEC_4_5, FEC_5_6, FEC_6_7, 680 FEC_7_8, FEC_8_9, FEC_9_10 681 }; 682 683 if (fec > MXL_HYDRA_FEC_9_10) 684 return FEC_NONE; 685 return fec2fec[fec]; 686 } 687 688 static int get_frontend(struct dvb_frontend *fe, 689 struct dtv_frontend_properties *p) 690 { 691 struct mxl *state = fe->demodulator_priv; 692 u32 reg_data[MXL_DEMOD_CHAN_PARAMS_BUFF_SIZE]; 693 u32 freq; 694 695 mutex_lock(&state->base->status_lock); 696 HYDRA_DEMOD_STATUS_LOCK(state, state->demod); 697 read_register_block(state, 698 (HYDRA_DMD_STANDARD_ADDR_OFFSET + 699 HYDRA_DMD_STATUS_OFFSET(state->demod)), 700 (MXL_DEMOD_CHAN_PARAMS_BUFF_SIZE * 4), /* 25 * 4 bytes */ 701 (u8 *) ®_data[0]); 702 /* read demod channel parameters */ 703 read_register_block(state, 704 (HYDRA_DMD_STATUS_CENTER_FREQ_IN_KHZ_ADDR + 705 HYDRA_DMD_STATUS_OFFSET(state->demod)), 706 (4), /* 4 bytes */ 707 (u8 *) &freq); 708 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod); 709 mutex_unlock(&state->base->status_lock); 710 711 dev_dbg(state->i2cdev, "freq=%u delsys=%u srate=%u\n", 712 freq * 1000, reg_data[DMD_STANDARD_ADDR], 713 reg_data[DMD_SYMBOL_RATE_ADDR]); 714 p->symbol_rate = reg_data[DMD_SYMBOL_RATE_ADDR]; 715 p->frequency = freq; 716 /* 717 * p->delivery_system = 718 * (MXL_HYDRA_BCAST_STD_E) regData[DMD_STANDARD_ADDR]; 719 * p->inversion = 720 * (MXL_HYDRA_SPECTRUM_E) regData[DMD_SPECTRUM_INVERSION_ADDR]; 721 * freqSearchRangeKHz = 722 * (regData[DMD_FREQ_SEARCH_RANGE_IN_KHZ_ADDR]); 723 */ 724 725 p->fec_inner = conv_fec(reg_data[DMD_FEC_CODE_RATE_ADDR]); 726 switch (p->delivery_system) { 727 case SYS_DSS: 728 break; 729 case SYS_DVBS2: 730 switch ((enum MXL_HYDRA_PILOTS_E) 731 reg_data[DMD_DVBS2_PILOT_ON_OFF_ADDR]) { 732 case MXL_HYDRA_PILOTS_OFF: 733 p->pilot = PILOT_OFF; 734 break; 735 case MXL_HYDRA_PILOTS_ON: 736 p->pilot = PILOT_ON; 737 break; 738 default: 739 break; 740 } 741 fallthrough; 742 case SYS_DVBS: 743 switch ((enum MXL_HYDRA_MODULATION_E) 744 reg_data[DMD_MODULATION_SCHEME_ADDR]) { 745 case MXL_HYDRA_MOD_QPSK: 746 p->modulation = QPSK; 747 break; 748 case MXL_HYDRA_MOD_8PSK: 749 p->modulation = PSK_8; 750 break; 751 default: 752 break; 753 } 754 switch ((enum MXL_HYDRA_ROLLOFF_E) 755 reg_data[DMD_SPECTRUM_ROLL_OFF_ADDR]) { 756 case MXL_HYDRA_ROLLOFF_0_20: 757 p->rolloff = ROLLOFF_20; 758 break; 759 case MXL_HYDRA_ROLLOFF_0_35: 760 p->rolloff = ROLLOFF_35; 761 break; 762 case MXL_HYDRA_ROLLOFF_0_25: 763 p->rolloff = ROLLOFF_25; 764 break; 765 default: 766 break; 767 } 768 break; 769 default: 770 return -EINVAL; 771 } 772 return 0; 773 } 774 775 static int set_input(struct dvb_frontend *fe, int input) 776 { 777 struct mxl *state = fe->demodulator_priv; 778 779 state->tuner = input; 780 return 0; 781 } 782 783 static const struct dvb_frontend_ops mxl_ops = { 784 .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS }, 785 .info = { 786 .name = "MaxLinear MxL5xx DVB-S/S2 tuner-demodulator", 787 .frequency_min_hz = 300 * MHz, 788 .frequency_max_hz = 2350 * MHz, 789 .symbol_rate_min = 1000000, 790 .symbol_rate_max = 45000000, 791 .caps = FE_CAN_INVERSION_AUTO | 792 FE_CAN_FEC_AUTO | 793 FE_CAN_QPSK | 794 FE_CAN_2G_MODULATION 795 }, 796 .init = init, 797 .release = release, 798 .get_frontend_algo = get_algo, 799 .tune = tune, 800 .read_status = read_status, 801 .sleep = sleep, 802 .get_frontend = get_frontend, 803 .diseqc_send_master_cmd = send_master_cmd, 804 }; 805 806 static struct mxl_base *match_base(struct i2c_adapter *i2c, u8 adr) 807 { 808 struct mxl_base *p; 809 810 list_for_each_entry(p, &mxllist, mxllist) 811 if (p->i2c == i2c && p->adr == adr) 812 return p; 813 return NULL; 814 } 815 816 static void cfg_dev_xtal(struct mxl *state, u32 freq, u32 cap, u32 enable) 817 { 818 if (state->base->can_clkout || !enable) 819 update_by_mnemonic(state, 0x90200054, 23, 1, enable); 820 821 if (freq == 24000000) 822 write_register(state, HYDRA_CRYSTAL_SETTING, 0); 823 else 824 write_register(state, HYDRA_CRYSTAL_SETTING, 1); 825 826 write_register(state, HYDRA_CRYSTAL_CAP, cap); 827 } 828 829 static u32 get_big_endian(u8 num_of_bits, const u8 buf[]) 830 { 831 u32 ret_value = 0; 832 833 switch (num_of_bits) { 834 case 24: 835 ret_value = (((u32) buf[0]) << 16) | 836 (((u32) buf[1]) << 8) | buf[2]; 837 break; 838 case 32: 839 ret_value = (((u32) buf[0]) << 24) | 840 (((u32) buf[1]) << 16) | 841 (((u32) buf[2]) << 8) | buf[3]; 842 break; 843 default: 844 break; 845 } 846 847 return ret_value; 848 } 849 850 static int write_fw_segment(struct mxl *state, 851 u32 mem_addr, u32 total_size, u8 *data_ptr) 852 { 853 int status; 854 u32 data_count = 0; 855 u32 size = 0; 856 u32 orig_size = 0; 857 u8 *w_buf_ptr = NULL; 858 u32 block_size = ((MXL_HYDRA_OEM_MAX_BLOCK_WRITE_LENGTH - 859 (MXL_HYDRA_I2C_HDR_SIZE + 860 MXL_HYDRA_REG_SIZE_IN_BYTES)) / 4) * 4; 861 u8 w_msg_buffer[MXL_HYDRA_OEM_MAX_BLOCK_WRITE_LENGTH - 862 (MXL_HYDRA_I2C_HDR_SIZE + MXL_HYDRA_REG_SIZE_IN_BYTES)]; 863 864 do { 865 size = orig_size = (((u32)(data_count + block_size)) > total_size) ? 866 (total_size - data_count) : block_size; 867 868 if (orig_size & 3) 869 size = (orig_size + 4) & ~3; 870 w_buf_ptr = &w_msg_buffer[0]; 871 memset((void *) w_buf_ptr, 0, size); 872 memcpy((void *) w_buf_ptr, (void *) data_ptr, orig_size); 873 convert_endian(1, size, w_buf_ptr); 874 status = write_firmware_block(state, mem_addr, size, w_buf_ptr); 875 if (status) 876 return status; 877 data_count += size; 878 mem_addr += size; 879 data_ptr += size; 880 } while (data_count < total_size); 881 882 return status; 883 } 884 885 static int do_firmware_download(struct mxl *state, u8 *mbin_buffer_ptr, 886 u32 mbin_buffer_size) 887 888 { 889 int status; 890 u32 index = 0; 891 u32 seg_length = 0; 892 u32 seg_address = 0; 893 struct MBIN_FILE_T *mbin_ptr = (struct MBIN_FILE_T *)mbin_buffer_ptr; 894 struct MBIN_SEGMENT_T *segment_ptr; 895 enum MXL_BOOL_E xcpu_fw_flag = MXL_FALSE; 896 897 if (mbin_ptr->header.id != MBIN_FILE_HEADER_ID) { 898 dev_err(state->i2cdev, "%s: Invalid file header ID (%c)\n", 899 __func__, mbin_ptr->header.id); 900 return -EINVAL; 901 } 902 status = write_register(state, FW_DL_SIGN_ADDR, 0); 903 if (status) 904 return status; 905 segment_ptr = (struct MBIN_SEGMENT_T *) (&mbin_ptr->data[0]); 906 for (index = 0; index < mbin_ptr->header.num_segments; index++) { 907 if (segment_ptr->header.id != MBIN_SEGMENT_HEADER_ID) { 908 dev_err(state->i2cdev, "%s: Invalid segment header ID (%c)\n", 909 __func__, segment_ptr->header.id); 910 return -EINVAL; 911 } 912 seg_length = get_big_endian(24, 913 &(segment_ptr->header.len24[0])); 914 seg_address = get_big_endian(32, 915 &(segment_ptr->header.address[0])); 916 917 if (state->base->type == MXL_HYDRA_DEVICE_568) { 918 if ((((seg_address & 0x90760000) == 0x90760000) || 919 ((seg_address & 0x90740000) == 0x90740000)) && 920 (xcpu_fw_flag == MXL_FALSE)) { 921 update_by_mnemonic(state, 0x8003003C, 0, 1, 1); 922 msleep(200); 923 write_register(state, 0x90720000, 0); 924 usleep_range(10000, 11000); 925 xcpu_fw_flag = MXL_TRUE; 926 } 927 status = write_fw_segment(state, seg_address, 928 seg_length, 929 (u8 *) segment_ptr->data); 930 } else { 931 if (((seg_address & 0x90760000) != 0x90760000) && 932 ((seg_address & 0x90740000) != 0x90740000)) 933 status = write_fw_segment(state, seg_address, 934 seg_length, (u8 *) segment_ptr->data); 935 } 936 if (status) 937 return status; 938 segment_ptr = (struct MBIN_SEGMENT_T *) 939 &(segment_ptr->data[((seg_length + 3) / 4) * 4]); 940 } 941 return status; 942 } 943 944 static int check_fw(struct mxl *state, u8 *mbin, u32 mbin_len) 945 { 946 struct MBIN_FILE_HEADER_T *fh = (struct MBIN_FILE_HEADER_T *) mbin; 947 u32 flen = (fh->image_size24[0] << 16) | 948 (fh->image_size24[1] << 8) | fh->image_size24[2]; 949 u8 *fw, cs = 0; 950 u32 i; 951 952 if (fh->id != 'M' || fh->fmt_version != '1' || flen > 0x3FFF0) { 953 dev_info(state->i2cdev, "Invalid FW Header\n"); 954 return -1; 955 } 956 fw = mbin + sizeof(struct MBIN_FILE_HEADER_T); 957 for (i = 0; i < flen; i += 1) 958 cs += fw[i]; 959 if (cs != fh->image_checksum) { 960 dev_info(state->i2cdev, "Invalid FW Checksum\n"); 961 return -1; 962 } 963 return 0; 964 } 965 966 static int firmware_download(struct mxl *state, u8 *mbin, u32 mbin_len) 967 { 968 int status; 969 u32 reg_data = 0; 970 struct MXL_HYDRA_SKU_COMMAND_T dev_sku_cfg; 971 u8 cmd_size = sizeof(struct MXL_HYDRA_SKU_COMMAND_T); 972 u8 cmd_buff[sizeof(struct MXL_HYDRA_SKU_COMMAND_T) + 6]; 973 974 if (check_fw(state, mbin, mbin_len)) 975 return -1; 976 977 /* put CPU into reset */ 978 status = update_by_mnemonic(state, 0x8003003C, 0, 1, 0); 979 if (status) 980 return status; 981 usleep_range(1000, 2000); 982 983 /* Reset TX FIFO's, BBAND, XBAR */ 984 status = write_register(state, HYDRA_RESET_TRANSPORT_FIFO_REG, 985 HYDRA_RESET_TRANSPORT_FIFO_DATA); 986 if (status) 987 return status; 988 status = write_register(state, HYDRA_RESET_BBAND_REG, 989 HYDRA_RESET_BBAND_DATA); 990 if (status) 991 return status; 992 status = write_register(state, HYDRA_RESET_XBAR_REG, 993 HYDRA_RESET_XBAR_DATA); 994 if (status) 995 return status; 996 997 /* Disable clock to Baseband, Wideband, SerDes, 998 * Alias ext & Transport modules 999 */ 1000 status = write_register(state, HYDRA_MODULES_CLK_2_REG, 1001 HYDRA_DISABLE_CLK_2); 1002 if (status) 1003 return status; 1004 /* Clear Software & Host interrupt status - (Clear on read) */ 1005 status = read_register(state, HYDRA_PRCM_ROOT_CLK_REG, ®_data); 1006 if (status) 1007 return status; 1008 status = do_firmware_download(state, mbin, mbin_len); 1009 if (status) 1010 return status; 1011 1012 if (state->base->type == MXL_HYDRA_DEVICE_568) { 1013 usleep_range(10000, 11000); 1014 1015 /* bring XCPU out of reset */ 1016 status = write_register(state, 0x90720000, 1); 1017 if (status) 1018 return status; 1019 msleep(500); 1020 1021 /* Enable XCPU UART message processing in MCPU */ 1022 status = write_register(state, 0x9076B510, 1); 1023 if (status) 1024 return status; 1025 } else { 1026 /* Bring CPU out of reset */ 1027 status = update_by_mnemonic(state, 0x8003003C, 0, 1, 1); 1028 if (status) 1029 return status; 1030 /* Wait until FW boots */ 1031 msleep(150); 1032 } 1033 1034 /* Initialize XPT XBAR */ 1035 status = write_register(state, XPT_DMD0_BASEADDR, 0x76543210); 1036 if (status) 1037 return status; 1038 1039 if (!firmware_is_alive(state)) 1040 return -1; 1041 1042 dev_info(state->i2cdev, "Hydra FW alive. Hail!\n"); 1043 1044 /* sometimes register values are wrong shortly 1045 * after first heart beats 1046 */ 1047 msleep(50); 1048 1049 dev_sku_cfg.sku_type = state->base->sku_type; 1050 BUILD_HYDRA_CMD(MXL_HYDRA_DEV_CFG_SKU_CMD, MXL_CMD_WRITE, 1051 cmd_size, &dev_sku_cfg, cmd_buff); 1052 status = send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE, 1053 &cmd_buff[0]); 1054 1055 return status; 1056 } 1057 1058 static int cfg_ts_pad_mux(struct mxl *state, enum MXL_BOOL_E enable_serial_ts) 1059 { 1060 int status = 0; 1061 u32 pad_mux_value = 0; 1062 1063 if (enable_serial_ts == MXL_TRUE) { 1064 pad_mux_value = 0; 1065 if ((state->base->type == MXL_HYDRA_DEVICE_541) || 1066 (state->base->type == MXL_HYDRA_DEVICE_541S)) 1067 pad_mux_value = 2; 1068 } else { 1069 if ((state->base->type == MXL_HYDRA_DEVICE_581) || 1070 (state->base->type == MXL_HYDRA_DEVICE_581S)) 1071 pad_mux_value = 2; 1072 else 1073 pad_mux_value = 3; 1074 } 1075 1076 switch (state->base->type) { 1077 case MXL_HYDRA_DEVICE_561: 1078 case MXL_HYDRA_DEVICE_581: 1079 case MXL_HYDRA_DEVICE_541: 1080 case MXL_HYDRA_DEVICE_541S: 1081 case MXL_HYDRA_DEVICE_561S: 1082 case MXL_HYDRA_DEVICE_581S: 1083 status |= update_by_mnemonic(state, 0x90000170, 24, 3, 1084 pad_mux_value); 1085 status |= update_by_mnemonic(state, 0x90000170, 28, 3, 1086 pad_mux_value); 1087 status |= update_by_mnemonic(state, 0x90000174, 0, 3, 1088 pad_mux_value); 1089 status |= update_by_mnemonic(state, 0x90000174, 4, 3, 1090 pad_mux_value); 1091 status |= update_by_mnemonic(state, 0x90000174, 8, 3, 1092 pad_mux_value); 1093 status |= update_by_mnemonic(state, 0x90000174, 12, 3, 1094 pad_mux_value); 1095 status |= update_by_mnemonic(state, 0x90000174, 16, 3, 1096 pad_mux_value); 1097 status |= update_by_mnemonic(state, 0x90000174, 20, 3, 1098 pad_mux_value); 1099 status |= update_by_mnemonic(state, 0x90000174, 24, 3, 1100 pad_mux_value); 1101 status |= update_by_mnemonic(state, 0x90000174, 28, 3, 1102 pad_mux_value); 1103 status |= update_by_mnemonic(state, 0x90000178, 0, 3, 1104 pad_mux_value); 1105 status |= update_by_mnemonic(state, 0x90000178, 4, 3, 1106 pad_mux_value); 1107 status |= update_by_mnemonic(state, 0x90000178, 8, 3, 1108 pad_mux_value); 1109 break; 1110 1111 case MXL_HYDRA_DEVICE_544: 1112 case MXL_HYDRA_DEVICE_542: 1113 status |= update_by_mnemonic(state, 0x9000016C, 4, 3, 1); 1114 status |= update_by_mnemonic(state, 0x9000016C, 8, 3, 0); 1115 status |= update_by_mnemonic(state, 0x9000016C, 12, 3, 0); 1116 status |= update_by_mnemonic(state, 0x9000016C, 16, 3, 0); 1117 status |= update_by_mnemonic(state, 0x90000170, 0, 3, 0); 1118 status |= update_by_mnemonic(state, 0x90000178, 12, 3, 1); 1119 status |= update_by_mnemonic(state, 0x90000178, 16, 3, 1); 1120 status |= update_by_mnemonic(state, 0x90000178, 20, 3, 1); 1121 status |= update_by_mnemonic(state, 0x90000178, 24, 3, 1); 1122 status |= update_by_mnemonic(state, 0x9000017C, 0, 3, 1); 1123 status |= update_by_mnemonic(state, 0x9000017C, 4, 3, 1); 1124 if (enable_serial_ts == MXL_ENABLE) { 1125 status |= update_by_mnemonic(state, 1126 0x90000170, 4, 3, 0); 1127 status |= update_by_mnemonic(state, 1128 0x90000170, 8, 3, 0); 1129 status |= update_by_mnemonic(state, 1130 0x90000170, 12, 3, 0); 1131 status |= update_by_mnemonic(state, 1132 0x90000170, 16, 3, 0); 1133 status |= update_by_mnemonic(state, 1134 0x90000170, 20, 3, 1); 1135 status |= update_by_mnemonic(state, 1136 0x90000170, 24, 3, 1); 1137 status |= update_by_mnemonic(state, 1138 0x90000170, 28, 3, 2); 1139 status |= update_by_mnemonic(state, 1140 0x90000174, 0, 3, 2); 1141 status |= update_by_mnemonic(state, 1142 0x90000174, 4, 3, 2); 1143 status |= update_by_mnemonic(state, 1144 0x90000174, 8, 3, 2); 1145 status |= update_by_mnemonic(state, 1146 0x90000174, 12, 3, 2); 1147 status |= update_by_mnemonic(state, 1148 0x90000174, 16, 3, 2); 1149 status |= update_by_mnemonic(state, 1150 0x90000174, 20, 3, 2); 1151 status |= update_by_mnemonic(state, 1152 0x90000174, 24, 3, 2); 1153 status |= update_by_mnemonic(state, 1154 0x90000174, 28, 3, 2); 1155 status |= update_by_mnemonic(state, 1156 0x90000178, 0, 3, 2); 1157 status |= update_by_mnemonic(state, 1158 0x90000178, 4, 3, 2); 1159 status |= update_by_mnemonic(state, 1160 0x90000178, 8, 3, 2); 1161 } else { 1162 status |= update_by_mnemonic(state, 1163 0x90000170, 4, 3, 3); 1164 status |= update_by_mnemonic(state, 1165 0x90000170, 8, 3, 3); 1166 status |= update_by_mnemonic(state, 1167 0x90000170, 12, 3, 3); 1168 status |= update_by_mnemonic(state, 1169 0x90000170, 16, 3, 3); 1170 status |= update_by_mnemonic(state, 1171 0x90000170, 20, 3, 3); 1172 status |= update_by_mnemonic(state, 1173 0x90000170, 24, 3, 3); 1174 status |= update_by_mnemonic(state, 1175 0x90000170, 28, 3, 3); 1176 status |= update_by_mnemonic(state, 1177 0x90000174, 0, 3, 3); 1178 status |= update_by_mnemonic(state, 1179 0x90000174, 4, 3, 3); 1180 status |= update_by_mnemonic(state, 1181 0x90000174, 8, 3, 3); 1182 status |= update_by_mnemonic(state, 1183 0x90000174, 12, 3, 3); 1184 status |= update_by_mnemonic(state, 1185 0x90000174, 16, 3, 3); 1186 status |= update_by_mnemonic(state, 1187 0x90000174, 20, 3, 1); 1188 status |= update_by_mnemonic(state, 1189 0x90000174, 24, 3, 1); 1190 status |= update_by_mnemonic(state, 1191 0x90000174, 28, 3, 1); 1192 status |= update_by_mnemonic(state, 1193 0x90000178, 0, 3, 1); 1194 status |= update_by_mnemonic(state, 1195 0x90000178, 4, 3, 1); 1196 status |= update_by_mnemonic(state, 1197 0x90000178, 8, 3, 1); 1198 } 1199 break; 1200 1201 case MXL_HYDRA_DEVICE_568: 1202 if (enable_serial_ts == MXL_FALSE) { 1203 status |= update_by_mnemonic(state, 1204 0x9000016C, 8, 3, 5); 1205 status |= update_by_mnemonic(state, 1206 0x9000016C, 12, 3, 5); 1207 status |= update_by_mnemonic(state, 1208 0x9000016C, 16, 3, 5); 1209 status |= update_by_mnemonic(state, 1210 0x9000016C, 20, 3, 5); 1211 status |= update_by_mnemonic(state, 1212 0x9000016C, 24, 3, 5); 1213 status |= update_by_mnemonic(state, 1214 0x9000016C, 28, 3, 5); 1215 status |= update_by_mnemonic(state, 1216 0x90000170, 0, 3, 5); 1217 status |= update_by_mnemonic(state, 1218 0x90000170, 4, 3, 5); 1219 status |= update_by_mnemonic(state, 1220 0x90000170, 8, 3, 5); 1221 status |= update_by_mnemonic(state, 1222 0x90000170, 12, 3, 5); 1223 status |= update_by_mnemonic(state, 1224 0x90000170, 16, 3, 5); 1225 status |= update_by_mnemonic(state, 1226 0x90000170, 20, 3, 5); 1227 1228 status |= update_by_mnemonic(state, 1229 0x90000170, 24, 3, pad_mux_value); 1230 status |= update_by_mnemonic(state, 1231 0x90000174, 0, 3, pad_mux_value); 1232 status |= update_by_mnemonic(state, 1233 0x90000174, 4, 3, pad_mux_value); 1234 status |= update_by_mnemonic(state, 1235 0x90000174, 8, 3, pad_mux_value); 1236 status |= update_by_mnemonic(state, 1237 0x90000174, 12, 3, pad_mux_value); 1238 status |= update_by_mnemonic(state, 1239 0x90000174, 16, 3, pad_mux_value); 1240 status |= update_by_mnemonic(state, 1241 0x90000174, 20, 3, pad_mux_value); 1242 status |= update_by_mnemonic(state, 1243 0x90000174, 24, 3, pad_mux_value); 1244 status |= update_by_mnemonic(state, 1245 0x90000174, 28, 3, pad_mux_value); 1246 status |= update_by_mnemonic(state, 1247 0x90000178, 0, 3, pad_mux_value); 1248 status |= update_by_mnemonic(state, 1249 0x90000178, 4, 3, pad_mux_value); 1250 1251 status |= update_by_mnemonic(state, 1252 0x90000178, 8, 3, 5); 1253 status |= update_by_mnemonic(state, 1254 0x90000178, 12, 3, 5); 1255 status |= update_by_mnemonic(state, 1256 0x90000178, 16, 3, 5); 1257 status |= update_by_mnemonic(state, 1258 0x90000178, 20, 3, 5); 1259 status |= update_by_mnemonic(state, 1260 0x90000178, 24, 3, 5); 1261 status |= update_by_mnemonic(state, 1262 0x90000178, 28, 3, 5); 1263 status |= update_by_mnemonic(state, 1264 0x9000017C, 0, 3, 5); 1265 status |= update_by_mnemonic(state, 1266 0x9000017C, 4, 3, 5); 1267 } else { 1268 status |= update_by_mnemonic(state, 1269 0x90000170, 4, 3, pad_mux_value); 1270 status |= update_by_mnemonic(state, 1271 0x90000170, 8, 3, pad_mux_value); 1272 status |= update_by_mnemonic(state, 1273 0x90000170, 12, 3, pad_mux_value); 1274 status |= update_by_mnemonic(state, 1275 0x90000170, 16, 3, pad_mux_value); 1276 status |= update_by_mnemonic(state, 1277 0x90000170, 20, 3, pad_mux_value); 1278 status |= update_by_mnemonic(state, 1279 0x90000170, 24, 3, pad_mux_value); 1280 status |= update_by_mnemonic(state, 1281 0x90000170, 28, 3, pad_mux_value); 1282 status |= update_by_mnemonic(state, 1283 0x90000174, 0, 3, pad_mux_value); 1284 status |= update_by_mnemonic(state, 1285 0x90000174, 4, 3, pad_mux_value); 1286 status |= update_by_mnemonic(state, 1287 0x90000174, 8, 3, pad_mux_value); 1288 status |= update_by_mnemonic(state, 1289 0x90000174, 12, 3, pad_mux_value); 1290 } 1291 break; 1292 1293 1294 case MXL_HYDRA_DEVICE_584: 1295 default: 1296 status |= update_by_mnemonic(state, 1297 0x90000170, 4, 3, pad_mux_value); 1298 status |= update_by_mnemonic(state, 1299 0x90000170, 8, 3, pad_mux_value); 1300 status |= update_by_mnemonic(state, 1301 0x90000170, 12, 3, pad_mux_value); 1302 status |= update_by_mnemonic(state, 1303 0x90000170, 16, 3, pad_mux_value); 1304 status |= update_by_mnemonic(state, 1305 0x90000170, 20, 3, pad_mux_value); 1306 status |= update_by_mnemonic(state, 1307 0x90000170, 24, 3, pad_mux_value); 1308 status |= update_by_mnemonic(state, 1309 0x90000170, 28, 3, pad_mux_value); 1310 status |= update_by_mnemonic(state, 1311 0x90000174, 0, 3, pad_mux_value); 1312 status |= update_by_mnemonic(state, 1313 0x90000174, 4, 3, pad_mux_value); 1314 status |= update_by_mnemonic(state, 1315 0x90000174, 8, 3, pad_mux_value); 1316 status |= update_by_mnemonic(state, 1317 0x90000174, 12, 3, pad_mux_value); 1318 break; 1319 } 1320 return status; 1321 } 1322 1323 static int set_drive_strength(struct mxl *state, 1324 enum MXL_HYDRA_TS_DRIVE_STRENGTH_E ts_drive_strength) 1325 { 1326 int stat = 0; 1327 u32 val; 1328 1329 read_register(state, 0x90000194, &val); 1330 dev_info(state->i2cdev, "DIGIO = %08x\n", val); 1331 dev_info(state->i2cdev, "set drive_strength = %u\n", ts_drive_strength); 1332 1333 1334 stat |= update_by_mnemonic(state, 0x90000194, 0, 3, ts_drive_strength); 1335 stat |= update_by_mnemonic(state, 0x90000194, 20, 3, ts_drive_strength); 1336 stat |= update_by_mnemonic(state, 0x90000194, 24, 3, ts_drive_strength); 1337 stat |= update_by_mnemonic(state, 0x90000198, 12, 3, ts_drive_strength); 1338 stat |= update_by_mnemonic(state, 0x90000198, 16, 3, ts_drive_strength); 1339 stat |= update_by_mnemonic(state, 0x90000198, 20, 3, ts_drive_strength); 1340 stat |= update_by_mnemonic(state, 0x90000198, 24, 3, ts_drive_strength); 1341 stat |= update_by_mnemonic(state, 0x9000019C, 0, 3, ts_drive_strength); 1342 stat |= update_by_mnemonic(state, 0x9000019C, 4, 3, ts_drive_strength); 1343 stat |= update_by_mnemonic(state, 0x9000019C, 8, 3, ts_drive_strength); 1344 stat |= update_by_mnemonic(state, 0x9000019C, 24, 3, ts_drive_strength); 1345 stat |= update_by_mnemonic(state, 0x9000019C, 28, 3, ts_drive_strength); 1346 stat |= update_by_mnemonic(state, 0x900001A0, 0, 3, ts_drive_strength); 1347 stat |= update_by_mnemonic(state, 0x900001A0, 4, 3, ts_drive_strength); 1348 stat |= update_by_mnemonic(state, 0x900001A0, 20, 3, ts_drive_strength); 1349 stat |= update_by_mnemonic(state, 0x900001A0, 24, 3, ts_drive_strength); 1350 stat |= update_by_mnemonic(state, 0x900001A0, 28, 3, ts_drive_strength); 1351 1352 return stat; 1353 } 1354 1355 static int enable_tuner(struct mxl *state, u32 tuner, u32 enable) 1356 { 1357 int stat = 0; 1358 struct MXL_HYDRA_TUNER_CMD ctrl_tuner_cmd; 1359 u8 cmd_size = sizeof(ctrl_tuner_cmd); 1360 u8 cmd_buff[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN]; 1361 u32 val, count = 10; 1362 1363 ctrl_tuner_cmd.tuner_id = tuner; 1364 ctrl_tuner_cmd.enable = enable; 1365 BUILD_HYDRA_CMD(MXL_HYDRA_TUNER_ACTIVATE_CMD, MXL_CMD_WRITE, 1366 cmd_size, &ctrl_tuner_cmd, cmd_buff); 1367 stat = send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE, 1368 &cmd_buff[0]); 1369 if (stat) 1370 return stat; 1371 read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val); 1372 while (--count && ((val >> tuner) & 1) != enable) { 1373 msleep(20); 1374 read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val); 1375 } 1376 if (!count) 1377 return -1; 1378 read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val); 1379 dev_dbg(state->i2cdev, "tuner %u ready = %u\n", 1380 tuner, (val >> tuner) & 1); 1381 1382 return 0; 1383 } 1384 1385 1386 static int config_ts(struct mxl *state, enum MXL_HYDRA_DEMOD_ID_E demod_id, 1387 struct MXL_HYDRA_MPEGOUT_PARAM_T *mpeg_out_param_ptr) 1388 { 1389 int status = 0; 1390 u32 nco_count_min = 0; 1391 u32 clk_type = 0; 1392 1393 struct MXL_REG_FIELD_T xpt_sync_polarity[MXL_HYDRA_DEMOD_MAX] = { 1394 {0x90700010, 8, 1}, {0x90700010, 9, 1}, 1395 {0x90700010, 10, 1}, {0x90700010, 11, 1}, 1396 {0x90700010, 12, 1}, {0x90700010, 13, 1}, 1397 {0x90700010, 14, 1}, {0x90700010, 15, 1} }; 1398 struct MXL_REG_FIELD_T xpt_clock_polarity[MXL_HYDRA_DEMOD_MAX] = { 1399 {0x90700010, 16, 1}, {0x90700010, 17, 1}, 1400 {0x90700010, 18, 1}, {0x90700010, 19, 1}, 1401 {0x90700010, 20, 1}, {0x90700010, 21, 1}, 1402 {0x90700010, 22, 1}, {0x90700010, 23, 1} }; 1403 struct MXL_REG_FIELD_T xpt_valid_polarity[MXL_HYDRA_DEMOD_MAX] = { 1404 {0x90700014, 0, 1}, {0x90700014, 1, 1}, 1405 {0x90700014, 2, 1}, {0x90700014, 3, 1}, 1406 {0x90700014, 4, 1}, {0x90700014, 5, 1}, 1407 {0x90700014, 6, 1}, {0x90700014, 7, 1} }; 1408 struct MXL_REG_FIELD_T xpt_ts_clock_phase[MXL_HYDRA_DEMOD_MAX] = { 1409 {0x90700018, 0, 3}, {0x90700018, 4, 3}, 1410 {0x90700018, 8, 3}, {0x90700018, 12, 3}, 1411 {0x90700018, 16, 3}, {0x90700018, 20, 3}, 1412 {0x90700018, 24, 3}, {0x90700018, 28, 3} }; 1413 struct MXL_REG_FIELD_T xpt_lsb_first[MXL_HYDRA_DEMOD_MAX] = { 1414 {0x9070000C, 16, 1}, {0x9070000C, 17, 1}, 1415 {0x9070000C, 18, 1}, {0x9070000C, 19, 1}, 1416 {0x9070000C, 20, 1}, {0x9070000C, 21, 1}, 1417 {0x9070000C, 22, 1}, {0x9070000C, 23, 1} }; 1418 struct MXL_REG_FIELD_T xpt_sync_byte[MXL_HYDRA_DEMOD_MAX] = { 1419 {0x90700010, 0, 1}, {0x90700010, 1, 1}, 1420 {0x90700010, 2, 1}, {0x90700010, 3, 1}, 1421 {0x90700010, 4, 1}, {0x90700010, 5, 1}, 1422 {0x90700010, 6, 1}, {0x90700010, 7, 1} }; 1423 struct MXL_REG_FIELD_T xpt_enable_output[MXL_HYDRA_DEMOD_MAX] = { 1424 {0x9070000C, 0, 1}, {0x9070000C, 1, 1}, 1425 {0x9070000C, 2, 1}, {0x9070000C, 3, 1}, 1426 {0x9070000C, 4, 1}, {0x9070000C, 5, 1}, 1427 {0x9070000C, 6, 1}, {0x9070000C, 7, 1} }; 1428 struct MXL_REG_FIELD_T xpt_err_replace_sync[MXL_HYDRA_DEMOD_MAX] = { 1429 {0x9070000C, 24, 1}, {0x9070000C, 25, 1}, 1430 {0x9070000C, 26, 1}, {0x9070000C, 27, 1}, 1431 {0x9070000C, 28, 1}, {0x9070000C, 29, 1}, 1432 {0x9070000C, 30, 1}, {0x9070000C, 31, 1} }; 1433 struct MXL_REG_FIELD_T xpt_err_replace_valid[MXL_HYDRA_DEMOD_MAX] = { 1434 {0x90700014, 8, 1}, {0x90700014, 9, 1}, 1435 {0x90700014, 10, 1}, {0x90700014, 11, 1}, 1436 {0x90700014, 12, 1}, {0x90700014, 13, 1}, 1437 {0x90700014, 14, 1}, {0x90700014, 15, 1} }; 1438 struct MXL_REG_FIELD_T xpt_continuous_clock[MXL_HYDRA_DEMOD_MAX] = { 1439 {0x907001D4, 0, 1}, {0x907001D4, 1, 1}, 1440 {0x907001D4, 2, 1}, {0x907001D4, 3, 1}, 1441 {0x907001D4, 4, 1}, {0x907001D4, 5, 1}, 1442 {0x907001D4, 6, 1}, {0x907001D4, 7, 1} }; 1443 struct MXL_REG_FIELD_T xpt_nco_clock_rate[MXL_HYDRA_DEMOD_MAX] = { 1444 {0x90700044, 16, 80}, {0x90700044, 16, 81}, 1445 {0x90700044, 16, 82}, {0x90700044, 16, 83}, 1446 {0x90700044, 16, 84}, {0x90700044, 16, 85}, 1447 {0x90700044, 16, 86}, {0x90700044, 16, 87} }; 1448 1449 demod_id = state->base->ts_map[demod_id]; 1450 1451 if (mpeg_out_param_ptr->enable == MXL_ENABLE) { 1452 if (mpeg_out_param_ptr->mpeg_mode == 1453 MXL_HYDRA_MPEG_MODE_PARALLEL) { 1454 } else { 1455 cfg_ts_pad_mux(state, MXL_TRUE); 1456 update_by_mnemonic(state, 1457 0x90700010, 27, 1, MXL_FALSE); 1458 } 1459 } 1460 1461 nco_count_min = 1462 (u32)(MXL_HYDRA_NCO_CLK / mpeg_out_param_ptr->max_mpeg_clk_rate); 1463 1464 if (state->base->chipversion >= 2) { 1465 status |= update_by_mnemonic(state, 1466 xpt_nco_clock_rate[demod_id].reg_addr, /* Reg Addr */ 1467 xpt_nco_clock_rate[demod_id].lsb_pos, /* LSB pos */ 1468 xpt_nco_clock_rate[demod_id].num_of_bits, /* Num of bits */ 1469 nco_count_min); /* Data */ 1470 } else 1471 update_by_mnemonic(state, 0x90700044, 16, 8, nco_count_min); 1472 1473 if (mpeg_out_param_ptr->mpeg_clk_type == MXL_HYDRA_MPEG_CLK_CONTINUOUS) 1474 clk_type = 1; 1475 1476 if (mpeg_out_param_ptr->mpeg_mode < MXL_HYDRA_MPEG_MODE_PARALLEL) { 1477 status |= update_by_mnemonic(state, 1478 xpt_continuous_clock[demod_id].reg_addr, 1479 xpt_continuous_clock[demod_id].lsb_pos, 1480 xpt_continuous_clock[demod_id].num_of_bits, 1481 clk_type); 1482 } else 1483 update_by_mnemonic(state, 0x907001D4, 8, 1, clk_type); 1484 1485 status |= update_by_mnemonic(state, 1486 xpt_sync_polarity[demod_id].reg_addr, 1487 xpt_sync_polarity[demod_id].lsb_pos, 1488 xpt_sync_polarity[demod_id].num_of_bits, 1489 mpeg_out_param_ptr->mpeg_sync_pol); 1490 1491 status |= update_by_mnemonic(state, 1492 xpt_valid_polarity[demod_id].reg_addr, 1493 xpt_valid_polarity[demod_id].lsb_pos, 1494 xpt_valid_polarity[demod_id].num_of_bits, 1495 mpeg_out_param_ptr->mpeg_valid_pol); 1496 1497 status |= update_by_mnemonic(state, 1498 xpt_clock_polarity[demod_id].reg_addr, 1499 xpt_clock_polarity[demod_id].lsb_pos, 1500 xpt_clock_polarity[demod_id].num_of_bits, 1501 mpeg_out_param_ptr->mpeg_clk_pol); 1502 1503 status |= update_by_mnemonic(state, 1504 xpt_sync_byte[demod_id].reg_addr, 1505 xpt_sync_byte[demod_id].lsb_pos, 1506 xpt_sync_byte[demod_id].num_of_bits, 1507 mpeg_out_param_ptr->mpeg_sync_pulse_width); 1508 1509 status |= update_by_mnemonic(state, 1510 xpt_ts_clock_phase[demod_id].reg_addr, 1511 xpt_ts_clock_phase[demod_id].lsb_pos, 1512 xpt_ts_clock_phase[demod_id].num_of_bits, 1513 mpeg_out_param_ptr->mpeg_clk_phase); 1514 1515 status |= update_by_mnemonic(state, 1516 xpt_lsb_first[demod_id].reg_addr, 1517 xpt_lsb_first[demod_id].lsb_pos, 1518 xpt_lsb_first[demod_id].num_of_bits, 1519 mpeg_out_param_ptr->lsb_or_msb_first); 1520 1521 switch (mpeg_out_param_ptr->mpeg_error_indication) { 1522 case MXL_HYDRA_MPEG_ERR_REPLACE_SYNC: 1523 status |= update_by_mnemonic(state, 1524 xpt_err_replace_sync[demod_id].reg_addr, 1525 xpt_err_replace_sync[demod_id].lsb_pos, 1526 xpt_err_replace_sync[demod_id].num_of_bits, 1527 MXL_TRUE); 1528 status |= update_by_mnemonic(state, 1529 xpt_err_replace_valid[demod_id].reg_addr, 1530 xpt_err_replace_valid[demod_id].lsb_pos, 1531 xpt_err_replace_valid[demod_id].num_of_bits, 1532 MXL_FALSE); 1533 break; 1534 1535 case MXL_HYDRA_MPEG_ERR_REPLACE_VALID: 1536 status |= update_by_mnemonic(state, 1537 xpt_err_replace_sync[demod_id].reg_addr, 1538 xpt_err_replace_sync[demod_id].lsb_pos, 1539 xpt_err_replace_sync[demod_id].num_of_bits, 1540 MXL_FALSE); 1541 1542 status |= update_by_mnemonic(state, 1543 xpt_err_replace_valid[demod_id].reg_addr, 1544 xpt_err_replace_valid[demod_id].lsb_pos, 1545 xpt_err_replace_valid[demod_id].num_of_bits, 1546 MXL_TRUE); 1547 break; 1548 1549 case MXL_HYDRA_MPEG_ERR_INDICATION_DISABLED: 1550 default: 1551 status |= update_by_mnemonic(state, 1552 xpt_err_replace_sync[demod_id].reg_addr, 1553 xpt_err_replace_sync[demod_id].lsb_pos, 1554 xpt_err_replace_sync[demod_id].num_of_bits, 1555 MXL_FALSE); 1556 1557 status |= update_by_mnemonic(state, 1558 xpt_err_replace_valid[demod_id].reg_addr, 1559 xpt_err_replace_valid[demod_id].lsb_pos, 1560 xpt_err_replace_valid[demod_id].num_of_bits, 1561 MXL_FALSE); 1562 1563 break; 1564 1565 } 1566 1567 if (mpeg_out_param_ptr->mpeg_mode != MXL_HYDRA_MPEG_MODE_PARALLEL) { 1568 status |= update_by_mnemonic(state, 1569 xpt_enable_output[demod_id].reg_addr, 1570 xpt_enable_output[demod_id].lsb_pos, 1571 xpt_enable_output[demod_id].num_of_bits, 1572 mpeg_out_param_ptr->enable); 1573 } 1574 return status; 1575 } 1576 1577 static int config_mux(struct mxl *state) 1578 { 1579 update_by_mnemonic(state, 0x9070000C, 0, 1, 0); 1580 update_by_mnemonic(state, 0x9070000C, 1, 1, 0); 1581 update_by_mnemonic(state, 0x9070000C, 2, 1, 0); 1582 update_by_mnemonic(state, 0x9070000C, 3, 1, 0); 1583 update_by_mnemonic(state, 0x9070000C, 4, 1, 0); 1584 update_by_mnemonic(state, 0x9070000C, 5, 1, 0); 1585 update_by_mnemonic(state, 0x9070000C, 6, 1, 0); 1586 update_by_mnemonic(state, 0x9070000C, 7, 1, 0); 1587 update_by_mnemonic(state, 0x90700008, 0, 2, 1); 1588 update_by_mnemonic(state, 0x90700008, 2, 2, 1); 1589 return 0; 1590 } 1591 1592 static int load_fw(struct mxl *state, struct mxl5xx_cfg *cfg) 1593 { 1594 int stat = 0; 1595 u8 *buf; 1596 1597 if (cfg->fw) 1598 return firmware_download(state, cfg->fw, cfg->fw_len); 1599 1600 if (!cfg->fw_read) 1601 return -1; 1602 1603 buf = vmalloc(0x40000); 1604 if (!buf) 1605 return -ENOMEM; 1606 1607 cfg->fw_read(cfg->fw_priv, buf, 0x40000); 1608 stat = firmware_download(state, buf, 0x40000); 1609 vfree(buf); 1610 1611 return stat; 1612 } 1613 1614 static int validate_sku(struct mxl *state) 1615 { 1616 u32 pad_mux_bond = 0, prcm_chip_id = 0, prcm_so_cid = 0; 1617 int status; 1618 u32 type = state->base->type; 1619 1620 status = read_by_mnemonic(state, 0x90000190, 0, 3, &pad_mux_bond); 1621 status |= read_by_mnemonic(state, 0x80030000, 0, 12, &prcm_chip_id); 1622 status |= read_by_mnemonic(state, 0x80030004, 24, 8, &prcm_so_cid); 1623 if (status) 1624 return -1; 1625 1626 dev_info(state->i2cdev, "padMuxBond=%08x, prcmChipId=%08x, prcmSoCId=%08x\n", 1627 pad_mux_bond, prcm_chip_id, prcm_so_cid); 1628 1629 if (prcm_chip_id != 0x560) { 1630 switch (pad_mux_bond) { 1631 case MXL_HYDRA_SKU_ID_581: 1632 if (type == MXL_HYDRA_DEVICE_581) 1633 return 0; 1634 if (type == MXL_HYDRA_DEVICE_581S) { 1635 state->base->type = MXL_HYDRA_DEVICE_581; 1636 return 0; 1637 } 1638 break; 1639 case MXL_HYDRA_SKU_ID_584: 1640 if (type == MXL_HYDRA_DEVICE_584) 1641 return 0; 1642 break; 1643 case MXL_HYDRA_SKU_ID_544: 1644 if (type == MXL_HYDRA_DEVICE_544) 1645 return 0; 1646 if (type == MXL_HYDRA_DEVICE_542) 1647 return 0; 1648 break; 1649 case MXL_HYDRA_SKU_ID_582: 1650 if (type == MXL_HYDRA_DEVICE_582) 1651 return 0; 1652 break; 1653 default: 1654 return -1; 1655 } 1656 } else { 1657 1658 } 1659 return -1; 1660 } 1661 1662 static int get_fwinfo(struct mxl *state) 1663 { 1664 int status; 1665 u32 val = 0; 1666 1667 status = read_by_mnemonic(state, 0x90000190, 0, 3, &val); 1668 if (status) 1669 return status; 1670 dev_info(state->i2cdev, "chipID=%08x\n", val); 1671 1672 status = read_by_mnemonic(state, 0x80030004, 8, 8, &val); 1673 if (status) 1674 return status; 1675 dev_info(state->i2cdev, "chipVer=%08x\n", val); 1676 1677 status = read_register(state, HYDRA_FIRMWARE_VERSION, &val); 1678 if (status) 1679 return status; 1680 dev_info(state->i2cdev, "FWVer=%08x\n", val); 1681 1682 state->base->fwversion = val; 1683 return status; 1684 } 1685 1686 1687 static u8 ts_map1_to_1[MXL_HYDRA_DEMOD_MAX] = { 1688 MXL_HYDRA_DEMOD_ID_0, 1689 MXL_HYDRA_DEMOD_ID_1, 1690 MXL_HYDRA_DEMOD_ID_2, 1691 MXL_HYDRA_DEMOD_ID_3, 1692 MXL_HYDRA_DEMOD_ID_4, 1693 MXL_HYDRA_DEMOD_ID_5, 1694 MXL_HYDRA_DEMOD_ID_6, 1695 MXL_HYDRA_DEMOD_ID_7, 1696 }; 1697 1698 static u8 ts_map54x[MXL_HYDRA_DEMOD_MAX] = { 1699 MXL_HYDRA_DEMOD_ID_2, 1700 MXL_HYDRA_DEMOD_ID_3, 1701 MXL_HYDRA_DEMOD_ID_4, 1702 MXL_HYDRA_DEMOD_ID_5, 1703 MXL_HYDRA_DEMOD_MAX, 1704 MXL_HYDRA_DEMOD_MAX, 1705 MXL_HYDRA_DEMOD_MAX, 1706 MXL_HYDRA_DEMOD_MAX, 1707 }; 1708 1709 static int probe(struct mxl *state, struct mxl5xx_cfg *cfg) 1710 { 1711 u32 chipver; 1712 int fw, status, j; 1713 struct MXL_HYDRA_MPEGOUT_PARAM_T mpeg_interface_cfg; 1714 1715 state->base->ts_map = ts_map1_to_1; 1716 1717 switch (state->base->type) { 1718 case MXL_HYDRA_DEVICE_581: 1719 case MXL_HYDRA_DEVICE_581S: 1720 state->base->can_clkout = 1; 1721 state->base->demod_num = 8; 1722 state->base->tuner_num = 1; 1723 state->base->sku_type = MXL_HYDRA_SKU_TYPE_581; 1724 break; 1725 case MXL_HYDRA_DEVICE_582: 1726 state->base->can_clkout = 1; 1727 state->base->demod_num = 8; 1728 state->base->tuner_num = 3; 1729 state->base->sku_type = MXL_HYDRA_SKU_TYPE_582; 1730 break; 1731 case MXL_HYDRA_DEVICE_585: 1732 state->base->can_clkout = 0; 1733 state->base->demod_num = 8; 1734 state->base->tuner_num = 4; 1735 state->base->sku_type = MXL_HYDRA_SKU_TYPE_585; 1736 break; 1737 case MXL_HYDRA_DEVICE_544: 1738 state->base->can_clkout = 0; 1739 state->base->demod_num = 4; 1740 state->base->tuner_num = 4; 1741 state->base->sku_type = MXL_HYDRA_SKU_TYPE_544; 1742 state->base->ts_map = ts_map54x; 1743 break; 1744 case MXL_HYDRA_DEVICE_541: 1745 case MXL_HYDRA_DEVICE_541S: 1746 state->base->can_clkout = 0; 1747 state->base->demod_num = 4; 1748 state->base->tuner_num = 1; 1749 state->base->sku_type = MXL_HYDRA_SKU_TYPE_541; 1750 state->base->ts_map = ts_map54x; 1751 break; 1752 case MXL_HYDRA_DEVICE_561: 1753 case MXL_HYDRA_DEVICE_561S: 1754 state->base->can_clkout = 0; 1755 state->base->demod_num = 6; 1756 state->base->tuner_num = 1; 1757 state->base->sku_type = MXL_HYDRA_SKU_TYPE_561; 1758 break; 1759 case MXL_HYDRA_DEVICE_568: 1760 state->base->can_clkout = 0; 1761 state->base->demod_num = 8; 1762 state->base->tuner_num = 1; 1763 state->base->chan_bond = 1; 1764 state->base->sku_type = MXL_HYDRA_SKU_TYPE_568; 1765 break; 1766 case MXL_HYDRA_DEVICE_542: 1767 state->base->can_clkout = 1; 1768 state->base->demod_num = 4; 1769 state->base->tuner_num = 3; 1770 state->base->sku_type = MXL_HYDRA_SKU_TYPE_542; 1771 state->base->ts_map = ts_map54x; 1772 break; 1773 case MXL_HYDRA_DEVICE_TEST: 1774 case MXL_HYDRA_DEVICE_584: 1775 default: 1776 state->base->can_clkout = 0; 1777 state->base->demod_num = 8; 1778 state->base->tuner_num = 4; 1779 state->base->sku_type = MXL_HYDRA_SKU_TYPE_584; 1780 break; 1781 } 1782 1783 status = validate_sku(state); 1784 if (status) 1785 return status; 1786 1787 update_by_mnemonic(state, 0x80030014, 9, 1, 1); 1788 update_by_mnemonic(state, 0x8003003C, 12, 1, 1); 1789 status = read_by_mnemonic(state, 0x80030000, 12, 4, &chipver); 1790 if (status) 1791 state->base->chipversion = 0; 1792 else 1793 state->base->chipversion = (chipver == 2) ? 2 : 1; 1794 dev_info(state->i2cdev, "Hydra chip version %u\n", 1795 state->base->chipversion); 1796 1797 cfg_dev_xtal(state, cfg->clk, cfg->cap, 0); 1798 1799 fw = firmware_is_alive(state); 1800 if (!fw) { 1801 status = load_fw(state, cfg); 1802 if (status) 1803 return status; 1804 } 1805 get_fwinfo(state); 1806 1807 config_mux(state); 1808 mpeg_interface_cfg.enable = MXL_ENABLE; 1809 mpeg_interface_cfg.lsb_or_msb_first = MXL_HYDRA_MPEG_SERIAL_MSB_1ST; 1810 /* supports only (0-104&139)MHz */ 1811 if (cfg->ts_clk) 1812 mpeg_interface_cfg.max_mpeg_clk_rate = cfg->ts_clk; 1813 else 1814 mpeg_interface_cfg.max_mpeg_clk_rate = 69; /* 139; */ 1815 mpeg_interface_cfg.mpeg_clk_phase = MXL_HYDRA_MPEG_CLK_PHASE_SHIFT_0_DEG; 1816 mpeg_interface_cfg.mpeg_clk_pol = MXL_HYDRA_MPEG_CLK_IN_PHASE; 1817 /* MXL_HYDRA_MPEG_CLK_GAPPED; */ 1818 mpeg_interface_cfg.mpeg_clk_type = MXL_HYDRA_MPEG_CLK_CONTINUOUS; 1819 mpeg_interface_cfg.mpeg_error_indication = 1820 MXL_HYDRA_MPEG_ERR_INDICATION_DISABLED; 1821 mpeg_interface_cfg.mpeg_mode = MXL_HYDRA_MPEG_MODE_SERIAL_3_WIRE; 1822 mpeg_interface_cfg.mpeg_sync_pol = MXL_HYDRA_MPEG_ACTIVE_HIGH; 1823 mpeg_interface_cfg.mpeg_sync_pulse_width = MXL_HYDRA_MPEG_SYNC_WIDTH_BIT; 1824 mpeg_interface_cfg.mpeg_valid_pol = MXL_HYDRA_MPEG_ACTIVE_HIGH; 1825 1826 for (j = 0; j < state->base->demod_num; j++) { 1827 status = config_ts(state, (enum MXL_HYDRA_DEMOD_ID_E) j, 1828 &mpeg_interface_cfg); 1829 if (status) 1830 return status; 1831 } 1832 set_drive_strength(state, 1); 1833 return 0; 1834 } 1835 1836 struct dvb_frontend *mxl5xx_attach(struct i2c_adapter *i2c, 1837 struct mxl5xx_cfg *cfg, u32 demod, u32 tuner, 1838 int (**fn_set_input)(struct dvb_frontend *, int)) 1839 { 1840 struct mxl *state; 1841 struct mxl_base *base; 1842 1843 state = kzalloc(sizeof(struct mxl), GFP_KERNEL); 1844 if (!state) 1845 return NULL; 1846 1847 state->demod = demod; 1848 state->tuner = tuner; 1849 state->tuner_in_use = 0xffffffff; 1850 state->i2cdev = &i2c->dev; 1851 1852 base = match_base(i2c, cfg->adr); 1853 if (base) { 1854 base->count++; 1855 if (base->count > base->demod_num) 1856 goto fail; 1857 state->base = base; 1858 } else { 1859 base = kzalloc(sizeof(struct mxl_base), GFP_KERNEL); 1860 if (!base) 1861 goto fail; 1862 base->i2c = i2c; 1863 base->adr = cfg->adr; 1864 base->type = cfg->type; 1865 base->count = 1; 1866 mutex_init(&base->i2c_lock); 1867 mutex_init(&base->status_lock); 1868 mutex_init(&base->tune_lock); 1869 INIT_LIST_HEAD(&base->mxls); 1870 1871 state->base = base; 1872 if (probe(state, cfg) < 0) { 1873 kfree(base); 1874 goto fail; 1875 } 1876 list_add(&base->mxllist, &mxllist); 1877 } 1878 state->fe.ops = mxl_ops; 1879 state->xbar[0] = 4; 1880 state->xbar[1] = demod; 1881 state->xbar[2] = 8; 1882 state->fe.demodulator_priv = state; 1883 *fn_set_input = set_input; 1884 1885 list_add(&state->mxl, &base->mxls); 1886 return &state->fe; 1887 1888 fail: 1889 kfree(state); 1890 return NULL; 1891 } 1892 EXPORT_SYMBOL_GPL(mxl5xx_attach); 1893 1894 MODULE_DESCRIPTION("MaxLinear MxL5xx DVB-S/S2 tuner-demodulator driver"); 1895 MODULE_AUTHOR("Ralph and Marcus Metzler, Metzler Brothers Systementwicklung GbR"); 1896 MODULE_LICENSE("GPL v2"); 1897