1 /* 2 * Driver for the MaxLinear MxL5xx family of tuners/demods 3 * 4 * Copyright (C) 2014-2015 Ralph Metzler <rjkm@metzlerbros.de> 5 * Marcus Metzler <mocm@metzlerbros.de> 6 * developed for Digital Devices GmbH 7 * 8 * based on code: 9 * Copyright (c) 2011-2013 MaxLinear, Inc. All rights reserved 10 * which was released under GPL V2 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License 14 * version 2, as published by the Free Software Foundation. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 */ 22 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/moduleparam.h> 26 #include <linux/init.h> 27 #include <linux/delay.h> 28 #include <linux/firmware.h> 29 #include <linux/i2c.h> 30 #include <linux/version.h> 31 #include <linux/mutex.h> 32 #include <linux/vmalloc.h> 33 #include <asm/div64.h> 34 #include <asm/unaligned.h> 35 36 #include <media/dvb_frontend.h> 37 #include "mxl5xx.h" 38 #include "mxl5xx_regs.h" 39 #include "mxl5xx_defs.h" 40 41 #define BYTE0(v) ((v >> 0) & 0xff) 42 #define BYTE1(v) ((v >> 8) & 0xff) 43 #define BYTE2(v) ((v >> 16) & 0xff) 44 #define BYTE3(v) ((v >> 24) & 0xff) 45 46 static LIST_HEAD(mxllist); 47 48 struct mxl_base { 49 struct list_head mxllist; 50 struct list_head mxls; 51 52 u8 adr; 53 struct i2c_adapter *i2c; 54 55 u32 count; 56 u32 type; 57 u32 sku_type; 58 u32 chipversion; 59 u32 clock; 60 u32 fwversion; 61 62 u8 *ts_map; 63 u8 can_clkout; 64 u8 chan_bond; 65 u8 demod_num; 66 u8 tuner_num; 67 68 unsigned long next_tune; 69 70 struct mutex i2c_lock; 71 struct mutex status_lock; 72 struct mutex tune_lock; 73 74 u8 buf[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN]; 75 76 u32 cmd_size; 77 u8 cmd_data[MAX_CMD_DATA]; 78 }; 79 80 struct mxl { 81 struct list_head mxl; 82 83 struct mxl_base *base; 84 struct dvb_frontend fe; 85 struct device *i2cdev; 86 u32 demod; 87 u32 tuner; 88 u32 tuner_in_use; 89 u8 xbar[3]; 90 91 unsigned long tune_time; 92 }; 93 94 static void convert_endian(u8 flag, u32 size, u8 *d) 95 { 96 u32 i; 97 98 if (!flag) 99 return; 100 for (i = 0; i < (size & ~3); i += 4) { 101 d[i + 0] ^= d[i + 3]; 102 d[i + 3] ^= d[i + 0]; 103 d[i + 0] ^= d[i + 3]; 104 105 d[i + 1] ^= d[i + 2]; 106 d[i + 2] ^= d[i + 1]; 107 d[i + 1] ^= d[i + 2]; 108 } 109 110 switch (size & 3) { 111 case 0: 112 case 1: 113 /* do nothing */ 114 break; 115 case 2: 116 d[i + 0] ^= d[i + 1]; 117 d[i + 1] ^= d[i + 0]; 118 d[i + 0] ^= d[i + 1]; 119 break; 120 121 case 3: 122 d[i + 0] ^= d[i + 2]; 123 d[i + 2] ^= d[i + 0]; 124 d[i + 0] ^= d[i + 2]; 125 break; 126 } 127 128 } 129 130 static int i2c_write(struct i2c_adapter *adap, u8 adr, 131 u8 *data, u32 len) 132 { 133 struct i2c_msg msg = {.addr = adr, .flags = 0, 134 .buf = data, .len = len}; 135 136 return (i2c_transfer(adap, &msg, 1) == 1) ? 0 : -1; 137 } 138 139 static int i2c_read(struct i2c_adapter *adap, u8 adr, 140 u8 *data, u32 len) 141 { 142 struct i2c_msg msg = {.addr = adr, .flags = I2C_M_RD, 143 .buf = data, .len = len}; 144 145 return (i2c_transfer(adap, &msg, 1) == 1) ? 0 : -1; 146 } 147 148 static int i2cread(struct mxl *state, u8 *data, int len) 149 { 150 return i2c_read(state->base->i2c, state->base->adr, data, len); 151 } 152 153 static int i2cwrite(struct mxl *state, u8 *data, int len) 154 { 155 return i2c_write(state->base->i2c, state->base->adr, data, len); 156 } 157 158 static int read_register_unlocked(struct mxl *state, u32 reg, u32 *val) 159 { 160 int stat; 161 u8 data[MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE] = { 162 MXL_HYDRA_PLID_REG_READ, 0x04, 163 GET_BYTE(reg, 0), GET_BYTE(reg, 1), 164 GET_BYTE(reg, 2), GET_BYTE(reg, 3), 165 }; 166 167 stat = i2cwrite(state, data, 168 MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE); 169 if (stat) 170 dev_err(state->i2cdev, "i2c read error 1\n"); 171 if (!stat) 172 stat = i2cread(state, (u8 *) val, 173 MXL_HYDRA_REG_SIZE_IN_BYTES); 174 le32_to_cpus(val); 175 if (stat) 176 dev_err(state->i2cdev, "i2c read error 2\n"); 177 return stat; 178 } 179 180 #define DMA_I2C_INTERRUPT_ADDR 0x8000011C 181 #define DMA_INTR_PROT_WR_CMP 0x08 182 183 static int send_command(struct mxl *state, u32 size, u8 *buf) 184 { 185 int stat; 186 u32 val, count = 10; 187 188 mutex_lock(&state->base->i2c_lock); 189 if (state->base->fwversion > 0x02010109) { 190 read_register_unlocked(state, DMA_I2C_INTERRUPT_ADDR, &val); 191 if (DMA_INTR_PROT_WR_CMP & val) 192 dev_info(state->i2cdev, "%s busy\n", __func__); 193 while ((DMA_INTR_PROT_WR_CMP & val) && --count) { 194 mutex_unlock(&state->base->i2c_lock); 195 usleep_range(1000, 2000); 196 mutex_lock(&state->base->i2c_lock); 197 read_register_unlocked(state, DMA_I2C_INTERRUPT_ADDR, 198 &val); 199 } 200 if (!count) { 201 dev_info(state->i2cdev, "%s busy\n", __func__); 202 mutex_unlock(&state->base->i2c_lock); 203 return -EBUSY; 204 } 205 } 206 stat = i2cwrite(state, buf, size); 207 mutex_unlock(&state->base->i2c_lock); 208 return stat; 209 } 210 211 static int write_register(struct mxl *state, u32 reg, u32 val) 212 { 213 int stat; 214 u8 data[MXL_HYDRA_REG_WRITE_LEN] = { 215 MXL_HYDRA_PLID_REG_WRITE, 0x08, 216 BYTE0(reg), BYTE1(reg), BYTE2(reg), BYTE3(reg), 217 BYTE0(val), BYTE1(val), BYTE2(val), BYTE3(val), 218 }; 219 mutex_lock(&state->base->i2c_lock); 220 stat = i2cwrite(state, data, sizeof(data)); 221 mutex_unlock(&state->base->i2c_lock); 222 if (stat) 223 dev_err(state->i2cdev, "i2c write error\n"); 224 return stat; 225 } 226 227 static int write_firmware_block(struct mxl *state, 228 u32 reg, u32 size, u8 *reg_data_ptr) 229 { 230 int stat; 231 u8 *buf = state->base->buf; 232 233 mutex_lock(&state->base->i2c_lock); 234 buf[0] = MXL_HYDRA_PLID_REG_WRITE; 235 buf[1] = size + 4; 236 buf[2] = GET_BYTE(reg, 0); 237 buf[3] = GET_BYTE(reg, 1); 238 buf[4] = GET_BYTE(reg, 2); 239 buf[5] = GET_BYTE(reg, 3); 240 memcpy(&buf[6], reg_data_ptr, size); 241 stat = i2cwrite(state, buf, 242 MXL_HYDRA_I2C_HDR_SIZE + 243 MXL_HYDRA_REG_SIZE_IN_BYTES + size); 244 mutex_unlock(&state->base->i2c_lock); 245 if (stat) 246 dev_err(state->i2cdev, "fw block write failed\n"); 247 return stat; 248 } 249 250 static int read_register(struct mxl *state, u32 reg, u32 *val) 251 { 252 int stat; 253 u8 data[MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE] = { 254 MXL_HYDRA_PLID_REG_READ, 0x04, 255 GET_BYTE(reg, 0), GET_BYTE(reg, 1), 256 GET_BYTE(reg, 2), GET_BYTE(reg, 3), 257 }; 258 259 mutex_lock(&state->base->i2c_lock); 260 stat = i2cwrite(state, data, 261 MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE); 262 if (stat) 263 dev_err(state->i2cdev, "i2c read error 1\n"); 264 if (!stat) 265 stat = i2cread(state, (u8 *) val, 266 MXL_HYDRA_REG_SIZE_IN_BYTES); 267 mutex_unlock(&state->base->i2c_lock); 268 le32_to_cpus(val); 269 if (stat) 270 dev_err(state->i2cdev, "i2c read error 2\n"); 271 return stat; 272 } 273 274 static int read_register_block(struct mxl *state, u32 reg, u32 size, u8 *data) 275 { 276 int stat; 277 u8 *buf = state->base->buf; 278 279 mutex_lock(&state->base->i2c_lock); 280 281 buf[0] = MXL_HYDRA_PLID_REG_READ; 282 buf[1] = size + 4; 283 buf[2] = GET_BYTE(reg, 0); 284 buf[3] = GET_BYTE(reg, 1); 285 buf[4] = GET_BYTE(reg, 2); 286 buf[5] = GET_BYTE(reg, 3); 287 stat = i2cwrite(state, buf, 288 MXL_HYDRA_I2C_HDR_SIZE + MXL_HYDRA_REG_SIZE_IN_BYTES); 289 if (!stat) { 290 stat = i2cread(state, data, size); 291 convert_endian(MXL_ENABLE_BIG_ENDIAN, size, data); 292 } 293 mutex_unlock(&state->base->i2c_lock); 294 return stat; 295 } 296 297 static int read_by_mnemonic(struct mxl *state, 298 u32 reg, u8 lsbloc, u8 numofbits, u32 *val) 299 { 300 u32 data = 0, mask = 0; 301 int stat; 302 303 stat = read_register(state, reg, &data); 304 if (stat) 305 return stat; 306 mask = MXL_GET_REG_MASK_32(lsbloc, numofbits); 307 data &= mask; 308 data >>= lsbloc; 309 *val = data; 310 return 0; 311 } 312 313 314 static int update_by_mnemonic(struct mxl *state, 315 u32 reg, u8 lsbloc, u8 numofbits, u32 val) 316 { 317 u32 data, mask; 318 int stat; 319 320 stat = read_register(state, reg, &data); 321 if (stat) 322 return stat; 323 mask = MXL_GET_REG_MASK_32(lsbloc, numofbits); 324 data = (data & ~mask) | ((val << lsbloc) & mask); 325 stat = write_register(state, reg, data); 326 return stat; 327 } 328 329 static int firmware_is_alive(struct mxl *state) 330 { 331 u32 hb0, hb1; 332 333 if (read_register(state, HYDRA_HEAR_BEAT, &hb0)) 334 return 0; 335 msleep(20); 336 if (read_register(state, HYDRA_HEAR_BEAT, &hb1)) 337 return 0; 338 if (hb1 == hb0) 339 return 0; 340 return 1; 341 } 342 343 static int init(struct dvb_frontend *fe) 344 { 345 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 346 347 /* init fe stats */ 348 p->strength.len = 1; 349 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 350 p->cnr.len = 1; 351 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 352 p->pre_bit_error.len = 1; 353 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 354 p->pre_bit_count.len = 1; 355 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 356 p->post_bit_error.len = 1; 357 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 358 p->post_bit_count.len = 1; 359 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 360 361 return 0; 362 } 363 364 static void release(struct dvb_frontend *fe) 365 { 366 struct mxl *state = fe->demodulator_priv; 367 368 list_del(&state->mxl); 369 /* Release one frontend, two more shall take its place! */ 370 state->base->count--; 371 if (state->base->count == 0) { 372 list_del(&state->base->mxllist); 373 kfree(state->base); 374 } 375 kfree(state); 376 } 377 378 static int get_algo(struct dvb_frontend *fe) 379 { 380 return DVBFE_ALGO_HW; 381 } 382 383 static u32 gold2root(u32 gold) 384 { 385 u32 x, g, tmp = gold; 386 387 if (tmp >= 0x3ffff) 388 tmp = 0; 389 for (g = 0, x = 1; g < tmp; g++) 390 x = (((x ^ (x >> 7)) & 1) << 17) | (x >> 1); 391 return x; 392 } 393 394 static int cfg_scrambler(struct mxl *state, u32 gold) 395 { 396 u32 root; 397 u8 buf[26] = { 398 MXL_HYDRA_PLID_CMD_WRITE, 24, 399 0, MXL_HYDRA_DEMOD_SCRAMBLE_CODE_CMD, 0, 0, 400 state->demod, 0, 0, 0, 401 0, 0, 0, 0, 0, 0, 0, 0, 402 0, 0, 0, 0, 1, 0, 0, 0, 403 }; 404 405 root = gold2root(gold); 406 407 buf[25] = (root >> 24) & 0xff; 408 buf[24] = (root >> 16) & 0xff; 409 buf[23] = (root >> 8) & 0xff; 410 buf[22] = root & 0xff; 411 412 return send_command(state, sizeof(buf), buf); 413 } 414 415 static int cfg_demod_abort_tune(struct mxl *state) 416 { 417 struct MXL_HYDRA_DEMOD_ABORT_TUNE_T abort_tune_cmd; 418 u8 cmd_size = sizeof(abort_tune_cmd); 419 u8 cmd_buff[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN]; 420 421 abort_tune_cmd.demod_id = state->demod; 422 BUILD_HYDRA_CMD(MXL_HYDRA_ABORT_TUNE_CMD, MXL_CMD_WRITE, 423 cmd_size, &abort_tune_cmd, cmd_buff); 424 return send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE, 425 &cmd_buff[0]); 426 } 427 428 static int send_master_cmd(struct dvb_frontend *fe, 429 struct dvb_diseqc_master_cmd *cmd) 430 { 431 /*struct mxl *state = fe->demodulator_priv;*/ 432 433 return 0; /*CfgDemodAbortTune(state);*/ 434 } 435 436 static int set_parameters(struct dvb_frontend *fe) 437 { 438 struct mxl *state = fe->demodulator_priv; 439 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 440 struct MXL_HYDRA_DEMOD_PARAM_T demod_chan_cfg; 441 u8 cmd_size = sizeof(demod_chan_cfg); 442 u8 cmd_buff[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN]; 443 u32 srange = 10; 444 int stat; 445 446 if (p->frequency < 950000 || p->frequency > 2150000) 447 return -EINVAL; 448 if (p->symbol_rate < 1000000 || p->symbol_rate > 45000000) 449 return -EINVAL; 450 451 /* CfgDemodAbortTune(state); */ 452 453 switch (p->delivery_system) { 454 case SYS_DSS: 455 demod_chan_cfg.standard = MXL_HYDRA_DSS; 456 demod_chan_cfg.roll_off = MXL_HYDRA_ROLLOFF_AUTO; 457 break; 458 case SYS_DVBS: 459 srange = p->symbol_rate / 1000000; 460 if (srange > 10) 461 srange = 10; 462 demod_chan_cfg.standard = MXL_HYDRA_DVBS; 463 demod_chan_cfg.roll_off = MXL_HYDRA_ROLLOFF_0_35; 464 demod_chan_cfg.modulation_scheme = MXL_HYDRA_MOD_QPSK; 465 demod_chan_cfg.pilots = MXL_HYDRA_PILOTS_OFF; 466 break; 467 case SYS_DVBS2: 468 demod_chan_cfg.standard = MXL_HYDRA_DVBS2; 469 demod_chan_cfg.roll_off = MXL_HYDRA_ROLLOFF_AUTO; 470 demod_chan_cfg.modulation_scheme = MXL_HYDRA_MOD_AUTO; 471 demod_chan_cfg.pilots = MXL_HYDRA_PILOTS_AUTO; 472 cfg_scrambler(state, p->scrambling_sequence_index); 473 break; 474 default: 475 return -EINVAL; 476 } 477 demod_chan_cfg.tuner_index = state->tuner; 478 demod_chan_cfg.demod_index = state->demod; 479 demod_chan_cfg.frequency_in_hz = p->frequency * 1000; 480 demod_chan_cfg.symbol_rate_in_hz = p->symbol_rate; 481 demod_chan_cfg.max_carrier_offset_in_mhz = srange; 482 demod_chan_cfg.spectrum_inversion = MXL_HYDRA_SPECTRUM_AUTO; 483 demod_chan_cfg.fec_code_rate = MXL_HYDRA_FEC_AUTO; 484 485 mutex_lock(&state->base->tune_lock); 486 if (time_after(jiffies + msecs_to_jiffies(200), 487 state->base->next_tune)) 488 while (time_before(jiffies, state->base->next_tune)) 489 usleep_range(10000, 11000); 490 state->base->next_tune = jiffies + msecs_to_jiffies(100); 491 state->tuner_in_use = state->tuner; 492 BUILD_HYDRA_CMD(MXL_HYDRA_DEMOD_SET_PARAM_CMD, MXL_CMD_WRITE, 493 cmd_size, &demod_chan_cfg, cmd_buff); 494 stat = send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE, 495 &cmd_buff[0]); 496 mutex_unlock(&state->base->tune_lock); 497 return stat; 498 } 499 500 static int enable_tuner(struct mxl *state, u32 tuner, u32 enable); 501 502 static int sleep(struct dvb_frontend *fe) 503 { 504 struct mxl *state = fe->demodulator_priv; 505 struct mxl *p; 506 507 cfg_demod_abort_tune(state); 508 if (state->tuner_in_use != 0xffffffff) { 509 mutex_lock(&state->base->tune_lock); 510 state->tuner_in_use = 0xffffffff; 511 list_for_each_entry(p, &state->base->mxls, mxl) { 512 if (p->tuner_in_use == state->tuner) 513 break; 514 } 515 if (&p->mxl == &state->base->mxls) 516 enable_tuner(state, state->tuner, 0); 517 mutex_unlock(&state->base->tune_lock); 518 } 519 return 0; 520 } 521 522 static int read_snr(struct dvb_frontend *fe) 523 { 524 struct mxl *state = fe->demodulator_priv; 525 int stat; 526 u32 reg_data = 0; 527 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 528 529 mutex_lock(&state->base->status_lock); 530 HYDRA_DEMOD_STATUS_LOCK(state, state->demod); 531 stat = read_register(state, (HYDRA_DMD_SNR_ADDR_OFFSET + 532 HYDRA_DMD_STATUS_OFFSET(state->demod)), 533 ®_data); 534 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod); 535 mutex_unlock(&state->base->status_lock); 536 537 p->cnr.stat[0].scale = FE_SCALE_DECIBEL; 538 p->cnr.stat[0].svalue = (s16)reg_data * 10; 539 540 return stat; 541 } 542 543 static int read_ber(struct dvb_frontend *fe) 544 { 545 struct mxl *state = fe->demodulator_priv; 546 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 547 u32 reg[8]; 548 549 mutex_lock(&state->base->status_lock); 550 HYDRA_DEMOD_STATUS_LOCK(state, state->demod); 551 read_register_block(state, 552 (HYDRA_DMD_DVBS_1ST_CORR_RS_ERRORS_ADDR_OFFSET + 553 HYDRA_DMD_STATUS_OFFSET(state->demod)), 554 (4 * sizeof(u32)), 555 (u8 *) ®[0]); 556 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod); 557 558 switch (p->delivery_system) { 559 case SYS_DSS: 560 case SYS_DVBS: 561 p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; 562 p->pre_bit_error.stat[0].uvalue = reg[2]; 563 p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; 564 p->pre_bit_count.stat[0].uvalue = reg[3]; 565 break; 566 default: 567 break; 568 } 569 570 read_register_block(state, 571 (HYDRA_DMD_DVBS2_CRC_ERRORS_ADDR_OFFSET + 572 HYDRA_DMD_STATUS_OFFSET(state->demod)), 573 (7 * sizeof(u32)), 574 (u8 *) ®[0]); 575 576 switch (p->delivery_system) { 577 case SYS_DSS: 578 case SYS_DVBS: 579 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; 580 p->post_bit_error.stat[0].uvalue = reg[5]; 581 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; 582 p->post_bit_count.stat[0].uvalue = reg[6]; 583 break; 584 case SYS_DVBS2: 585 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; 586 p->post_bit_error.stat[0].uvalue = reg[1]; 587 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; 588 p->post_bit_count.stat[0].uvalue = reg[2]; 589 break; 590 default: 591 break; 592 } 593 594 mutex_unlock(&state->base->status_lock); 595 596 return 0; 597 } 598 599 static int read_signal_strength(struct dvb_frontend *fe) 600 { 601 struct mxl *state = fe->demodulator_priv; 602 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 603 int stat; 604 u32 reg_data = 0; 605 606 mutex_lock(&state->base->status_lock); 607 HYDRA_DEMOD_STATUS_LOCK(state, state->demod); 608 stat = read_register(state, (HYDRA_DMD_STATUS_INPUT_POWER_ADDR + 609 HYDRA_DMD_STATUS_OFFSET(state->demod)), 610 ®_data); 611 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod); 612 mutex_unlock(&state->base->status_lock); 613 614 p->strength.stat[0].scale = FE_SCALE_DECIBEL; 615 p->strength.stat[0].svalue = (s16) reg_data * 10; /* fix scale */ 616 617 return stat; 618 } 619 620 static int read_status(struct dvb_frontend *fe, enum fe_status *status) 621 { 622 struct mxl *state = fe->demodulator_priv; 623 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 624 u32 reg_data = 0; 625 626 mutex_lock(&state->base->status_lock); 627 HYDRA_DEMOD_STATUS_LOCK(state, state->demod); 628 read_register(state, (HYDRA_DMD_LOCK_STATUS_ADDR_OFFSET + 629 HYDRA_DMD_STATUS_OFFSET(state->demod)), 630 ®_data); 631 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod); 632 mutex_unlock(&state->base->status_lock); 633 634 *status = (reg_data == 1) ? 0x1f : 0; 635 636 /* signal statistics */ 637 638 /* signal strength is always available */ 639 read_signal_strength(fe); 640 641 if (*status & FE_HAS_CARRIER) 642 read_snr(fe); 643 else 644 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 645 646 if (*status & FE_HAS_SYNC) 647 read_ber(fe); 648 else { 649 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 650 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 651 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 652 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 653 } 654 655 return 0; 656 } 657 658 static int tune(struct dvb_frontend *fe, bool re_tune, 659 unsigned int mode_flags, 660 unsigned int *delay, enum fe_status *status) 661 { 662 struct mxl *state = fe->demodulator_priv; 663 int r = 0; 664 665 *delay = HZ / 2; 666 if (re_tune) { 667 r = set_parameters(fe); 668 if (r) 669 return r; 670 state->tune_time = jiffies; 671 } 672 673 return read_status(fe, status); 674 } 675 676 static enum fe_code_rate conv_fec(enum MXL_HYDRA_FEC_E fec) 677 { 678 enum fe_code_rate fec2fec[11] = { 679 FEC_NONE, FEC_1_2, FEC_3_5, FEC_2_3, 680 FEC_3_4, FEC_4_5, FEC_5_6, FEC_6_7, 681 FEC_7_8, FEC_8_9, FEC_9_10 682 }; 683 684 if (fec > MXL_HYDRA_FEC_9_10) 685 return FEC_NONE; 686 return fec2fec[fec]; 687 } 688 689 static int get_frontend(struct dvb_frontend *fe, 690 struct dtv_frontend_properties *p) 691 { 692 struct mxl *state = fe->demodulator_priv; 693 u32 reg_data[MXL_DEMOD_CHAN_PARAMS_BUFF_SIZE]; 694 u32 freq; 695 696 mutex_lock(&state->base->status_lock); 697 HYDRA_DEMOD_STATUS_LOCK(state, state->demod); 698 read_register_block(state, 699 (HYDRA_DMD_STANDARD_ADDR_OFFSET + 700 HYDRA_DMD_STATUS_OFFSET(state->demod)), 701 (MXL_DEMOD_CHAN_PARAMS_BUFF_SIZE * 4), /* 25 * 4 bytes */ 702 (u8 *) ®_data[0]); 703 /* read demod channel parameters */ 704 read_register_block(state, 705 (HYDRA_DMD_STATUS_CENTER_FREQ_IN_KHZ_ADDR + 706 HYDRA_DMD_STATUS_OFFSET(state->demod)), 707 (4), /* 4 bytes */ 708 (u8 *) &freq); 709 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod); 710 mutex_unlock(&state->base->status_lock); 711 712 dev_dbg(state->i2cdev, "freq=%u delsys=%u srate=%u\n", 713 freq * 1000, reg_data[DMD_STANDARD_ADDR], 714 reg_data[DMD_SYMBOL_RATE_ADDR]); 715 p->symbol_rate = reg_data[DMD_SYMBOL_RATE_ADDR]; 716 p->frequency = freq; 717 /* 718 * p->delivery_system = 719 * (MXL_HYDRA_BCAST_STD_E) regData[DMD_STANDARD_ADDR]; 720 * p->inversion = 721 * (MXL_HYDRA_SPECTRUM_E) regData[DMD_SPECTRUM_INVERSION_ADDR]; 722 * freqSearchRangeKHz = 723 * (regData[DMD_FREQ_SEARCH_RANGE_IN_KHZ_ADDR]); 724 */ 725 726 p->fec_inner = conv_fec(reg_data[DMD_FEC_CODE_RATE_ADDR]); 727 switch (p->delivery_system) { 728 case SYS_DSS: 729 break; 730 case SYS_DVBS2: 731 switch ((enum MXL_HYDRA_PILOTS_E) 732 reg_data[DMD_DVBS2_PILOT_ON_OFF_ADDR]) { 733 case MXL_HYDRA_PILOTS_OFF: 734 p->pilot = PILOT_OFF; 735 break; 736 case MXL_HYDRA_PILOTS_ON: 737 p->pilot = PILOT_ON; 738 break; 739 default: 740 break; 741 } 742 case SYS_DVBS: 743 switch ((enum MXL_HYDRA_MODULATION_E) 744 reg_data[DMD_MODULATION_SCHEME_ADDR]) { 745 case MXL_HYDRA_MOD_QPSK: 746 p->modulation = QPSK; 747 break; 748 case MXL_HYDRA_MOD_8PSK: 749 p->modulation = PSK_8; 750 break; 751 default: 752 break; 753 } 754 switch ((enum MXL_HYDRA_ROLLOFF_E) 755 reg_data[DMD_SPECTRUM_ROLL_OFF_ADDR]) { 756 case MXL_HYDRA_ROLLOFF_0_20: 757 p->rolloff = ROLLOFF_20; 758 break; 759 case MXL_HYDRA_ROLLOFF_0_35: 760 p->rolloff = ROLLOFF_35; 761 break; 762 case MXL_HYDRA_ROLLOFF_0_25: 763 p->rolloff = ROLLOFF_25; 764 break; 765 default: 766 break; 767 } 768 break; 769 default: 770 return -EINVAL; 771 } 772 return 0; 773 } 774 775 static int set_input(struct dvb_frontend *fe, int input) 776 { 777 struct mxl *state = fe->demodulator_priv; 778 779 state->tuner = input; 780 return 0; 781 } 782 783 static struct dvb_frontend_ops mxl_ops = { 784 .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS }, 785 .info = { 786 .name = "MaxLinear MxL5xx DVB-S/S2 tuner-demodulator", 787 .frequency_min = 300000, 788 .frequency_max = 2350000, 789 .frequency_stepsize = 0, 790 .frequency_tolerance = 0, 791 .symbol_rate_min = 1000000, 792 .symbol_rate_max = 45000000, 793 .caps = FE_CAN_INVERSION_AUTO | 794 FE_CAN_FEC_AUTO | 795 FE_CAN_QPSK | 796 FE_CAN_2G_MODULATION 797 }, 798 .init = init, 799 .release = release, 800 .get_frontend_algo = get_algo, 801 .tune = tune, 802 .read_status = read_status, 803 .sleep = sleep, 804 .get_frontend = get_frontend, 805 .diseqc_send_master_cmd = send_master_cmd, 806 }; 807 808 static struct mxl_base *match_base(struct i2c_adapter *i2c, u8 adr) 809 { 810 struct mxl_base *p; 811 812 list_for_each_entry(p, &mxllist, mxllist) 813 if (p->i2c == i2c && p->adr == adr) 814 return p; 815 return NULL; 816 } 817 818 static void cfg_dev_xtal(struct mxl *state, u32 freq, u32 cap, u32 enable) 819 { 820 if (state->base->can_clkout || !enable) 821 update_by_mnemonic(state, 0x90200054, 23, 1, enable); 822 823 if (freq == 24000000) 824 write_register(state, HYDRA_CRYSTAL_SETTING, 0); 825 else 826 write_register(state, HYDRA_CRYSTAL_SETTING, 1); 827 828 write_register(state, HYDRA_CRYSTAL_CAP, cap); 829 } 830 831 static u32 get_big_endian(u8 num_of_bits, const u8 buf[]) 832 { 833 u32 ret_value = 0; 834 835 switch (num_of_bits) { 836 case 24: 837 ret_value = (((u32) buf[0]) << 16) | 838 (((u32) buf[1]) << 8) | buf[2]; 839 break; 840 case 32: 841 ret_value = (((u32) buf[0]) << 24) | 842 (((u32) buf[1]) << 16) | 843 (((u32) buf[2]) << 8) | buf[3]; 844 break; 845 default: 846 break; 847 } 848 849 return ret_value; 850 } 851 852 static int write_fw_segment(struct mxl *state, 853 u32 mem_addr, u32 total_size, u8 *data_ptr) 854 { 855 int status; 856 u32 data_count = 0; 857 u32 size = 0; 858 u32 orig_size = 0; 859 u8 *w_buf_ptr = NULL; 860 u32 block_size = ((MXL_HYDRA_OEM_MAX_BLOCK_WRITE_LENGTH - 861 (MXL_HYDRA_I2C_HDR_SIZE + 862 MXL_HYDRA_REG_SIZE_IN_BYTES)) / 4) * 4; 863 u8 w_msg_buffer[MXL_HYDRA_OEM_MAX_BLOCK_WRITE_LENGTH - 864 (MXL_HYDRA_I2C_HDR_SIZE + MXL_HYDRA_REG_SIZE_IN_BYTES)]; 865 866 do { 867 size = orig_size = (((u32)(data_count + block_size)) > total_size) ? 868 (total_size - data_count) : block_size; 869 870 if (orig_size & 3) 871 size = (orig_size + 4) & ~3; 872 w_buf_ptr = &w_msg_buffer[0]; 873 memset((void *) w_buf_ptr, 0, size); 874 memcpy((void *) w_buf_ptr, (void *) data_ptr, orig_size); 875 convert_endian(1, size, w_buf_ptr); 876 status = write_firmware_block(state, mem_addr, size, w_buf_ptr); 877 if (status) 878 return status; 879 data_count += size; 880 mem_addr += size; 881 data_ptr += size; 882 } while (data_count < total_size); 883 884 return status; 885 } 886 887 static int do_firmware_download(struct mxl *state, u8 *mbin_buffer_ptr, 888 u32 mbin_buffer_size) 889 890 { 891 int status; 892 u32 index = 0; 893 u32 seg_length = 0; 894 u32 seg_address = 0; 895 struct MBIN_FILE_T *mbin_ptr = (struct MBIN_FILE_T *)mbin_buffer_ptr; 896 struct MBIN_SEGMENT_T *segment_ptr; 897 enum MXL_BOOL_E xcpu_fw_flag = MXL_FALSE; 898 899 if (mbin_ptr->header.id != MBIN_FILE_HEADER_ID) { 900 dev_err(state->i2cdev, "%s: Invalid file header ID (%c)\n", 901 __func__, mbin_ptr->header.id); 902 return -EINVAL; 903 } 904 status = write_register(state, FW_DL_SIGN_ADDR, 0); 905 if (status) 906 return status; 907 segment_ptr = (struct MBIN_SEGMENT_T *) (&mbin_ptr->data[0]); 908 for (index = 0; index < mbin_ptr->header.num_segments; index++) { 909 if (segment_ptr->header.id != MBIN_SEGMENT_HEADER_ID) { 910 dev_err(state->i2cdev, "%s: Invalid segment header ID (%c)\n", 911 __func__, segment_ptr->header.id); 912 return -EINVAL; 913 } 914 seg_length = get_big_endian(24, 915 &(segment_ptr->header.len24[0])); 916 seg_address = get_big_endian(32, 917 &(segment_ptr->header.address[0])); 918 919 if (state->base->type == MXL_HYDRA_DEVICE_568) { 920 if ((((seg_address & 0x90760000) == 0x90760000) || 921 ((seg_address & 0x90740000) == 0x90740000)) && 922 (xcpu_fw_flag == MXL_FALSE)) { 923 update_by_mnemonic(state, 0x8003003C, 0, 1, 1); 924 msleep(200); 925 write_register(state, 0x90720000, 0); 926 usleep_range(10000, 11000); 927 xcpu_fw_flag = MXL_TRUE; 928 } 929 status = write_fw_segment(state, seg_address, 930 seg_length, 931 (u8 *) segment_ptr->data); 932 } else { 933 if (((seg_address & 0x90760000) != 0x90760000) && 934 ((seg_address & 0x90740000) != 0x90740000)) 935 status = write_fw_segment(state, seg_address, 936 seg_length, (u8 *) segment_ptr->data); 937 } 938 if (status) 939 return status; 940 segment_ptr = (struct MBIN_SEGMENT_T *) 941 &(segment_ptr->data[((seg_length + 3) / 4) * 4]); 942 } 943 return status; 944 } 945 946 static int check_fw(struct mxl *state, u8 *mbin, u32 mbin_len) 947 { 948 struct MBIN_FILE_HEADER_T *fh = (struct MBIN_FILE_HEADER_T *) mbin; 949 u32 flen = (fh->image_size24[0] << 16) | 950 (fh->image_size24[1] << 8) | fh->image_size24[2]; 951 u8 *fw, cs = 0; 952 u32 i; 953 954 if (fh->id != 'M' || fh->fmt_version != '1' || flen > 0x3FFF0) { 955 dev_info(state->i2cdev, "Invalid FW Header\n"); 956 return -1; 957 } 958 fw = mbin + sizeof(struct MBIN_FILE_HEADER_T); 959 for (i = 0; i < flen; i += 1) 960 cs += fw[i]; 961 if (cs != fh->image_checksum) { 962 dev_info(state->i2cdev, "Invalid FW Checksum\n"); 963 return -1; 964 } 965 return 0; 966 } 967 968 static int firmware_download(struct mxl *state, u8 *mbin, u32 mbin_len) 969 { 970 int status; 971 u32 reg_data = 0; 972 struct MXL_HYDRA_SKU_COMMAND_T dev_sku_cfg; 973 u8 cmd_size = sizeof(struct MXL_HYDRA_SKU_COMMAND_T); 974 u8 cmd_buff[sizeof(struct MXL_HYDRA_SKU_COMMAND_T) + 6]; 975 976 if (check_fw(state, mbin, mbin_len)) 977 return -1; 978 979 /* put CPU into reset */ 980 status = update_by_mnemonic(state, 0x8003003C, 0, 1, 0); 981 if (status) 982 return status; 983 usleep_range(1000, 2000); 984 985 /* Reset TX FIFO's, BBAND, XBAR */ 986 status = write_register(state, HYDRA_RESET_TRANSPORT_FIFO_REG, 987 HYDRA_RESET_TRANSPORT_FIFO_DATA); 988 if (status) 989 return status; 990 status = write_register(state, HYDRA_RESET_BBAND_REG, 991 HYDRA_RESET_BBAND_DATA); 992 if (status) 993 return status; 994 status = write_register(state, HYDRA_RESET_XBAR_REG, 995 HYDRA_RESET_XBAR_DATA); 996 if (status) 997 return status; 998 999 /* Disable clock to Baseband, Wideband, SerDes, 1000 * Alias ext & Transport modules 1001 */ 1002 status = write_register(state, HYDRA_MODULES_CLK_2_REG, 1003 HYDRA_DISABLE_CLK_2); 1004 if (status) 1005 return status; 1006 /* Clear Software & Host interrupt status - (Clear on read) */ 1007 status = read_register(state, HYDRA_PRCM_ROOT_CLK_REG, ®_data); 1008 if (status) 1009 return status; 1010 status = do_firmware_download(state, mbin, mbin_len); 1011 if (status) 1012 return status; 1013 1014 if (state->base->type == MXL_HYDRA_DEVICE_568) { 1015 usleep_range(10000, 11000); 1016 1017 /* bring XCPU out of reset */ 1018 status = write_register(state, 0x90720000, 1); 1019 if (status) 1020 return status; 1021 msleep(500); 1022 1023 /* Enable XCPU UART message processing in MCPU */ 1024 status = write_register(state, 0x9076B510, 1); 1025 if (status) 1026 return status; 1027 } else { 1028 /* Bring CPU out of reset */ 1029 status = update_by_mnemonic(state, 0x8003003C, 0, 1, 1); 1030 if (status) 1031 return status; 1032 /* Wait until FW boots */ 1033 msleep(150); 1034 } 1035 1036 /* Initialize XPT XBAR */ 1037 status = write_register(state, XPT_DMD0_BASEADDR, 0x76543210); 1038 if (status) 1039 return status; 1040 1041 if (!firmware_is_alive(state)) 1042 return -1; 1043 1044 dev_info(state->i2cdev, "Hydra FW alive. Hail!\n"); 1045 1046 /* sometimes register values are wrong shortly 1047 * after first heart beats 1048 */ 1049 msleep(50); 1050 1051 dev_sku_cfg.sku_type = state->base->sku_type; 1052 BUILD_HYDRA_CMD(MXL_HYDRA_DEV_CFG_SKU_CMD, MXL_CMD_WRITE, 1053 cmd_size, &dev_sku_cfg, cmd_buff); 1054 status = send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE, 1055 &cmd_buff[0]); 1056 1057 return status; 1058 } 1059 1060 static int cfg_ts_pad_mux(struct mxl *state, enum MXL_BOOL_E enable_serial_ts) 1061 { 1062 int status = 0; 1063 u32 pad_mux_value = 0; 1064 1065 if (enable_serial_ts == MXL_TRUE) { 1066 pad_mux_value = 0; 1067 if ((state->base->type == MXL_HYDRA_DEVICE_541) || 1068 (state->base->type == MXL_HYDRA_DEVICE_541S)) 1069 pad_mux_value = 2; 1070 } else { 1071 if ((state->base->type == MXL_HYDRA_DEVICE_581) || 1072 (state->base->type == MXL_HYDRA_DEVICE_581S)) 1073 pad_mux_value = 2; 1074 else 1075 pad_mux_value = 3; 1076 } 1077 1078 switch (state->base->type) { 1079 case MXL_HYDRA_DEVICE_561: 1080 case MXL_HYDRA_DEVICE_581: 1081 case MXL_HYDRA_DEVICE_541: 1082 case MXL_HYDRA_DEVICE_541S: 1083 case MXL_HYDRA_DEVICE_561S: 1084 case MXL_HYDRA_DEVICE_581S: 1085 status |= update_by_mnemonic(state, 0x90000170, 24, 3, 1086 pad_mux_value); 1087 status |= update_by_mnemonic(state, 0x90000170, 28, 3, 1088 pad_mux_value); 1089 status |= update_by_mnemonic(state, 0x90000174, 0, 3, 1090 pad_mux_value); 1091 status |= update_by_mnemonic(state, 0x90000174, 4, 3, 1092 pad_mux_value); 1093 status |= update_by_mnemonic(state, 0x90000174, 8, 3, 1094 pad_mux_value); 1095 status |= update_by_mnemonic(state, 0x90000174, 12, 3, 1096 pad_mux_value); 1097 status |= update_by_mnemonic(state, 0x90000174, 16, 3, 1098 pad_mux_value); 1099 status |= update_by_mnemonic(state, 0x90000174, 20, 3, 1100 pad_mux_value); 1101 status |= update_by_mnemonic(state, 0x90000174, 24, 3, 1102 pad_mux_value); 1103 status |= update_by_mnemonic(state, 0x90000174, 28, 3, 1104 pad_mux_value); 1105 status |= update_by_mnemonic(state, 0x90000178, 0, 3, 1106 pad_mux_value); 1107 status |= update_by_mnemonic(state, 0x90000178, 4, 3, 1108 pad_mux_value); 1109 status |= update_by_mnemonic(state, 0x90000178, 8, 3, 1110 pad_mux_value); 1111 break; 1112 1113 case MXL_HYDRA_DEVICE_544: 1114 case MXL_HYDRA_DEVICE_542: 1115 status |= update_by_mnemonic(state, 0x9000016C, 4, 3, 1); 1116 status |= update_by_mnemonic(state, 0x9000016C, 8, 3, 0); 1117 status |= update_by_mnemonic(state, 0x9000016C, 12, 3, 0); 1118 status |= update_by_mnemonic(state, 0x9000016C, 16, 3, 0); 1119 status |= update_by_mnemonic(state, 0x90000170, 0, 3, 0); 1120 status |= update_by_mnemonic(state, 0x90000178, 12, 3, 1); 1121 status |= update_by_mnemonic(state, 0x90000178, 16, 3, 1); 1122 status |= update_by_mnemonic(state, 0x90000178, 20, 3, 1); 1123 status |= update_by_mnemonic(state, 0x90000178, 24, 3, 1); 1124 status |= update_by_mnemonic(state, 0x9000017C, 0, 3, 1); 1125 status |= update_by_mnemonic(state, 0x9000017C, 4, 3, 1); 1126 if (enable_serial_ts == MXL_ENABLE) { 1127 status |= update_by_mnemonic(state, 1128 0x90000170, 4, 3, 0); 1129 status |= update_by_mnemonic(state, 1130 0x90000170, 8, 3, 0); 1131 status |= update_by_mnemonic(state, 1132 0x90000170, 12, 3, 0); 1133 status |= update_by_mnemonic(state, 1134 0x90000170, 16, 3, 0); 1135 status |= update_by_mnemonic(state, 1136 0x90000170, 20, 3, 1); 1137 status |= update_by_mnemonic(state, 1138 0x90000170, 24, 3, 1); 1139 status |= update_by_mnemonic(state, 1140 0x90000170, 28, 3, 2); 1141 status |= update_by_mnemonic(state, 1142 0x90000174, 0, 3, 2); 1143 status |= update_by_mnemonic(state, 1144 0x90000174, 4, 3, 2); 1145 status |= update_by_mnemonic(state, 1146 0x90000174, 8, 3, 2); 1147 status |= update_by_mnemonic(state, 1148 0x90000174, 12, 3, 2); 1149 status |= update_by_mnemonic(state, 1150 0x90000174, 16, 3, 2); 1151 status |= update_by_mnemonic(state, 1152 0x90000174, 20, 3, 2); 1153 status |= update_by_mnemonic(state, 1154 0x90000174, 24, 3, 2); 1155 status |= update_by_mnemonic(state, 1156 0x90000174, 28, 3, 2); 1157 status |= update_by_mnemonic(state, 1158 0x90000178, 0, 3, 2); 1159 status |= update_by_mnemonic(state, 1160 0x90000178, 4, 3, 2); 1161 status |= update_by_mnemonic(state, 1162 0x90000178, 8, 3, 2); 1163 } else { 1164 status |= update_by_mnemonic(state, 1165 0x90000170, 4, 3, 3); 1166 status |= update_by_mnemonic(state, 1167 0x90000170, 8, 3, 3); 1168 status |= update_by_mnemonic(state, 1169 0x90000170, 12, 3, 3); 1170 status |= update_by_mnemonic(state, 1171 0x90000170, 16, 3, 3); 1172 status |= update_by_mnemonic(state, 1173 0x90000170, 20, 3, 3); 1174 status |= update_by_mnemonic(state, 1175 0x90000170, 24, 3, 3); 1176 status |= update_by_mnemonic(state, 1177 0x90000170, 28, 3, 3); 1178 status |= update_by_mnemonic(state, 1179 0x90000174, 0, 3, 3); 1180 status |= update_by_mnemonic(state, 1181 0x90000174, 4, 3, 3); 1182 status |= update_by_mnemonic(state, 1183 0x90000174, 8, 3, 3); 1184 status |= update_by_mnemonic(state, 1185 0x90000174, 12, 3, 3); 1186 status |= update_by_mnemonic(state, 1187 0x90000174, 16, 3, 3); 1188 status |= update_by_mnemonic(state, 1189 0x90000174, 20, 3, 1); 1190 status |= update_by_mnemonic(state, 1191 0x90000174, 24, 3, 1); 1192 status |= update_by_mnemonic(state, 1193 0x90000174, 28, 3, 1); 1194 status |= update_by_mnemonic(state, 1195 0x90000178, 0, 3, 1); 1196 status |= update_by_mnemonic(state, 1197 0x90000178, 4, 3, 1); 1198 status |= update_by_mnemonic(state, 1199 0x90000178, 8, 3, 1); 1200 } 1201 break; 1202 1203 case MXL_HYDRA_DEVICE_568: 1204 if (enable_serial_ts == MXL_FALSE) { 1205 status |= update_by_mnemonic(state, 1206 0x9000016C, 8, 3, 5); 1207 status |= update_by_mnemonic(state, 1208 0x9000016C, 12, 3, 5); 1209 status |= update_by_mnemonic(state, 1210 0x9000016C, 16, 3, 5); 1211 status |= update_by_mnemonic(state, 1212 0x9000016C, 20, 3, 5); 1213 status |= update_by_mnemonic(state, 1214 0x9000016C, 24, 3, 5); 1215 status |= update_by_mnemonic(state, 1216 0x9000016C, 28, 3, 5); 1217 status |= update_by_mnemonic(state, 1218 0x90000170, 0, 3, 5); 1219 status |= update_by_mnemonic(state, 1220 0x90000170, 4, 3, 5); 1221 status |= update_by_mnemonic(state, 1222 0x90000170, 8, 3, 5); 1223 status |= update_by_mnemonic(state, 1224 0x90000170, 12, 3, 5); 1225 status |= update_by_mnemonic(state, 1226 0x90000170, 16, 3, 5); 1227 status |= update_by_mnemonic(state, 1228 0x90000170, 20, 3, 5); 1229 1230 status |= update_by_mnemonic(state, 1231 0x90000170, 24, 3, pad_mux_value); 1232 status |= update_by_mnemonic(state, 1233 0x90000174, 0, 3, pad_mux_value); 1234 status |= update_by_mnemonic(state, 1235 0x90000174, 4, 3, pad_mux_value); 1236 status |= update_by_mnemonic(state, 1237 0x90000174, 8, 3, pad_mux_value); 1238 status |= update_by_mnemonic(state, 1239 0x90000174, 12, 3, pad_mux_value); 1240 status |= update_by_mnemonic(state, 1241 0x90000174, 16, 3, pad_mux_value); 1242 status |= update_by_mnemonic(state, 1243 0x90000174, 20, 3, pad_mux_value); 1244 status |= update_by_mnemonic(state, 1245 0x90000174, 24, 3, pad_mux_value); 1246 status |= update_by_mnemonic(state, 1247 0x90000174, 28, 3, pad_mux_value); 1248 status |= update_by_mnemonic(state, 1249 0x90000178, 0, 3, pad_mux_value); 1250 status |= update_by_mnemonic(state, 1251 0x90000178, 4, 3, pad_mux_value); 1252 1253 status |= update_by_mnemonic(state, 1254 0x90000178, 8, 3, 5); 1255 status |= update_by_mnemonic(state, 1256 0x90000178, 12, 3, 5); 1257 status |= update_by_mnemonic(state, 1258 0x90000178, 16, 3, 5); 1259 status |= update_by_mnemonic(state, 1260 0x90000178, 20, 3, 5); 1261 status |= update_by_mnemonic(state, 1262 0x90000178, 24, 3, 5); 1263 status |= update_by_mnemonic(state, 1264 0x90000178, 28, 3, 5); 1265 status |= update_by_mnemonic(state, 1266 0x9000017C, 0, 3, 5); 1267 status |= update_by_mnemonic(state, 1268 0x9000017C, 4, 3, 5); 1269 } else { 1270 status |= update_by_mnemonic(state, 1271 0x90000170, 4, 3, pad_mux_value); 1272 status |= update_by_mnemonic(state, 1273 0x90000170, 8, 3, pad_mux_value); 1274 status |= update_by_mnemonic(state, 1275 0x90000170, 12, 3, pad_mux_value); 1276 status |= update_by_mnemonic(state, 1277 0x90000170, 16, 3, pad_mux_value); 1278 status |= update_by_mnemonic(state, 1279 0x90000170, 20, 3, pad_mux_value); 1280 status |= update_by_mnemonic(state, 1281 0x90000170, 24, 3, pad_mux_value); 1282 status |= update_by_mnemonic(state, 1283 0x90000170, 28, 3, pad_mux_value); 1284 status |= update_by_mnemonic(state, 1285 0x90000174, 0, 3, pad_mux_value); 1286 status |= update_by_mnemonic(state, 1287 0x90000174, 4, 3, pad_mux_value); 1288 status |= update_by_mnemonic(state, 1289 0x90000174, 8, 3, pad_mux_value); 1290 status |= update_by_mnemonic(state, 1291 0x90000174, 12, 3, pad_mux_value); 1292 } 1293 break; 1294 1295 1296 case MXL_HYDRA_DEVICE_584: 1297 default: 1298 status |= update_by_mnemonic(state, 1299 0x90000170, 4, 3, pad_mux_value); 1300 status |= update_by_mnemonic(state, 1301 0x90000170, 8, 3, pad_mux_value); 1302 status |= update_by_mnemonic(state, 1303 0x90000170, 12, 3, pad_mux_value); 1304 status |= update_by_mnemonic(state, 1305 0x90000170, 16, 3, pad_mux_value); 1306 status |= update_by_mnemonic(state, 1307 0x90000170, 20, 3, pad_mux_value); 1308 status |= update_by_mnemonic(state, 1309 0x90000170, 24, 3, pad_mux_value); 1310 status |= update_by_mnemonic(state, 1311 0x90000170, 28, 3, pad_mux_value); 1312 status |= update_by_mnemonic(state, 1313 0x90000174, 0, 3, pad_mux_value); 1314 status |= update_by_mnemonic(state, 1315 0x90000174, 4, 3, pad_mux_value); 1316 status |= update_by_mnemonic(state, 1317 0x90000174, 8, 3, pad_mux_value); 1318 status |= update_by_mnemonic(state, 1319 0x90000174, 12, 3, pad_mux_value); 1320 break; 1321 } 1322 return status; 1323 } 1324 1325 static int set_drive_strength(struct mxl *state, 1326 enum MXL_HYDRA_TS_DRIVE_STRENGTH_E ts_drive_strength) 1327 { 1328 int stat = 0; 1329 u32 val; 1330 1331 read_register(state, 0x90000194, &val); 1332 dev_info(state->i2cdev, "DIGIO = %08x\n", val); 1333 dev_info(state->i2cdev, "set drive_strength = %u\n", ts_drive_strength); 1334 1335 1336 stat |= update_by_mnemonic(state, 0x90000194, 0, 3, ts_drive_strength); 1337 stat |= update_by_mnemonic(state, 0x90000194, 20, 3, ts_drive_strength); 1338 stat |= update_by_mnemonic(state, 0x90000194, 24, 3, ts_drive_strength); 1339 stat |= update_by_mnemonic(state, 0x90000198, 12, 3, ts_drive_strength); 1340 stat |= update_by_mnemonic(state, 0x90000198, 16, 3, ts_drive_strength); 1341 stat |= update_by_mnemonic(state, 0x90000198, 20, 3, ts_drive_strength); 1342 stat |= update_by_mnemonic(state, 0x90000198, 24, 3, ts_drive_strength); 1343 stat |= update_by_mnemonic(state, 0x9000019C, 0, 3, ts_drive_strength); 1344 stat |= update_by_mnemonic(state, 0x9000019C, 4, 3, ts_drive_strength); 1345 stat |= update_by_mnemonic(state, 0x9000019C, 8, 3, ts_drive_strength); 1346 stat |= update_by_mnemonic(state, 0x9000019C, 24, 3, ts_drive_strength); 1347 stat |= update_by_mnemonic(state, 0x9000019C, 28, 3, ts_drive_strength); 1348 stat |= update_by_mnemonic(state, 0x900001A0, 0, 3, ts_drive_strength); 1349 stat |= update_by_mnemonic(state, 0x900001A0, 4, 3, ts_drive_strength); 1350 stat |= update_by_mnemonic(state, 0x900001A0, 20, 3, ts_drive_strength); 1351 stat |= update_by_mnemonic(state, 0x900001A0, 24, 3, ts_drive_strength); 1352 stat |= update_by_mnemonic(state, 0x900001A0, 28, 3, ts_drive_strength); 1353 1354 return stat; 1355 } 1356 1357 static int enable_tuner(struct mxl *state, u32 tuner, u32 enable) 1358 { 1359 int stat = 0; 1360 struct MXL_HYDRA_TUNER_CMD ctrl_tuner_cmd; 1361 u8 cmd_size = sizeof(ctrl_tuner_cmd); 1362 u8 cmd_buff[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN]; 1363 u32 val, count = 10; 1364 1365 ctrl_tuner_cmd.tuner_id = tuner; 1366 ctrl_tuner_cmd.enable = enable; 1367 BUILD_HYDRA_CMD(MXL_HYDRA_TUNER_ACTIVATE_CMD, MXL_CMD_WRITE, 1368 cmd_size, &ctrl_tuner_cmd, cmd_buff); 1369 stat = send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE, 1370 &cmd_buff[0]); 1371 if (stat) 1372 return stat; 1373 read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val); 1374 while (--count && ((val >> tuner) & 1) != enable) { 1375 msleep(20); 1376 read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val); 1377 } 1378 if (!count) 1379 return -1; 1380 read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val); 1381 dev_dbg(state->i2cdev, "tuner %u ready = %u\n", 1382 tuner, (val >> tuner) & 1); 1383 1384 return 0; 1385 } 1386 1387 1388 static int config_ts(struct mxl *state, enum MXL_HYDRA_DEMOD_ID_E demod_id, 1389 struct MXL_HYDRA_MPEGOUT_PARAM_T *mpeg_out_param_ptr) 1390 { 1391 int status = 0; 1392 u32 nco_count_min = 0; 1393 u32 clk_type = 0; 1394 1395 struct MXL_REG_FIELD_T xpt_sync_polarity[MXL_HYDRA_DEMOD_MAX] = { 1396 {0x90700010, 8, 1}, {0x90700010, 9, 1}, 1397 {0x90700010, 10, 1}, {0x90700010, 11, 1}, 1398 {0x90700010, 12, 1}, {0x90700010, 13, 1}, 1399 {0x90700010, 14, 1}, {0x90700010, 15, 1} }; 1400 struct MXL_REG_FIELD_T xpt_clock_polarity[MXL_HYDRA_DEMOD_MAX] = { 1401 {0x90700010, 16, 1}, {0x90700010, 17, 1}, 1402 {0x90700010, 18, 1}, {0x90700010, 19, 1}, 1403 {0x90700010, 20, 1}, {0x90700010, 21, 1}, 1404 {0x90700010, 22, 1}, {0x90700010, 23, 1} }; 1405 struct MXL_REG_FIELD_T xpt_valid_polarity[MXL_HYDRA_DEMOD_MAX] = { 1406 {0x90700014, 0, 1}, {0x90700014, 1, 1}, 1407 {0x90700014, 2, 1}, {0x90700014, 3, 1}, 1408 {0x90700014, 4, 1}, {0x90700014, 5, 1}, 1409 {0x90700014, 6, 1}, {0x90700014, 7, 1} }; 1410 struct MXL_REG_FIELD_T xpt_ts_clock_phase[MXL_HYDRA_DEMOD_MAX] = { 1411 {0x90700018, 0, 3}, {0x90700018, 4, 3}, 1412 {0x90700018, 8, 3}, {0x90700018, 12, 3}, 1413 {0x90700018, 16, 3}, {0x90700018, 20, 3}, 1414 {0x90700018, 24, 3}, {0x90700018, 28, 3} }; 1415 struct MXL_REG_FIELD_T xpt_lsb_first[MXL_HYDRA_DEMOD_MAX] = { 1416 {0x9070000C, 16, 1}, {0x9070000C, 17, 1}, 1417 {0x9070000C, 18, 1}, {0x9070000C, 19, 1}, 1418 {0x9070000C, 20, 1}, {0x9070000C, 21, 1}, 1419 {0x9070000C, 22, 1}, {0x9070000C, 23, 1} }; 1420 struct MXL_REG_FIELD_T xpt_sync_byte[MXL_HYDRA_DEMOD_MAX] = { 1421 {0x90700010, 0, 1}, {0x90700010, 1, 1}, 1422 {0x90700010, 2, 1}, {0x90700010, 3, 1}, 1423 {0x90700010, 4, 1}, {0x90700010, 5, 1}, 1424 {0x90700010, 6, 1}, {0x90700010, 7, 1} }; 1425 struct MXL_REG_FIELD_T xpt_enable_output[MXL_HYDRA_DEMOD_MAX] = { 1426 {0x9070000C, 0, 1}, {0x9070000C, 1, 1}, 1427 {0x9070000C, 2, 1}, {0x9070000C, 3, 1}, 1428 {0x9070000C, 4, 1}, {0x9070000C, 5, 1}, 1429 {0x9070000C, 6, 1}, {0x9070000C, 7, 1} }; 1430 struct MXL_REG_FIELD_T xpt_err_replace_sync[MXL_HYDRA_DEMOD_MAX] = { 1431 {0x9070000C, 24, 1}, {0x9070000C, 25, 1}, 1432 {0x9070000C, 26, 1}, {0x9070000C, 27, 1}, 1433 {0x9070000C, 28, 1}, {0x9070000C, 29, 1}, 1434 {0x9070000C, 30, 1}, {0x9070000C, 31, 1} }; 1435 struct MXL_REG_FIELD_T xpt_err_replace_valid[MXL_HYDRA_DEMOD_MAX] = { 1436 {0x90700014, 8, 1}, {0x90700014, 9, 1}, 1437 {0x90700014, 10, 1}, {0x90700014, 11, 1}, 1438 {0x90700014, 12, 1}, {0x90700014, 13, 1}, 1439 {0x90700014, 14, 1}, {0x90700014, 15, 1} }; 1440 struct MXL_REG_FIELD_T xpt_continuous_clock[MXL_HYDRA_DEMOD_MAX] = { 1441 {0x907001D4, 0, 1}, {0x907001D4, 1, 1}, 1442 {0x907001D4, 2, 1}, {0x907001D4, 3, 1}, 1443 {0x907001D4, 4, 1}, {0x907001D4, 5, 1}, 1444 {0x907001D4, 6, 1}, {0x907001D4, 7, 1} }; 1445 struct MXL_REG_FIELD_T xpt_nco_clock_rate[MXL_HYDRA_DEMOD_MAX] = { 1446 {0x90700044, 16, 80}, {0x90700044, 16, 81}, 1447 {0x90700044, 16, 82}, {0x90700044, 16, 83}, 1448 {0x90700044, 16, 84}, {0x90700044, 16, 85}, 1449 {0x90700044, 16, 86}, {0x90700044, 16, 87} }; 1450 1451 demod_id = state->base->ts_map[demod_id]; 1452 1453 if (mpeg_out_param_ptr->enable == MXL_ENABLE) { 1454 if (mpeg_out_param_ptr->mpeg_mode == 1455 MXL_HYDRA_MPEG_MODE_PARALLEL) { 1456 } else { 1457 cfg_ts_pad_mux(state, MXL_TRUE); 1458 update_by_mnemonic(state, 1459 0x90700010, 27, 1, MXL_FALSE); 1460 } 1461 } 1462 1463 nco_count_min = 1464 (u32)(MXL_HYDRA_NCO_CLK / mpeg_out_param_ptr->max_mpeg_clk_rate); 1465 1466 if (state->base->chipversion >= 2) { 1467 status |= update_by_mnemonic(state, 1468 xpt_nco_clock_rate[demod_id].reg_addr, /* Reg Addr */ 1469 xpt_nco_clock_rate[demod_id].lsb_pos, /* LSB pos */ 1470 xpt_nco_clock_rate[demod_id].num_of_bits, /* Num of bits */ 1471 nco_count_min); /* Data */ 1472 } else 1473 update_by_mnemonic(state, 0x90700044, 16, 8, nco_count_min); 1474 1475 if (mpeg_out_param_ptr->mpeg_clk_type == MXL_HYDRA_MPEG_CLK_CONTINUOUS) 1476 clk_type = 1; 1477 1478 if (mpeg_out_param_ptr->mpeg_mode < MXL_HYDRA_MPEG_MODE_PARALLEL) { 1479 status |= update_by_mnemonic(state, 1480 xpt_continuous_clock[demod_id].reg_addr, 1481 xpt_continuous_clock[demod_id].lsb_pos, 1482 xpt_continuous_clock[demod_id].num_of_bits, 1483 clk_type); 1484 } else 1485 update_by_mnemonic(state, 0x907001D4, 8, 1, clk_type); 1486 1487 status |= update_by_mnemonic(state, 1488 xpt_sync_polarity[demod_id].reg_addr, 1489 xpt_sync_polarity[demod_id].lsb_pos, 1490 xpt_sync_polarity[demod_id].num_of_bits, 1491 mpeg_out_param_ptr->mpeg_sync_pol); 1492 1493 status |= update_by_mnemonic(state, 1494 xpt_valid_polarity[demod_id].reg_addr, 1495 xpt_valid_polarity[demod_id].lsb_pos, 1496 xpt_valid_polarity[demod_id].num_of_bits, 1497 mpeg_out_param_ptr->mpeg_valid_pol); 1498 1499 status |= update_by_mnemonic(state, 1500 xpt_clock_polarity[demod_id].reg_addr, 1501 xpt_clock_polarity[demod_id].lsb_pos, 1502 xpt_clock_polarity[demod_id].num_of_bits, 1503 mpeg_out_param_ptr->mpeg_clk_pol); 1504 1505 status |= update_by_mnemonic(state, 1506 xpt_sync_byte[demod_id].reg_addr, 1507 xpt_sync_byte[demod_id].lsb_pos, 1508 xpt_sync_byte[demod_id].num_of_bits, 1509 mpeg_out_param_ptr->mpeg_sync_pulse_width); 1510 1511 status |= update_by_mnemonic(state, 1512 xpt_ts_clock_phase[demod_id].reg_addr, 1513 xpt_ts_clock_phase[demod_id].lsb_pos, 1514 xpt_ts_clock_phase[demod_id].num_of_bits, 1515 mpeg_out_param_ptr->mpeg_clk_phase); 1516 1517 status |= update_by_mnemonic(state, 1518 xpt_lsb_first[demod_id].reg_addr, 1519 xpt_lsb_first[demod_id].lsb_pos, 1520 xpt_lsb_first[demod_id].num_of_bits, 1521 mpeg_out_param_ptr->lsb_or_msb_first); 1522 1523 switch (mpeg_out_param_ptr->mpeg_error_indication) { 1524 case MXL_HYDRA_MPEG_ERR_REPLACE_SYNC: 1525 status |= update_by_mnemonic(state, 1526 xpt_err_replace_sync[demod_id].reg_addr, 1527 xpt_err_replace_sync[demod_id].lsb_pos, 1528 xpt_err_replace_sync[demod_id].num_of_bits, 1529 MXL_TRUE); 1530 status |= update_by_mnemonic(state, 1531 xpt_err_replace_valid[demod_id].reg_addr, 1532 xpt_err_replace_valid[demod_id].lsb_pos, 1533 xpt_err_replace_valid[demod_id].num_of_bits, 1534 MXL_FALSE); 1535 break; 1536 1537 case MXL_HYDRA_MPEG_ERR_REPLACE_VALID: 1538 status |= update_by_mnemonic(state, 1539 xpt_err_replace_sync[demod_id].reg_addr, 1540 xpt_err_replace_sync[demod_id].lsb_pos, 1541 xpt_err_replace_sync[demod_id].num_of_bits, 1542 MXL_FALSE); 1543 1544 status |= update_by_mnemonic(state, 1545 xpt_err_replace_valid[demod_id].reg_addr, 1546 xpt_err_replace_valid[demod_id].lsb_pos, 1547 xpt_err_replace_valid[demod_id].num_of_bits, 1548 MXL_TRUE); 1549 break; 1550 1551 case MXL_HYDRA_MPEG_ERR_INDICATION_DISABLED: 1552 default: 1553 status |= update_by_mnemonic(state, 1554 xpt_err_replace_sync[demod_id].reg_addr, 1555 xpt_err_replace_sync[demod_id].lsb_pos, 1556 xpt_err_replace_sync[demod_id].num_of_bits, 1557 MXL_FALSE); 1558 1559 status |= update_by_mnemonic(state, 1560 xpt_err_replace_valid[demod_id].reg_addr, 1561 xpt_err_replace_valid[demod_id].lsb_pos, 1562 xpt_err_replace_valid[demod_id].num_of_bits, 1563 MXL_FALSE); 1564 1565 break; 1566 1567 } 1568 1569 if (mpeg_out_param_ptr->mpeg_mode != MXL_HYDRA_MPEG_MODE_PARALLEL) { 1570 status |= update_by_mnemonic(state, 1571 xpt_enable_output[demod_id].reg_addr, 1572 xpt_enable_output[demod_id].lsb_pos, 1573 xpt_enable_output[demod_id].num_of_bits, 1574 mpeg_out_param_ptr->enable); 1575 } 1576 return status; 1577 } 1578 1579 static int config_mux(struct mxl *state) 1580 { 1581 update_by_mnemonic(state, 0x9070000C, 0, 1, 0); 1582 update_by_mnemonic(state, 0x9070000C, 1, 1, 0); 1583 update_by_mnemonic(state, 0x9070000C, 2, 1, 0); 1584 update_by_mnemonic(state, 0x9070000C, 3, 1, 0); 1585 update_by_mnemonic(state, 0x9070000C, 4, 1, 0); 1586 update_by_mnemonic(state, 0x9070000C, 5, 1, 0); 1587 update_by_mnemonic(state, 0x9070000C, 6, 1, 0); 1588 update_by_mnemonic(state, 0x9070000C, 7, 1, 0); 1589 update_by_mnemonic(state, 0x90700008, 0, 2, 1); 1590 update_by_mnemonic(state, 0x90700008, 2, 2, 1); 1591 return 0; 1592 } 1593 1594 static int load_fw(struct mxl *state, struct mxl5xx_cfg *cfg) 1595 { 1596 int stat = 0; 1597 u8 *buf; 1598 1599 if (cfg->fw) 1600 return firmware_download(state, cfg->fw, cfg->fw_len); 1601 1602 if (!cfg->fw_read) 1603 return -1; 1604 1605 buf = vmalloc(0x40000); 1606 if (!buf) 1607 return -ENOMEM; 1608 1609 cfg->fw_read(cfg->fw_priv, buf, 0x40000); 1610 stat = firmware_download(state, buf, 0x40000); 1611 vfree(buf); 1612 1613 return stat; 1614 } 1615 1616 static int validate_sku(struct mxl *state) 1617 { 1618 u32 pad_mux_bond = 0, prcm_chip_id = 0, prcm_so_cid = 0; 1619 int status; 1620 u32 type = state->base->type; 1621 1622 status = read_by_mnemonic(state, 0x90000190, 0, 3, &pad_mux_bond); 1623 status |= read_by_mnemonic(state, 0x80030000, 0, 12, &prcm_chip_id); 1624 status |= read_by_mnemonic(state, 0x80030004, 24, 8, &prcm_so_cid); 1625 if (status) 1626 return -1; 1627 1628 dev_info(state->i2cdev, "padMuxBond=%08x, prcmChipId=%08x, prcmSoCId=%08x\n", 1629 pad_mux_bond, prcm_chip_id, prcm_so_cid); 1630 1631 if (prcm_chip_id != 0x560) { 1632 switch (pad_mux_bond) { 1633 case MXL_HYDRA_SKU_ID_581: 1634 if (type == MXL_HYDRA_DEVICE_581) 1635 return 0; 1636 if (type == MXL_HYDRA_DEVICE_581S) { 1637 state->base->type = MXL_HYDRA_DEVICE_581; 1638 return 0; 1639 } 1640 break; 1641 case MXL_HYDRA_SKU_ID_584: 1642 if (type == MXL_HYDRA_DEVICE_584) 1643 return 0; 1644 break; 1645 case MXL_HYDRA_SKU_ID_544: 1646 if (type == MXL_HYDRA_DEVICE_544) 1647 return 0; 1648 if (type == MXL_HYDRA_DEVICE_542) 1649 return 0; 1650 break; 1651 case MXL_HYDRA_SKU_ID_582: 1652 if (type == MXL_HYDRA_DEVICE_582) 1653 return 0; 1654 break; 1655 default: 1656 return -1; 1657 } 1658 } else { 1659 1660 } 1661 return -1; 1662 } 1663 1664 static int get_fwinfo(struct mxl *state) 1665 { 1666 int status; 1667 u32 val = 0; 1668 1669 status = read_by_mnemonic(state, 0x90000190, 0, 3, &val); 1670 if (status) 1671 return status; 1672 dev_info(state->i2cdev, "chipID=%08x\n", val); 1673 1674 status = read_by_mnemonic(state, 0x80030004, 8, 8, &val); 1675 if (status) 1676 return status; 1677 dev_info(state->i2cdev, "chipVer=%08x\n", val); 1678 1679 status = read_register(state, HYDRA_FIRMWARE_VERSION, &val); 1680 if (status) 1681 return status; 1682 dev_info(state->i2cdev, "FWVer=%08x\n", val); 1683 1684 state->base->fwversion = val; 1685 return status; 1686 } 1687 1688 1689 static u8 ts_map1_to_1[MXL_HYDRA_DEMOD_MAX] = { 1690 MXL_HYDRA_DEMOD_ID_0, 1691 MXL_HYDRA_DEMOD_ID_1, 1692 MXL_HYDRA_DEMOD_ID_2, 1693 MXL_HYDRA_DEMOD_ID_3, 1694 MXL_HYDRA_DEMOD_ID_4, 1695 MXL_HYDRA_DEMOD_ID_5, 1696 MXL_HYDRA_DEMOD_ID_6, 1697 MXL_HYDRA_DEMOD_ID_7, 1698 }; 1699 1700 static u8 ts_map54x[MXL_HYDRA_DEMOD_MAX] = { 1701 MXL_HYDRA_DEMOD_ID_2, 1702 MXL_HYDRA_DEMOD_ID_3, 1703 MXL_HYDRA_DEMOD_ID_4, 1704 MXL_HYDRA_DEMOD_ID_5, 1705 MXL_HYDRA_DEMOD_MAX, 1706 MXL_HYDRA_DEMOD_MAX, 1707 MXL_HYDRA_DEMOD_MAX, 1708 MXL_HYDRA_DEMOD_MAX, 1709 }; 1710 1711 static int probe(struct mxl *state, struct mxl5xx_cfg *cfg) 1712 { 1713 u32 chipver; 1714 int fw, status, j; 1715 struct MXL_HYDRA_MPEGOUT_PARAM_T mpeg_interface_cfg; 1716 1717 state->base->ts_map = ts_map1_to_1; 1718 1719 switch (state->base->type) { 1720 case MXL_HYDRA_DEVICE_581: 1721 case MXL_HYDRA_DEVICE_581S: 1722 state->base->can_clkout = 1; 1723 state->base->demod_num = 8; 1724 state->base->tuner_num = 1; 1725 state->base->sku_type = MXL_HYDRA_SKU_TYPE_581; 1726 break; 1727 case MXL_HYDRA_DEVICE_582: 1728 state->base->can_clkout = 1; 1729 state->base->demod_num = 8; 1730 state->base->tuner_num = 3; 1731 state->base->sku_type = MXL_HYDRA_SKU_TYPE_582; 1732 break; 1733 case MXL_HYDRA_DEVICE_585: 1734 state->base->can_clkout = 0; 1735 state->base->demod_num = 8; 1736 state->base->tuner_num = 4; 1737 state->base->sku_type = MXL_HYDRA_SKU_TYPE_585; 1738 break; 1739 case MXL_HYDRA_DEVICE_544: 1740 state->base->can_clkout = 0; 1741 state->base->demod_num = 4; 1742 state->base->tuner_num = 4; 1743 state->base->sku_type = MXL_HYDRA_SKU_TYPE_544; 1744 state->base->ts_map = ts_map54x; 1745 break; 1746 case MXL_HYDRA_DEVICE_541: 1747 case MXL_HYDRA_DEVICE_541S: 1748 state->base->can_clkout = 0; 1749 state->base->demod_num = 4; 1750 state->base->tuner_num = 1; 1751 state->base->sku_type = MXL_HYDRA_SKU_TYPE_541; 1752 state->base->ts_map = ts_map54x; 1753 break; 1754 case MXL_HYDRA_DEVICE_561: 1755 case MXL_HYDRA_DEVICE_561S: 1756 state->base->can_clkout = 0; 1757 state->base->demod_num = 6; 1758 state->base->tuner_num = 1; 1759 state->base->sku_type = MXL_HYDRA_SKU_TYPE_561; 1760 break; 1761 case MXL_HYDRA_DEVICE_568: 1762 state->base->can_clkout = 0; 1763 state->base->demod_num = 8; 1764 state->base->tuner_num = 1; 1765 state->base->chan_bond = 1; 1766 state->base->sku_type = MXL_HYDRA_SKU_TYPE_568; 1767 break; 1768 case MXL_HYDRA_DEVICE_542: 1769 state->base->can_clkout = 1; 1770 state->base->demod_num = 4; 1771 state->base->tuner_num = 3; 1772 state->base->sku_type = MXL_HYDRA_SKU_TYPE_542; 1773 state->base->ts_map = ts_map54x; 1774 break; 1775 case MXL_HYDRA_DEVICE_TEST: 1776 case MXL_HYDRA_DEVICE_584: 1777 default: 1778 state->base->can_clkout = 0; 1779 state->base->demod_num = 8; 1780 state->base->tuner_num = 4; 1781 state->base->sku_type = MXL_HYDRA_SKU_TYPE_584; 1782 break; 1783 } 1784 1785 status = validate_sku(state); 1786 if (status) 1787 return status; 1788 1789 update_by_mnemonic(state, 0x80030014, 9, 1, 1); 1790 update_by_mnemonic(state, 0x8003003C, 12, 1, 1); 1791 status = read_by_mnemonic(state, 0x80030000, 12, 4, &chipver); 1792 if (status) 1793 state->base->chipversion = 0; 1794 else 1795 state->base->chipversion = (chipver == 2) ? 2 : 1; 1796 dev_info(state->i2cdev, "Hydra chip version %u\n", 1797 state->base->chipversion); 1798 1799 cfg_dev_xtal(state, cfg->clk, cfg->cap, 0); 1800 1801 fw = firmware_is_alive(state); 1802 if (!fw) { 1803 status = load_fw(state, cfg); 1804 if (status) 1805 return status; 1806 } 1807 get_fwinfo(state); 1808 1809 config_mux(state); 1810 mpeg_interface_cfg.enable = MXL_ENABLE; 1811 mpeg_interface_cfg.lsb_or_msb_first = MXL_HYDRA_MPEG_SERIAL_MSB_1ST; 1812 /* supports only (0-104&139)MHz */ 1813 if (cfg->ts_clk) 1814 mpeg_interface_cfg.max_mpeg_clk_rate = cfg->ts_clk; 1815 else 1816 mpeg_interface_cfg.max_mpeg_clk_rate = 69; /* 139; */ 1817 mpeg_interface_cfg.mpeg_clk_phase = MXL_HYDRA_MPEG_CLK_PHASE_SHIFT_0_DEG; 1818 mpeg_interface_cfg.mpeg_clk_pol = MXL_HYDRA_MPEG_CLK_IN_PHASE; 1819 /* MXL_HYDRA_MPEG_CLK_GAPPED; */ 1820 mpeg_interface_cfg.mpeg_clk_type = MXL_HYDRA_MPEG_CLK_CONTINUOUS; 1821 mpeg_interface_cfg.mpeg_error_indication = 1822 MXL_HYDRA_MPEG_ERR_INDICATION_DISABLED; 1823 mpeg_interface_cfg.mpeg_mode = MXL_HYDRA_MPEG_MODE_SERIAL_3_WIRE; 1824 mpeg_interface_cfg.mpeg_sync_pol = MXL_HYDRA_MPEG_ACTIVE_HIGH; 1825 mpeg_interface_cfg.mpeg_sync_pulse_width = MXL_HYDRA_MPEG_SYNC_WIDTH_BIT; 1826 mpeg_interface_cfg.mpeg_valid_pol = MXL_HYDRA_MPEG_ACTIVE_HIGH; 1827 1828 for (j = 0; j < state->base->demod_num; j++) { 1829 status = config_ts(state, (enum MXL_HYDRA_DEMOD_ID_E) j, 1830 &mpeg_interface_cfg); 1831 if (status) 1832 return status; 1833 } 1834 set_drive_strength(state, 1); 1835 return 0; 1836 } 1837 1838 struct dvb_frontend *mxl5xx_attach(struct i2c_adapter *i2c, 1839 struct mxl5xx_cfg *cfg, u32 demod, u32 tuner, 1840 int (**fn_set_input)(struct dvb_frontend *, int)) 1841 { 1842 struct mxl *state; 1843 struct mxl_base *base; 1844 1845 state = kzalloc(sizeof(struct mxl), GFP_KERNEL); 1846 if (!state) 1847 return NULL; 1848 1849 state->demod = demod; 1850 state->tuner = tuner; 1851 state->tuner_in_use = 0xffffffff; 1852 state->i2cdev = &i2c->dev; 1853 1854 base = match_base(i2c, cfg->adr); 1855 if (base) { 1856 base->count++; 1857 if (base->count > base->demod_num) 1858 goto fail; 1859 state->base = base; 1860 } else { 1861 base = kzalloc(sizeof(struct mxl_base), GFP_KERNEL); 1862 if (!base) 1863 goto fail; 1864 base->i2c = i2c; 1865 base->adr = cfg->adr; 1866 base->type = cfg->type; 1867 base->count = 1; 1868 mutex_init(&base->i2c_lock); 1869 mutex_init(&base->status_lock); 1870 mutex_init(&base->tune_lock); 1871 INIT_LIST_HEAD(&base->mxls); 1872 1873 state->base = base; 1874 if (probe(state, cfg) < 0) { 1875 kfree(base); 1876 goto fail; 1877 } 1878 list_add(&base->mxllist, &mxllist); 1879 } 1880 state->fe.ops = mxl_ops; 1881 state->xbar[0] = 4; 1882 state->xbar[1] = demod; 1883 state->xbar[2] = 8; 1884 state->fe.demodulator_priv = state; 1885 *fn_set_input = set_input; 1886 1887 list_add(&state->mxl, &base->mxls); 1888 return &state->fe; 1889 1890 fail: 1891 kfree(state); 1892 return NULL; 1893 } 1894 EXPORT_SYMBOL_GPL(mxl5xx_attach); 1895 1896 MODULE_DESCRIPTION("MaxLinear MxL5xx DVB-S/S2 tuner-demodulator driver"); 1897 MODULE_AUTHOR("Ralph and Marcus Metzler, Metzler Brothers Systementwicklung GbR"); 1898 MODULE_LICENSE("GPL"); 1899