1 /* 2 * Driver for Zarlink DVB-T MT352 demodulator 3 * 4 * Written by Holger Waechtler <holger@qanu.de> 5 * and Daniel Mack <daniel@qanu.de> 6 * 7 * AVerMedia AVerTV DVB-T 771 support by 8 * Wolfram Joost <dbox2@frokaschwei.de> 9 * 10 * Support for Samsung TDTC9251DH01C(M) tuner 11 * Copyright (C) 2004 Antonio Mancuso <antonio.mancuso@digitaltelevision.it> 12 * Amauri Celani <acelani@essegi.net> 13 * 14 * DVICO FusionHDTV DVB-T1 and DVICO FusionHDTV DVB-T Lite support by 15 * Christopher Pascoe <c.pascoe@itee.uq.edu.au> 16 * 17 * This program is free software; you can redistribute it and/or modify 18 * it under the terms of the GNU General Public License as published by 19 * the Free Software Foundation; either version 2 of the License, or 20 * (at your option) any later version. 21 * 22 * This program is distributed in the hope that it will be useful, 23 * but WITHOUT ANY WARRANTY; without even the implied warranty of 24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 * 26 * GNU General Public License for more details. 27 */ 28 29 #include <linux/kernel.h> 30 #include <linux/module.h> 31 #include <linux/init.h> 32 #include <linux/delay.h> 33 #include <linux/string.h> 34 #include <linux/slab.h> 35 36 #include <media/dvb_frontend.h> 37 #include "mt352_priv.h" 38 #include "mt352.h" 39 40 struct mt352_state { 41 struct i2c_adapter* i2c; 42 struct dvb_frontend frontend; 43 44 /* configuration settings */ 45 struct mt352_config config; 46 }; 47 48 static int debug; 49 #define dprintk(args...) \ 50 do { \ 51 if (debug) printk(KERN_DEBUG "mt352: " args); \ 52 } while (0) 53 54 static int mt352_single_write(struct dvb_frontend *fe, u8 reg, u8 val) 55 { 56 struct mt352_state* state = fe->demodulator_priv; 57 u8 buf[2] = { reg, val }; 58 struct i2c_msg msg = { .addr = state->config.demod_address, .flags = 0, 59 .buf = buf, .len = 2 }; 60 int err = i2c_transfer(state->i2c, &msg, 1); 61 if (err != 1) { 62 printk("mt352_write() to reg %x failed (err = %d)!\n", reg, err); 63 return err; 64 } 65 return 0; 66 } 67 68 static int _mt352_write(struct dvb_frontend* fe, const u8 ibuf[], int ilen) 69 { 70 int err,i; 71 for (i=0; i < ilen-1; i++) 72 if ((err = mt352_single_write(fe,ibuf[0]+i,ibuf[i+1]))) 73 return err; 74 75 return 0; 76 } 77 78 static int mt352_read_register(struct mt352_state* state, u8 reg) 79 { 80 int ret; 81 u8 b0 [] = { reg }; 82 u8 b1 [] = { 0 }; 83 struct i2c_msg msg [] = { { .addr = state->config.demod_address, 84 .flags = 0, 85 .buf = b0, .len = 1 }, 86 { .addr = state->config.demod_address, 87 .flags = I2C_M_RD, 88 .buf = b1, .len = 1 } }; 89 90 ret = i2c_transfer(state->i2c, msg, 2); 91 92 if (ret != 2) { 93 printk("%s: readreg error (reg=%d, ret==%i)\n", 94 __func__, reg, ret); 95 return ret; 96 } 97 98 return b1[0]; 99 } 100 101 static int mt352_sleep(struct dvb_frontend* fe) 102 { 103 static u8 mt352_softdown[] = { CLOCK_CTL, 0x20, 0x08 }; 104 105 _mt352_write(fe, mt352_softdown, sizeof(mt352_softdown)); 106 return 0; 107 } 108 109 static void mt352_calc_nominal_rate(struct mt352_state* state, 110 u32 bandwidth, 111 unsigned char *buf) 112 { 113 u32 adc_clock = 20480; /* 20.340 MHz */ 114 u32 bw,value; 115 116 switch (bandwidth) { 117 case 6000000: 118 bw = 6; 119 break; 120 case 7000000: 121 bw = 7; 122 break; 123 case 8000000: 124 default: 125 bw = 8; 126 break; 127 } 128 if (state->config.adc_clock) 129 adc_clock = state->config.adc_clock; 130 131 value = 64 * bw * (1<<16) / (7 * 8); 132 value = value * 1000 / adc_clock; 133 dprintk("%s: bw %d, adc_clock %d => 0x%x\n", 134 __func__, bw, adc_clock, value); 135 buf[0] = msb(value); 136 buf[1] = lsb(value); 137 } 138 139 static void mt352_calc_input_freq(struct mt352_state* state, 140 unsigned char *buf) 141 { 142 int adc_clock = 20480; /* 20.480000 MHz */ 143 int if2 = 36167; /* 36.166667 MHz */ 144 int ife,value; 145 146 if (state->config.adc_clock) 147 adc_clock = state->config.adc_clock; 148 if (state->config.if2) 149 if2 = state->config.if2; 150 151 if (adc_clock >= if2 * 2) 152 ife = if2; 153 else { 154 ife = adc_clock - (if2 % adc_clock); 155 if (ife > adc_clock / 2) 156 ife = adc_clock - ife; 157 } 158 value = -16374 * ife / adc_clock; 159 dprintk("%s: if2 %d, ife %d, adc_clock %d => %d / 0x%x\n", 160 __func__, if2, ife, adc_clock, value, value & 0x3fff); 161 buf[0] = msb(value); 162 buf[1] = lsb(value); 163 } 164 165 static int mt352_set_parameters(struct dvb_frontend *fe) 166 { 167 struct dtv_frontend_properties *op = &fe->dtv_property_cache; 168 struct mt352_state* state = fe->demodulator_priv; 169 unsigned char buf[13]; 170 static unsigned char tuner_go[] = { 0x5d, 0x01 }; 171 static unsigned char fsm_go[] = { 0x5e, 0x01 }; 172 unsigned int tps = 0; 173 174 switch (op->code_rate_HP) { 175 case FEC_2_3: 176 tps |= (1 << 7); 177 break; 178 case FEC_3_4: 179 tps |= (2 << 7); 180 break; 181 case FEC_5_6: 182 tps |= (3 << 7); 183 break; 184 case FEC_7_8: 185 tps |= (4 << 7); 186 break; 187 case FEC_1_2: 188 case FEC_AUTO: 189 break; 190 default: 191 return -EINVAL; 192 } 193 194 switch (op->code_rate_LP) { 195 case FEC_2_3: 196 tps |= (1 << 4); 197 break; 198 case FEC_3_4: 199 tps |= (2 << 4); 200 break; 201 case FEC_5_6: 202 tps |= (3 << 4); 203 break; 204 case FEC_7_8: 205 tps |= (4 << 4); 206 break; 207 case FEC_1_2: 208 case FEC_AUTO: 209 break; 210 case FEC_NONE: 211 if (op->hierarchy == HIERARCHY_AUTO || 212 op->hierarchy == HIERARCHY_NONE) 213 break; 214 /* fall through */ 215 default: 216 return -EINVAL; 217 } 218 219 switch (op->modulation) { 220 case QPSK: 221 break; 222 case QAM_AUTO: 223 case QAM_16: 224 tps |= (1 << 13); 225 break; 226 case QAM_64: 227 tps |= (2 << 13); 228 break; 229 default: 230 return -EINVAL; 231 } 232 233 switch (op->transmission_mode) { 234 case TRANSMISSION_MODE_2K: 235 case TRANSMISSION_MODE_AUTO: 236 break; 237 case TRANSMISSION_MODE_8K: 238 tps |= (1 << 0); 239 break; 240 default: 241 return -EINVAL; 242 } 243 244 switch (op->guard_interval) { 245 case GUARD_INTERVAL_1_32: 246 case GUARD_INTERVAL_AUTO: 247 break; 248 case GUARD_INTERVAL_1_16: 249 tps |= (1 << 2); 250 break; 251 case GUARD_INTERVAL_1_8: 252 tps |= (2 << 2); 253 break; 254 case GUARD_INTERVAL_1_4: 255 tps |= (3 << 2); 256 break; 257 default: 258 return -EINVAL; 259 } 260 261 switch (op->hierarchy) { 262 case HIERARCHY_AUTO: 263 case HIERARCHY_NONE: 264 break; 265 case HIERARCHY_1: 266 tps |= (1 << 10); 267 break; 268 case HIERARCHY_2: 269 tps |= (2 << 10); 270 break; 271 case HIERARCHY_4: 272 tps |= (3 << 10); 273 break; 274 default: 275 return -EINVAL; 276 } 277 278 279 buf[0] = TPS_GIVEN_1; /* TPS_GIVEN_1 and following registers */ 280 281 buf[1] = msb(tps); /* TPS_GIVEN_(1|0) */ 282 buf[2] = lsb(tps); 283 284 buf[3] = 0x50; // old 285 // buf[3] = 0xf4; // pinnacle 286 287 mt352_calc_nominal_rate(state, op->bandwidth_hz, buf+4); 288 mt352_calc_input_freq(state, buf+6); 289 290 if (state->config.no_tuner) { 291 if (fe->ops.tuner_ops.set_params) { 292 fe->ops.tuner_ops.set_params(fe); 293 if (fe->ops.i2c_gate_ctrl) 294 fe->ops.i2c_gate_ctrl(fe, 0); 295 } 296 297 _mt352_write(fe, buf, 8); 298 _mt352_write(fe, fsm_go, 2); 299 } else { 300 if (fe->ops.tuner_ops.calc_regs) { 301 fe->ops.tuner_ops.calc_regs(fe, buf+8, 5); 302 buf[8] <<= 1; 303 _mt352_write(fe, buf, sizeof(buf)); 304 _mt352_write(fe, tuner_go, 2); 305 } 306 } 307 308 return 0; 309 } 310 311 static int mt352_get_parameters(struct dvb_frontend* fe, 312 struct dtv_frontend_properties *op) 313 { 314 struct mt352_state* state = fe->demodulator_priv; 315 u16 tps; 316 u16 div; 317 u8 trl; 318 static const u8 tps_fec_to_api[8] = 319 { 320 FEC_1_2, 321 FEC_2_3, 322 FEC_3_4, 323 FEC_5_6, 324 FEC_7_8, 325 FEC_AUTO, 326 FEC_AUTO, 327 FEC_AUTO 328 }; 329 330 if ( (mt352_read_register(state,0x00) & 0xC0) != 0xC0 ) 331 return -EINVAL; 332 333 /* Use TPS_RECEIVED-registers, not the TPS_CURRENT-registers because 334 * the mt352 sometimes works with the wrong parameters 335 */ 336 tps = (mt352_read_register(state, TPS_RECEIVED_1) << 8) | mt352_read_register(state, TPS_RECEIVED_0); 337 div = (mt352_read_register(state, CHAN_START_1) << 8) | mt352_read_register(state, CHAN_START_0); 338 trl = mt352_read_register(state, TRL_NOMINAL_RATE_1); 339 340 op->code_rate_HP = tps_fec_to_api[(tps >> 7) & 7]; 341 op->code_rate_LP = tps_fec_to_api[(tps >> 4) & 7]; 342 343 switch ( (tps >> 13) & 3) 344 { 345 case 0: 346 op->modulation = QPSK; 347 break; 348 case 1: 349 op->modulation = QAM_16; 350 break; 351 case 2: 352 op->modulation = QAM_64; 353 break; 354 default: 355 op->modulation = QAM_AUTO; 356 break; 357 } 358 359 op->transmission_mode = (tps & 0x01) ? TRANSMISSION_MODE_8K : TRANSMISSION_MODE_2K; 360 361 switch ( (tps >> 2) & 3) 362 { 363 case 0: 364 op->guard_interval = GUARD_INTERVAL_1_32; 365 break; 366 case 1: 367 op->guard_interval = GUARD_INTERVAL_1_16; 368 break; 369 case 2: 370 op->guard_interval = GUARD_INTERVAL_1_8; 371 break; 372 case 3: 373 op->guard_interval = GUARD_INTERVAL_1_4; 374 break; 375 default: 376 op->guard_interval = GUARD_INTERVAL_AUTO; 377 break; 378 } 379 380 switch ( (tps >> 10) & 7) 381 { 382 case 0: 383 op->hierarchy = HIERARCHY_NONE; 384 break; 385 case 1: 386 op->hierarchy = HIERARCHY_1; 387 break; 388 case 2: 389 op->hierarchy = HIERARCHY_2; 390 break; 391 case 3: 392 op->hierarchy = HIERARCHY_4; 393 break; 394 default: 395 op->hierarchy = HIERARCHY_AUTO; 396 break; 397 } 398 399 op->frequency = (500 * (div - IF_FREQUENCYx6)) / 3 * 1000; 400 401 if (trl == 0x72) 402 op->bandwidth_hz = 8000000; 403 else if (trl == 0x64) 404 op->bandwidth_hz = 7000000; 405 else 406 op->bandwidth_hz = 6000000; 407 408 409 if (mt352_read_register(state, STATUS_2) & 0x02) 410 op->inversion = INVERSION_OFF; 411 else 412 op->inversion = INVERSION_ON; 413 414 return 0; 415 } 416 417 static int mt352_read_status(struct dvb_frontend *fe, enum fe_status *status) 418 { 419 struct mt352_state* state = fe->demodulator_priv; 420 int s0, s1, s3; 421 422 /* FIXME: 423 * 424 * The MT352 design manual from Zarlink states (page 46-47): 425 * 426 * Notes about the TUNER_GO register: 427 * 428 * If the Read_Tuner_Byte (bit-1) is activated, then the tuner status 429 * byte is copied from the tuner to the STATUS_3 register and 430 * completion of the read operation is indicated by bit-5 of the 431 * INTERRUPT_3 register. 432 */ 433 434 if ((s0 = mt352_read_register(state, STATUS_0)) < 0) 435 return -EREMOTEIO; 436 if ((s1 = mt352_read_register(state, STATUS_1)) < 0) 437 return -EREMOTEIO; 438 if ((s3 = mt352_read_register(state, STATUS_3)) < 0) 439 return -EREMOTEIO; 440 441 *status = 0; 442 if (s0 & (1 << 4)) 443 *status |= FE_HAS_CARRIER; 444 if (s0 & (1 << 1)) 445 *status |= FE_HAS_VITERBI; 446 if (s0 & (1 << 5)) 447 *status |= FE_HAS_LOCK; 448 if (s1 & (1 << 1)) 449 *status |= FE_HAS_SYNC; 450 if (s3 & (1 << 6)) 451 *status |= FE_HAS_SIGNAL; 452 453 if ((*status & (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)) != 454 (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)) 455 *status &= ~FE_HAS_LOCK; 456 457 return 0; 458 } 459 460 static int mt352_read_ber(struct dvb_frontend* fe, u32* ber) 461 { 462 struct mt352_state* state = fe->demodulator_priv; 463 464 *ber = (mt352_read_register (state, RS_ERR_CNT_2) << 16) | 465 (mt352_read_register (state, RS_ERR_CNT_1) << 8) | 466 (mt352_read_register (state, RS_ERR_CNT_0)); 467 468 return 0; 469 } 470 471 static int mt352_read_signal_strength(struct dvb_frontend* fe, u16* strength) 472 { 473 struct mt352_state* state = fe->demodulator_priv; 474 475 /* align the 12 bit AGC gain with the most significant bits */ 476 u16 signal = ((mt352_read_register(state, AGC_GAIN_1) & 0x0f) << 12) | 477 (mt352_read_register(state, AGC_GAIN_0) << 4); 478 479 /* inverse of gain is signal strength */ 480 *strength = ~signal; 481 return 0; 482 } 483 484 static int mt352_read_snr(struct dvb_frontend* fe, u16* snr) 485 { 486 struct mt352_state* state = fe->demodulator_priv; 487 488 u8 _snr = mt352_read_register (state, SNR); 489 *snr = (_snr << 8) | _snr; 490 491 return 0; 492 } 493 494 static int mt352_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks) 495 { 496 struct mt352_state* state = fe->demodulator_priv; 497 498 *ucblocks = (mt352_read_register (state, RS_UBC_1) << 8) | 499 (mt352_read_register (state, RS_UBC_0)); 500 501 return 0; 502 } 503 504 static int mt352_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fe_tune_settings) 505 { 506 fe_tune_settings->min_delay_ms = 800; 507 fe_tune_settings->step_size = 0; 508 fe_tune_settings->max_drift = 0; 509 510 return 0; 511 } 512 513 static int mt352_init(struct dvb_frontend* fe) 514 { 515 struct mt352_state* state = fe->demodulator_priv; 516 517 static u8 mt352_reset_attach [] = { RESET, 0xC0 }; 518 519 dprintk("%s: hello\n",__func__); 520 521 if ((mt352_read_register(state, CLOCK_CTL) & 0x10) == 0 || 522 (mt352_read_register(state, CONFIG) & 0x20) == 0) { 523 524 /* Do a "hard" reset */ 525 _mt352_write(fe, mt352_reset_attach, sizeof(mt352_reset_attach)); 526 return state->config.demod_init(fe); 527 } 528 529 return 0; 530 } 531 532 static void mt352_release(struct dvb_frontend* fe) 533 { 534 struct mt352_state* state = fe->demodulator_priv; 535 kfree(state); 536 } 537 538 static const struct dvb_frontend_ops mt352_ops; 539 540 struct dvb_frontend* mt352_attach(const struct mt352_config* config, 541 struct i2c_adapter* i2c) 542 { 543 struct mt352_state* state = NULL; 544 545 /* allocate memory for the internal state */ 546 state = kzalloc(sizeof(struct mt352_state), GFP_KERNEL); 547 if (state == NULL) goto error; 548 549 /* setup the state */ 550 state->i2c = i2c; 551 memcpy(&state->config,config,sizeof(struct mt352_config)); 552 553 /* check if the demod is there */ 554 if (mt352_read_register(state, CHIP_ID) != ID_MT352) goto error; 555 556 /* create dvb_frontend */ 557 memcpy(&state->frontend.ops, &mt352_ops, sizeof(struct dvb_frontend_ops)); 558 state->frontend.demodulator_priv = state; 559 return &state->frontend; 560 561 error: 562 kfree(state); 563 return NULL; 564 } 565 566 static const struct dvb_frontend_ops mt352_ops = { 567 .delsys = { SYS_DVBT }, 568 .info = { 569 .name = "Zarlink MT352 DVB-T", 570 .frequency_min_hz = 174 * MHz, 571 .frequency_max_hz = 862 * MHz, 572 .frequency_stepsize_hz = 166667, 573 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | 574 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | 575 FE_CAN_FEC_AUTO | 576 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | 577 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | 578 FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | 579 FE_CAN_MUTE_TS 580 }, 581 582 .release = mt352_release, 583 584 .init = mt352_init, 585 .sleep = mt352_sleep, 586 .write = _mt352_write, 587 588 .set_frontend = mt352_set_parameters, 589 .get_frontend = mt352_get_parameters, 590 .get_tune_settings = mt352_get_tune_settings, 591 592 .read_status = mt352_read_status, 593 .read_ber = mt352_read_ber, 594 .read_signal_strength = mt352_read_signal_strength, 595 .read_snr = mt352_read_snr, 596 .read_ucblocks = mt352_read_ucblocks, 597 }; 598 599 module_param(debug, int, 0644); 600 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); 601 602 MODULE_DESCRIPTION("Zarlink MT352 DVB-T Demodulator driver"); 603 MODULE_AUTHOR("Holger Waechtler, Daniel Mack, Antonio Mancuso"); 604 MODULE_LICENSE("GPL"); 605 606 EXPORT_SYMBOL(mt352_attach); 607