1 /* 2 Driver for Zarlink VP310/MT312/ZL10313 Satellite Channel Decoder 3 4 Copyright (C) 2003 Andreas Oberritter <obi@linuxtv.org> 5 Copyright (C) 2008 Matthias Schwarzott <zzam@gentoo.org> 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software 20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 22 References: 23 http://products.zarlink.com/product_profiles/MT312.htm 24 http://products.zarlink.com/product_profiles/SL1935.htm 25 */ 26 27 #include <linux/delay.h> 28 #include <linux/errno.h> 29 #include <linux/init.h> 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/string.h> 33 #include <linux/slab.h> 34 35 #include <media/dvb_frontend.h> 36 #include "mt312_priv.h" 37 #include "mt312.h" 38 39 /* Max transfer size done by I2C transfer functions */ 40 #define MAX_XFER_SIZE 64 41 42 struct mt312_state { 43 struct i2c_adapter *i2c; 44 /* configuration settings */ 45 const struct mt312_config *config; 46 struct dvb_frontend frontend; 47 48 u8 id; 49 unsigned long xtal; 50 u8 freq_mult; 51 }; 52 53 static int debug; 54 #define dprintk(args...) \ 55 do { \ 56 if (debug) \ 57 printk(KERN_DEBUG "mt312: " args); \ 58 } while (0) 59 60 #define MT312_PLL_CLK 10000000UL /* 10 MHz */ 61 #define MT312_PLL_CLK_10_111 10111000UL /* 10.111 MHz */ 62 63 static int mt312_read(struct mt312_state *state, const enum mt312_reg_addr reg, 64 u8 *buf, const size_t count) 65 { 66 int ret; 67 struct i2c_msg msg[2]; 68 u8 regbuf[1] = { reg }; 69 70 msg[0].addr = state->config->demod_address; 71 msg[0].flags = 0; 72 msg[0].buf = regbuf; 73 msg[0].len = 1; 74 msg[1].addr = state->config->demod_address; 75 msg[1].flags = I2C_M_RD; 76 msg[1].buf = buf; 77 msg[1].len = count; 78 79 ret = i2c_transfer(state->i2c, msg, 2); 80 81 if (ret != 2) { 82 printk(KERN_DEBUG "%s: ret == %d\n", __func__, ret); 83 return -EREMOTEIO; 84 } 85 86 if (debug) { 87 int i; 88 dprintk("R(%d):", reg & 0x7f); 89 for (i = 0; i < count; i++) 90 printk(KERN_CONT " %02x", buf[i]); 91 printk("\n"); 92 } 93 94 return 0; 95 } 96 97 static int mt312_write(struct mt312_state *state, const enum mt312_reg_addr reg, 98 const u8 *src, const size_t count) 99 { 100 int ret; 101 u8 buf[MAX_XFER_SIZE]; 102 struct i2c_msg msg; 103 104 if (1 + count > sizeof(buf)) { 105 printk(KERN_WARNING 106 "mt312: write: len=%zu is too big!\n", count); 107 return -EINVAL; 108 } 109 110 if (debug) { 111 int i; 112 dprintk("W(%d):", reg & 0x7f); 113 for (i = 0; i < count; i++) 114 printk(KERN_CONT " %02x", src[i]); 115 printk("\n"); 116 } 117 118 buf[0] = reg; 119 memcpy(&buf[1], src, count); 120 121 msg.addr = state->config->demod_address; 122 msg.flags = 0; 123 msg.buf = buf; 124 msg.len = count + 1; 125 126 ret = i2c_transfer(state->i2c, &msg, 1); 127 128 if (ret != 1) { 129 dprintk("%s: ret == %d\n", __func__, ret); 130 return -EREMOTEIO; 131 } 132 133 return 0; 134 } 135 136 static inline int mt312_readreg(struct mt312_state *state, 137 const enum mt312_reg_addr reg, u8 *val) 138 { 139 return mt312_read(state, reg, val, 1); 140 } 141 142 static inline int mt312_writereg(struct mt312_state *state, 143 const enum mt312_reg_addr reg, const u8 val) 144 { 145 u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */ 146 147 148 return mt312_write(state, reg, &tmp, 1); 149 } 150 151 static inline u32 mt312_div(u32 a, u32 b) 152 { 153 return (a + (b / 2)) / b; 154 } 155 156 static int mt312_reset(struct mt312_state *state, const u8 full) 157 { 158 return mt312_writereg(state, RESET, full ? 0x80 : 0x40); 159 } 160 161 static int mt312_get_inversion(struct mt312_state *state, 162 enum fe_spectral_inversion *i) 163 { 164 int ret; 165 u8 vit_mode; 166 167 ret = mt312_readreg(state, VIT_MODE, &vit_mode); 168 if (ret < 0) 169 return ret; 170 171 if (vit_mode & 0x80) /* auto inversion was used */ 172 *i = (vit_mode & 0x40) ? INVERSION_ON : INVERSION_OFF; 173 174 return 0; 175 } 176 177 static int mt312_get_symbol_rate(struct mt312_state *state, u32 *sr) 178 { 179 int ret; 180 u8 sym_rate_h; 181 u8 dec_ratio; 182 u16 sym_rat_op; 183 u16 monitor; 184 u8 buf[2]; 185 186 ret = mt312_readreg(state, SYM_RATE_H, &sym_rate_h); 187 if (ret < 0) 188 return ret; 189 190 if (sym_rate_h & 0x80) { 191 /* symbol rate search was used */ 192 ret = mt312_writereg(state, MON_CTRL, 0x03); 193 if (ret < 0) 194 return ret; 195 196 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf)); 197 if (ret < 0) 198 return ret; 199 200 monitor = (buf[0] << 8) | buf[1]; 201 202 dprintk("sr(auto) = %u\n", 203 mt312_div(monitor * 15625, 4)); 204 } else { 205 ret = mt312_writereg(state, MON_CTRL, 0x05); 206 if (ret < 0) 207 return ret; 208 209 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf)); 210 if (ret < 0) 211 return ret; 212 213 dec_ratio = ((buf[0] >> 5) & 0x07) * 32; 214 215 ret = mt312_read(state, SYM_RAT_OP_H, buf, sizeof(buf)); 216 if (ret < 0) 217 return ret; 218 219 sym_rat_op = (buf[0] << 8) | buf[1]; 220 221 dprintk("sym_rat_op=%d dec_ratio=%d\n", 222 sym_rat_op, dec_ratio); 223 dprintk("*sr(manual) = %lu\n", 224 (((state->xtal * 8192) / (sym_rat_op + 8192)) * 225 2) - dec_ratio); 226 } 227 228 return 0; 229 } 230 231 static int mt312_get_code_rate(struct mt312_state *state, enum fe_code_rate *cr) 232 { 233 const enum fe_code_rate fec_tab[8] = 234 { FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_6_7, FEC_7_8, 235 FEC_AUTO, FEC_AUTO }; 236 237 int ret; 238 u8 fec_status; 239 240 ret = mt312_readreg(state, FEC_STATUS, &fec_status); 241 if (ret < 0) 242 return ret; 243 244 *cr = fec_tab[(fec_status >> 4) & 0x07]; 245 246 return 0; 247 } 248 249 static int mt312_initfe(struct dvb_frontend *fe) 250 { 251 struct mt312_state *state = fe->demodulator_priv; 252 int ret; 253 u8 buf[2]; 254 255 /* wake up */ 256 ret = mt312_writereg(state, CONFIG, 257 (state->freq_mult == 6 ? 0x88 : 0x8c)); 258 if (ret < 0) 259 return ret; 260 261 /* wait at least 150 usec */ 262 udelay(150); 263 264 /* full reset */ 265 ret = mt312_reset(state, 1); 266 if (ret < 0) 267 return ret; 268 269 /* Per datasheet, write correct values. 09/28/03 ACCJr. 270 * If we don't do this, we won't get FE_HAS_VITERBI in the VP310. */ 271 { 272 u8 buf_def[8] = { 0x14, 0x12, 0x03, 0x02, 273 0x01, 0x00, 0x00, 0x00 }; 274 275 ret = mt312_write(state, VIT_SETUP, buf_def, sizeof(buf_def)); 276 if (ret < 0) 277 return ret; 278 } 279 280 switch (state->id) { 281 case ID_ZL10313: 282 /* enable ADC */ 283 ret = mt312_writereg(state, GPP_CTRL, 0x80); 284 if (ret < 0) 285 return ret; 286 287 /* configure ZL10313 for optimal ADC performance */ 288 buf[0] = 0x80; 289 buf[1] = 0xB0; 290 ret = mt312_write(state, HW_CTRL, buf, 2); 291 if (ret < 0) 292 return ret; 293 294 /* enable MPEG output and ADCs */ 295 ret = mt312_writereg(state, HW_CTRL, 0x00); 296 if (ret < 0) 297 return ret; 298 299 ret = mt312_writereg(state, MPEG_CTRL, 0x00); 300 if (ret < 0) 301 return ret; 302 303 break; 304 } 305 306 /* SYS_CLK */ 307 buf[0] = mt312_div(state->xtal * state->freq_mult * 2, 1000000); 308 309 /* DISEQC_RATIO */ 310 buf[1] = mt312_div(state->xtal, 22000 * 4); 311 312 ret = mt312_write(state, SYS_CLK, buf, sizeof(buf)); 313 if (ret < 0) 314 return ret; 315 316 ret = mt312_writereg(state, SNR_THS_HIGH, 0x32); 317 if (ret < 0) 318 return ret; 319 320 /* different MOCLK polarity */ 321 switch (state->id) { 322 case ID_ZL10313: 323 buf[0] = 0x33; 324 break; 325 default: 326 buf[0] = 0x53; 327 break; 328 } 329 330 ret = mt312_writereg(state, OP_CTRL, buf[0]); 331 if (ret < 0) 332 return ret; 333 334 /* TS_SW_LIM */ 335 buf[0] = 0x8c; 336 buf[1] = 0x98; 337 338 ret = mt312_write(state, TS_SW_LIM_L, buf, sizeof(buf)); 339 if (ret < 0) 340 return ret; 341 342 ret = mt312_writereg(state, CS_SW_LIM, 0x69); 343 if (ret < 0) 344 return ret; 345 346 return 0; 347 } 348 349 static int mt312_send_master_cmd(struct dvb_frontend *fe, 350 struct dvb_diseqc_master_cmd *c) 351 { 352 struct mt312_state *state = fe->demodulator_priv; 353 int ret; 354 u8 diseqc_mode; 355 356 if ((c->msg_len == 0) || (c->msg_len > sizeof(c->msg))) 357 return -EINVAL; 358 359 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode); 360 if (ret < 0) 361 return ret; 362 363 ret = mt312_write(state, (0x80 | DISEQC_INSTR), c->msg, c->msg_len); 364 if (ret < 0) 365 return ret; 366 367 ret = mt312_writereg(state, DISEQC_MODE, 368 (diseqc_mode & 0x40) | ((c->msg_len - 1) << 3) 369 | 0x04); 370 if (ret < 0) 371 return ret; 372 373 /* is there a better way to wait for message to be transmitted */ 374 msleep(100); 375 376 /* set DISEQC_MODE[2:0] to zero if a return message is expected */ 377 if (c->msg[0] & 0x02) { 378 ret = mt312_writereg(state, DISEQC_MODE, (diseqc_mode & 0x40)); 379 if (ret < 0) 380 return ret; 381 } 382 383 return 0; 384 } 385 386 static int mt312_send_burst(struct dvb_frontend *fe, 387 const enum fe_sec_mini_cmd c) 388 { 389 struct mt312_state *state = fe->demodulator_priv; 390 const u8 mini_tab[2] = { 0x02, 0x03 }; 391 392 int ret; 393 u8 diseqc_mode; 394 395 if (c > SEC_MINI_B) 396 return -EINVAL; 397 398 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode); 399 if (ret < 0) 400 return ret; 401 402 ret = mt312_writereg(state, DISEQC_MODE, 403 (diseqc_mode & 0x40) | mini_tab[c]); 404 if (ret < 0) 405 return ret; 406 407 return 0; 408 } 409 410 static int mt312_set_tone(struct dvb_frontend *fe, 411 const enum fe_sec_tone_mode t) 412 { 413 struct mt312_state *state = fe->demodulator_priv; 414 const u8 tone_tab[2] = { 0x01, 0x00 }; 415 416 int ret; 417 u8 diseqc_mode; 418 419 if (t > SEC_TONE_OFF) 420 return -EINVAL; 421 422 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode); 423 if (ret < 0) 424 return ret; 425 426 ret = mt312_writereg(state, DISEQC_MODE, 427 (diseqc_mode & 0x40) | tone_tab[t]); 428 if (ret < 0) 429 return ret; 430 431 return 0; 432 } 433 434 static int mt312_set_voltage(struct dvb_frontend *fe, 435 const enum fe_sec_voltage v) 436 { 437 struct mt312_state *state = fe->demodulator_priv; 438 const u8 volt_tab[3] = { 0x00, 0x40, 0x00 }; 439 u8 val; 440 441 if (v > SEC_VOLTAGE_OFF) 442 return -EINVAL; 443 444 val = volt_tab[v]; 445 if (state->config->voltage_inverted) 446 val ^= 0x40; 447 448 return mt312_writereg(state, DISEQC_MODE, val); 449 } 450 451 static int mt312_read_status(struct dvb_frontend *fe, enum fe_status *s) 452 { 453 struct mt312_state *state = fe->demodulator_priv; 454 int ret; 455 u8 status[3]; 456 457 *s = 0; 458 459 ret = mt312_read(state, QPSK_STAT_H, status, sizeof(status)); 460 if (ret < 0) 461 return ret; 462 463 dprintk("QPSK_STAT_H: 0x%02x, QPSK_STAT_L: 0x%02x, FEC_STATUS: 0x%02x\n", 464 status[0], status[1], status[2]); 465 466 if (status[0] & 0xc0) 467 *s |= FE_HAS_SIGNAL; /* signal noise ratio */ 468 if (status[0] & 0x04) 469 *s |= FE_HAS_CARRIER; /* qpsk carrier lock */ 470 if (status[2] & 0x02) 471 *s |= FE_HAS_VITERBI; /* viterbi lock */ 472 if (status[2] & 0x04) 473 *s |= FE_HAS_SYNC; /* byte align lock */ 474 if (status[0] & 0x01) 475 *s |= FE_HAS_LOCK; /* qpsk lock */ 476 477 return 0; 478 } 479 480 static int mt312_read_ber(struct dvb_frontend *fe, u32 *ber) 481 { 482 struct mt312_state *state = fe->demodulator_priv; 483 int ret; 484 u8 buf[3]; 485 486 ret = mt312_read(state, RS_BERCNT_H, buf, 3); 487 if (ret < 0) 488 return ret; 489 490 *ber = ((buf[0] << 16) | (buf[1] << 8) | buf[2]) * 64; 491 492 return 0; 493 } 494 495 static int mt312_read_signal_strength(struct dvb_frontend *fe, 496 u16 *signal_strength) 497 { 498 struct mt312_state *state = fe->demodulator_priv; 499 int ret; 500 u8 buf[3]; 501 u16 agc; 502 s16 err_db; 503 504 ret = mt312_read(state, AGC_H, buf, sizeof(buf)); 505 if (ret < 0) 506 return ret; 507 508 agc = (buf[0] << 6) | (buf[1] >> 2); 509 err_db = (s16) (((buf[1] & 0x03) << 14) | buf[2] << 6) >> 6; 510 511 *signal_strength = agc; 512 513 dprintk("agc=%08x err_db=%hd\n", agc, err_db); 514 515 return 0; 516 } 517 518 static int mt312_read_snr(struct dvb_frontend *fe, u16 *snr) 519 { 520 struct mt312_state *state = fe->demodulator_priv; 521 int ret; 522 u8 buf[2]; 523 524 ret = mt312_read(state, M_SNR_H, buf, sizeof(buf)); 525 if (ret < 0) 526 return ret; 527 528 *snr = 0xFFFF - ((((buf[0] & 0x7f) << 8) | buf[1]) << 1); 529 530 return 0; 531 } 532 533 static int mt312_read_ucblocks(struct dvb_frontend *fe, u32 *ubc) 534 { 535 struct mt312_state *state = fe->demodulator_priv; 536 int ret; 537 u8 buf[2]; 538 539 ret = mt312_read(state, RS_UBC_H, buf, sizeof(buf)); 540 if (ret < 0) 541 return ret; 542 543 *ubc = (buf[0] << 8) | buf[1]; 544 545 return 0; 546 } 547 548 static int mt312_set_frontend(struct dvb_frontend *fe) 549 { 550 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 551 struct mt312_state *state = fe->demodulator_priv; 552 int ret; 553 u8 buf[5], config_val; 554 u16 sr; 555 556 const u8 fec_tab[10] = 557 { 0x00, 0x01, 0x02, 0x04, 0x3f, 0x08, 0x10, 0x20, 0x3f, 0x3f }; 558 const u8 inv_tab[3] = { 0x00, 0x40, 0x80 }; 559 560 dprintk("%s: Freq %d\n", __func__, p->frequency); 561 562 if ((p->frequency < fe->ops.info.frequency_min_hz / kHz) 563 || (p->frequency > fe->ops.info.frequency_max_hz / kHz)) 564 return -EINVAL; 565 566 if (((int)p->inversion < INVERSION_OFF) 567 || (p->inversion > INVERSION_ON)) 568 return -EINVAL; 569 570 if ((p->symbol_rate < fe->ops.info.symbol_rate_min) 571 || (p->symbol_rate > fe->ops.info.symbol_rate_max)) 572 return -EINVAL; 573 574 if (((int)p->fec_inner < FEC_NONE) 575 || (p->fec_inner > FEC_AUTO)) 576 return -EINVAL; 577 578 if ((p->fec_inner == FEC_4_5) 579 || (p->fec_inner == FEC_8_9)) 580 return -EINVAL; 581 582 switch (state->id) { 583 case ID_VP310: 584 /* For now we will do this only for the VP310. 585 * It should be better for the mt312 as well, 586 * but tuning will be slower. ACCJr 09/29/03 587 */ 588 ret = mt312_readreg(state, CONFIG, &config_val); 589 if (ret < 0) 590 return ret; 591 if (p->symbol_rate >= 30000000) { 592 /* Note that 30MS/s should use 90MHz */ 593 if (state->freq_mult == 6) { 594 /* We are running 60MHz */ 595 state->freq_mult = 9; 596 ret = mt312_initfe(fe); 597 if (ret < 0) 598 return ret; 599 } 600 } else { 601 if (state->freq_mult == 9) { 602 /* We are running 90MHz */ 603 state->freq_mult = 6; 604 ret = mt312_initfe(fe); 605 if (ret < 0) 606 return ret; 607 } 608 } 609 break; 610 611 case ID_MT312: 612 case ID_ZL10313: 613 break; 614 615 default: 616 return -EINVAL; 617 } 618 619 if (fe->ops.tuner_ops.set_params) { 620 fe->ops.tuner_ops.set_params(fe); 621 if (fe->ops.i2c_gate_ctrl) 622 fe->ops.i2c_gate_ctrl(fe, 0); 623 } 624 625 /* sr = (u16)(sr * 256.0 / 1000000.0) */ 626 sr = mt312_div(p->symbol_rate * 4, 15625); 627 628 /* SYM_RATE */ 629 buf[0] = (sr >> 8) & 0x3f; 630 buf[1] = (sr >> 0) & 0xff; 631 632 /* VIT_MODE */ 633 buf[2] = inv_tab[p->inversion] | fec_tab[p->fec_inner]; 634 635 /* QPSK_CTRL */ 636 buf[3] = 0x40; /* swap I and Q before QPSK demodulation */ 637 638 if (p->symbol_rate < 10000000) 639 buf[3] |= 0x04; /* use afc mode */ 640 641 /* GO */ 642 buf[4] = 0x01; 643 644 ret = mt312_write(state, SYM_RATE_H, buf, sizeof(buf)); 645 if (ret < 0) 646 return ret; 647 648 ret = mt312_reset(state, 0); 649 if (ret < 0) 650 return ret; 651 652 return 0; 653 } 654 655 static int mt312_get_frontend(struct dvb_frontend *fe, 656 struct dtv_frontend_properties *p) 657 { 658 struct mt312_state *state = fe->demodulator_priv; 659 int ret; 660 661 ret = mt312_get_inversion(state, &p->inversion); 662 if (ret < 0) 663 return ret; 664 665 ret = mt312_get_symbol_rate(state, &p->symbol_rate); 666 if (ret < 0) 667 return ret; 668 669 ret = mt312_get_code_rate(state, &p->fec_inner); 670 if (ret < 0) 671 return ret; 672 673 return 0; 674 } 675 676 static int mt312_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) 677 { 678 struct mt312_state *state = fe->demodulator_priv; 679 680 u8 val = 0x00; 681 int ret; 682 683 switch (state->id) { 684 case ID_ZL10313: 685 ret = mt312_readreg(state, GPP_CTRL, &val); 686 if (ret < 0) 687 goto error; 688 689 /* preserve this bit to not accidentally shutdown ADC */ 690 val &= 0x80; 691 break; 692 } 693 694 if (enable) 695 val |= 0x40; 696 else 697 val &= ~0x40; 698 699 ret = mt312_writereg(state, GPP_CTRL, val); 700 701 error: 702 return ret; 703 } 704 705 static int mt312_sleep(struct dvb_frontend *fe) 706 { 707 struct mt312_state *state = fe->demodulator_priv; 708 int ret; 709 u8 config; 710 711 /* reset all registers to defaults */ 712 ret = mt312_reset(state, 1); 713 if (ret < 0) 714 return ret; 715 716 if (state->id == ID_ZL10313) { 717 /* reset ADC */ 718 ret = mt312_writereg(state, GPP_CTRL, 0x00); 719 if (ret < 0) 720 return ret; 721 722 /* full shutdown of ADCs, mpeg bus tristated */ 723 ret = mt312_writereg(state, HW_CTRL, 0x0d); 724 if (ret < 0) 725 return ret; 726 } 727 728 ret = mt312_readreg(state, CONFIG, &config); 729 if (ret < 0) 730 return ret; 731 732 /* enter standby */ 733 ret = mt312_writereg(state, CONFIG, config & 0x7f); 734 if (ret < 0) 735 return ret; 736 737 return 0; 738 } 739 740 static int mt312_get_tune_settings(struct dvb_frontend *fe, 741 struct dvb_frontend_tune_settings *fesettings) 742 { 743 fesettings->min_delay_ms = 50; 744 fesettings->step_size = 0; 745 fesettings->max_drift = 0; 746 return 0; 747 } 748 749 static void mt312_release(struct dvb_frontend *fe) 750 { 751 struct mt312_state *state = fe->demodulator_priv; 752 kfree(state); 753 } 754 755 #define MT312_SYS_CLK 90000000UL /* 90 MHz */ 756 static const struct dvb_frontend_ops mt312_ops = { 757 .delsys = { SYS_DVBS }, 758 .info = { 759 .name = "Zarlink ???? DVB-S", 760 .frequency_min_hz = 950 * MHz, 761 .frequency_max_hz = 2150 * MHz, 762 /* FIXME: adjust freq to real used xtal */ 763 .frequency_stepsize_hz = MT312_PLL_CLK / 128, 764 .symbol_rate_min = MT312_SYS_CLK / 128, /* FIXME as above */ 765 .symbol_rate_max = MT312_SYS_CLK / 2, 766 .caps = 767 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | 768 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | 769 FE_CAN_FEC_AUTO | FE_CAN_QPSK | FE_CAN_MUTE_TS | 770 FE_CAN_RECOVER 771 }, 772 773 .release = mt312_release, 774 775 .init = mt312_initfe, 776 .sleep = mt312_sleep, 777 .i2c_gate_ctrl = mt312_i2c_gate_ctrl, 778 779 .set_frontend = mt312_set_frontend, 780 .get_frontend = mt312_get_frontend, 781 .get_tune_settings = mt312_get_tune_settings, 782 783 .read_status = mt312_read_status, 784 .read_ber = mt312_read_ber, 785 .read_signal_strength = mt312_read_signal_strength, 786 .read_snr = mt312_read_snr, 787 .read_ucblocks = mt312_read_ucblocks, 788 789 .diseqc_send_master_cmd = mt312_send_master_cmd, 790 .diseqc_send_burst = mt312_send_burst, 791 .set_tone = mt312_set_tone, 792 .set_voltage = mt312_set_voltage, 793 }; 794 795 struct dvb_frontend *mt312_attach(const struct mt312_config *config, 796 struct i2c_adapter *i2c) 797 { 798 struct mt312_state *state = NULL; 799 800 /* allocate memory for the internal state */ 801 state = kzalloc(sizeof(struct mt312_state), GFP_KERNEL); 802 if (state == NULL) 803 goto error; 804 805 /* setup the state */ 806 state->config = config; 807 state->i2c = i2c; 808 809 /* check if the demod is there */ 810 if (mt312_readreg(state, ID, &state->id) < 0) 811 goto error; 812 813 /* create dvb_frontend */ 814 memcpy(&state->frontend.ops, &mt312_ops, 815 sizeof(struct dvb_frontend_ops)); 816 state->frontend.demodulator_priv = state; 817 818 switch (state->id) { 819 case ID_VP310: 820 strscpy(state->frontend.ops.info.name, "Zarlink VP310 DVB-S", 821 sizeof(state->frontend.ops.info.name)); 822 state->xtal = MT312_PLL_CLK; 823 state->freq_mult = 9; 824 break; 825 case ID_MT312: 826 strscpy(state->frontend.ops.info.name, "Zarlink MT312 DVB-S", 827 sizeof(state->frontend.ops.info.name)); 828 state->xtal = MT312_PLL_CLK; 829 state->freq_mult = 6; 830 break; 831 case ID_ZL10313: 832 strscpy(state->frontend.ops.info.name, "Zarlink ZL10313 DVB-S", 833 sizeof(state->frontend.ops.info.name)); 834 state->xtal = MT312_PLL_CLK_10_111; 835 state->freq_mult = 9; 836 break; 837 default: 838 printk(KERN_WARNING "Only Zarlink VP310/MT312/ZL10313 are supported chips.\n"); 839 goto error; 840 } 841 842 return &state->frontend; 843 844 error: 845 kfree(state); 846 return NULL; 847 } 848 EXPORT_SYMBOL(mt312_attach); 849 850 module_param(debug, int, 0644); 851 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); 852 853 MODULE_DESCRIPTION("Zarlink VP310/MT312/ZL10313 DVB-S Demodulator driver"); 854 MODULE_AUTHOR("Andreas Oberritter <obi@linuxtv.org>"); 855 MODULE_AUTHOR("Matthias Schwarzott <zzam@gentoo.org>"); 856 MODULE_LICENSE("GPL"); 857 858