1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Montage Technology M88DS3103/M88RS6000 demodulator driver 4 * 5 * Copyright (C) 2013 Antti Palosaari <crope@iki.fi> 6 */ 7 8 #include "m88ds3103_priv.h" 9 10 static const struct dvb_frontend_ops m88ds3103_ops; 11 12 /* write single register with mask */ 13 static int m88ds3103_update_bits(struct m88ds3103_dev *dev, 14 u8 reg, u8 mask, u8 val) 15 { 16 int ret; 17 u8 tmp; 18 19 /* no need for read if whole reg is written */ 20 if (mask != 0xff) { 21 ret = regmap_bulk_read(dev->regmap, reg, &tmp, 1); 22 if (ret) 23 return ret; 24 25 val &= mask; 26 tmp &= ~mask; 27 val |= tmp; 28 } 29 30 return regmap_bulk_write(dev->regmap, reg, &val, 1); 31 } 32 33 /* write reg val table using reg addr auto increment */ 34 static int m88ds3103_wr_reg_val_tab(struct m88ds3103_dev *dev, 35 const struct m88ds3103_reg_val *tab, int tab_len) 36 { 37 struct i2c_client *client = dev->client; 38 int ret, i, j; 39 u8 buf[83]; 40 41 dev_dbg(&client->dev, "tab_len=%d\n", tab_len); 42 43 if (tab_len > 86) { 44 ret = -EINVAL; 45 goto err; 46 } 47 48 for (i = 0, j = 0; i < tab_len; i++, j++) { 49 buf[j] = tab[i].val; 50 51 if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1 || 52 !((j + 1) % (dev->cfg->i2c_wr_max - 1))) { 53 ret = regmap_bulk_write(dev->regmap, tab[i].reg - j, buf, j + 1); 54 if (ret) 55 goto err; 56 57 j = -1; 58 } 59 } 60 61 return 0; 62 err: 63 dev_dbg(&client->dev, "failed=%d\n", ret); 64 return ret; 65 } 66 67 /* 68 * m88ds3103b demod has an internal device related to clocking. First the i2c 69 * gate must be opened, for one transaction, then writes will be allowed. 70 */ 71 static int m88ds3103b_dt_write(struct m88ds3103_dev *dev, int reg, int data) 72 { 73 struct i2c_client *client = dev->client; 74 u8 buf[] = {reg, data}; 75 u8 val; 76 int ret; 77 struct i2c_msg msg = { 78 .addr = dev->dt_addr, .flags = 0, .buf = buf, .len = 2 79 }; 80 81 if (dev->chip_id == M88DS3103C_CHIP_ID) 82 m88ds3103_update_bits(dev, 0x04, 0x10, 0x00); 83 else 84 m88ds3103_update_bits(dev, 0x11, 0x01, 0x00); 85 86 val = 0x11; 87 ret = regmap_write(dev->regmap, 0x03, val); 88 if (ret) 89 dev_dbg(&client->dev, "fail=%d\n", ret); 90 91 ret = i2c_transfer(dev->dt_client->adapter, &msg, 1); 92 if (ret != 1) { 93 dev_err(&client->dev, "0x%02x (ret=%i, reg=0x%02x, value=0x%02x)\n", 94 dev->dt_addr, ret, reg, data); 95 96 if (dev->chip_id == M88DS3103C_CHIP_ID) 97 m88ds3103_update_bits(dev, 0x04, 0x10, 0x10); 98 else 99 m88ds3103_update_bits(dev, 0x11, 0x01, 0x01); 100 101 return -EREMOTEIO; 102 } 103 104 if (dev->chip_id == M88DS3103C_CHIP_ID) 105 m88ds3103_update_bits(dev, 0x04, 0x10, 0x10); 106 else 107 m88ds3103_update_bits(dev, 0x11, 0x01, 0x01); 108 109 dev_dbg(&client->dev, "0x%02x reg 0x%02x, value 0x%02x\n", 110 dev->dt_addr, reg, data); 111 112 return 0; 113 } 114 115 /* 116 * m88ds3103b demod has an internal device related to clocking. First the i2c 117 * gate must be opened, for two transactions, then reads will be allowed. 118 */ 119 static int m88ds3103b_dt_read(struct m88ds3103_dev *dev, u8 reg) 120 { 121 struct i2c_client *client = dev->client; 122 int ret; 123 u8 val; 124 u8 b0[] = { reg }; 125 u8 b1[] = { 0 }; 126 struct i2c_msg msg[] = { 127 { 128 .addr = dev->dt_addr, 129 .flags = 0, 130 .buf = b0, 131 .len = 1 132 }, 133 { 134 .addr = dev->dt_addr, 135 .flags = I2C_M_RD, 136 .buf = b1, 137 .len = 1 138 } 139 }; 140 141 if (dev->chip_id == M88DS3103C_CHIP_ID) { 142 m88ds3103_update_bits(dev, 0x04, 0x10, 0x00); 143 val = 0x11; 144 } else { 145 m88ds3103_update_bits(dev, 0x11, 0x01, 0x00); 146 val = 0x12; 147 } 148 149 ret = regmap_write(dev->regmap, 0x03, val); 150 if (ret) 151 dev_dbg(&client->dev, "fail=%d\n", ret); 152 153 ret = i2c_transfer(dev->dt_client->adapter, msg, 2); 154 if (ret != 2) { 155 dev_err(&client->dev, "0x%02x (ret=%d, reg=0x%02x)\n", 156 dev->dt_addr, ret, reg); 157 158 if (dev->chip_id == M88DS3103C_CHIP_ID) 159 m88ds3103_update_bits(dev, 0x04, 0x10, 0x10); 160 else 161 m88ds3103_update_bits(dev, 0x11, 0x01, 0x01); 162 163 return -EREMOTEIO; 164 } 165 166 if (dev->chip_id == M88DS3103C_CHIP_ID) 167 m88ds3103_update_bits(dev, 0x04, 0x10, 0x10); 168 else 169 m88ds3103_update_bits(dev, 0x11, 0x01, 0x01); 170 171 dev_dbg(&client->dev, "0x%02x reg 0x%02x, value 0x%02x\n", 172 dev->dt_addr, reg, b1[0]); 173 174 return b1[0]; 175 } 176 177 /* 178 * Get the demodulator AGC PWM voltage setting supplied to the tuner. 179 */ 180 int m88ds3103_get_agc_pwm(struct dvb_frontend *fe, u8 *_agc_pwm) 181 { 182 struct m88ds3103_dev *dev = fe->demodulator_priv; 183 unsigned tmp; 184 int ret; 185 186 ret = regmap_read(dev->regmap, 0x3f, &tmp); 187 if (ret == 0) 188 *_agc_pwm = tmp; 189 return ret; 190 } 191 EXPORT_SYMBOL(m88ds3103_get_agc_pwm); 192 193 static int m88ds3103_read_status(struct dvb_frontend *fe, 194 enum fe_status *status) 195 { 196 struct m88ds3103_dev *dev = fe->demodulator_priv; 197 struct i2c_client *client = dev->client; 198 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 199 int ret, i, itmp; 200 unsigned int utmp; 201 u8 buf[3]; 202 203 *status = 0; 204 205 if (!dev->warm) { 206 ret = -EAGAIN; 207 goto err; 208 } 209 210 switch (c->delivery_system) { 211 case SYS_DVBS: 212 if (dev->chiptype == M88DS3103_CHIPTYPE_3103C) { 213 ret = regmap_read(dev->regmap, 0x0d, &utmp); 214 if (ret) 215 goto err; 216 217 if ((utmp & 0xf7) == 0xf7) 218 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | 219 FE_HAS_VITERBI | FE_HAS_SYNC | 220 FE_HAS_LOCK; 221 } else { 222 ret = regmap_read(dev->regmap, 0xd1, &utmp); 223 if (ret) 224 goto err; 225 226 if ((utmp & 0x07) == 0x07) 227 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | 228 FE_HAS_VITERBI | FE_HAS_SYNC | 229 FE_HAS_LOCK; 230 } 231 break; 232 case SYS_DVBS2: 233 ret = regmap_read(dev->regmap, 0x0d, &utmp); 234 if (ret) 235 goto err; 236 237 if ((utmp & 0x8f) == 0x8f) 238 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | 239 FE_HAS_VITERBI | FE_HAS_SYNC | 240 FE_HAS_LOCK; 241 break; 242 default: 243 dev_dbg(&client->dev, "invalid delivery_system\n"); 244 ret = -EINVAL; 245 goto err; 246 } 247 248 dev->fe_status = *status; 249 dev_dbg(&client->dev, "lock=%02x status=%02x\n", utmp, *status); 250 251 /* CNR */ 252 if (dev->fe_status & FE_HAS_VITERBI) { 253 unsigned int cnr, noise, signal, noise_tot, signal_tot; 254 255 cnr = 0; 256 /* more iterations for more accurate estimation */ 257 #define M88DS3103_SNR_ITERATIONS 3 258 259 switch (c->delivery_system) { 260 case SYS_DVBS: 261 itmp = 0; 262 263 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) { 264 ret = regmap_read(dev->regmap, 0xff, &utmp); 265 if (ret) 266 goto err; 267 268 itmp += utmp; 269 } 270 271 /* use of single register limits max value to 15 dB */ 272 /* SNR(X) dB = 10 * ln(X) / ln(10) dB */ 273 itmp = DIV_ROUND_CLOSEST(itmp, 8 * M88DS3103_SNR_ITERATIONS); 274 if (itmp) 275 cnr = div_u64((u64) 10000 * intlog2(itmp), intlog2(10)); 276 break; 277 case SYS_DVBS2: 278 noise_tot = 0; 279 signal_tot = 0; 280 281 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) { 282 ret = regmap_bulk_read(dev->regmap, 0x8c, buf, 3); 283 if (ret) 284 goto err; 285 286 noise = buf[1] << 6; /* [13:6] */ 287 noise |= buf[0] & 0x3f; /* [5:0] */ 288 noise >>= 2; 289 signal = buf[2] * buf[2]; 290 signal >>= 1; 291 292 noise_tot += noise; 293 signal_tot += signal; 294 } 295 296 noise = noise_tot / M88DS3103_SNR_ITERATIONS; 297 signal = signal_tot / M88DS3103_SNR_ITERATIONS; 298 299 /* SNR(X) dB = 10 * log10(X) dB */ 300 if (signal > noise) { 301 itmp = signal / noise; 302 cnr = div_u64((u64) 10000 * intlog10(itmp), (1 << 24)); 303 } 304 break; 305 default: 306 dev_dbg(&client->dev, "invalid delivery_system\n"); 307 ret = -EINVAL; 308 goto err; 309 } 310 311 if (cnr) { 312 c->cnr.stat[0].scale = FE_SCALE_DECIBEL; 313 c->cnr.stat[0].svalue = cnr; 314 } else { 315 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 316 } 317 } else { 318 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 319 } 320 321 /* BER */ 322 if (dev->fe_status & FE_HAS_LOCK) { 323 unsigned int utmp, post_bit_error, post_bit_count; 324 325 switch (c->delivery_system) { 326 case SYS_DVBS: 327 ret = regmap_write(dev->regmap, 0xf9, 0x04); 328 if (ret) 329 goto err; 330 331 ret = regmap_read(dev->regmap, 0xf8, &utmp); 332 if (ret) 333 goto err; 334 335 /* measurement ready? */ 336 if (!(utmp & 0x10)) { 337 ret = regmap_bulk_read(dev->regmap, 0xf6, buf, 2); 338 if (ret) 339 goto err; 340 341 post_bit_error = buf[1] << 8 | buf[0] << 0; 342 post_bit_count = 0x800000; 343 dev->post_bit_error += post_bit_error; 344 dev->post_bit_count += post_bit_count; 345 dev->dvbv3_ber = post_bit_error; 346 347 /* restart measurement */ 348 utmp |= 0x10; 349 ret = regmap_write(dev->regmap, 0xf8, utmp); 350 if (ret) 351 goto err; 352 } 353 break; 354 case SYS_DVBS2: 355 ret = regmap_bulk_read(dev->regmap, 0xd5, buf, 3); 356 if (ret) 357 goto err; 358 359 utmp = buf[2] << 16 | buf[1] << 8 | buf[0] << 0; 360 361 /* enough data? */ 362 if (utmp > 4000) { 363 ret = regmap_bulk_read(dev->regmap, 0xf7, buf, 2); 364 if (ret) 365 goto err; 366 367 post_bit_error = buf[1] << 8 | buf[0] << 0; 368 post_bit_count = 32 * utmp; /* TODO: FEC */ 369 dev->post_bit_error += post_bit_error; 370 dev->post_bit_count += post_bit_count; 371 dev->dvbv3_ber = post_bit_error; 372 373 /* restart measurement */ 374 ret = regmap_write(dev->regmap, 0xd1, 0x01); 375 if (ret) 376 goto err; 377 378 ret = regmap_write(dev->regmap, 0xf9, 0x01); 379 if (ret) 380 goto err; 381 382 ret = regmap_write(dev->regmap, 0xf9, 0x00); 383 if (ret) 384 goto err; 385 386 ret = regmap_write(dev->regmap, 0xd1, 0x00); 387 if (ret) 388 goto err; 389 } 390 break; 391 default: 392 dev_dbg(&client->dev, "invalid delivery_system\n"); 393 ret = -EINVAL; 394 goto err; 395 } 396 397 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; 398 c->post_bit_error.stat[0].uvalue = dev->post_bit_error; 399 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; 400 c->post_bit_count.stat[0].uvalue = dev->post_bit_count; 401 } else { 402 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 403 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 404 } 405 406 return 0; 407 err: 408 dev_dbg(&client->dev, "failed=%d\n", ret); 409 410 return ret; 411 } 412 413 static int m88ds3103b_select_mclk(struct m88ds3103_dev *dev) 414 { 415 struct i2c_client *client = dev->client; 416 struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache; 417 u32 adc_Freq_MHz[3] = {96, 93, 99}; 418 u8 reg16_list[3] = {96, 92, 100}, reg16, reg15; 419 u32 offset_MHz[3]; 420 u32 max_offset = 0; 421 u32 old_setting = dev->mclk; 422 u32 tuner_freq_MHz = c->frequency / 1000; 423 u8 i; 424 char big_symbol = 0; 425 426 big_symbol = (c->symbol_rate > 45010000) ? 1 : 0; 427 428 if (big_symbol) { 429 reg16 = 115; 430 } else { 431 reg16 = 96; 432 433 /* TODO: IS THIS NECESSARY ? */ 434 for (i = 0; i < 3; i++) { 435 offset_MHz[i] = tuner_freq_MHz % adc_Freq_MHz[i]; 436 437 if (offset_MHz[i] > (adc_Freq_MHz[i] / 2)) 438 offset_MHz[i] = adc_Freq_MHz[i] - offset_MHz[i]; 439 440 if (offset_MHz[i] > max_offset) { 441 max_offset = offset_MHz[i]; 442 reg16 = reg16_list[i]; 443 dev->mclk = adc_Freq_MHz[i] * 1000 * 1000; 444 445 if (big_symbol) 446 dev->mclk /= 2; 447 448 dev_dbg(&client->dev, "modifying mclk %u -> %u\n", 449 old_setting, dev->mclk); 450 } 451 } 452 } 453 454 if (dev->mclk == 93000000) 455 regmap_write(dev->regmap, 0xA0, 0x42); 456 else if (dev->mclk == 96000000) 457 regmap_write(dev->regmap, 0xA0, 0x44); 458 else if (dev->mclk == 99000000) 459 regmap_write(dev->regmap, 0xA0, 0x46); 460 else if (dev->mclk == 110250000) 461 regmap_write(dev->regmap, 0xA0, 0x4E); 462 else 463 regmap_write(dev->regmap, 0xA0, 0x44); 464 465 reg15 = m88ds3103b_dt_read(dev, 0x15); 466 467 if (dev->chiptype != M88DS3103_CHIPTYPE_3103C) { 468 m88ds3103b_dt_write(dev, 0x05, 0x40); 469 m88ds3103b_dt_write(dev, 0x11, 0x08); 470 } 471 472 if (big_symbol) 473 reg15 |= 0x02; 474 else 475 reg15 &= ~0x02; 476 477 m88ds3103b_dt_write(dev, 0x15, reg15); 478 m88ds3103b_dt_write(dev, 0x16, reg16); 479 480 usleep_range(5000, 5500); 481 482 if (dev->chiptype != M88DS3103_CHIPTYPE_3103C) { 483 m88ds3103b_dt_write(dev, 0x05, 0x00); 484 m88ds3103b_dt_write(dev, 0x11, (u8)(big_symbol ? 0x0E : 0x0A)); 485 } 486 487 usleep_range(5000, 5500); 488 489 return 0; 490 } 491 492 static int m88ds3103b_set_mclk(struct m88ds3103_dev *dev, u32 mclk_khz) 493 { 494 u8 reg15, reg16, reg1D, reg1E, reg1F, tmp; 495 u8 sm, f0 = 0, f1 = 0, f2 = 0, f3 = 0; 496 u16 pll_div_fb, N; 497 u32 div; 498 499 reg15 = m88ds3103b_dt_read(dev, 0x15); 500 reg16 = m88ds3103b_dt_read(dev, 0x16); 501 reg1D = m88ds3103b_dt_read(dev, 0x1D); 502 503 if (dev->cfg->ts_mode != M88DS3103_TS_SERIAL) { 504 if (reg16 == 92) 505 tmp = 93; 506 else if (reg16 == 100) 507 tmp = 99; 508 else 509 tmp = 96; 510 511 mclk_khz *= tmp; 512 mclk_khz /= 96; 513 } 514 515 pll_div_fb = (reg15 & 0x01) << 8; 516 pll_div_fb += reg16; 517 pll_div_fb += 32; 518 519 div = 9000 * pll_div_fb * 4; 520 div /= mclk_khz; 521 522 if (dev->cfg->ts_mode == M88DS3103_TS_SERIAL) { 523 if (div <= 32) { 524 N = 2; 525 526 f0 = 0; 527 f1 = div / N; 528 f2 = div - f1; 529 f3 = 0; 530 } else if (div <= 34) { 531 N = 3; 532 533 f0 = div / N; 534 f1 = (div - f0) / (N - 1); 535 f2 = div - f0 - f1; 536 f3 = 0; 537 } else if (div <= 64) { 538 N = 4; 539 540 f0 = div / N; 541 f1 = (div - f0) / (N - 1); 542 f2 = (div - f0 - f1) / (N - 2); 543 f3 = div - f0 - f1 - f2; 544 } else { 545 N = 4; 546 547 f0 = 16; 548 f1 = 16; 549 f2 = 16; 550 f3 = 16; 551 } 552 553 if (f0 == 16) 554 f0 = 0; 555 else if ((f0 < 8) && (f0 != 0)) 556 f0 = 8; 557 558 if (f1 == 16) 559 f1 = 0; 560 else if ((f1 < 8) && (f1 != 0)) 561 f1 = 8; 562 563 if (f2 == 16) 564 f2 = 0; 565 else if ((f2 < 8) && (f2 != 0)) 566 f2 = 8; 567 568 if (f3 == 16) 569 f3 = 0; 570 else if ((f3 < 8) && (f3 != 0)) 571 f3 = 8; 572 } else { 573 if (div <= 32) { 574 N = 2; 575 576 f0 = 0; 577 f1 = div / N; 578 f2 = div - f1; 579 f3 = 0; 580 } else if (div <= 48) { 581 N = 3; 582 583 f0 = div / N; 584 f1 = (div - f0) / (N - 1); 585 f2 = div - f0 - f1; 586 f3 = 0; 587 } else if (div <= 64) { 588 N = 4; 589 590 f0 = div / N; 591 f1 = (div - f0) / (N - 1); 592 f2 = (div - f0 - f1) / (N - 2); 593 f3 = div - f0 - f1 - f2; 594 } else { 595 N = 4; 596 597 f0 = 16; 598 f1 = 16; 599 f2 = 16; 600 f3 = 16; 601 } 602 603 if (f0 == 16) 604 f0 = 0; 605 else if ((f0 < 9) && (f0 != 0)) 606 f0 = 9; 607 608 if (f1 == 16) 609 f1 = 0; 610 else if ((f1 < 9) && (f1 != 0)) 611 f1 = 9; 612 613 if (f2 == 16) 614 f2 = 0; 615 else if ((f2 < 9) && (f2 != 0)) 616 f2 = 9; 617 618 if (f3 == 16) 619 f3 = 0; 620 else if ((f3 < 9) && (f3 != 0)) 621 f3 = 9; 622 } 623 624 sm = N - 1; 625 626 reg1D &= ~0x03; 627 reg1D |= sm; 628 reg1D |= 0x80; 629 630 reg1E = ((f3 << 4) + f2) & 0xFF; 631 reg1F = ((f1 << 4) + f0) & 0xFF; 632 633 if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) { 634 m88ds3103b_dt_write(dev, 0x05, 0x40); 635 m88ds3103b_dt_write(dev, 0x11, 0x08); 636 } 637 638 m88ds3103b_dt_write(dev, 0x1D, reg1D); 639 m88ds3103b_dt_write(dev, 0x1E, reg1E); 640 m88ds3103b_dt_write(dev, 0x1F, reg1F); 641 642 m88ds3103b_dt_write(dev, 0x17, 0xc1); 643 m88ds3103b_dt_write(dev, 0x17, 0x81); 644 645 usleep_range(5000, 5500); 646 647 if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) { 648 m88ds3103b_dt_write(dev, 0x05, 0x00); 649 m88ds3103b_dt_write(dev, 0x11, 0x0A); 650 } 651 652 usleep_range(5000, 5500); 653 654 return 0; 655 } 656 657 static int mt_fe_dmd_ds3103c_set_ts_out_mode(struct dvb_frontend *fe, enum m88ds3103_ts_mode mode) 658 { 659 struct m88ds3103_dev *dev = fe->demodulator_priv; 660 661 unsigned int tmp, val = 0; 662 663 regmap_read(dev->regmap, 0x0b, &val); 664 val &= ~0x01; 665 regmap_write(dev->regmap, 0x0b, val); 666 667 regmap_read(dev->regmap, 0xfd, &tmp); 668 if (mode == M88DS3103_TS_PARALLEL) { 669 tmp &= ~0x01; 670 tmp &= ~0x04; 671 672 regmap_write(dev->regmap, 0xfa, 0x01); 673 regmap_write(dev->regmap, 0xf1, 0x60); 674 regmap_write(dev->regmap, 0xfa, 0x00); 675 } else if (mode == M88DS3103_TS_SERIAL) { 676 tmp &= ~0x01; 677 tmp |= 0x04; 678 } else { 679 tmp |= 0x01; 680 tmp &= ~0x04; 681 682 regmap_write(dev->regmap, 0xfa, 0x01); 683 regmap_write(dev->regmap, 0xf1, 0x60); 684 regmap_write(dev->regmap, 0xfa, 0x00); 685 } 686 687 if (dev->cfg->ts_clk_pol) { 688 tmp &= ~0xf8; 689 tmp |= 0x02; 690 } else { 691 tmp &= ~0xb8; 692 tmp |= 0x42; 693 } 694 695 tmp |= 0x80; 696 regmap_write(dev->regmap, 0xfd, tmp); 697 698 val = 0; 699 if (mode != M88DS3103_TS_SERIAL) { 700 tmp = M88DS3103_TS_CI; 701 702 val |= tmp & 0x03; 703 val |= (tmp << 2) & 0x0C; 704 val |= (tmp << 4) & 0x30; 705 val |= (tmp << 6) & 0xC0; 706 } else { 707 val = 0x00; 708 } 709 710 regmap_write(dev->regmap, 0x0a, val); 711 712 regmap_read(dev->regmap, 0x0b, &tmp); 713 714 tmp &= ~0x20; 715 tmp |= 0x01; 716 717 regmap_write(dev->regmap, 0x0b, tmp); 718 719 regmap_read(dev->regmap, 0x0c, &tmp); 720 721 regmap_write(dev->regmap, 0xf4, 0x01); 722 723 tmp &= ~0x80; 724 regmap_write(dev->regmap, 0x0c, tmp); 725 726 return 0; 727 } 728 729 static int m88ds3103_set_frontend(struct dvb_frontend *fe) 730 { 731 struct m88ds3103_dev *dev = fe->demodulator_priv; 732 struct i2c_client *client = dev->client; 733 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 734 int ret, len; 735 const struct m88ds3103_reg_val *init; 736 u8 u8tmp, u8tmp1 = 0, u8tmp2 = 0; /* silence compiler warning */ 737 u8 buf[3]; 738 u16 u16tmp; 739 u32 tuner_frequency_khz, target_mclk, u32tmp; 740 s32 s32tmp; 741 unsigned int utmp; 742 static const struct reg_sequence reset_buf[] = { 743 {0x07, 0x80}, {0x07, 0x00} 744 }; 745 746 dev_dbg(&client->dev, 747 "delivery_system=%d modulation=%d frequency=%u symbol_rate=%d inversion=%d pilot=%d rolloff=%d\n", 748 c->delivery_system, c->modulation, c->frequency, c->symbol_rate, 749 c->inversion, c->pilot, c->rolloff); 750 751 if (!dev->warm) { 752 ret = -EAGAIN; 753 goto err; 754 } 755 756 /* reset */ 757 ret = regmap_multi_reg_write(dev->regmap, reset_buf, 2); 758 if (ret) 759 goto err; 760 761 /* Clear TS */ 762 ret = regmap_write(dev->regmap, 0xf5, 0x00); 763 764 /* Disable demod clock path */ 765 if (dev->chip_id == M88RS6000_CHIP_ID || 766 dev->chip_id == M88DS3103C_CHIP_ID) { 767 if (dev->chiptype == M88DS3103_CHIPTYPE_3103B || 768 dev->chiptype == M88DS3103_CHIPTYPE_3103C) { 769 ret = regmap_read(dev->regmap, 0xb2, &u32tmp); 770 if (ret) 771 goto err; 772 if (u32tmp == 0x01) { 773 ret = regmap_write(dev->regmap, 0x00, 0x00); 774 if (ret) 775 goto err; 776 ret = regmap_write(dev->regmap, 0xb2, 0x00); 777 if (ret) 778 goto err; 779 } 780 } 781 782 ret = regmap_write(dev->regmap, 0x06, 0xe0); 783 if (ret) 784 goto err; 785 } 786 787 /* program tuner */ 788 if (fe->ops.tuner_ops.set_params) { 789 ret = fe->ops.tuner_ops.set_params(fe); 790 if (ret) 791 goto err; 792 } 793 794 if (fe->ops.tuner_ops.get_frequency) { 795 ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_frequency_khz); 796 if (ret) 797 goto err; 798 } else { 799 /* 800 * Use nominal target frequency as tuner driver does not provide 801 * actual frequency used. Carrier offset calculation is not 802 * valid. 803 */ 804 tuner_frequency_khz = c->frequency; 805 } 806 807 /* set M88RS6000/DS3103B demod main mclk and ts mclk from tuner die */ 808 if (dev->chip_id == M88RS6000_CHIP_ID || 809 dev->chip_id == M88DS3103C_CHIP_ID) { 810 if (c->symbol_rate > 45010000) 811 dev->mclk = 110250000; 812 else 813 dev->mclk = 96000000; 814 815 if (c->delivery_system == SYS_DVBS) 816 target_mclk = 96000000; 817 else 818 target_mclk = 144000000; 819 820 if (dev->chiptype == M88DS3103_CHIPTYPE_3103B || 821 dev->chiptype == M88DS3103_CHIPTYPE_3103C) { 822 m88ds3103b_select_mclk(dev); 823 m88ds3103b_set_mclk(dev, target_mclk / 1000); 824 } 825 826 /* Enable demod clock path */ 827 ret = regmap_write(dev->regmap, 0x06, 0x00); 828 if (ret) 829 goto err; 830 usleep_range(10000, 20000); 831 } else { 832 /* set M88DS3103 mclk and ts mclk. */ 833 dev->mclk = 96000000; 834 835 switch (dev->cfg->ts_mode) { 836 case M88DS3103_TS_SERIAL: 837 case M88DS3103_TS_SERIAL_D7: 838 target_mclk = dev->cfg->ts_clk; 839 break; 840 case M88DS3103_TS_PARALLEL: 841 case M88DS3103_TS_CI: 842 if (c->delivery_system == SYS_DVBS) 843 target_mclk = 96000000; 844 else { 845 if (c->symbol_rate < 18000000) 846 target_mclk = 96000000; 847 else if (c->symbol_rate < 28000000) 848 target_mclk = 144000000; 849 else 850 target_mclk = 192000000; 851 } 852 break; 853 default: 854 dev_dbg(&client->dev, "invalid ts_mode\n"); 855 ret = -EINVAL; 856 goto err; 857 } 858 859 switch (target_mclk) { 860 case 96000000: 861 u8tmp1 = 0x02; /* 0b10 */ 862 u8tmp2 = 0x01; /* 0b01 */ 863 break; 864 case 144000000: 865 u8tmp1 = 0x00; /* 0b00 */ 866 u8tmp2 = 0x01; /* 0b01 */ 867 break; 868 case 192000000: 869 u8tmp1 = 0x03; /* 0b11 */ 870 u8tmp2 = 0x00; /* 0b00 */ 871 break; 872 } 873 ret = m88ds3103_update_bits(dev, 0x22, 0xc0, u8tmp1 << 6); 874 if (ret) 875 goto err; 876 ret = m88ds3103_update_bits(dev, 0x24, 0xc0, u8tmp2 << 6); 877 if (ret) 878 goto err; 879 } 880 881 ret = regmap_write(dev->regmap, 0xb2, 0x01); 882 if (ret) 883 goto err; 884 885 ret = regmap_write(dev->regmap, 0x00, 0x01); 886 if (ret) 887 goto err; 888 889 switch (c->delivery_system) { 890 case SYS_DVBS: 891 if (dev->chip_id == M88RS6000_CHIP_ID) { 892 len = ARRAY_SIZE(m88rs6000_dvbs_init_reg_vals); 893 init = m88rs6000_dvbs_init_reg_vals; 894 } else if (dev->chip_id == M88DS3103C_CHIP_ID) { 895 len = ARRAY_SIZE(m88ds3103c_dvbs_init_reg_vals); 896 init = m88ds3103c_dvbs_init_reg_vals; 897 } else { 898 len = ARRAY_SIZE(m88ds3103_dvbs_init_reg_vals); 899 init = m88ds3103_dvbs_init_reg_vals; 900 } 901 break; 902 case SYS_DVBS2: 903 if (dev->chip_id == M88RS6000_CHIP_ID) { 904 len = ARRAY_SIZE(m88rs6000_dvbs2_init_reg_vals); 905 init = m88rs6000_dvbs2_init_reg_vals; 906 } else if (dev->chip_id == M88DS3103C_CHIP_ID) { 907 len = ARRAY_SIZE(m88ds3103c_dvbs_init_reg_vals); 908 init = m88ds3103c_dvbs_init_reg_vals; 909 } else { 910 len = ARRAY_SIZE(m88ds3103_dvbs2_init_reg_vals); 911 init = m88ds3103_dvbs2_init_reg_vals; 912 } 913 break; 914 default: 915 dev_dbg(&client->dev, "invalid delivery_system\n"); 916 ret = -EINVAL; 917 goto err; 918 } 919 920 /* program init table */ 921 if (c->delivery_system != dev->delivery_system) { 922 ret = m88ds3103_wr_reg_val_tab(dev, init, len); 923 if (ret) 924 goto err; 925 } 926 927 if (dev->chip_id == M88RS6000_CHIP_ID || 928 dev->chip_id == M88DS3103C_CHIP_ID) { 929 if (c->delivery_system == SYS_DVBS2 && 930 c->symbol_rate <= 5000000) { 931 ret = regmap_write(dev->regmap, 0xc0, 0x04); 932 if (ret) 933 goto err; 934 buf[0] = 0x09; 935 buf[1] = 0x22; 936 buf[2] = 0x88; 937 ret = regmap_bulk_write(dev->regmap, 0x8a, buf, 3); 938 if (ret) 939 goto err; 940 } 941 if (dev->chip_id != M88DS3103C_CHIP_ID) { 942 ret = m88ds3103_update_bits(dev, 0x9d, 0x08, 0x08); 943 if (ret) 944 goto err; 945 } 946 947 if (dev->chiptype == M88DS3103_CHIPTYPE_3103B || 948 dev->chiptype == M88DS3103_CHIPTYPE_3103C) { 949 buf[0] = m88ds3103b_dt_read(dev, 0x15); 950 buf[1] = m88ds3103b_dt_read(dev, 0x16); 951 952 if (c->symbol_rate > 45010000) { 953 buf[0] &= ~0x03; 954 buf[0] |= 0x02; 955 buf[0] |= ((147 - 32) >> 8) & 0x01; 956 buf[1] = (147 - 32) & 0xFF; 957 958 dev->mclk = 110250 * 1000; 959 } else { 960 buf[0] &= ~0x03; 961 buf[0] |= ((128 - 32) >> 8) & 0x01; 962 buf[1] = (128 - 32) & 0xFF; 963 964 dev->mclk = 96000 * 1000; 965 } 966 m88ds3103b_dt_write(dev, 0x15, buf[0]); 967 m88ds3103b_dt_write(dev, 0x16, buf[1]); 968 969 regmap_read(dev->regmap, 0x30, &u32tmp); 970 if (dev->chip_id == M88DS3103C_CHIP_ID) { 971 regmap_write(dev->regmap, 0x30, dev->config.agc_inv ? 0x18 : 0x08); 972 } else { 973 u32tmp &= ~0x80; 974 regmap_write(dev->regmap, 0x30, u32tmp & 0xff); 975 } 976 } 977 978 if (dev->chip_id != M88DS3103C_CHIP_ID) { 979 ret = regmap_write(dev->regmap, 0xf1, 0x01); 980 if (ret) 981 goto err; 982 } 983 984 if (dev->chiptype != M88DS3103_CHIPTYPE_3103B && 985 dev->chiptype != M88DS3103_CHIPTYPE_3103C) { 986 ret = m88ds3103_update_bits(dev, 0x30, 0x80, 0x80); 987 if (ret) 988 goto err; 989 } 990 } 991 992 switch (dev->cfg->ts_mode) { 993 case M88DS3103_TS_SERIAL: 994 u8tmp1 = 0x00; 995 u8tmp = 0x06; 996 break; 997 case M88DS3103_TS_SERIAL_D7: 998 u8tmp1 = 0x20; 999 u8tmp = 0x06; 1000 break; 1001 case M88DS3103_TS_PARALLEL: 1002 u8tmp = 0x02; 1003 if (dev->chiptype == M88DS3103_CHIPTYPE_3103B || 1004 dev->chiptype == M88DS3103_CHIPTYPE_3103C) { 1005 u8tmp = 0x01; 1006 u8tmp1 = 0x01; 1007 } 1008 break; 1009 case M88DS3103_TS_CI: 1010 u8tmp = 0x03; 1011 break; 1012 default: 1013 dev_dbg(&client->dev, "invalid ts_mode\n"); 1014 ret = -EINVAL; 1015 goto err; 1016 } 1017 1018 if (dev->cfg->ts_clk_pol) 1019 u8tmp |= 0x40; 1020 1021 if (dev->chiptype != M88DS3103_CHIPTYPE_3103C) { 1022 /* TS mode */ 1023 ret = regmap_write(dev->regmap, 0xfd, u8tmp); 1024 if (ret) 1025 goto err; 1026 } 1027 1028 switch (dev->cfg->ts_mode) { 1029 case M88DS3103_TS_SERIAL: 1030 case M88DS3103_TS_SERIAL_D7: 1031 ret = m88ds3103_update_bits(dev, 0x29, 0x20, u8tmp1); 1032 if (ret) 1033 goto err; 1034 u16tmp = 0; 1035 u8tmp1 = 0x3f; 1036 u8tmp2 = 0x3f; 1037 break; 1038 case M88DS3103_TS_PARALLEL: 1039 if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) { 1040 ret = m88ds3103_update_bits(dev, 0x29, 0x01, u8tmp1); 1041 if (ret) 1042 goto err; 1043 } 1044 fallthrough; 1045 default: 1046 u16tmp = DIV_ROUND_UP(target_mclk, dev->cfg->ts_clk); 1047 u8tmp1 = u16tmp / 2 - 1; 1048 u8tmp2 = DIV_ROUND_UP(u16tmp, 2) - 1; 1049 } 1050 1051 dev_dbg(&client->dev, "target_mclk=%u ts_clk=%u ts_clk_divide_ratio=%u\n", 1052 target_mclk, dev->cfg->ts_clk, u16tmp); 1053 1054 /* u8tmp1[5:2] => fe[3:0], u8tmp1[1:0] => ea[7:6] */ 1055 /* u8tmp2[5:0] => ea[5:0] */ 1056 u8tmp = (u8tmp1 >> 2) & 0x0f; 1057 ret = regmap_update_bits(dev->regmap, 0xfe, 0x0f, u8tmp); 1058 if (ret) 1059 goto err; 1060 1061 if (dev->chiptype == M88DS3103_CHIPTYPE_3103C) 1062 u8tmp = 0xcb; 1063 else 1064 u8tmp = ((u8tmp1 & 0x03) << 6) | u8tmp2 >> 0; 1065 1066 ret = regmap_write(dev->regmap, 0xea, u8tmp); 1067 if (ret) 1068 goto err; 1069 1070 if (c->symbol_rate <= 3000000) 1071 u8tmp = 0x20; 1072 else if (c->symbol_rate <= 10000000) 1073 u8tmp = 0x10; 1074 else 1075 u8tmp = 0x06; 1076 1077 if (dev->chiptype == M88DS3103_CHIPTYPE_3103B || 1078 dev->chiptype == M88DS3103_CHIPTYPE_3103C) 1079 m88ds3103b_set_mclk(dev, target_mclk / 1000); 1080 1081 ret = regmap_write(dev->regmap, 0xc3, 0x08); 1082 if (ret) 1083 goto err; 1084 1085 ret = regmap_write(dev->regmap, 0xc8, u8tmp); 1086 if (ret) 1087 goto err; 1088 1089 ret = regmap_write(dev->regmap, 0xc4, 0x08); 1090 if (ret) 1091 goto err; 1092 1093 ret = regmap_write(dev->regmap, 0xc7, 0x00); 1094 if (ret) 1095 goto err; 1096 1097 if (dev->chiptype == M88DS3103_CHIPTYPE_3103C) 1098 u16tmp = DIV_ROUND_CLOSEST_ULL((((u64)c->symbol_rate << 15) + dev->mclk / 4), 1099 (dev->mclk / 2)); 1100 else 1101 u16tmp = DIV_ROUND_CLOSEST_ULL((u64)c->symbol_rate * 0x10000, dev->mclk); 1102 1103 buf[0] = (u16tmp >> 0) & 0xff; 1104 buf[1] = (u16tmp >> 8) & 0xff; 1105 1106 ret = regmap_bulk_write(dev->regmap, 0x61, buf, 2); 1107 if (ret) 1108 goto err; 1109 1110 ret = m88ds3103_update_bits(dev, 0x4d, 0x02, dev->cfg->spec_inv << 1); 1111 if (ret) 1112 goto err; 1113 1114 if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) { 1115 ret = m88ds3103_update_bits(dev, 0x30, 0x08, dev->cfg->agc_inv << 3); 1116 } else if (dev->chiptype == M88DS3103_CHIPTYPE_3103C) { 1117 ret = m88ds3103_update_bits(dev, 0x08, 0x43, 0x43); 1118 1119 ret = m88ds3103_update_bits(dev, 0x30, 0x18, dev->cfg->agc_inv ? 0x18 : 0x08); 1120 } else { 1121 ret = m88ds3103_update_bits(dev, 0x30, 0x10, dev->cfg->agc_inv << 4); 1122 } 1123 if (ret) 1124 goto err; 1125 1126 ret = regmap_write(dev->regmap, 0x33, dev->cfg->agc); 1127 if (ret) 1128 goto err; 1129 1130 if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) { 1131 /* enable/disable 192M LDPC clock */ 1132 ret = m88ds3103_update_bits(dev, 0x29, 0x10, 1133 (c->delivery_system == SYS_DVBS) ? 0x10 : 0x0); 1134 if (ret) 1135 goto err; 1136 } 1137 1138 if (dev->chiptype == M88DS3103_CHIPTYPE_3103C) { 1139 ret = m88ds3103_update_bits(dev, 0x76, 0x80, 0x00); 1140 if (ret) 1141 goto err; 1142 1143 ret = m88ds3103_update_bits(dev, 0x22, 0x01, 0x01); 1144 ret = m88ds3103_update_bits(dev, 0x23, 0x01, 0x00); 1145 ret = m88ds3103_update_bits(dev, 0x24, 0x01, 0x00); 1146 1147 ret = m88ds3103_update_bits(dev, 0xc9, 0x08, 0x08); 1148 if (ret) 1149 goto err; 1150 1151 ret = regmap_read(dev->regmap, 0x08, &utmp); 1152 if (ret) 1153 goto err; 1154 1155 if (c->delivery_system == SYS_DVBS) { 1156 utmp = (utmp & 0xfb) | 0x40; 1157 regmap_write(dev->regmap, 0x08, utmp); 1158 regmap_write(dev->regmap, 0xe0, 0xf8); 1159 } else if (c->delivery_system == SYS_DVBS2) { 1160 utmp = utmp | 0x44; 1161 regmap_write(dev->regmap, 0x08, utmp); 1162 } else { 1163 utmp = utmp & 0xbb; 1164 regmap_write(dev->regmap, 0x08, utmp); 1165 regmap_write(dev->regmap, 0xe0, 0xf8); 1166 } 1167 } 1168 1169 dev_dbg(&client->dev, "carrier offset=%d\n", 1170 (tuner_frequency_khz - c->frequency)); 1171 1172 /* Use 32-bit calc as there is no s64 version of DIV_ROUND_CLOSEST() */ 1173 s32tmp = 0x10000 * (tuner_frequency_khz - c->frequency); 1174 s32tmp = DIV_ROUND_CLOSEST(s32tmp, dev->mclk / 1000); 1175 1176 usleep_range(1000, 1200); 1177 1178 buf[0] = (s32tmp >> 0) & 0xff; 1179 buf[1] = (s32tmp >> 8) & 0xff; 1180 1181 ret = regmap_bulk_write(dev->regmap, 0x5e, buf, 2); 1182 if (ret) 1183 goto err; 1184 1185 ret = regmap_write(dev->regmap, 0x00, 0x00); 1186 if (ret) 1187 goto err; 1188 1189 ret = regmap_write(dev->regmap, 0xb2, 0x00); 1190 if (ret) 1191 goto err; 1192 1193 if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) { 1194 /* to light up the LOCK led */ 1195 ret = m88ds3103_update_bits(dev, 0x11, 0x80, 0x00); 1196 if (ret) 1197 goto err; 1198 } 1199 1200 dev->delivery_system = c->delivery_system; 1201 1202 return 0; 1203 err: 1204 dev_dbg(&client->dev, "failed=%d\n", ret); 1205 1206 return ret; 1207 } 1208 1209 static int m88ds3103_init(struct dvb_frontend *fe) 1210 { 1211 struct m88ds3103_dev *dev = fe->demodulator_priv; 1212 struct i2c_client *client = dev->client; 1213 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 1214 int ret, len, rem; 1215 unsigned int utmp; 1216 const struct firmware *firmware; 1217 const char *name; 1218 1219 dev_dbg(&client->dev, "\n"); 1220 1221 /* set cold state by default */ 1222 dev->warm = false; 1223 1224 /* wake up device from sleep */ 1225 if (dev->chiptype == M88DS3103_CHIPTYPE_3103C) { 1226 ret = m88ds3103_update_bits(dev, 0x0b, 0x90, 0x80); /* set dt_addr */ 1227 1228 m88ds3103b_dt_write(dev, 0x04, 0x01); /* reset */ 1229 m88ds3103b_dt_write(dev, 0x04, 0x00); 1230 usleep_range(800, 1200); 1231 1232 ret = m88ds3103_update_bits(dev, 0x04, 0x01, 0x00); 1233 if (ret) 1234 goto err; 1235 1236 m88ds3103b_dt_write(dev, 0x10, 0x01); /* wakeup */ 1237 m88ds3103b_dt_write(dev, 0x11, 0x01); /* wakeup */ 1238 1239 ret = m88ds3103_update_bits(dev, 0x08, 0x01, 0x01); 1240 if (ret) 1241 goto err; 1242 1243 ret = m88ds3103_update_bits(dev, 0x0b, 0x01, 0x01); 1244 if (ret) 1245 goto err; 1246 /* global reset, global diseqc reset, global fec reset */ 1247 ret = regmap_write(dev->regmap, 0x07, 0x80); 1248 if (ret) 1249 goto err; 1250 ret = regmap_write(dev->regmap, 0x07, 0x00); 1251 if (ret) 1252 goto err; 1253 usleep_range(800, 1200); 1254 1255 ret = m88ds3103_update_bits(dev, 0x08, 0x01, 0x01); 1256 if (ret) 1257 goto err; 1258 } else { 1259 ret = m88ds3103_update_bits(dev, 0x08, 0x01, 0x01); 1260 if (ret) 1261 goto err; 1262 ret = m88ds3103_update_bits(dev, 0x04, 0x01, 0x00); 1263 if (ret) 1264 goto err; 1265 ret = m88ds3103_update_bits(dev, 0x23, 0x10, 0x00); 1266 if (ret) 1267 goto err; 1268 } 1269 1270 if (dev->chiptype == M88DS3103_CHIPTYPE_3103C) { 1271 m88ds3103b_dt_write(dev, 0x10, 0x01); /* wakeup */ 1272 m88ds3103b_dt_write(dev, 0x11, 0x01); /* wakeup */ 1273 m88ds3103b_dt_write(dev, 0x24, 0x04); 1274 m88ds3103b_dt_write(dev, 0x84, 0x04); 1275 m88ds3103b_dt_write(dev, 0x15, 0x6c); 1276 usleep_range(800, 1200); 1277 } 1278 1279 /* global reset, global diseqc reset, global fec reset */ 1280 ret = regmap_write(dev->regmap, 0x07, 0xe0); 1281 if (ret) 1282 goto err; 1283 ret = regmap_write(dev->regmap, 0x07, 0x00); 1284 if (ret) 1285 goto err; 1286 1287 /* firmware status */ 1288 ret = regmap_read(dev->regmap, 0xb9, &utmp); 1289 if (ret) 1290 goto err; 1291 1292 dev_dbg(&client->dev, "firmware=%02x\n", utmp); 1293 1294 if (utmp) 1295 goto warm; 1296 1297 /* cold state - try to download firmware */ 1298 dev_info(&client->dev, "found a '%s' in cold state\n", 1299 dev->fe.ops.info.name); 1300 1301 if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) 1302 name = M88DS3103B_FIRMWARE; 1303 else if (dev->chiptype == M88DS3103_CHIPTYPE_3103C) 1304 name = M88DS3103C_FIRMWARE; 1305 else if (dev->chip_id == M88RS6000_CHIP_ID) 1306 name = M88RS6000_FIRMWARE; 1307 else 1308 name = M88DS3103_FIRMWARE; 1309 1310 /* request the firmware, this will block and timeout */ 1311 ret = request_firmware(&firmware, name, &client->dev); 1312 if (ret) { 1313 dev_err(&client->dev, "firmware file '%s' not found\n", name); 1314 goto err; 1315 } 1316 1317 dev_info(&client->dev, "downloading firmware from file '%s'\n", name); 1318 1319 ret = regmap_write(dev->regmap, 0xb2, 0x01); 1320 if (ret) 1321 goto err_release_firmware; 1322 1323 for (rem = firmware->size; rem > 0; rem -= (dev->cfg->i2c_wr_max - 1)) { 1324 len = min(dev->cfg->i2c_wr_max - 1, rem); 1325 ret = regmap_bulk_write(dev->regmap, 0xb0, 1326 &firmware->data[firmware->size - rem], 1327 len); 1328 if (ret) { 1329 dev_err(&client->dev, "firmware download failed %d\n", 1330 ret); 1331 goto err_release_firmware; 1332 } 1333 } 1334 1335 ret = regmap_write(dev->regmap, 0xb2, 0x00); 1336 if (ret) 1337 goto err_release_firmware; 1338 1339 release_firmware(firmware); 1340 1341 ret = regmap_read(dev->regmap, 0xb9, &utmp); 1342 if (ret) 1343 goto err; 1344 1345 if (!utmp) { 1346 ret = -EINVAL; 1347 dev_info(&client->dev, "firmware did not run\n"); 1348 goto err; 1349 } 1350 1351 dev_info(&client->dev, "found a '%s' in warm state\n", 1352 dev->fe.ops.info.name); 1353 dev_info(&client->dev, "firmware version: %X.%X\n", 1354 (utmp >> 4) & 0xf, (utmp >> 0 & 0xf)); 1355 1356 if (dev->chiptype == M88DS3103_CHIPTYPE_3103C) { 1357 mt_fe_dmd_ds3103c_set_ts_out_mode(fe, dev->cfg->ts_mode); 1358 1359 ret = m88ds3103_update_bits(dev, 0x4d, 0x02, dev->cfg->spec_inv << 1); 1360 if (ret) 1361 goto err; 1362 1363 ret = m88ds3103_update_bits(dev, 0x30, 0x10, dev->cfg->agc_inv ? 0x10 : 0x00); 1364 if (ret) 1365 goto err; 1366 } 1367 1368 if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) { 1369 m88ds3103b_dt_write(dev, 0x21, 0x92); 1370 m88ds3103b_dt_write(dev, 0x15, 0x6C); 1371 m88ds3103b_dt_write(dev, 0x17, 0xC1); 1372 m88ds3103b_dt_write(dev, 0x17, 0x81); 1373 } 1374 warm: 1375 /* warm state */ 1376 dev->warm = true; 1377 1378 /* init stats here in order signal app which stats are supported */ 1379 c->cnr.len = 1; 1380 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1381 c->post_bit_error.len = 1; 1382 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1383 c->post_bit_count.len = 1; 1384 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 1385 1386 return 0; 1387 err_release_firmware: 1388 release_firmware(firmware); 1389 err: 1390 dev_dbg(&client->dev, "failed=%d\n", ret); 1391 1392 return ret; 1393 } 1394 1395 static int m88ds3103_sleep(struct dvb_frontend *fe) 1396 { 1397 struct m88ds3103_dev *dev = fe->demodulator_priv; 1398 struct i2c_client *client = dev->client; 1399 int ret; 1400 unsigned int utmp; 1401 1402 dev_dbg(&client->dev, "\n"); 1403 1404 dev->fe_status = 0; 1405 dev->delivery_system = SYS_UNDEFINED; 1406 1407 /* TS Hi-Z */ 1408 if (dev->chip_id == M88RS6000_CHIP_ID) 1409 utmp = 0x29; 1410 else if (dev->chip_id == M88DS3103C_CHIP_ID) 1411 utmp = 0x0b; 1412 else 1413 utmp = 0x27; 1414 ret = m88ds3103_update_bits(dev, utmp, 0x01, 0x00); 1415 if (ret) 1416 goto err; 1417 1418 /* sleep */ 1419 ret = m88ds3103_update_bits(dev, 0x08, 0x01, 0x00); 1420 if (ret) 1421 goto err; 1422 1423 /* Internal tuner sleep */ 1424 if (dev->chip_id == M88DS3103C_CHIP_ID) { 1425 ret = m88ds3103b_dt_write(dev, 0x10, 0x00); 1426 if (ret) 1427 goto err; 1428 ret = m88ds3103b_dt_write(dev, 0x11, 0x00); 1429 if (ret) 1430 goto err; 1431 } 1432 1433 ret = m88ds3103_update_bits(dev, 0x04, 0x01, 0x01); 1434 if (ret) 1435 goto err; 1436 ret = m88ds3103_update_bits(dev, 0x23, 0x10, 0x10); 1437 if (ret) 1438 goto err; 1439 1440 return 0; 1441 err: 1442 dev_dbg(&client->dev, "failed=%d\n", ret); 1443 1444 return ret; 1445 } 1446 1447 static int m88ds3103_get_frontend(struct dvb_frontend *fe, 1448 struct dtv_frontend_properties *c) 1449 { 1450 struct m88ds3103_dev *dev = fe->demodulator_priv; 1451 struct i2c_client *client = dev->client; 1452 int ret; 1453 u8 buf[3]; 1454 1455 dev_dbg(&client->dev, "\n"); 1456 1457 if (!dev->warm || !(dev->fe_status & FE_HAS_LOCK)) { 1458 ret = 0; 1459 goto err; 1460 } 1461 1462 switch (c->delivery_system) { 1463 case SYS_DVBS: 1464 ret = regmap_bulk_read(dev->regmap, 0xe0, &buf[0], 1); 1465 if (ret) 1466 goto err; 1467 1468 ret = regmap_bulk_read(dev->regmap, 0xe6, &buf[1], 1); 1469 if (ret) 1470 goto err; 1471 1472 switch ((buf[0] >> 2) & 0x01) { 1473 case 0: 1474 c->inversion = INVERSION_OFF; 1475 break; 1476 case 1: 1477 c->inversion = INVERSION_ON; 1478 break; 1479 } 1480 1481 switch ((buf[1] >> 5) & 0x07) { 1482 case 0: 1483 c->fec_inner = FEC_7_8; 1484 break; 1485 case 1: 1486 c->fec_inner = FEC_5_6; 1487 break; 1488 case 2: 1489 c->fec_inner = FEC_3_4; 1490 break; 1491 case 3: 1492 c->fec_inner = FEC_2_3; 1493 break; 1494 case 4: 1495 c->fec_inner = FEC_1_2; 1496 break; 1497 default: 1498 dev_dbg(&client->dev, "invalid fec_inner\n"); 1499 } 1500 1501 c->modulation = QPSK; 1502 1503 break; 1504 case SYS_DVBS2: 1505 ret = regmap_bulk_read(dev->regmap, 0x7e, &buf[0], 1); 1506 if (ret) 1507 goto err; 1508 1509 ret = regmap_bulk_read(dev->regmap, 0x89, &buf[1], 1); 1510 if (ret) 1511 goto err; 1512 1513 ret = regmap_bulk_read(dev->regmap, 0xf2, &buf[2], 1); 1514 if (ret) 1515 goto err; 1516 1517 switch ((buf[0] >> 0) & 0x0f) { 1518 case 2: 1519 c->fec_inner = FEC_2_5; 1520 break; 1521 case 3: 1522 c->fec_inner = FEC_1_2; 1523 break; 1524 case 4: 1525 c->fec_inner = FEC_3_5; 1526 break; 1527 case 5: 1528 c->fec_inner = FEC_2_3; 1529 break; 1530 case 6: 1531 c->fec_inner = FEC_3_4; 1532 break; 1533 case 7: 1534 c->fec_inner = FEC_4_5; 1535 break; 1536 case 8: 1537 c->fec_inner = FEC_5_6; 1538 break; 1539 case 9: 1540 c->fec_inner = FEC_8_9; 1541 break; 1542 case 10: 1543 c->fec_inner = FEC_9_10; 1544 break; 1545 default: 1546 dev_dbg(&client->dev, "invalid fec_inner\n"); 1547 } 1548 1549 switch ((buf[0] >> 5) & 0x01) { 1550 case 0: 1551 c->pilot = PILOT_OFF; 1552 break; 1553 case 1: 1554 c->pilot = PILOT_ON; 1555 break; 1556 } 1557 1558 switch ((buf[0] >> 6) & 0x07) { 1559 case 0: 1560 c->modulation = QPSK; 1561 break; 1562 case 1: 1563 c->modulation = PSK_8; 1564 break; 1565 case 2: 1566 c->modulation = APSK_16; 1567 break; 1568 case 3: 1569 c->modulation = APSK_32; 1570 break; 1571 default: 1572 dev_dbg(&client->dev, "invalid modulation\n"); 1573 } 1574 1575 switch ((buf[1] >> 7) & 0x01) { 1576 case 0: 1577 c->inversion = INVERSION_OFF; 1578 break; 1579 case 1: 1580 c->inversion = INVERSION_ON; 1581 break; 1582 } 1583 1584 switch ((buf[2] >> 0) & 0x03) { 1585 case 0: 1586 c->rolloff = ROLLOFF_35; 1587 break; 1588 case 1: 1589 c->rolloff = ROLLOFF_25; 1590 break; 1591 case 2: 1592 c->rolloff = ROLLOFF_20; 1593 break; 1594 default: 1595 dev_dbg(&client->dev, "invalid rolloff\n"); 1596 } 1597 break; 1598 default: 1599 dev_dbg(&client->dev, "invalid delivery_system\n"); 1600 ret = -EINVAL; 1601 goto err; 1602 } 1603 1604 ret = regmap_bulk_read(dev->regmap, 0x6d, buf, 2); 1605 if (ret) 1606 goto err; 1607 1608 // dev_dbg(&client->dev, "%s() 0x%X | 0x%X\n", __func__, buf[0], buf[1]); 1609 c->symbol_rate = DIV_ROUND_CLOSEST_ULL((u64)(buf[1] << 8 | buf[0] << 0) * dev->mclk, 0x10000); 1610 1611 return 0; 1612 err: 1613 dev_dbg(&client->dev, "failed=%d\n", ret); 1614 1615 return ret; 1616 } 1617 1618 static int m88ds3103_read_snr(struct dvb_frontend *fe, u16 *snr) 1619 { 1620 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 1621 1622 if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL) 1623 *snr = div_s64(c->cnr.stat[0].svalue, 100); 1624 else 1625 *snr = 0; 1626 1627 return 0; 1628 } 1629 1630 static int m88ds3103_read_ber(struct dvb_frontend *fe, u32 *ber) 1631 { 1632 struct m88ds3103_dev *dev = fe->demodulator_priv; 1633 1634 *ber = dev->dvbv3_ber; 1635 1636 return 0; 1637 } 1638 1639 static int m88ds3103_set_tone(struct dvb_frontend *fe, 1640 enum fe_sec_tone_mode fe_sec_tone_mode) 1641 { 1642 struct m88ds3103_dev *dev = fe->demodulator_priv; 1643 struct i2c_client *client = dev->client; 1644 int ret; 1645 unsigned int utmp, tone, reg_a1_mask; 1646 1647 dev_dbg(&client->dev, "fe_sec_tone_mode=%s\n", 1648 fe_sec_tone_mode == SEC_TONE_ON ? "ON" : "OFF"); 1649 1650 if (!dev->warm) { 1651 ret = -EAGAIN; 1652 goto err; 1653 } 1654 1655 switch (fe_sec_tone_mode) { 1656 case SEC_TONE_ON: 1657 tone = 0; 1658 reg_a1_mask = 0x47; 1659 break; 1660 case SEC_TONE_OFF: 1661 tone = 1; 1662 reg_a1_mask = 0x00; 1663 break; 1664 default: 1665 dev_dbg(&client->dev, "invalid fe_sec_tone_mode\n"); 1666 ret = -EINVAL; 1667 goto err; 1668 } 1669 1670 utmp = tone << 7 | dev->cfg->envelope_mode << 5; 1671 ret = m88ds3103_update_bits(dev, 0xa2, 0xe0, utmp); 1672 if (ret) 1673 goto err; 1674 1675 utmp = 1 << 2; 1676 ret = m88ds3103_update_bits(dev, 0xa1, reg_a1_mask, utmp); 1677 if (ret) 1678 goto err; 1679 1680 return 0; 1681 err: 1682 dev_dbg(&client->dev, "failed=%d\n", ret); 1683 1684 return ret; 1685 } 1686 1687 static int m88ds3103_set_voltage(struct dvb_frontend *fe, 1688 enum fe_sec_voltage fe_sec_voltage) 1689 { 1690 struct m88ds3103_dev *dev = fe->demodulator_priv; 1691 struct i2c_client *client = dev->client; 1692 int ret; 1693 unsigned int utmp; 1694 bool voltage_sel, voltage_dis; 1695 1696 dev_dbg(&client->dev, "fe_sec_voltage=%d\n", fe_sec_voltage); 1697 1698 if (!dev->warm) { 1699 ret = -EAGAIN; 1700 goto err; 1701 } 1702 1703 switch (fe_sec_voltage) { 1704 case SEC_VOLTAGE_18: 1705 voltage_sel = true; 1706 voltage_dis = false; 1707 break; 1708 case SEC_VOLTAGE_13: 1709 voltage_sel = false; 1710 voltage_dis = false; 1711 break; 1712 case SEC_VOLTAGE_OFF: 1713 voltage_sel = false; 1714 voltage_dis = true; 1715 break; 1716 default: 1717 dev_dbg(&client->dev, "invalid fe_sec_voltage\n"); 1718 ret = -EINVAL; 1719 goto err; 1720 } 1721 1722 /* output pin polarity */ 1723 voltage_sel ^= dev->cfg->lnb_hv_pol; 1724 voltage_dis ^= dev->cfg->lnb_en_pol; 1725 1726 utmp = voltage_dis << 1 | voltage_sel << 0; 1727 ret = m88ds3103_update_bits(dev, 0xa2, 0x03, utmp); 1728 if (ret) 1729 goto err; 1730 1731 return 0; 1732 err: 1733 dev_dbg(&client->dev, "failed=%d\n", ret); 1734 1735 return ret; 1736 } 1737 1738 static int m88ds3103_diseqc_send_master_cmd(struct dvb_frontend *fe, 1739 struct dvb_diseqc_master_cmd *diseqc_cmd) 1740 { 1741 struct m88ds3103_dev *dev = fe->demodulator_priv; 1742 struct i2c_client *client = dev->client; 1743 int ret; 1744 unsigned int utmp; 1745 unsigned long timeout; 1746 1747 dev_dbg(&client->dev, "msg=%*ph\n", 1748 diseqc_cmd->msg_len, diseqc_cmd->msg); 1749 1750 if (!dev->warm) { 1751 ret = -EAGAIN; 1752 goto err; 1753 } 1754 1755 if (diseqc_cmd->msg_len < 3 || diseqc_cmd->msg_len > 6) { 1756 ret = -EINVAL; 1757 goto err; 1758 } 1759 1760 utmp = dev->cfg->envelope_mode << 5; 1761 ret = m88ds3103_update_bits(dev, 0xa2, 0xe0, utmp); 1762 if (ret) 1763 goto err; 1764 1765 ret = regmap_bulk_write(dev->regmap, 0xa3, diseqc_cmd->msg, 1766 diseqc_cmd->msg_len); 1767 if (ret) 1768 goto err; 1769 1770 ret = regmap_write(dev->regmap, 0xa1, 1771 (diseqc_cmd->msg_len - 1) << 3 | 0x07); 1772 if (ret) 1773 goto err; 1774 1775 /* wait DiSEqC TX ready */ 1776 #define SEND_MASTER_CMD_TIMEOUT 120 1777 timeout = jiffies + msecs_to_jiffies(SEND_MASTER_CMD_TIMEOUT); 1778 1779 /* DiSEqC message period is 13.5 ms per byte */ 1780 utmp = diseqc_cmd->msg_len * 13500; 1781 usleep_range(utmp - 4000, utmp); 1782 1783 for (utmp = 1; !time_after(jiffies, timeout) && utmp;) { 1784 ret = regmap_read(dev->regmap, 0xa1, &utmp); 1785 if (ret) 1786 goto err; 1787 utmp = (utmp >> 6) & 0x1; 1788 } 1789 1790 if (utmp == 0) { 1791 dev_dbg(&client->dev, "diseqc tx took %u ms\n", 1792 jiffies_to_msecs(jiffies) - 1793 (jiffies_to_msecs(timeout) - SEND_MASTER_CMD_TIMEOUT)); 1794 } else { 1795 dev_dbg(&client->dev, "diseqc tx timeout\n"); 1796 1797 ret = m88ds3103_update_bits(dev, 0xa1, 0xc0, 0x40); 1798 if (ret) 1799 goto err; 1800 } 1801 1802 ret = m88ds3103_update_bits(dev, 0xa2, 0xc0, 0x80); 1803 if (ret) 1804 goto err; 1805 1806 if (utmp == 1) { 1807 ret = -ETIMEDOUT; 1808 goto err; 1809 } 1810 1811 return 0; 1812 err: 1813 dev_dbg(&client->dev, "failed=%d\n", ret); 1814 1815 return ret; 1816 } 1817 1818 static int m88ds3103_diseqc_send_burst(struct dvb_frontend *fe, 1819 enum fe_sec_mini_cmd fe_sec_mini_cmd) 1820 { 1821 struct m88ds3103_dev *dev = fe->demodulator_priv; 1822 struct i2c_client *client = dev->client; 1823 int ret; 1824 unsigned int utmp, burst; 1825 unsigned long timeout; 1826 1827 dev_dbg(&client->dev, "fe_sec_mini_cmd=%d\n", fe_sec_mini_cmd); 1828 1829 if (!dev->warm) { 1830 ret = -EAGAIN; 1831 goto err; 1832 } 1833 1834 utmp = dev->cfg->envelope_mode << 5; 1835 ret = m88ds3103_update_bits(dev, 0xa2, 0xe0, utmp); 1836 if (ret) 1837 goto err; 1838 1839 switch (fe_sec_mini_cmd) { 1840 case SEC_MINI_A: 1841 burst = 0x02; 1842 break; 1843 case SEC_MINI_B: 1844 burst = 0x01; 1845 break; 1846 default: 1847 dev_dbg(&client->dev, "invalid fe_sec_mini_cmd\n"); 1848 ret = -EINVAL; 1849 goto err; 1850 } 1851 1852 ret = regmap_write(dev->regmap, 0xa1, burst); 1853 if (ret) 1854 goto err; 1855 1856 /* wait DiSEqC TX ready */ 1857 #define SEND_BURST_TIMEOUT 40 1858 timeout = jiffies + msecs_to_jiffies(SEND_BURST_TIMEOUT); 1859 1860 /* DiSEqC ToneBurst period is 12.5 ms */ 1861 usleep_range(8500, 12500); 1862 1863 for (utmp = 1; !time_after(jiffies, timeout) && utmp;) { 1864 ret = regmap_read(dev->regmap, 0xa1, &utmp); 1865 if (ret) 1866 goto err; 1867 utmp = (utmp >> 6) & 0x1; 1868 } 1869 1870 if (utmp == 0) { 1871 dev_dbg(&client->dev, "diseqc tx took %u ms\n", 1872 jiffies_to_msecs(jiffies) - 1873 (jiffies_to_msecs(timeout) - SEND_BURST_TIMEOUT)); 1874 } else { 1875 dev_dbg(&client->dev, "diseqc tx timeout\n"); 1876 1877 ret = m88ds3103_update_bits(dev, 0xa1, 0xc0, 0x40); 1878 if (ret) 1879 goto err; 1880 } 1881 1882 ret = m88ds3103_update_bits(dev, 0xa2, 0xc0, 0x80); 1883 if (ret) 1884 goto err; 1885 1886 if (utmp == 1) { 1887 ret = -ETIMEDOUT; 1888 goto err; 1889 } 1890 1891 return 0; 1892 err: 1893 dev_dbg(&client->dev, "failed=%d\n", ret); 1894 1895 return ret; 1896 } 1897 1898 static int m88ds3103_get_tune_settings(struct dvb_frontend *fe, 1899 struct dvb_frontend_tune_settings *s) 1900 { 1901 s->min_delay_ms = 3000; 1902 1903 return 0; 1904 } 1905 1906 static void m88ds3103_release(struct dvb_frontend *fe) 1907 { 1908 struct m88ds3103_dev *dev = fe->demodulator_priv; 1909 struct i2c_client *client = dev->client; 1910 1911 i2c_unregister_device(client); 1912 } 1913 1914 static int m88ds3103_select(struct i2c_mux_core *muxc, u32 chan) 1915 { 1916 struct m88ds3103_dev *dev = i2c_mux_priv(muxc); 1917 struct i2c_client *client = dev->client; 1918 int ret; 1919 struct i2c_msg msg = { 1920 .addr = client->addr, 1921 .flags = 0, 1922 .len = 2, 1923 .buf = "\x03\x11", 1924 }; 1925 1926 /* Open tuner I2C repeater for 1 xfer, closes automatically */ 1927 ret = __i2c_transfer(client->adapter, &msg, 1); 1928 if (ret != 1) { 1929 dev_warn(&client->dev, "i2c wr failed=%d\n", ret); 1930 if (ret >= 0) 1931 ret = -EREMOTEIO; 1932 return ret; 1933 } 1934 1935 return 0; 1936 } 1937 1938 /* 1939 * XXX: That is wrapper to m88ds3103_probe() via driver core in order to provide 1940 * proper I2C client for legacy media attach binding. 1941 * New users must use I2C client binding directly! 1942 */ 1943 struct dvb_frontend *m88ds3103_attach(const struct m88ds3103_config *cfg, 1944 struct i2c_adapter *i2c, 1945 struct i2c_adapter **tuner_i2c_adapter) 1946 { 1947 struct i2c_client *client; 1948 struct i2c_board_info board_info; 1949 struct m88ds3103_platform_data pdata = {}; 1950 1951 pdata.clk = cfg->clock; 1952 pdata.i2c_wr_max = cfg->i2c_wr_max; 1953 pdata.ts_mode = cfg->ts_mode; 1954 pdata.ts_clk = cfg->ts_clk; 1955 pdata.ts_clk_pol = cfg->ts_clk_pol; 1956 pdata.spec_inv = cfg->spec_inv; 1957 pdata.agc = cfg->agc; 1958 pdata.agc_inv = cfg->agc_inv; 1959 pdata.clk_out = cfg->clock_out; 1960 pdata.envelope_mode = cfg->envelope_mode; 1961 pdata.lnb_hv_pol = cfg->lnb_hv_pol; 1962 pdata.lnb_en_pol = cfg->lnb_en_pol; 1963 pdata.attach_in_use = true; 1964 1965 memset(&board_info, 0, sizeof(board_info)); 1966 strscpy(board_info.type, "m88ds3103", I2C_NAME_SIZE); 1967 board_info.addr = cfg->i2c_addr; 1968 board_info.platform_data = &pdata; 1969 client = i2c_new_client_device(i2c, &board_info); 1970 if (!i2c_client_has_driver(client)) 1971 return NULL; 1972 1973 *tuner_i2c_adapter = pdata.get_i2c_adapter(client); 1974 return pdata.get_dvb_frontend(client); 1975 } 1976 EXPORT_SYMBOL_GPL(m88ds3103_attach); 1977 1978 static const struct dvb_frontend_ops m88ds3103_ops = { 1979 .delsys = {SYS_DVBS, SYS_DVBS2}, 1980 .info = { 1981 .name = "Montage Technology M88DS3103", 1982 .frequency_min_hz = 950 * MHz, 1983 .frequency_max_hz = 2150 * MHz, 1984 .frequency_tolerance_hz = 5 * MHz, 1985 .symbol_rate_min = 1000000, 1986 .symbol_rate_max = 45000000, 1987 .caps = FE_CAN_INVERSION_AUTO | 1988 FE_CAN_FEC_1_2 | 1989 FE_CAN_FEC_2_3 | 1990 FE_CAN_FEC_3_4 | 1991 FE_CAN_FEC_4_5 | 1992 FE_CAN_FEC_5_6 | 1993 FE_CAN_FEC_6_7 | 1994 FE_CAN_FEC_7_8 | 1995 FE_CAN_FEC_8_9 | 1996 FE_CAN_FEC_AUTO | 1997 FE_CAN_QPSK | 1998 FE_CAN_RECOVER | 1999 FE_CAN_2G_MODULATION 2000 }, 2001 2002 .release = m88ds3103_release, 2003 2004 .get_tune_settings = m88ds3103_get_tune_settings, 2005 2006 .init = m88ds3103_init, 2007 .sleep = m88ds3103_sleep, 2008 2009 .set_frontend = m88ds3103_set_frontend, 2010 .get_frontend = m88ds3103_get_frontend, 2011 2012 .read_status = m88ds3103_read_status, 2013 .read_snr = m88ds3103_read_snr, 2014 .read_ber = m88ds3103_read_ber, 2015 2016 .diseqc_send_master_cmd = m88ds3103_diseqc_send_master_cmd, 2017 .diseqc_send_burst = m88ds3103_diseqc_send_burst, 2018 2019 .set_tone = m88ds3103_set_tone, 2020 .set_voltage = m88ds3103_set_voltage, 2021 }; 2022 2023 static struct dvb_frontend *m88ds3103_get_dvb_frontend(struct i2c_client *client) 2024 { 2025 struct m88ds3103_dev *dev = i2c_get_clientdata(client); 2026 2027 dev_dbg(&client->dev, "\n"); 2028 2029 return &dev->fe; 2030 } 2031 2032 static struct i2c_adapter *m88ds3103_get_i2c_adapter(struct i2c_client *client) 2033 { 2034 struct m88ds3103_dev *dev = i2c_get_clientdata(client); 2035 2036 dev_dbg(&client->dev, "\n"); 2037 2038 return dev->muxc->adapter[0]; 2039 } 2040 2041 static int m88ds3103_probe(struct i2c_client *client) 2042 { 2043 const struct i2c_device_id *id = i2c_client_get_device_id(client); 2044 struct m88ds3103_dev *dev; 2045 struct m88ds3103_platform_data *pdata = client->dev.platform_data; 2046 int ret; 2047 unsigned int utmp; 2048 2049 dev = kzalloc_obj(*dev); 2050 if (!dev) { 2051 ret = -ENOMEM; 2052 goto err; 2053 } 2054 2055 dev->client = client; 2056 dev->config.clock = pdata->clk; 2057 dev->config.i2c_wr_max = pdata->i2c_wr_max; 2058 dev->config.ts_mode = pdata->ts_mode; 2059 dev->config.ts_clk = pdata->ts_clk * 1000; 2060 dev->config.ts_clk_pol = pdata->ts_clk_pol; 2061 dev->config.spec_inv = pdata->spec_inv; 2062 dev->config.agc_inv = pdata->agc_inv; 2063 dev->config.clock_out = pdata->clk_out; 2064 dev->config.envelope_mode = pdata->envelope_mode; 2065 dev->config.agc = pdata->agc; 2066 dev->config.lnb_hv_pol = pdata->lnb_hv_pol; 2067 dev->config.lnb_en_pol = pdata->lnb_en_pol; 2068 dev->cfg = &dev->config; 2069 /* create regmap */ 2070 dev->regmap_config.reg_bits = 8; 2071 dev->regmap_config.val_bits = 8; 2072 dev->regmap_config.lock_arg = dev; 2073 dev->regmap = devm_regmap_init_i2c(client, &dev->regmap_config); 2074 if (IS_ERR(dev->regmap)) { 2075 ret = PTR_ERR(dev->regmap); 2076 goto err_kfree; 2077 } 2078 2079 /* 0x00: chip id[6:0], 0x01: chip ver[7:0], 0x02: chip ver[15:8] */ 2080 ret = regmap_read(dev->regmap, 0x00, &utmp); 2081 if (ret) 2082 goto err_kfree; 2083 2084 dev->chip_id = utmp >> 1; 2085 dev->chiptype = (u8)id->driver_data; 2086 2087 dev_dbg(&client->dev, "chip_id=%02x\n", dev->chip_id); 2088 2089 switch (dev->chip_id) { 2090 case M88RS6000_CHIP_ID: 2091 case M88DS3103_CHIP_ID: 2092 case M88DS3103C_CHIP_ID: 2093 break; 2094 default: 2095 ret = -ENODEV; 2096 dev_err(&client->dev, "Unknown device. Chip_id=%02x\n", dev->chip_id); 2097 goto err_kfree; 2098 } 2099 2100 switch (dev->cfg->clock_out) { 2101 case M88DS3103_CLOCK_OUT_DISABLED: 2102 utmp = 0x80; 2103 break; 2104 case M88DS3103_CLOCK_OUT_ENABLED: 2105 utmp = 0x00; 2106 break; 2107 case M88DS3103_CLOCK_OUT_ENABLED_DIV2: 2108 utmp = 0x10; 2109 break; 2110 default: 2111 ret = -EINVAL; 2112 goto err_kfree; 2113 } 2114 2115 if (!pdata->ts_clk) { 2116 ret = -EINVAL; 2117 goto err_kfree; 2118 } 2119 2120 /* 0x29 register is defined differently for m88rs6000. */ 2121 /* set internal tuner address to 0x21 */ 2122 if (dev->chip_id == M88RS6000_CHIP_ID || 2123 dev->chip_id == M88DS3103C_CHIP_ID) 2124 utmp = 0x00; 2125 2126 ret = regmap_write(dev->regmap, 0x29, utmp); 2127 if (ret) 2128 goto err_kfree; 2129 2130 /* sleep */ 2131 ret = m88ds3103_update_bits(dev, 0x08, 0x01, 0x00); 2132 if (ret) 2133 goto err_kfree; 2134 ret = m88ds3103_update_bits(dev, 0x04, 0x01, 0x01); 2135 if (ret) 2136 goto err_kfree; 2137 ret = m88ds3103_update_bits(dev, 0x23, 0x10, 0x10); 2138 if (ret) 2139 goto err_kfree; 2140 2141 /* create mux i2c adapter for tuner */ 2142 dev->muxc = i2c_mux_alloc(client->adapter, &client->dev, 1, 0, 0, 2143 m88ds3103_select, NULL); 2144 if (!dev->muxc) { 2145 ret = -ENOMEM; 2146 goto err_kfree; 2147 } 2148 dev->muxc->priv = dev; 2149 ret = i2c_mux_add_adapter(dev->muxc, 0, 0); 2150 if (ret) 2151 goto err_kfree; 2152 2153 /* create dvb_frontend */ 2154 memcpy(&dev->fe.ops, &m88ds3103_ops, sizeof(struct dvb_frontend_ops)); 2155 if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) 2156 strscpy(dev->fe.ops.info.name, "Montage Technology M88DS3103B", 2157 sizeof(dev->fe.ops.info.name)); 2158 if (dev->chiptype == M88DS3103_CHIPTYPE_3103C) 2159 strscpy(dev->fe.ops.info.name, "Montage Technology M88DS3103C", 2160 sizeof(dev->fe.ops.info.name)); 2161 else if (dev->chip_id == M88RS6000_CHIP_ID) 2162 strscpy(dev->fe.ops.info.name, "Montage Technology M88RS6000", 2163 sizeof(dev->fe.ops.info.name)); 2164 if (!pdata->attach_in_use) 2165 dev->fe.ops.release = NULL; 2166 dev->fe.demodulator_priv = dev; 2167 i2c_set_clientdata(client, dev); 2168 2169 /* setup callbacks */ 2170 pdata->get_dvb_frontend = m88ds3103_get_dvb_frontend; 2171 pdata->get_i2c_adapter = m88ds3103_get_i2c_adapter; 2172 2173 if (dev->chiptype == M88DS3103_CHIPTYPE_3103B || 2174 dev->chiptype == M88DS3103_CHIPTYPE_3103C) { 2175 /* enable i2c repeater for tuner */ 2176 if (dev->chip_id == M88DS3103C_CHIP_ID) 2177 m88ds3103_update_bits(dev, 0x04, 0x10, 0x10); 2178 else 2179 m88ds3103_update_bits(dev, 0x11, 0x01, 0x01); 2180 2181 /* get frontend address */ 2182 ret = regmap_read(dev->regmap, 0x29, &utmp); 2183 if (ret) 2184 goto err_del_adapters; 2185 2186 dev->dt_addr = ((utmp & 0x80) == 0) ? 0x42 >> 1 : 0x40 >> 1; 2187 if (dev->chiptype == M88DS3103_CHIPTYPE_3103C) 2188 dev->dt_addr = 0x5c >> 1; 2189 dev_dbg(&client->dev, "dt addr is 0x%02x\n", dev->dt_addr); 2190 2191 dev->dt_client = i2c_new_dummy_device(client->adapter, 2192 dev->dt_addr); 2193 if (IS_ERR(dev->dt_client)) { 2194 ret = PTR_ERR(dev->dt_client); 2195 goto err_del_adapters; 2196 } 2197 } 2198 2199 return 0; 2200 2201 err_del_adapters: 2202 i2c_mux_del_adapters(dev->muxc); 2203 err_kfree: 2204 kfree(dev); 2205 err: 2206 dev_dbg(&client->dev, "failed=%d\n", ret); 2207 return ret; 2208 } 2209 2210 static void m88ds3103_remove(struct i2c_client *client) 2211 { 2212 struct m88ds3103_dev *dev = i2c_get_clientdata(client); 2213 2214 dev_dbg(&client->dev, "\n"); 2215 2216 i2c_unregister_device(dev->dt_client); 2217 2218 i2c_mux_del_adapters(dev->muxc); 2219 2220 kfree(dev); 2221 } 2222 2223 static const struct i2c_device_id m88ds3103_id_table[] = { 2224 {"m88ds3103", M88DS3103_CHIPTYPE_3103}, 2225 {"m88rs6000", M88DS3103_CHIPTYPE_RS6000}, 2226 {"m88ds3103b", M88DS3103_CHIPTYPE_3103B}, 2227 {"m88ds3103c", M88DS3103_CHIPTYPE_3103C}, 2228 {} 2229 }; 2230 MODULE_DEVICE_TABLE(i2c, m88ds3103_id_table); 2231 2232 static struct i2c_driver m88ds3103_driver = { 2233 .driver = { 2234 .name = "m88ds3103", 2235 .suppress_bind_attrs = true, 2236 }, 2237 .probe = m88ds3103_probe, 2238 .remove = m88ds3103_remove, 2239 .id_table = m88ds3103_id_table, 2240 }; 2241 2242 module_i2c_driver(m88ds3103_driver); 2243 2244 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>"); 2245 MODULE_DESCRIPTION("Montage Technology M88DS3103 DVB-S/S2 demodulator driver"); 2246 MODULE_LICENSE("GPL"); 2247 MODULE_FIRMWARE(M88DS3103_FIRMWARE); 2248 MODULE_FIRMWARE(M88RS6000_FIRMWARE); 2249 MODULE_FIRMWARE(M88DS3103B_FIRMWARE); 2250