1 /* 2 Montage Technology DS3000 - DVBS/S2 Demodulator driver 3 Copyright (C) 2009-2012 Konstantin Dimitrov <kosio.dimitrov@gmail.com> 4 5 Copyright (C) 2009-2012 TurboSight.com 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program; if not, write to the Free Software 19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 */ 21 22 #include <linux/slab.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/moduleparam.h> 26 #include <linux/init.h> 27 #include <linux/firmware.h> 28 29 #include "dvb_frontend.h" 30 #include "ds3000.h" 31 32 static int debug; 33 34 #define dprintk(args...) \ 35 do { \ 36 if (debug) \ 37 printk(args); \ 38 } while (0) 39 40 /* as of March 2009 current DS3000 firmware version is 1.78 */ 41 /* DS3000 FW v1.78 MD5: a32d17910c4f370073f9346e71d34b80 */ 42 #define DS3000_DEFAULT_FIRMWARE "dvb-fe-ds3000.fw" 43 44 #define DS3000_SAMPLE_RATE 96000 /* in kHz */ 45 46 /* Register values to initialise the demod in DVB-S mode */ 47 static u8 ds3000_dvbs_init_tab[] = { 48 0x23, 0x05, 49 0x08, 0x03, 50 0x0c, 0x00, 51 0x21, 0x54, 52 0x25, 0x82, 53 0x27, 0x31, 54 0x30, 0x08, 55 0x31, 0x40, 56 0x32, 0x32, 57 0x33, 0x35, 58 0x35, 0xff, 59 0x3a, 0x00, 60 0x37, 0x10, 61 0x38, 0x10, 62 0x39, 0x02, 63 0x42, 0x60, 64 0x4a, 0x40, 65 0x4b, 0x04, 66 0x4d, 0x91, 67 0x5d, 0xc8, 68 0x50, 0x77, 69 0x51, 0x77, 70 0x52, 0x36, 71 0x53, 0x36, 72 0x56, 0x01, 73 0x63, 0x43, 74 0x64, 0x30, 75 0x65, 0x40, 76 0x68, 0x26, 77 0x69, 0x4c, 78 0x70, 0x20, 79 0x71, 0x70, 80 0x72, 0x04, 81 0x73, 0x00, 82 0x70, 0x40, 83 0x71, 0x70, 84 0x72, 0x04, 85 0x73, 0x00, 86 0x70, 0x60, 87 0x71, 0x70, 88 0x72, 0x04, 89 0x73, 0x00, 90 0x70, 0x80, 91 0x71, 0x70, 92 0x72, 0x04, 93 0x73, 0x00, 94 0x70, 0xa0, 95 0x71, 0x70, 96 0x72, 0x04, 97 0x73, 0x00, 98 0x70, 0x1f, 99 0x76, 0x00, 100 0x77, 0xd1, 101 0x78, 0x0c, 102 0x79, 0x80, 103 0x7f, 0x04, 104 0x7c, 0x00, 105 0x80, 0x86, 106 0x81, 0xa6, 107 0x85, 0x04, 108 0xcd, 0xf4, 109 0x90, 0x33, 110 0xa0, 0x44, 111 0xc0, 0x18, 112 0xc3, 0x10, 113 0xc4, 0x08, 114 0xc5, 0x80, 115 0xc6, 0x80, 116 0xc7, 0x0a, 117 0xc8, 0x1a, 118 0xc9, 0x80, 119 0xfe, 0x92, 120 0xe0, 0xf8, 121 0xe6, 0x8b, 122 0xd0, 0x40, 123 0xf8, 0x20, 124 0xfa, 0x0f, 125 0xfd, 0x20, 126 0xad, 0x20, 127 0xae, 0x07, 128 0xb8, 0x00, 129 }; 130 131 /* Register values to initialise the demod in DVB-S2 mode */ 132 static u8 ds3000_dvbs2_init_tab[] = { 133 0x23, 0x0f, 134 0x08, 0x07, 135 0x0c, 0x00, 136 0x21, 0x54, 137 0x25, 0x82, 138 0x27, 0x31, 139 0x30, 0x08, 140 0x31, 0x32, 141 0x32, 0x32, 142 0x33, 0x35, 143 0x35, 0xff, 144 0x3a, 0x00, 145 0x37, 0x10, 146 0x38, 0x10, 147 0x39, 0x02, 148 0x42, 0x60, 149 0x4a, 0x80, 150 0x4b, 0x04, 151 0x4d, 0x81, 152 0x5d, 0x88, 153 0x50, 0x36, 154 0x51, 0x36, 155 0x52, 0x36, 156 0x53, 0x36, 157 0x63, 0x60, 158 0x64, 0x10, 159 0x65, 0x10, 160 0x68, 0x04, 161 0x69, 0x29, 162 0x70, 0x20, 163 0x71, 0x70, 164 0x72, 0x04, 165 0x73, 0x00, 166 0x70, 0x40, 167 0x71, 0x70, 168 0x72, 0x04, 169 0x73, 0x00, 170 0x70, 0x60, 171 0x71, 0x70, 172 0x72, 0x04, 173 0x73, 0x00, 174 0x70, 0x80, 175 0x71, 0x70, 176 0x72, 0x04, 177 0x73, 0x00, 178 0x70, 0xa0, 179 0x71, 0x70, 180 0x72, 0x04, 181 0x73, 0x00, 182 0x70, 0x1f, 183 0xa0, 0x44, 184 0xc0, 0x08, 185 0xc1, 0x10, 186 0xc2, 0x08, 187 0xc3, 0x10, 188 0xc4, 0x08, 189 0xc5, 0xf0, 190 0xc6, 0xf0, 191 0xc7, 0x0a, 192 0xc8, 0x1a, 193 0xc9, 0x80, 194 0xca, 0x23, 195 0xcb, 0x24, 196 0xce, 0x74, 197 0x90, 0x03, 198 0x76, 0x80, 199 0x77, 0x42, 200 0x78, 0x0a, 201 0x79, 0x80, 202 0xad, 0x40, 203 0xae, 0x07, 204 0x7f, 0xd4, 205 0x7c, 0x00, 206 0x80, 0xa8, 207 0x81, 0xda, 208 0x7c, 0x01, 209 0x80, 0xda, 210 0x81, 0xec, 211 0x7c, 0x02, 212 0x80, 0xca, 213 0x81, 0xeb, 214 0x7c, 0x03, 215 0x80, 0xba, 216 0x81, 0xdb, 217 0x85, 0x08, 218 0x86, 0x00, 219 0x87, 0x02, 220 0x89, 0x80, 221 0x8b, 0x44, 222 0x8c, 0xaa, 223 0x8a, 0x10, 224 0xba, 0x00, 225 0xf5, 0x04, 226 0xfe, 0x44, 227 0xd2, 0x32, 228 0xb8, 0x00, 229 }; 230 231 struct ds3000_state { 232 struct i2c_adapter *i2c; 233 const struct ds3000_config *config; 234 struct dvb_frontend frontend; 235 /* previous uncorrected block counter for DVB-S2 */ 236 u16 prevUCBS2; 237 }; 238 239 static int ds3000_writereg(struct ds3000_state *state, int reg, int data) 240 { 241 u8 buf[] = { reg, data }; 242 struct i2c_msg msg = { .addr = state->config->demod_address, 243 .flags = 0, .buf = buf, .len = 2 }; 244 int err; 245 246 dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data); 247 248 err = i2c_transfer(state->i2c, &msg, 1); 249 if (err != 1) { 250 printk(KERN_ERR "%s: writereg error(err == %i, reg == 0x%02x," 251 " value == 0x%02x)\n", __func__, err, reg, data); 252 return -EREMOTEIO; 253 } 254 255 return 0; 256 } 257 258 static int ds3000_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) 259 { 260 struct ds3000_state *state = fe->demodulator_priv; 261 262 if (enable) 263 ds3000_writereg(state, 0x03, 0x12); 264 else 265 ds3000_writereg(state, 0x03, 0x02); 266 267 return 0; 268 } 269 270 /* I2C write for 8k firmware load */ 271 static int ds3000_writeFW(struct ds3000_state *state, int reg, 272 const u8 *data, u16 len) 273 { 274 int i, ret = -EREMOTEIO; 275 struct i2c_msg msg; 276 u8 *buf; 277 278 buf = kmalloc(33, GFP_KERNEL); 279 if (buf == NULL) { 280 printk(KERN_ERR "Unable to kmalloc\n"); 281 ret = -ENOMEM; 282 goto error; 283 } 284 285 *(buf) = reg; 286 287 msg.addr = state->config->demod_address; 288 msg.flags = 0; 289 msg.buf = buf; 290 msg.len = 33; 291 292 for (i = 0; i < len; i += 32) { 293 memcpy(buf + 1, data + i, 32); 294 295 dprintk("%s: write reg 0x%02x, len = %d\n", __func__, reg, len); 296 297 ret = i2c_transfer(state->i2c, &msg, 1); 298 if (ret != 1) { 299 printk(KERN_ERR "%s: write error(err == %i, " 300 "reg == 0x%02x\n", __func__, ret, reg); 301 ret = -EREMOTEIO; 302 } 303 } 304 305 error: 306 kfree(buf); 307 308 return ret; 309 } 310 311 static int ds3000_readreg(struct ds3000_state *state, u8 reg) 312 { 313 int ret; 314 u8 b0[] = { reg }; 315 u8 b1[] = { 0 }; 316 struct i2c_msg msg[] = { 317 { 318 .addr = state->config->demod_address, 319 .flags = 0, 320 .buf = b0, 321 .len = 1 322 }, { 323 .addr = state->config->demod_address, 324 .flags = I2C_M_RD, 325 .buf = b1, 326 .len = 1 327 } 328 }; 329 330 ret = i2c_transfer(state->i2c, msg, 2); 331 332 if (ret != 2) { 333 printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret); 334 return ret; 335 } 336 337 dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]); 338 339 return b1[0]; 340 } 341 342 static int ds3000_load_firmware(struct dvb_frontend *fe, 343 const struct firmware *fw); 344 345 static int ds3000_firmware_ondemand(struct dvb_frontend *fe) 346 { 347 struct ds3000_state *state = fe->demodulator_priv; 348 const struct firmware *fw; 349 int ret = 0; 350 351 dprintk("%s()\n", __func__); 352 353 ret = ds3000_readreg(state, 0xb2); 354 if (ret < 0) 355 return ret; 356 357 /* Load firmware */ 358 /* request the firmware, this will block until someone uploads it */ 359 printk(KERN_INFO "%s: Waiting for firmware upload (%s)...\n", __func__, 360 DS3000_DEFAULT_FIRMWARE); 361 ret = request_firmware(&fw, DS3000_DEFAULT_FIRMWARE, 362 state->i2c->dev.parent); 363 printk(KERN_INFO "%s: Waiting for firmware upload(2)...\n", __func__); 364 if (ret) { 365 printk(KERN_ERR "%s: No firmware uploaded (timeout or file not " 366 "found?)\n", __func__); 367 return ret; 368 } 369 370 ret = ds3000_load_firmware(fe, fw); 371 if (ret) 372 printk("%s: Writing firmware to device failed\n", __func__); 373 374 release_firmware(fw); 375 376 dprintk("%s: Firmware upload %s\n", __func__, 377 ret == 0 ? "complete" : "failed"); 378 379 return ret; 380 } 381 382 static int ds3000_load_firmware(struct dvb_frontend *fe, 383 const struct firmware *fw) 384 { 385 struct ds3000_state *state = fe->demodulator_priv; 386 387 dprintk("%s\n", __func__); 388 dprintk("Firmware is %zu bytes (%02x %02x .. %02x %02x)\n", 389 fw->size, 390 fw->data[0], 391 fw->data[1], 392 fw->data[fw->size - 2], 393 fw->data[fw->size - 1]); 394 395 /* Begin the firmware load process */ 396 ds3000_writereg(state, 0xb2, 0x01); 397 /* write the entire firmware */ 398 ds3000_writeFW(state, 0xb0, fw->data, fw->size); 399 ds3000_writereg(state, 0xb2, 0x00); 400 401 return 0; 402 } 403 404 static int ds3000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage) 405 { 406 struct ds3000_state *state = fe->demodulator_priv; 407 u8 data; 408 409 dprintk("%s(%d)\n", __func__, voltage); 410 411 data = ds3000_readreg(state, 0xa2); 412 data |= 0x03; /* bit0 V/H, bit1 off/on */ 413 414 switch (voltage) { 415 case SEC_VOLTAGE_18: 416 data &= ~0x03; 417 break; 418 case SEC_VOLTAGE_13: 419 data &= ~0x03; 420 data |= 0x01; 421 break; 422 case SEC_VOLTAGE_OFF: 423 break; 424 } 425 426 ds3000_writereg(state, 0xa2, data); 427 428 return 0; 429 } 430 431 static int ds3000_read_status(struct dvb_frontend *fe, fe_status_t* status) 432 { 433 struct ds3000_state *state = fe->demodulator_priv; 434 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 435 int lock; 436 437 *status = 0; 438 439 switch (c->delivery_system) { 440 case SYS_DVBS: 441 lock = ds3000_readreg(state, 0xd1); 442 if ((lock & 0x07) == 0x07) 443 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | 444 FE_HAS_VITERBI | FE_HAS_SYNC | 445 FE_HAS_LOCK; 446 447 break; 448 case SYS_DVBS2: 449 lock = ds3000_readreg(state, 0x0d); 450 if ((lock & 0x8f) == 0x8f) 451 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | 452 FE_HAS_VITERBI | FE_HAS_SYNC | 453 FE_HAS_LOCK; 454 455 break; 456 default: 457 return 1; 458 } 459 460 dprintk("%s: status = 0x%02x\n", __func__, lock); 461 462 return 0; 463 } 464 465 /* read DS3000 BER value */ 466 static int ds3000_read_ber(struct dvb_frontend *fe, u32* ber) 467 { 468 struct ds3000_state *state = fe->demodulator_priv; 469 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 470 u8 data; 471 u32 ber_reading, lpdc_frames; 472 473 dprintk("%s()\n", __func__); 474 475 switch (c->delivery_system) { 476 case SYS_DVBS: 477 /* set the number of bytes checked during 478 BER estimation */ 479 ds3000_writereg(state, 0xf9, 0x04); 480 /* read BER estimation status */ 481 data = ds3000_readreg(state, 0xf8); 482 /* check if BER estimation is ready */ 483 if ((data & 0x10) == 0) { 484 /* this is the number of error bits, 485 to calculate the bit error rate 486 divide to 8388608 */ 487 *ber = (ds3000_readreg(state, 0xf7) << 8) | 488 ds3000_readreg(state, 0xf6); 489 /* start counting error bits */ 490 /* need to be set twice 491 otherwise it fails sometimes */ 492 data |= 0x10; 493 ds3000_writereg(state, 0xf8, data); 494 ds3000_writereg(state, 0xf8, data); 495 } else 496 /* used to indicate that BER estimation 497 is not ready, i.e. BER is unknown */ 498 *ber = 0xffffffff; 499 break; 500 case SYS_DVBS2: 501 /* read the number of LPDC decoded frames */ 502 lpdc_frames = (ds3000_readreg(state, 0xd7) << 16) | 503 (ds3000_readreg(state, 0xd6) << 8) | 504 ds3000_readreg(state, 0xd5); 505 /* read the number of packets with bad CRC */ 506 ber_reading = (ds3000_readreg(state, 0xf8) << 8) | 507 ds3000_readreg(state, 0xf7); 508 if (lpdc_frames > 750) { 509 /* clear LPDC frame counters */ 510 ds3000_writereg(state, 0xd1, 0x01); 511 /* clear bad packets counter */ 512 ds3000_writereg(state, 0xf9, 0x01); 513 /* enable bad packets counter */ 514 ds3000_writereg(state, 0xf9, 0x00); 515 /* enable LPDC frame counters */ 516 ds3000_writereg(state, 0xd1, 0x00); 517 *ber = ber_reading; 518 } else 519 /* used to indicate that BER estimation is not ready, 520 i.e. BER is unknown */ 521 *ber = 0xffffffff; 522 break; 523 default: 524 return 1; 525 } 526 527 return 0; 528 } 529 530 /* calculate DS3000 snr value in dB */ 531 static int ds3000_read_snr(struct dvb_frontend *fe, u16 *snr) 532 { 533 struct ds3000_state *state = fe->demodulator_priv; 534 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 535 u8 snr_reading, snr_value; 536 u32 dvbs2_signal_reading, dvbs2_noise_reading, tmp; 537 static const u16 dvbs_snr_tab[] = { /* 20 x Table (rounded up) */ 538 0x0000, 0x1b13, 0x2aea, 0x3627, 0x3ede, 0x45fe, 0x4c03, 539 0x513a, 0x55d4, 0x59f2, 0x5dab, 0x6111, 0x6431, 0x6717, 540 0x69c9, 0x6c4e, 0x6eac, 0x70e8, 0x7304, 0x7505 541 }; 542 static const u16 dvbs2_snr_tab[] = { /* 80 x Table (rounded up) */ 543 0x0000, 0x0bc2, 0x12a3, 0x1785, 0x1b4e, 0x1e65, 0x2103, 544 0x2347, 0x2546, 0x2710, 0x28ae, 0x2a28, 0x2b83, 0x2cc5, 545 0x2df1, 0x2f09, 0x3010, 0x3109, 0x31f4, 0x32d2, 0x33a6, 546 0x3470, 0x3531, 0x35ea, 0x369b, 0x3746, 0x37ea, 0x3888, 547 0x3920, 0x39b3, 0x3a42, 0x3acc, 0x3b51, 0x3bd3, 0x3c51, 548 0x3ccb, 0x3d42, 0x3db6, 0x3e27, 0x3e95, 0x3f00, 0x3f68, 549 0x3fcf, 0x4033, 0x4094, 0x40f4, 0x4151, 0x41ac, 0x4206, 550 0x425e, 0x42b4, 0x4308, 0x435b, 0x43ac, 0x43fc, 0x444a, 551 0x4497, 0x44e2, 0x452d, 0x4576, 0x45bd, 0x4604, 0x4649, 552 0x468e, 0x46d1, 0x4713, 0x4755, 0x4795, 0x47d4, 0x4813, 553 0x4851, 0x488d, 0x48c9, 0x4904, 0x493f, 0x4978, 0x49b1, 554 0x49e9, 0x4a20, 0x4a57 555 }; 556 557 dprintk("%s()\n", __func__); 558 559 switch (c->delivery_system) { 560 case SYS_DVBS: 561 snr_reading = ds3000_readreg(state, 0xff); 562 snr_reading /= 8; 563 if (snr_reading == 0) 564 *snr = 0x0000; 565 else { 566 if (snr_reading > 20) 567 snr_reading = 20; 568 snr_value = dvbs_snr_tab[snr_reading - 1] * 10 / 23026; 569 /* cook the value to be suitable for szap-s2 570 human readable output */ 571 *snr = snr_value * 8 * 655; 572 } 573 dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__, 574 snr_reading, *snr); 575 break; 576 case SYS_DVBS2: 577 dvbs2_noise_reading = (ds3000_readreg(state, 0x8c) & 0x3f) + 578 (ds3000_readreg(state, 0x8d) << 4); 579 dvbs2_signal_reading = ds3000_readreg(state, 0x8e); 580 tmp = dvbs2_signal_reading * dvbs2_signal_reading >> 1; 581 if (tmp == 0) { 582 *snr = 0x0000; 583 return 0; 584 } 585 if (dvbs2_noise_reading == 0) { 586 snr_value = 0x0013; 587 /* cook the value to be suitable for szap-s2 588 human readable output */ 589 *snr = 0xffff; 590 return 0; 591 } 592 if (tmp > dvbs2_noise_reading) { 593 snr_reading = tmp / dvbs2_noise_reading; 594 if (snr_reading > 80) 595 snr_reading = 80; 596 snr_value = dvbs2_snr_tab[snr_reading - 1] / 1000; 597 /* cook the value to be suitable for szap-s2 598 human readable output */ 599 *snr = snr_value * 5 * 655; 600 } else { 601 snr_reading = dvbs2_noise_reading / tmp; 602 if (snr_reading > 80) 603 snr_reading = 80; 604 *snr = -(dvbs2_snr_tab[snr_reading] / 1000); 605 } 606 dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__, 607 snr_reading, *snr); 608 break; 609 default: 610 return 1; 611 } 612 613 return 0; 614 } 615 616 /* read DS3000 uncorrected blocks */ 617 static int ds3000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 618 { 619 struct ds3000_state *state = fe->demodulator_priv; 620 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 621 u8 data; 622 u16 _ucblocks; 623 624 dprintk("%s()\n", __func__); 625 626 switch (c->delivery_system) { 627 case SYS_DVBS: 628 *ucblocks = (ds3000_readreg(state, 0xf5) << 8) | 629 ds3000_readreg(state, 0xf4); 630 data = ds3000_readreg(state, 0xf8); 631 /* clear packet counters */ 632 data &= ~0x20; 633 ds3000_writereg(state, 0xf8, data); 634 /* enable packet counters */ 635 data |= 0x20; 636 ds3000_writereg(state, 0xf8, data); 637 break; 638 case SYS_DVBS2: 639 _ucblocks = (ds3000_readreg(state, 0xe2) << 8) | 640 ds3000_readreg(state, 0xe1); 641 if (_ucblocks > state->prevUCBS2) 642 *ucblocks = _ucblocks - state->prevUCBS2; 643 else 644 *ucblocks = state->prevUCBS2 - _ucblocks; 645 state->prevUCBS2 = _ucblocks; 646 break; 647 default: 648 return 1; 649 } 650 651 return 0; 652 } 653 654 static int ds3000_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone) 655 { 656 struct ds3000_state *state = fe->demodulator_priv; 657 u8 data; 658 659 dprintk("%s(%d)\n", __func__, tone); 660 if ((tone != SEC_TONE_ON) && (tone != SEC_TONE_OFF)) { 661 printk(KERN_ERR "%s: Invalid, tone=%d\n", __func__, tone); 662 return -EINVAL; 663 } 664 665 data = ds3000_readreg(state, 0xa2); 666 data &= ~0xc0; 667 ds3000_writereg(state, 0xa2, data); 668 669 switch (tone) { 670 case SEC_TONE_ON: 671 dprintk("%s: setting tone on\n", __func__); 672 data = ds3000_readreg(state, 0xa1); 673 data &= ~0x43; 674 data |= 0x04; 675 ds3000_writereg(state, 0xa1, data); 676 break; 677 case SEC_TONE_OFF: 678 dprintk("%s: setting tone off\n", __func__); 679 data = ds3000_readreg(state, 0xa2); 680 data |= 0x80; 681 ds3000_writereg(state, 0xa2, data); 682 break; 683 } 684 685 return 0; 686 } 687 688 static int ds3000_send_diseqc_msg(struct dvb_frontend *fe, 689 struct dvb_diseqc_master_cmd *d) 690 { 691 struct ds3000_state *state = fe->demodulator_priv; 692 int i; 693 u8 data; 694 695 /* Dump DiSEqC message */ 696 dprintk("%s(", __func__); 697 for (i = 0 ; i < d->msg_len;) { 698 dprintk("0x%02x", d->msg[i]); 699 if (++i < d->msg_len) 700 dprintk(", "); 701 } 702 703 /* enable DiSEqC message send pin */ 704 data = ds3000_readreg(state, 0xa2); 705 data &= ~0xc0; 706 ds3000_writereg(state, 0xa2, data); 707 708 /* DiSEqC message */ 709 for (i = 0; i < d->msg_len; i++) 710 ds3000_writereg(state, 0xa3 + i, d->msg[i]); 711 712 data = ds3000_readreg(state, 0xa1); 713 /* clear DiSEqC message length and status, 714 enable DiSEqC message send */ 715 data &= ~0xf8; 716 /* set DiSEqC mode, modulation active during 33 pulses, 717 set DiSEqC message length */ 718 data |= ((d->msg_len - 1) << 3) | 0x07; 719 ds3000_writereg(state, 0xa1, data); 720 721 /* wait up to 150ms for DiSEqC transmission to complete */ 722 for (i = 0; i < 15; i++) { 723 data = ds3000_readreg(state, 0xa1); 724 if ((data & 0x40) == 0) 725 break; 726 msleep(10); 727 } 728 729 /* DiSEqC timeout after 150ms */ 730 if (i == 15) { 731 data = ds3000_readreg(state, 0xa1); 732 data &= ~0x80; 733 data |= 0x40; 734 ds3000_writereg(state, 0xa1, data); 735 736 data = ds3000_readreg(state, 0xa2); 737 data &= ~0xc0; 738 data |= 0x80; 739 ds3000_writereg(state, 0xa2, data); 740 741 return 1; 742 } 743 744 data = ds3000_readreg(state, 0xa2); 745 data &= ~0xc0; 746 data |= 0x80; 747 ds3000_writereg(state, 0xa2, data); 748 749 return 0; 750 } 751 752 /* Send DiSEqC burst */ 753 static int ds3000_diseqc_send_burst(struct dvb_frontend *fe, 754 fe_sec_mini_cmd_t burst) 755 { 756 struct ds3000_state *state = fe->demodulator_priv; 757 int i; 758 u8 data; 759 760 dprintk("%s()\n", __func__); 761 762 data = ds3000_readreg(state, 0xa2); 763 data &= ~0xc0; 764 ds3000_writereg(state, 0xa2, data); 765 766 /* DiSEqC burst */ 767 if (burst == SEC_MINI_A) 768 /* Unmodulated tone burst */ 769 ds3000_writereg(state, 0xa1, 0x02); 770 else if (burst == SEC_MINI_B) 771 /* Modulated tone burst */ 772 ds3000_writereg(state, 0xa1, 0x01); 773 else 774 return -EINVAL; 775 776 msleep(13); 777 for (i = 0; i < 5; i++) { 778 data = ds3000_readreg(state, 0xa1); 779 if ((data & 0x40) == 0) 780 break; 781 msleep(1); 782 } 783 784 if (i == 5) { 785 data = ds3000_readreg(state, 0xa1); 786 data &= ~0x80; 787 data |= 0x40; 788 ds3000_writereg(state, 0xa1, data); 789 790 data = ds3000_readreg(state, 0xa2); 791 data &= ~0xc0; 792 data |= 0x80; 793 ds3000_writereg(state, 0xa2, data); 794 795 return 1; 796 } 797 798 data = ds3000_readreg(state, 0xa2); 799 data &= ~0xc0; 800 data |= 0x80; 801 ds3000_writereg(state, 0xa2, data); 802 803 return 0; 804 } 805 806 static void ds3000_release(struct dvb_frontend *fe) 807 { 808 struct ds3000_state *state = fe->demodulator_priv; 809 dprintk("%s\n", __func__); 810 kfree(state); 811 } 812 813 static struct dvb_frontend_ops ds3000_ops; 814 815 struct dvb_frontend *ds3000_attach(const struct ds3000_config *config, 816 struct i2c_adapter *i2c) 817 { 818 struct ds3000_state *state = NULL; 819 int ret; 820 821 dprintk("%s\n", __func__); 822 823 /* allocate memory for the internal state */ 824 state = kzalloc(sizeof(struct ds3000_state), GFP_KERNEL); 825 if (state == NULL) { 826 printk(KERN_ERR "Unable to kmalloc\n"); 827 goto error2; 828 } 829 830 state->config = config; 831 state->i2c = i2c; 832 state->prevUCBS2 = 0; 833 834 /* check if the demod is present */ 835 ret = ds3000_readreg(state, 0x00) & 0xfe; 836 if (ret != 0xe0) { 837 printk(KERN_ERR "Invalid probe, probably not a DS3000\n"); 838 goto error3; 839 } 840 841 printk(KERN_INFO "DS3000 chip version: %d.%d attached.\n", 842 ds3000_readreg(state, 0x02), 843 ds3000_readreg(state, 0x01)); 844 845 memcpy(&state->frontend.ops, &ds3000_ops, 846 sizeof(struct dvb_frontend_ops)); 847 state->frontend.demodulator_priv = state; 848 return &state->frontend; 849 850 error3: 851 kfree(state); 852 error2: 853 return NULL; 854 } 855 EXPORT_SYMBOL(ds3000_attach); 856 857 static int ds3000_set_carrier_offset(struct dvb_frontend *fe, 858 s32 carrier_offset_khz) 859 { 860 struct ds3000_state *state = fe->demodulator_priv; 861 s32 tmp; 862 863 tmp = carrier_offset_khz; 864 tmp *= 65536; 865 tmp = (2 * tmp + DS3000_SAMPLE_RATE) / (2 * DS3000_SAMPLE_RATE); 866 867 if (tmp < 0) 868 tmp += 65536; 869 870 ds3000_writereg(state, 0x5f, tmp >> 8); 871 ds3000_writereg(state, 0x5e, tmp & 0xff); 872 873 return 0; 874 } 875 876 static int ds3000_set_frontend(struct dvb_frontend *fe) 877 { 878 struct ds3000_state *state = fe->demodulator_priv; 879 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 880 881 int i; 882 fe_status_t status; 883 s32 offset_khz; 884 u32 frequency; 885 u16 value; 886 887 dprintk("%s() ", __func__); 888 889 if (state->config->set_ts_params) 890 state->config->set_ts_params(fe, 0); 891 /* Tune */ 892 if (fe->ops.tuner_ops.set_params) 893 fe->ops.tuner_ops.set_params(fe); 894 895 /* ds3000 global reset */ 896 ds3000_writereg(state, 0x07, 0x80); 897 ds3000_writereg(state, 0x07, 0x00); 898 /* ds3000 build-in uC reset */ 899 ds3000_writereg(state, 0xb2, 0x01); 900 /* ds3000 software reset */ 901 ds3000_writereg(state, 0x00, 0x01); 902 903 switch (c->delivery_system) { 904 case SYS_DVBS: 905 /* initialise the demod in DVB-S mode */ 906 for (i = 0; i < sizeof(ds3000_dvbs_init_tab); i += 2) 907 ds3000_writereg(state, 908 ds3000_dvbs_init_tab[i], 909 ds3000_dvbs_init_tab[i + 1]); 910 value = ds3000_readreg(state, 0xfe); 911 value &= 0xc0; 912 value |= 0x1b; 913 ds3000_writereg(state, 0xfe, value); 914 break; 915 case SYS_DVBS2: 916 /* initialise the demod in DVB-S2 mode */ 917 for (i = 0; i < sizeof(ds3000_dvbs2_init_tab); i += 2) 918 ds3000_writereg(state, 919 ds3000_dvbs2_init_tab[i], 920 ds3000_dvbs2_init_tab[i + 1]); 921 if (c->symbol_rate >= 30000000) 922 ds3000_writereg(state, 0xfe, 0x54); 923 else 924 ds3000_writereg(state, 0xfe, 0x98); 925 break; 926 default: 927 return 1; 928 } 929 930 /* enable 27MHz clock output */ 931 ds3000_writereg(state, 0x29, 0x80); 932 /* enable ac coupling */ 933 ds3000_writereg(state, 0x25, 0x8a); 934 935 /* enhance symbol rate performance */ 936 if ((c->symbol_rate / 1000) <= 5000) { 937 value = 29777 / (c->symbol_rate / 1000) + 1; 938 if (value % 2 != 0) 939 value++; 940 ds3000_writereg(state, 0xc3, 0x0d); 941 ds3000_writereg(state, 0xc8, value); 942 ds3000_writereg(state, 0xc4, 0x10); 943 ds3000_writereg(state, 0xc7, 0x0e); 944 } else if ((c->symbol_rate / 1000) <= 10000) { 945 value = 92166 / (c->symbol_rate / 1000) + 1; 946 if (value % 2 != 0) 947 value++; 948 ds3000_writereg(state, 0xc3, 0x07); 949 ds3000_writereg(state, 0xc8, value); 950 ds3000_writereg(state, 0xc4, 0x09); 951 ds3000_writereg(state, 0xc7, 0x12); 952 } else if ((c->symbol_rate / 1000) <= 20000) { 953 value = 64516 / (c->symbol_rate / 1000) + 1; 954 ds3000_writereg(state, 0xc3, value); 955 ds3000_writereg(state, 0xc8, 0x0e); 956 ds3000_writereg(state, 0xc4, 0x07); 957 ds3000_writereg(state, 0xc7, 0x18); 958 } else { 959 value = 129032 / (c->symbol_rate / 1000) + 1; 960 ds3000_writereg(state, 0xc3, value); 961 ds3000_writereg(state, 0xc8, 0x0a); 962 ds3000_writereg(state, 0xc4, 0x05); 963 ds3000_writereg(state, 0xc7, 0x24); 964 } 965 966 /* normalized symbol rate rounded to the closest integer */ 967 value = (((c->symbol_rate / 1000) << 16) + 968 (DS3000_SAMPLE_RATE / 2)) / DS3000_SAMPLE_RATE; 969 ds3000_writereg(state, 0x61, value & 0x00ff); 970 ds3000_writereg(state, 0x62, (value & 0xff00) >> 8); 971 972 /* co-channel interference cancellation disabled */ 973 ds3000_writereg(state, 0x56, 0x00); 974 975 /* equalizer disabled */ 976 ds3000_writereg(state, 0x76, 0x00); 977 978 /*ds3000_writereg(state, 0x08, 0x03); 979 ds3000_writereg(state, 0xfd, 0x22); 980 ds3000_writereg(state, 0x08, 0x07); 981 ds3000_writereg(state, 0xfd, 0x42); 982 ds3000_writereg(state, 0x08, 0x07);*/ 983 984 if (state->config->ci_mode) { 985 switch (c->delivery_system) { 986 case SYS_DVBS: 987 default: 988 ds3000_writereg(state, 0xfd, 0x80); 989 break; 990 case SYS_DVBS2: 991 ds3000_writereg(state, 0xfd, 0x01); 992 break; 993 } 994 } 995 996 /* ds3000 out of software reset */ 997 ds3000_writereg(state, 0x00, 0x00); 998 /* start ds3000 build-in uC */ 999 ds3000_writereg(state, 0xb2, 0x00); 1000 1001 if (fe->ops.tuner_ops.get_frequency) { 1002 fe->ops.tuner_ops.get_frequency(fe, &frequency); 1003 offset_khz = frequency - c->frequency; 1004 ds3000_set_carrier_offset(fe, offset_khz); 1005 } 1006 1007 for (i = 0; i < 30 ; i++) { 1008 ds3000_read_status(fe, &status); 1009 if (status & FE_HAS_LOCK) 1010 break; 1011 1012 msleep(10); 1013 } 1014 1015 return 0; 1016 } 1017 1018 static int ds3000_tune(struct dvb_frontend *fe, 1019 bool re_tune, 1020 unsigned int mode_flags, 1021 unsigned int *delay, 1022 fe_status_t *status) 1023 { 1024 if (re_tune) { 1025 int ret = ds3000_set_frontend(fe); 1026 if (ret) 1027 return ret; 1028 } 1029 1030 *delay = HZ / 5; 1031 1032 return ds3000_read_status(fe, status); 1033 } 1034 1035 static enum dvbfe_algo ds3000_get_algo(struct dvb_frontend *fe) 1036 { 1037 dprintk("%s()\n", __func__); 1038 return DVBFE_ALGO_HW; 1039 } 1040 1041 /* 1042 * Initialise or wake up device 1043 * 1044 * Power config will reset and load initial firmware if required 1045 */ 1046 static int ds3000_initfe(struct dvb_frontend *fe) 1047 { 1048 struct ds3000_state *state = fe->demodulator_priv; 1049 int ret; 1050 1051 dprintk("%s()\n", __func__); 1052 /* hard reset */ 1053 ds3000_writereg(state, 0x08, 0x01 | ds3000_readreg(state, 0x08)); 1054 msleep(1); 1055 1056 /* Load the firmware if required */ 1057 ret = ds3000_firmware_ondemand(fe); 1058 if (ret != 0) { 1059 printk(KERN_ERR "%s: Unable initialize firmware\n", __func__); 1060 return ret; 1061 } 1062 1063 return 0; 1064 } 1065 1066 static struct dvb_frontend_ops ds3000_ops = { 1067 .delsys = { SYS_DVBS, SYS_DVBS2 }, 1068 .info = { 1069 .name = "Montage Technology DS3000", 1070 .frequency_min = 950000, 1071 .frequency_max = 2150000, 1072 .frequency_stepsize = 1011, /* kHz for QPSK frontends */ 1073 .frequency_tolerance = 5000, 1074 .symbol_rate_min = 1000000, 1075 .symbol_rate_max = 45000000, 1076 .caps = FE_CAN_INVERSION_AUTO | 1077 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 1078 FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 | 1079 FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 1080 FE_CAN_2G_MODULATION | 1081 FE_CAN_QPSK | FE_CAN_RECOVER 1082 }, 1083 1084 .release = ds3000_release, 1085 1086 .init = ds3000_initfe, 1087 .i2c_gate_ctrl = ds3000_i2c_gate_ctrl, 1088 .read_status = ds3000_read_status, 1089 .read_ber = ds3000_read_ber, 1090 .read_snr = ds3000_read_snr, 1091 .read_ucblocks = ds3000_read_ucblocks, 1092 .set_voltage = ds3000_set_voltage, 1093 .set_tone = ds3000_set_tone, 1094 .diseqc_send_master_cmd = ds3000_send_diseqc_msg, 1095 .diseqc_send_burst = ds3000_diseqc_send_burst, 1096 .get_frontend_algo = ds3000_get_algo, 1097 1098 .set_frontend = ds3000_set_frontend, 1099 .tune = ds3000_tune, 1100 }; 1101 1102 module_param(debug, int, 0644); 1103 MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)"); 1104 1105 MODULE_DESCRIPTION("DVB Frontend module for Montage Technology " 1106 "DS3000 hardware"); 1107 MODULE_AUTHOR("Konstantin Dimitrov <kosio.dimitrov@gmail.com>"); 1108 MODULE_LICENSE("GPL"); 1109 MODULE_FIRMWARE(DS3000_DEFAULT_FIRMWARE); 1110