1 /* 2 Montage Technology DS3000 - DVBS/S2 Demodulator driver 3 Copyright (C) 2009-2012 Konstantin Dimitrov <kosio.dimitrov@gmail.com> 4 5 Copyright (C) 2009-2012 TurboSight.com 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program; if not, write to the Free Software 19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 */ 21 22 #include <linux/slab.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/moduleparam.h> 26 #include <linux/init.h> 27 #include <linux/firmware.h> 28 29 #include "dvb_frontend.h" 30 #include "ts2020.h" 31 #include "ds3000.h" 32 33 static int debug; 34 35 #define dprintk(args...) \ 36 do { \ 37 if (debug) \ 38 printk(args); \ 39 } while (0) 40 41 /* as of March 2009 current DS3000 firmware version is 1.78 */ 42 /* DS3000 FW v1.78 MD5: a32d17910c4f370073f9346e71d34b80 */ 43 #define DS3000_DEFAULT_FIRMWARE "dvb-fe-ds3000.fw" 44 45 #define DS3000_SAMPLE_RATE 96000 /* in kHz */ 46 47 /* Register values to initialise the demod in DVB-S mode */ 48 static u8 ds3000_dvbs_init_tab[] = { 49 0x23, 0x05, 50 0x08, 0x03, 51 0x0c, 0x00, 52 0x21, 0x54, 53 0x25, 0x82, 54 0x27, 0x31, 55 0x30, 0x08, 56 0x31, 0x40, 57 0x32, 0x32, 58 0x33, 0x35, 59 0x35, 0xff, 60 0x3a, 0x00, 61 0x37, 0x10, 62 0x38, 0x10, 63 0x39, 0x02, 64 0x42, 0x60, 65 0x4a, 0x40, 66 0x4b, 0x04, 67 0x4d, 0x91, 68 0x5d, 0xc8, 69 0x50, 0x77, 70 0x51, 0x77, 71 0x52, 0x36, 72 0x53, 0x36, 73 0x56, 0x01, 74 0x63, 0x43, 75 0x64, 0x30, 76 0x65, 0x40, 77 0x68, 0x26, 78 0x69, 0x4c, 79 0x70, 0x20, 80 0x71, 0x70, 81 0x72, 0x04, 82 0x73, 0x00, 83 0x70, 0x40, 84 0x71, 0x70, 85 0x72, 0x04, 86 0x73, 0x00, 87 0x70, 0x60, 88 0x71, 0x70, 89 0x72, 0x04, 90 0x73, 0x00, 91 0x70, 0x80, 92 0x71, 0x70, 93 0x72, 0x04, 94 0x73, 0x00, 95 0x70, 0xa0, 96 0x71, 0x70, 97 0x72, 0x04, 98 0x73, 0x00, 99 0x70, 0x1f, 100 0x76, 0x00, 101 0x77, 0xd1, 102 0x78, 0x0c, 103 0x79, 0x80, 104 0x7f, 0x04, 105 0x7c, 0x00, 106 0x80, 0x86, 107 0x81, 0xa6, 108 0x85, 0x04, 109 0xcd, 0xf4, 110 0x90, 0x33, 111 0xa0, 0x44, 112 0xc0, 0x18, 113 0xc3, 0x10, 114 0xc4, 0x08, 115 0xc5, 0x80, 116 0xc6, 0x80, 117 0xc7, 0x0a, 118 0xc8, 0x1a, 119 0xc9, 0x80, 120 0xfe, 0x92, 121 0xe0, 0xf8, 122 0xe6, 0x8b, 123 0xd0, 0x40, 124 0xf8, 0x20, 125 0xfa, 0x0f, 126 0xfd, 0x20, 127 0xad, 0x20, 128 0xae, 0x07, 129 0xb8, 0x00, 130 }; 131 132 /* Register values to initialise the demod in DVB-S2 mode */ 133 static u8 ds3000_dvbs2_init_tab[] = { 134 0x23, 0x0f, 135 0x08, 0x07, 136 0x0c, 0x00, 137 0x21, 0x54, 138 0x25, 0x82, 139 0x27, 0x31, 140 0x30, 0x08, 141 0x31, 0x32, 142 0x32, 0x32, 143 0x33, 0x35, 144 0x35, 0xff, 145 0x3a, 0x00, 146 0x37, 0x10, 147 0x38, 0x10, 148 0x39, 0x02, 149 0x42, 0x60, 150 0x4a, 0x80, 151 0x4b, 0x04, 152 0x4d, 0x81, 153 0x5d, 0x88, 154 0x50, 0x36, 155 0x51, 0x36, 156 0x52, 0x36, 157 0x53, 0x36, 158 0x63, 0x60, 159 0x64, 0x10, 160 0x65, 0x10, 161 0x68, 0x04, 162 0x69, 0x29, 163 0x70, 0x20, 164 0x71, 0x70, 165 0x72, 0x04, 166 0x73, 0x00, 167 0x70, 0x40, 168 0x71, 0x70, 169 0x72, 0x04, 170 0x73, 0x00, 171 0x70, 0x60, 172 0x71, 0x70, 173 0x72, 0x04, 174 0x73, 0x00, 175 0x70, 0x80, 176 0x71, 0x70, 177 0x72, 0x04, 178 0x73, 0x00, 179 0x70, 0xa0, 180 0x71, 0x70, 181 0x72, 0x04, 182 0x73, 0x00, 183 0x70, 0x1f, 184 0xa0, 0x44, 185 0xc0, 0x08, 186 0xc1, 0x10, 187 0xc2, 0x08, 188 0xc3, 0x10, 189 0xc4, 0x08, 190 0xc5, 0xf0, 191 0xc6, 0xf0, 192 0xc7, 0x0a, 193 0xc8, 0x1a, 194 0xc9, 0x80, 195 0xca, 0x23, 196 0xcb, 0x24, 197 0xce, 0x74, 198 0x90, 0x03, 199 0x76, 0x80, 200 0x77, 0x42, 201 0x78, 0x0a, 202 0x79, 0x80, 203 0xad, 0x40, 204 0xae, 0x07, 205 0x7f, 0xd4, 206 0x7c, 0x00, 207 0x80, 0xa8, 208 0x81, 0xda, 209 0x7c, 0x01, 210 0x80, 0xda, 211 0x81, 0xec, 212 0x7c, 0x02, 213 0x80, 0xca, 214 0x81, 0xeb, 215 0x7c, 0x03, 216 0x80, 0xba, 217 0x81, 0xdb, 218 0x85, 0x08, 219 0x86, 0x00, 220 0x87, 0x02, 221 0x89, 0x80, 222 0x8b, 0x44, 223 0x8c, 0xaa, 224 0x8a, 0x10, 225 0xba, 0x00, 226 0xf5, 0x04, 227 0xfe, 0x44, 228 0xd2, 0x32, 229 0xb8, 0x00, 230 }; 231 232 struct ds3000_state { 233 struct i2c_adapter *i2c; 234 const struct ds3000_config *config; 235 struct dvb_frontend frontend; 236 /* previous uncorrected block counter for DVB-S2 */ 237 u16 prevUCBS2; 238 }; 239 240 static int ds3000_writereg(struct ds3000_state *state, int reg, int data) 241 { 242 u8 buf[] = { reg, data }; 243 struct i2c_msg msg = { .addr = state->config->demod_address, 244 .flags = 0, .buf = buf, .len = 2 }; 245 int err; 246 247 dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data); 248 249 err = i2c_transfer(state->i2c, &msg, 1); 250 if (err != 1) { 251 printk(KERN_ERR "%s: writereg error(err == %i, reg == 0x%02x," 252 " value == 0x%02x)\n", __func__, err, reg, data); 253 return -EREMOTEIO; 254 } 255 256 return 0; 257 } 258 259 static int ds3000_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) 260 { 261 struct ds3000_state *state = fe->demodulator_priv; 262 263 if (enable) 264 ds3000_writereg(state, 0x03, 0x12); 265 else 266 ds3000_writereg(state, 0x03, 0x02); 267 268 return 0; 269 } 270 271 /* I2C write for 8k firmware load */ 272 static int ds3000_writeFW(struct ds3000_state *state, int reg, 273 const u8 *data, u16 len) 274 { 275 int i, ret = -EREMOTEIO; 276 struct i2c_msg msg; 277 u8 *buf; 278 279 buf = kmalloc(33, GFP_KERNEL); 280 if (buf == NULL) { 281 printk(KERN_ERR "Unable to kmalloc\n"); 282 ret = -ENOMEM; 283 goto error; 284 } 285 286 *(buf) = reg; 287 288 msg.addr = state->config->demod_address; 289 msg.flags = 0; 290 msg.buf = buf; 291 msg.len = 33; 292 293 for (i = 0; i < len; i += 32) { 294 memcpy(buf + 1, data + i, 32); 295 296 dprintk("%s: write reg 0x%02x, len = %d\n", __func__, reg, len); 297 298 ret = i2c_transfer(state->i2c, &msg, 1); 299 if (ret != 1) { 300 printk(KERN_ERR "%s: write error(err == %i, " 301 "reg == 0x%02x\n", __func__, ret, reg); 302 ret = -EREMOTEIO; 303 } 304 } 305 306 error: 307 kfree(buf); 308 309 return ret; 310 } 311 312 static int ds3000_readreg(struct ds3000_state *state, u8 reg) 313 { 314 int ret; 315 u8 b0[] = { reg }; 316 u8 b1[] = { 0 }; 317 struct i2c_msg msg[] = { 318 { 319 .addr = state->config->demod_address, 320 .flags = 0, 321 .buf = b0, 322 .len = 1 323 }, { 324 .addr = state->config->demod_address, 325 .flags = I2C_M_RD, 326 .buf = b1, 327 .len = 1 328 } 329 }; 330 331 ret = i2c_transfer(state->i2c, msg, 2); 332 333 if (ret != 2) { 334 printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret); 335 return ret; 336 } 337 338 dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]); 339 340 return b1[0]; 341 } 342 343 static int ds3000_load_firmware(struct dvb_frontend *fe, 344 const struct firmware *fw); 345 346 static int ds3000_firmware_ondemand(struct dvb_frontend *fe) 347 { 348 struct ds3000_state *state = fe->demodulator_priv; 349 const struct firmware *fw; 350 int ret = 0; 351 352 dprintk("%s()\n", __func__); 353 354 ret = ds3000_readreg(state, 0xb2); 355 if (ret < 0) 356 return ret; 357 358 /* Load firmware */ 359 /* request the firmware, this will block until someone uploads it */ 360 printk(KERN_INFO "%s: Waiting for firmware upload (%s)...\n", __func__, 361 DS3000_DEFAULT_FIRMWARE); 362 ret = request_firmware(&fw, DS3000_DEFAULT_FIRMWARE, 363 state->i2c->dev.parent); 364 printk(KERN_INFO "%s: Waiting for firmware upload(2)...\n", __func__); 365 if (ret) { 366 printk(KERN_ERR "%s: No firmware uploaded (timeout or file not " 367 "found?)\n", __func__); 368 return ret; 369 } 370 371 ret = ds3000_load_firmware(fe, fw); 372 if (ret) 373 printk("%s: Writing firmware to device failed\n", __func__); 374 375 release_firmware(fw); 376 377 dprintk("%s: Firmware upload %s\n", __func__, 378 ret == 0 ? "complete" : "failed"); 379 380 return ret; 381 } 382 383 static int ds3000_load_firmware(struct dvb_frontend *fe, 384 const struct firmware *fw) 385 { 386 struct ds3000_state *state = fe->demodulator_priv; 387 388 dprintk("%s\n", __func__); 389 dprintk("Firmware is %zu bytes (%02x %02x .. %02x %02x)\n", 390 fw->size, 391 fw->data[0], 392 fw->data[1], 393 fw->data[fw->size - 2], 394 fw->data[fw->size - 1]); 395 396 /* Begin the firmware load process */ 397 ds3000_writereg(state, 0xb2, 0x01); 398 /* write the entire firmware */ 399 ds3000_writeFW(state, 0xb0, fw->data, fw->size); 400 ds3000_writereg(state, 0xb2, 0x00); 401 402 return 0; 403 } 404 405 static int ds3000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage) 406 { 407 struct ds3000_state *state = fe->demodulator_priv; 408 u8 data; 409 410 dprintk("%s(%d)\n", __func__, voltage); 411 412 data = ds3000_readreg(state, 0xa2); 413 data |= 0x03; /* bit0 V/H, bit1 off/on */ 414 415 switch (voltage) { 416 case SEC_VOLTAGE_18: 417 data &= ~0x03; 418 break; 419 case SEC_VOLTAGE_13: 420 data &= ~0x03; 421 data |= 0x01; 422 break; 423 case SEC_VOLTAGE_OFF: 424 break; 425 } 426 427 ds3000_writereg(state, 0xa2, data); 428 429 return 0; 430 } 431 432 static int ds3000_read_status(struct dvb_frontend *fe, fe_status_t* status) 433 { 434 struct ds3000_state *state = fe->demodulator_priv; 435 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 436 int lock; 437 438 *status = 0; 439 440 switch (c->delivery_system) { 441 case SYS_DVBS: 442 lock = ds3000_readreg(state, 0xd1); 443 if ((lock & 0x07) == 0x07) 444 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | 445 FE_HAS_VITERBI | FE_HAS_SYNC | 446 FE_HAS_LOCK; 447 448 break; 449 case SYS_DVBS2: 450 lock = ds3000_readreg(state, 0x0d); 451 if ((lock & 0x8f) == 0x8f) 452 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | 453 FE_HAS_VITERBI | FE_HAS_SYNC | 454 FE_HAS_LOCK; 455 456 break; 457 default: 458 return 1; 459 } 460 461 dprintk("%s: status = 0x%02x\n", __func__, lock); 462 463 return 0; 464 } 465 466 /* read DS3000 BER value */ 467 static int ds3000_read_ber(struct dvb_frontend *fe, u32* ber) 468 { 469 struct ds3000_state *state = fe->demodulator_priv; 470 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 471 u8 data; 472 u32 ber_reading, lpdc_frames; 473 474 dprintk("%s()\n", __func__); 475 476 switch (c->delivery_system) { 477 case SYS_DVBS: 478 /* set the number of bytes checked during 479 BER estimation */ 480 ds3000_writereg(state, 0xf9, 0x04); 481 /* read BER estimation status */ 482 data = ds3000_readreg(state, 0xf8); 483 /* check if BER estimation is ready */ 484 if ((data & 0x10) == 0) { 485 /* this is the number of error bits, 486 to calculate the bit error rate 487 divide to 8388608 */ 488 *ber = (ds3000_readreg(state, 0xf7) << 8) | 489 ds3000_readreg(state, 0xf6); 490 /* start counting error bits */ 491 /* need to be set twice 492 otherwise it fails sometimes */ 493 data |= 0x10; 494 ds3000_writereg(state, 0xf8, data); 495 ds3000_writereg(state, 0xf8, data); 496 } else 497 /* used to indicate that BER estimation 498 is not ready, i.e. BER is unknown */ 499 *ber = 0xffffffff; 500 break; 501 case SYS_DVBS2: 502 /* read the number of LPDC decoded frames */ 503 lpdc_frames = (ds3000_readreg(state, 0xd7) << 16) | 504 (ds3000_readreg(state, 0xd6) << 8) | 505 ds3000_readreg(state, 0xd5); 506 /* read the number of packets with bad CRC */ 507 ber_reading = (ds3000_readreg(state, 0xf8) << 8) | 508 ds3000_readreg(state, 0xf7); 509 if (lpdc_frames > 750) { 510 /* clear LPDC frame counters */ 511 ds3000_writereg(state, 0xd1, 0x01); 512 /* clear bad packets counter */ 513 ds3000_writereg(state, 0xf9, 0x01); 514 /* enable bad packets counter */ 515 ds3000_writereg(state, 0xf9, 0x00); 516 /* enable LPDC frame counters */ 517 ds3000_writereg(state, 0xd1, 0x00); 518 *ber = ber_reading; 519 } else 520 /* used to indicate that BER estimation is not ready, 521 i.e. BER is unknown */ 522 *ber = 0xffffffff; 523 break; 524 default: 525 return 1; 526 } 527 528 return 0; 529 } 530 531 /* calculate DS3000 snr value in dB */ 532 static int ds3000_read_snr(struct dvb_frontend *fe, u16 *snr) 533 { 534 struct ds3000_state *state = fe->demodulator_priv; 535 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 536 u8 snr_reading, snr_value; 537 u32 dvbs2_signal_reading, dvbs2_noise_reading, tmp; 538 static const u16 dvbs_snr_tab[] = { /* 20 x Table (rounded up) */ 539 0x0000, 0x1b13, 0x2aea, 0x3627, 0x3ede, 0x45fe, 0x4c03, 540 0x513a, 0x55d4, 0x59f2, 0x5dab, 0x6111, 0x6431, 0x6717, 541 0x69c9, 0x6c4e, 0x6eac, 0x70e8, 0x7304, 0x7505 542 }; 543 static const u16 dvbs2_snr_tab[] = { /* 80 x Table (rounded up) */ 544 0x0000, 0x0bc2, 0x12a3, 0x1785, 0x1b4e, 0x1e65, 0x2103, 545 0x2347, 0x2546, 0x2710, 0x28ae, 0x2a28, 0x2b83, 0x2cc5, 546 0x2df1, 0x2f09, 0x3010, 0x3109, 0x31f4, 0x32d2, 0x33a6, 547 0x3470, 0x3531, 0x35ea, 0x369b, 0x3746, 0x37ea, 0x3888, 548 0x3920, 0x39b3, 0x3a42, 0x3acc, 0x3b51, 0x3bd3, 0x3c51, 549 0x3ccb, 0x3d42, 0x3db6, 0x3e27, 0x3e95, 0x3f00, 0x3f68, 550 0x3fcf, 0x4033, 0x4094, 0x40f4, 0x4151, 0x41ac, 0x4206, 551 0x425e, 0x42b4, 0x4308, 0x435b, 0x43ac, 0x43fc, 0x444a, 552 0x4497, 0x44e2, 0x452d, 0x4576, 0x45bd, 0x4604, 0x4649, 553 0x468e, 0x46d1, 0x4713, 0x4755, 0x4795, 0x47d4, 0x4813, 554 0x4851, 0x488d, 0x48c9, 0x4904, 0x493f, 0x4978, 0x49b1, 555 0x49e9, 0x4a20, 0x4a57 556 }; 557 558 dprintk("%s()\n", __func__); 559 560 switch (c->delivery_system) { 561 case SYS_DVBS: 562 snr_reading = ds3000_readreg(state, 0xff); 563 snr_reading /= 8; 564 if (snr_reading == 0) 565 *snr = 0x0000; 566 else { 567 if (snr_reading > 20) 568 snr_reading = 20; 569 snr_value = dvbs_snr_tab[snr_reading - 1] * 10 / 23026; 570 /* cook the value to be suitable for szap-s2 571 human readable output */ 572 *snr = snr_value * 8 * 655; 573 } 574 dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__, 575 snr_reading, *snr); 576 break; 577 case SYS_DVBS2: 578 dvbs2_noise_reading = (ds3000_readreg(state, 0x8c) & 0x3f) + 579 (ds3000_readreg(state, 0x8d) << 4); 580 dvbs2_signal_reading = ds3000_readreg(state, 0x8e); 581 tmp = dvbs2_signal_reading * dvbs2_signal_reading >> 1; 582 if (tmp == 0) { 583 *snr = 0x0000; 584 return 0; 585 } 586 if (dvbs2_noise_reading == 0) { 587 snr_value = 0x0013; 588 /* cook the value to be suitable for szap-s2 589 human readable output */ 590 *snr = 0xffff; 591 return 0; 592 } 593 if (tmp > dvbs2_noise_reading) { 594 snr_reading = tmp / dvbs2_noise_reading; 595 if (snr_reading > 80) 596 snr_reading = 80; 597 snr_value = dvbs2_snr_tab[snr_reading - 1] / 1000; 598 /* cook the value to be suitable for szap-s2 599 human readable output */ 600 *snr = snr_value * 5 * 655; 601 } else { 602 snr_reading = dvbs2_noise_reading / tmp; 603 if (snr_reading > 80) 604 snr_reading = 80; 605 *snr = -(dvbs2_snr_tab[snr_reading] / 1000); 606 } 607 dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__, 608 snr_reading, *snr); 609 break; 610 default: 611 return 1; 612 } 613 614 return 0; 615 } 616 617 /* read DS3000 uncorrected blocks */ 618 static int ds3000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 619 { 620 struct ds3000_state *state = fe->demodulator_priv; 621 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 622 u8 data; 623 u16 _ucblocks; 624 625 dprintk("%s()\n", __func__); 626 627 switch (c->delivery_system) { 628 case SYS_DVBS: 629 *ucblocks = (ds3000_readreg(state, 0xf5) << 8) | 630 ds3000_readreg(state, 0xf4); 631 data = ds3000_readreg(state, 0xf8); 632 /* clear packet counters */ 633 data &= ~0x20; 634 ds3000_writereg(state, 0xf8, data); 635 /* enable packet counters */ 636 data |= 0x20; 637 ds3000_writereg(state, 0xf8, data); 638 break; 639 case SYS_DVBS2: 640 _ucblocks = (ds3000_readreg(state, 0xe2) << 8) | 641 ds3000_readreg(state, 0xe1); 642 if (_ucblocks > state->prevUCBS2) 643 *ucblocks = _ucblocks - state->prevUCBS2; 644 else 645 *ucblocks = state->prevUCBS2 - _ucblocks; 646 state->prevUCBS2 = _ucblocks; 647 break; 648 default: 649 return 1; 650 } 651 652 return 0; 653 } 654 655 static int ds3000_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone) 656 { 657 struct ds3000_state *state = fe->demodulator_priv; 658 u8 data; 659 660 dprintk("%s(%d)\n", __func__, tone); 661 if ((tone != SEC_TONE_ON) && (tone != SEC_TONE_OFF)) { 662 printk(KERN_ERR "%s: Invalid, tone=%d\n", __func__, tone); 663 return -EINVAL; 664 } 665 666 data = ds3000_readreg(state, 0xa2); 667 data &= ~0xc0; 668 ds3000_writereg(state, 0xa2, data); 669 670 switch (tone) { 671 case SEC_TONE_ON: 672 dprintk("%s: setting tone on\n", __func__); 673 data = ds3000_readreg(state, 0xa1); 674 data &= ~0x43; 675 data |= 0x04; 676 ds3000_writereg(state, 0xa1, data); 677 break; 678 case SEC_TONE_OFF: 679 dprintk("%s: setting tone off\n", __func__); 680 data = ds3000_readreg(state, 0xa2); 681 data |= 0x80; 682 ds3000_writereg(state, 0xa2, data); 683 break; 684 } 685 686 return 0; 687 } 688 689 static int ds3000_send_diseqc_msg(struct dvb_frontend *fe, 690 struct dvb_diseqc_master_cmd *d) 691 { 692 struct ds3000_state *state = fe->demodulator_priv; 693 int i; 694 u8 data; 695 696 /* Dump DiSEqC message */ 697 dprintk("%s(", __func__); 698 for (i = 0 ; i < d->msg_len;) { 699 dprintk("0x%02x", d->msg[i]); 700 if (++i < d->msg_len) 701 dprintk(", "); 702 } 703 704 /* enable DiSEqC message send pin */ 705 data = ds3000_readreg(state, 0xa2); 706 data &= ~0xc0; 707 ds3000_writereg(state, 0xa2, data); 708 709 /* DiSEqC message */ 710 for (i = 0; i < d->msg_len; i++) 711 ds3000_writereg(state, 0xa3 + i, d->msg[i]); 712 713 data = ds3000_readreg(state, 0xa1); 714 /* clear DiSEqC message length and status, 715 enable DiSEqC message send */ 716 data &= ~0xf8; 717 /* set DiSEqC mode, modulation active during 33 pulses, 718 set DiSEqC message length */ 719 data |= ((d->msg_len - 1) << 3) | 0x07; 720 ds3000_writereg(state, 0xa1, data); 721 722 /* wait up to 150ms for DiSEqC transmission to complete */ 723 for (i = 0; i < 15; i++) { 724 data = ds3000_readreg(state, 0xa1); 725 if ((data & 0x40) == 0) 726 break; 727 msleep(10); 728 } 729 730 /* DiSEqC timeout after 150ms */ 731 if (i == 15) { 732 data = ds3000_readreg(state, 0xa1); 733 data &= ~0x80; 734 data |= 0x40; 735 ds3000_writereg(state, 0xa1, data); 736 737 data = ds3000_readreg(state, 0xa2); 738 data &= ~0xc0; 739 data |= 0x80; 740 ds3000_writereg(state, 0xa2, data); 741 742 return 1; 743 } 744 745 data = ds3000_readreg(state, 0xa2); 746 data &= ~0xc0; 747 data |= 0x80; 748 ds3000_writereg(state, 0xa2, data); 749 750 return 0; 751 } 752 753 /* Send DiSEqC burst */ 754 static int ds3000_diseqc_send_burst(struct dvb_frontend *fe, 755 fe_sec_mini_cmd_t burst) 756 { 757 struct ds3000_state *state = fe->demodulator_priv; 758 int i; 759 u8 data; 760 761 dprintk("%s()\n", __func__); 762 763 data = ds3000_readreg(state, 0xa2); 764 data &= ~0xc0; 765 ds3000_writereg(state, 0xa2, data); 766 767 /* DiSEqC burst */ 768 if (burst == SEC_MINI_A) 769 /* Unmodulated tone burst */ 770 ds3000_writereg(state, 0xa1, 0x02); 771 else if (burst == SEC_MINI_B) 772 /* Modulated tone burst */ 773 ds3000_writereg(state, 0xa1, 0x01); 774 else 775 return -EINVAL; 776 777 msleep(13); 778 for (i = 0; i < 5; i++) { 779 data = ds3000_readreg(state, 0xa1); 780 if ((data & 0x40) == 0) 781 break; 782 msleep(1); 783 } 784 785 if (i == 5) { 786 data = ds3000_readreg(state, 0xa1); 787 data &= ~0x80; 788 data |= 0x40; 789 ds3000_writereg(state, 0xa1, data); 790 791 data = ds3000_readreg(state, 0xa2); 792 data &= ~0xc0; 793 data |= 0x80; 794 ds3000_writereg(state, 0xa2, data); 795 796 return 1; 797 } 798 799 data = ds3000_readreg(state, 0xa2); 800 data &= ~0xc0; 801 data |= 0x80; 802 ds3000_writereg(state, 0xa2, data); 803 804 return 0; 805 } 806 807 static void ds3000_release(struct dvb_frontend *fe) 808 { 809 struct ds3000_state *state = fe->demodulator_priv; 810 dprintk("%s\n", __func__); 811 kfree(state); 812 } 813 814 static struct dvb_frontend_ops ds3000_ops; 815 816 struct dvb_frontend *ds3000_attach(const struct ds3000_config *config, 817 struct i2c_adapter *i2c) 818 { 819 struct ds3000_state *state = NULL; 820 int ret; 821 822 dprintk("%s\n", __func__); 823 824 /* allocate memory for the internal state */ 825 state = kzalloc(sizeof(struct ds3000_state), GFP_KERNEL); 826 if (state == NULL) { 827 printk(KERN_ERR "Unable to kmalloc\n"); 828 goto error2; 829 } 830 831 state->config = config; 832 state->i2c = i2c; 833 state->prevUCBS2 = 0; 834 835 /* check if the demod is present */ 836 ret = ds3000_readreg(state, 0x00) & 0xfe; 837 if (ret != 0xe0) { 838 printk(KERN_ERR "Invalid probe, probably not a DS3000\n"); 839 goto error3; 840 } 841 842 printk(KERN_INFO "DS3000 chip version: %d.%d attached.\n", 843 ds3000_readreg(state, 0x02), 844 ds3000_readreg(state, 0x01)); 845 846 memcpy(&state->frontend.ops, &ds3000_ops, 847 sizeof(struct dvb_frontend_ops)); 848 state->frontend.demodulator_priv = state; 849 return &state->frontend; 850 851 error3: 852 kfree(state); 853 error2: 854 return NULL; 855 } 856 EXPORT_SYMBOL(ds3000_attach); 857 858 static int ds3000_set_carrier_offset(struct dvb_frontend *fe, 859 s32 carrier_offset_khz) 860 { 861 struct ds3000_state *state = fe->demodulator_priv; 862 s32 tmp; 863 864 tmp = carrier_offset_khz; 865 tmp *= 65536; 866 tmp = (2 * tmp + DS3000_SAMPLE_RATE) / (2 * DS3000_SAMPLE_RATE); 867 868 if (tmp < 0) 869 tmp += 65536; 870 871 ds3000_writereg(state, 0x5f, tmp >> 8); 872 ds3000_writereg(state, 0x5e, tmp & 0xff); 873 874 return 0; 875 } 876 877 static int ds3000_set_frontend(struct dvb_frontend *fe) 878 { 879 struct ds3000_state *state = fe->demodulator_priv; 880 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 881 882 int i; 883 fe_status_t status; 884 s32 offset_khz; 885 u32 frequency; 886 u16 value; 887 888 dprintk("%s() ", __func__); 889 890 if (state->config->set_ts_params) 891 state->config->set_ts_params(fe, 0); 892 /* Tune */ 893 if (fe->ops.tuner_ops.set_params) 894 fe->ops.tuner_ops.set_params(fe); 895 896 /* ds3000 global reset */ 897 ds3000_writereg(state, 0x07, 0x80); 898 ds3000_writereg(state, 0x07, 0x00); 899 /* ds3000 build-in uC reset */ 900 ds3000_writereg(state, 0xb2, 0x01); 901 /* ds3000 software reset */ 902 ds3000_writereg(state, 0x00, 0x01); 903 904 switch (c->delivery_system) { 905 case SYS_DVBS: 906 /* initialise the demod in DVB-S mode */ 907 for (i = 0; i < sizeof(ds3000_dvbs_init_tab); i += 2) 908 ds3000_writereg(state, 909 ds3000_dvbs_init_tab[i], 910 ds3000_dvbs_init_tab[i + 1]); 911 value = ds3000_readreg(state, 0xfe); 912 value &= 0xc0; 913 value |= 0x1b; 914 ds3000_writereg(state, 0xfe, value); 915 break; 916 case SYS_DVBS2: 917 /* initialise the demod in DVB-S2 mode */ 918 for (i = 0; i < sizeof(ds3000_dvbs2_init_tab); i += 2) 919 ds3000_writereg(state, 920 ds3000_dvbs2_init_tab[i], 921 ds3000_dvbs2_init_tab[i + 1]); 922 if (c->symbol_rate >= 30000000) 923 ds3000_writereg(state, 0xfe, 0x54); 924 else 925 ds3000_writereg(state, 0xfe, 0x98); 926 break; 927 default: 928 return 1; 929 } 930 931 /* enable 27MHz clock output */ 932 ds3000_writereg(state, 0x29, 0x80); 933 /* enable ac coupling */ 934 ds3000_writereg(state, 0x25, 0x8a); 935 936 /* enhance symbol rate performance */ 937 if ((c->symbol_rate / 1000) <= 5000) { 938 value = 29777 / (c->symbol_rate / 1000) + 1; 939 if (value % 2 != 0) 940 value++; 941 ds3000_writereg(state, 0xc3, 0x0d); 942 ds3000_writereg(state, 0xc8, value); 943 ds3000_writereg(state, 0xc4, 0x10); 944 ds3000_writereg(state, 0xc7, 0x0e); 945 } else if ((c->symbol_rate / 1000) <= 10000) { 946 value = 92166 / (c->symbol_rate / 1000) + 1; 947 if (value % 2 != 0) 948 value++; 949 ds3000_writereg(state, 0xc3, 0x07); 950 ds3000_writereg(state, 0xc8, value); 951 ds3000_writereg(state, 0xc4, 0x09); 952 ds3000_writereg(state, 0xc7, 0x12); 953 } else if ((c->symbol_rate / 1000) <= 20000) { 954 value = 64516 / (c->symbol_rate / 1000) + 1; 955 ds3000_writereg(state, 0xc3, value); 956 ds3000_writereg(state, 0xc8, 0x0e); 957 ds3000_writereg(state, 0xc4, 0x07); 958 ds3000_writereg(state, 0xc7, 0x18); 959 } else { 960 value = 129032 / (c->symbol_rate / 1000) + 1; 961 ds3000_writereg(state, 0xc3, value); 962 ds3000_writereg(state, 0xc8, 0x0a); 963 ds3000_writereg(state, 0xc4, 0x05); 964 ds3000_writereg(state, 0xc7, 0x24); 965 } 966 967 /* normalized symbol rate rounded to the closest integer */ 968 value = (((c->symbol_rate / 1000) << 16) + 969 (DS3000_SAMPLE_RATE / 2)) / DS3000_SAMPLE_RATE; 970 ds3000_writereg(state, 0x61, value & 0x00ff); 971 ds3000_writereg(state, 0x62, (value & 0xff00) >> 8); 972 973 /* co-channel interference cancellation disabled */ 974 ds3000_writereg(state, 0x56, 0x00); 975 976 /* equalizer disabled */ 977 ds3000_writereg(state, 0x76, 0x00); 978 979 /*ds3000_writereg(state, 0x08, 0x03); 980 ds3000_writereg(state, 0xfd, 0x22); 981 ds3000_writereg(state, 0x08, 0x07); 982 ds3000_writereg(state, 0xfd, 0x42); 983 ds3000_writereg(state, 0x08, 0x07);*/ 984 985 if (state->config->ci_mode) { 986 switch (c->delivery_system) { 987 case SYS_DVBS: 988 default: 989 ds3000_writereg(state, 0xfd, 0x80); 990 break; 991 case SYS_DVBS2: 992 ds3000_writereg(state, 0xfd, 0x01); 993 break; 994 } 995 } 996 997 /* ds3000 out of software reset */ 998 ds3000_writereg(state, 0x00, 0x00); 999 /* start ds3000 build-in uC */ 1000 ds3000_writereg(state, 0xb2, 0x00); 1001 1002 if (fe->ops.tuner_ops.get_frequency) { 1003 fe->ops.tuner_ops.get_frequency(fe, &frequency); 1004 offset_khz = frequency - c->frequency; 1005 ds3000_set_carrier_offset(fe, offset_khz); 1006 } 1007 1008 for (i = 0; i < 30 ; i++) { 1009 ds3000_read_status(fe, &status); 1010 if (status & FE_HAS_LOCK) 1011 break; 1012 1013 msleep(10); 1014 } 1015 1016 return 0; 1017 } 1018 1019 static int ds3000_tune(struct dvb_frontend *fe, 1020 bool re_tune, 1021 unsigned int mode_flags, 1022 unsigned int *delay, 1023 fe_status_t *status) 1024 { 1025 if (re_tune) { 1026 int ret = ds3000_set_frontend(fe); 1027 if (ret) 1028 return ret; 1029 } 1030 1031 *delay = HZ / 5; 1032 1033 return ds3000_read_status(fe, status); 1034 } 1035 1036 static enum dvbfe_algo ds3000_get_algo(struct dvb_frontend *fe) 1037 { 1038 dprintk("%s()\n", __func__); 1039 return DVBFE_ALGO_HW; 1040 } 1041 1042 /* 1043 * Initialise or wake up device 1044 * 1045 * Power config will reset and load initial firmware if required 1046 */ 1047 static int ds3000_initfe(struct dvb_frontend *fe) 1048 { 1049 struct ds3000_state *state = fe->demodulator_priv; 1050 int ret; 1051 1052 dprintk("%s()\n", __func__); 1053 /* hard reset */ 1054 ds3000_writereg(state, 0x08, 0x01 | ds3000_readreg(state, 0x08)); 1055 msleep(1); 1056 1057 /* Load the firmware if required */ 1058 ret = ds3000_firmware_ondemand(fe); 1059 if (ret != 0) { 1060 printk(KERN_ERR "%s: Unable initialize firmware\n", __func__); 1061 return ret; 1062 } 1063 1064 return 0; 1065 } 1066 1067 static struct dvb_frontend_ops ds3000_ops = { 1068 .delsys = { SYS_DVBS, SYS_DVBS2 }, 1069 .info = { 1070 .name = "Montage Technology DS3000", 1071 .frequency_min = 950000, 1072 .frequency_max = 2150000, 1073 .frequency_stepsize = 1011, /* kHz for QPSK frontends */ 1074 .frequency_tolerance = 5000, 1075 .symbol_rate_min = 1000000, 1076 .symbol_rate_max = 45000000, 1077 .caps = FE_CAN_INVERSION_AUTO | 1078 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 1079 FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 | 1080 FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 1081 FE_CAN_2G_MODULATION | 1082 FE_CAN_QPSK | FE_CAN_RECOVER 1083 }, 1084 1085 .release = ds3000_release, 1086 1087 .init = ds3000_initfe, 1088 .i2c_gate_ctrl = ds3000_i2c_gate_ctrl, 1089 .read_status = ds3000_read_status, 1090 .read_ber = ds3000_read_ber, 1091 .read_snr = ds3000_read_snr, 1092 .read_ucblocks = ds3000_read_ucblocks, 1093 .set_voltage = ds3000_set_voltage, 1094 .set_tone = ds3000_set_tone, 1095 .diseqc_send_master_cmd = ds3000_send_diseqc_msg, 1096 .diseqc_send_burst = ds3000_diseqc_send_burst, 1097 .get_frontend_algo = ds3000_get_algo, 1098 1099 .set_frontend = ds3000_set_frontend, 1100 .tune = ds3000_tune, 1101 }; 1102 1103 module_param(debug, int, 0644); 1104 MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)"); 1105 1106 MODULE_DESCRIPTION("DVB Frontend module for Montage Technology " 1107 "DS3000 hardware"); 1108 MODULE_AUTHOR("Konstantin Dimitrov <kosio.dimitrov@gmail.com>"); 1109 MODULE_LICENSE("GPL"); 1110 MODULE_FIRMWARE(DS3000_DEFAULT_FIRMWARE); 1111