1 /* 2 * drxk_hard: DRX-K DVB-C/T demodulator driver 3 * 4 * Copyright (C) 2010-2011 Digital Devices GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * version 2 only, as published by the Free Software Foundation. 9 * 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * To obtain the license, point your browser to 17 * http://www.gnu.org/copyleft/gpl.html 18 */ 19 20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/moduleparam.h> 25 #include <linux/init.h> 26 #include <linux/delay.h> 27 #include <linux/firmware.h> 28 #include <linux/i2c.h> 29 #include <linux/hardirq.h> 30 #include <asm/div64.h> 31 32 #include "dvb_frontend.h" 33 #include "drxk.h" 34 #include "drxk_hard.h" 35 #include "dvb_math.h" 36 37 static int power_down_dvbt(struct drxk_state *state, bool set_power_mode); 38 static int power_down_qam(struct drxk_state *state); 39 static int set_dvbt_standard(struct drxk_state *state, 40 enum operation_mode o_mode); 41 static int set_qam_standard(struct drxk_state *state, 42 enum operation_mode o_mode); 43 static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz, 44 s32 tuner_freq_offset); 45 static int set_dvbt_standard(struct drxk_state *state, 46 enum operation_mode o_mode); 47 static int dvbt_start(struct drxk_state *state); 48 static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, 49 s32 tuner_freq_offset); 50 static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status); 51 static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status); 52 static int switch_antenna_to_qam(struct drxk_state *state); 53 static int switch_antenna_to_dvbt(struct drxk_state *state); 54 55 static bool is_dvbt(struct drxk_state *state) 56 { 57 return state->m_operation_mode == OM_DVBT; 58 } 59 60 static bool is_qam(struct drxk_state *state) 61 { 62 return state->m_operation_mode == OM_QAM_ITU_A || 63 state->m_operation_mode == OM_QAM_ITU_B || 64 state->m_operation_mode == OM_QAM_ITU_C; 65 } 66 67 #define NOA1ROM 0 68 69 #define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0) 70 #define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0) 71 72 #define DEFAULT_MER_83 165 73 #define DEFAULT_MER_93 250 74 75 #ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH 76 #define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02) 77 #endif 78 79 #ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH 80 #define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03) 81 #endif 82 83 #define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700 84 #define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500 85 86 #ifndef DRXK_KI_RAGC_ATV 87 #define DRXK_KI_RAGC_ATV 4 88 #endif 89 #ifndef DRXK_KI_IAGC_ATV 90 #define DRXK_KI_IAGC_ATV 6 91 #endif 92 #ifndef DRXK_KI_DAGC_ATV 93 #define DRXK_KI_DAGC_ATV 7 94 #endif 95 96 #ifndef DRXK_KI_RAGC_QAM 97 #define DRXK_KI_RAGC_QAM 3 98 #endif 99 #ifndef DRXK_KI_IAGC_QAM 100 #define DRXK_KI_IAGC_QAM 4 101 #endif 102 #ifndef DRXK_KI_DAGC_QAM 103 #define DRXK_KI_DAGC_QAM 7 104 #endif 105 #ifndef DRXK_KI_RAGC_DVBT 106 #define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2) 107 #endif 108 #ifndef DRXK_KI_IAGC_DVBT 109 #define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2) 110 #endif 111 #ifndef DRXK_KI_DAGC_DVBT 112 #define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7) 113 #endif 114 115 #ifndef DRXK_AGC_DAC_OFFSET 116 #define DRXK_AGC_DAC_OFFSET (0x800) 117 #endif 118 119 #ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ 120 #define DRXK_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L) 121 #endif 122 123 #ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ 124 #define DRXK_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L) 125 #endif 126 127 #ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ 128 #define DRXK_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L) 129 #endif 130 131 #ifndef DRXK_QAM_SYMBOLRATE_MAX 132 #define DRXK_QAM_SYMBOLRATE_MAX (7233000) 133 #endif 134 135 #define DRXK_BL_ROM_OFFSET_TAPS_DVBT 56 136 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_A 64 137 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_C 0x5FE0 138 #define DRXK_BL_ROM_OFFSET_TAPS_BG 24 139 #define DRXK_BL_ROM_OFFSET_TAPS_DKILLP 32 140 #define DRXK_BL_ROM_OFFSET_TAPS_NTSC 40 141 #define DRXK_BL_ROM_OFFSET_TAPS_FM 48 142 #define DRXK_BL_ROM_OFFSET_UCODE 0 143 144 #define DRXK_BLC_TIMEOUT 100 145 146 #define DRXK_BLCC_NR_ELEMENTS_TAPS 2 147 #define DRXK_BLCC_NR_ELEMENTS_UCODE 6 148 149 #define DRXK_BLDC_NR_ELEMENTS_TAPS 28 150 151 #ifndef DRXK_OFDM_NE_NOTCH_WIDTH 152 #define DRXK_OFDM_NE_NOTCH_WIDTH (4) 153 #endif 154 155 #define DRXK_QAM_SL_SIG_POWER_QAM16 (40960) 156 #define DRXK_QAM_SL_SIG_POWER_QAM32 (20480) 157 #define DRXK_QAM_SL_SIG_POWER_QAM64 (43008) 158 #define DRXK_QAM_SL_SIG_POWER_QAM128 (20992) 159 #define DRXK_QAM_SL_SIG_POWER_QAM256 (43520) 160 161 static unsigned int debug; 162 module_param(debug, int, 0644); 163 MODULE_PARM_DESC(debug, "enable debug messages"); 164 165 #define dprintk(level, fmt, arg...) do { \ 166 if (debug >= level) \ 167 printk(KERN_DEBUG KBUILD_MODNAME ": %s " fmt, __func__, ##arg); \ 168 } while (0) 169 170 171 static inline u32 MulDiv32(u32 a, u32 b, u32 c) 172 { 173 u64 tmp64; 174 175 tmp64 = (u64) a * (u64) b; 176 do_div(tmp64, c); 177 178 return (u32) tmp64; 179 } 180 181 static inline u32 Frac28a(u32 a, u32 c) 182 { 183 int i = 0; 184 u32 Q1 = 0; 185 u32 R0 = 0; 186 187 R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */ 188 Q1 = a / c; /* 189 * integer part, only the 4 least significant 190 * bits will be visible in the result 191 */ 192 193 /* division using radix 16, 7 nibbles in the result */ 194 for (i = 0; i < 7; i++) { 195 Q1 = (Q1 << 4) | (R0 / c); 196 R0 = (R0 % c) << 4; 197 } 198 /* rounding */ 199 if ((R0 >> 3) >= c) 200 Q1++; 201 202 return Q1; 203 } 204 205 static inline u32 log10times100(u32 value) 206 { 207 return (100L * intlog10(value)) >> 24; 208 } 209 210 /****************************************************************************/ 211 /* I2C **********************************************************************/ 212 /****************************************************************************/ 213 214 static int drxk_i2c_lock(struct drxk_state *state) 215 { 216 i2c_lock_adapter(state->i2c); 217 state->drxk_i2c_exclusive_lock = true; 218 219 return 0; 220 } 221 222 static void drxk_i2c_unlock(struct drxk_state *state) 223 { 224 if (!state->drxk_i2c_exclusive_lock) 225 return; 226 227 i2c_unlock_adapter(state->i2c); 228 state->drxk_i2c_exclusive_lock = false; 229 } 230 231 static int drxk_i2c_transfer(struct drxk_state *state, struct i2c_msg *msgs, 232 unsigned len) 233 { 234 if (state->drxk_i2c_exclusive_lock) 235 return __i2c_transfer(state->i2c, msgs, len); 236 else 237 return i2c_transfer(state->i2c, msgs, len); 238 } 239 240 static int i2c_read1(struct drxk_state *state, u8 adr, u8 *val) 241 { 242 struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD, 243 .buf = val, .len = 1} 244 }; 245 246 return drxk_i2c_transfer(state, msgs, 1); 247 } 248 249 static int i2c_write(struct drxk_state *state, u8 adr, u8 *data, int len) 250 { 251 int status; 252 struct i2c_msg msg = { 253 .addr = adr, .flags = 0, .buf = data, .len = len }; 254 255 dprintk(3, ":"); 256 if (debug > 2) { 257 int i; 258 for (i = 0; i < len; i++) 259 pr_cont(" %02x", data[i]); 260 pr_cont("\n"); 261 } 262 status = drxk_i2c_transfer(state, &msg, 1); 263 if (status >= 0 && status != 1) 264 status = -EIO; 265 266 if (status < 0) 267 pr_err("i2c write error at addr 0x%02x\n", adr); 268 269 return status; 270 } 271 272 static int i2c_read(struct drxk_state *state, 273 u8 adr, u8 *msg, int len, u8 *answ, int alen) 274 { 275 int status; 276 struct i2c_msg msgs[2] = { 277 {.addr = adr, .flags = 0, 278 .buf = msg, .len = len}, 279 {.addr = adr, .flags = I2C_M_RD, 280 .buf = answ, .len = alen} 281 }; 282 283 status = drxk_i2c_transfer(state, msgs, 2); 284 if (status != 2) { 285 if (debug > 2) 286 pr_cont(": ERROR!\n"); 287 if (status >= 0) 288 status = -EIO; 289 290 pr_err("i2c read error at addr 0x%02x\n", adr); 291 return status; 292 } 293 if (debug > 2) { 294 int i; 295 dprintk(2, ": read from"); 296 for (i = 0; i < len; i++) 297 pr_cont(" %02x", msg[i]); 298 pr_cont(", value = "); 299 for (i = 0; i < alen; i++) 300 pr_cont(" %02x", answ[i]); 301 pr_cont("\n"); 302 } 303 return 0; 304 } 305 306 static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags) 307 { 308 int status; 309 u8 adr = state->demod_address, mm1[4], mm2[2], len; 310 311 if (state->single_master) 312 flags |= 0xC0; 313 314 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { 315 mm1[0] = (((reg << 1) & 0xFF) | 0x01); 316 mm1[1] = ((reg >> 16) & 0xFF); 317 mm1[2] = ((reg >> 24) & 0xFF) | flags; 318 mm1[3] = ((reg >> 7) & 0xFF); 319 len = 4; 320 } else { 321 mm1[0] = ((reg << 1) & 0xFF); 322 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); 323 len = 2; 324 } 325 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags); 326 status = i2c_read(state, adr, mm1, len, mm2, 2); 327 if (status < 0) 328 return status; 329 if (data) 330 *data = mm2[0] | (mm2[1] << 8); 331 332 return 0; 333 } 334 335 static int read16(struct drxk_state *state, u32 reg, u16 *data) 336 { 337 return read16_flags(state, reg, data, 0); 338 } 339 340 static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags) 341 { 342 int status; 343 u8 adr = state->demod_address, mm1[4], mm2[4], len; 344 345 if (state->single_master) 346 flags |= 0xC0; 347 348 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { 349 mm1[0] = (((reg << 1) & 0xFF) | 0x01); 350 mm1[1] = ((reg >> 16) & 0xFF); 351 mm1[2] = ((reg >> 24) & 0xFF) | flags; 352 mm1[3] = ((reg >> 7) & 0xFF); 353 len = 4; 354 } else { 355 mm1[0] = ((reg << 1) & 0xFF); 356 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); 357 len = 2; 358 } 359 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags); 360 status = i2c_read(state, adr, mm1, len, mm2, 4); 361 if (status < 0) 362 return status; 363 if (data) 364 *data = mm2[0] | (mm2[1] << 8) | 365 (mm2[2] << 16) | (mm2[3] << 24); 366 367 return 0; 368 } 369 370 static int read32(struct drxk_state *state, u32 reg, u32 *data) 371 { 372 return read32_flags(state, reg, data, 0); 373 } 374 375 static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags) 376 { 377 u8 adr = state->demod_address, mm[6], len; 378 379 if (state->single_master) 380 flags |= 0xC0; 381 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { 382 mm[0] = (((reg << 1) & 0xFF) | 0x01); 383 mm[1] = ((reg >> 16) & 0xFF); 384 mm[2] = ((reg >> 24) & 0xFF) | flags; 385 mm[3] = ((reg >> 7) & 0xFF); 386 len = 4; 387 } else { 388 mm[0] = ((reg << 1) & 0xFF); 389 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); 390 len = 2; 391 } 392 mm[len] = data & 0xff; 393 mm[len + 1] = (data >> 8) & 0xff; 394 395 dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags); 396 return i2c_write(state, adr, mm, len + 2); 397 } 398 399 static int write16(struct drxk_state *state, u32 reg, u16 data) 400 { 401 return write16_flags(state, reg, data, 0); 402 } 403 404 static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags) 405 { 406 u8 adr = state->demod_address, mm[8], len; 407 408 if (state->single_master) 409 flags |= 0xC0; 410 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { 411 mm[0] = (((reg << 1) & 0xFF) | 0x01); 412 mm[1] = ((reg >> 16) & 0xFF); 413 mm[2] = ((reg >> 24) & 0xFF) | flags; 414 mm[3] = ((reg >> 7) & 0xFF); 415 len = 4; 416 } else { 417 mm[0] = ((reg << 1) & 0xFF); 418 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); 419 len = 2; 420 } 421 mm[len] = data & 0xff; 422 mm[len + 1] = (data >> 8) & 0xff; 423 mm[len + 2] = (data >> 16) & 0xff; 424 mm[len + 3] = (data >> 24) & 0xff; 425 dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags); 426 427 return i2c_write(state, adr, mm, len + 4); 428 } 429 430 static int write32(struct drxk_state *state, u32 reg, u32 data) 431 { 432 return write32_flags(state, reg, data, 0); 433 } 434 435 static int write_block(struct drxk_state *state, u32 address, 436 const int block_size, const u8 p_block[]) 437 { 438 int status = 0, blk_size = block_size; 439 u8 flags = 0; 440 441 if (state->single_master) 442 flags |= 0xC0; 443 444 while (blk_size > 0) { 445 int chunk = blk_size > state->m_chunk_size ? 446 state->m_chunk_size : blk_size; 447 u8 *adr_buf = &state->chunk[0]; 448 u32 adr_length = 0; 449 450 if (DRXDAP_FASI_LONG_FORMAT(address) || (flags != 0)) { 451 adr_buf[0] = (((address << 1) & 0xFF) | 0x01); 452 adr_buf[1] = ((address >> 16) & 0xFF); 453 adr_buf[2] = ((address >> 24) & 0xFF); 454 adr_buf[3] = ((address >> 7) & 0xFF); 455 adr_buf[2] |= flags; 456 adr_length = 4; 457 if (chunk == state->m_chunk_size) 458 chunk -= 2; 459 } else { 460 adr_buf[0] = ((address << 1) & 0xFF); 461 adr_buf[1] = (((address >> 16) & 0x0F) | 462 ((address >> 18) & 0xF0)); 463 adr_length = 2; 464 } 465 memcpy(&state->chunk[adr_length], p_block, chunk); 466 dprintk(2, "(0x%08x, 0x%02x)\n", address, flags); 467 if (debug > 1) { 468 int i; 469 if (p_block) 470 for (i = 0; i < chunk; i++) 471 pr_cont(" %02x", p_block[i]); 472 pr_cont("\n"); 473 } 474 status = i2c_write(state, state->demod_address, 475 &state->chunk[0], chunk + adr_length); 476 if (status < 0) { 477 pr_err("%s: i2c write error at addr 0x%02x\n", 478 __func__, address); 479 break; 480 } 481 p_block += chunk; 482 address += (chunk >> 1); 483 blk_size -= chunk; 484 } 485 return status; 486 } 487 488 #ifndef DRXK_MAX_RETRIES_POWERUP 489 #define DRXK_MAX_RETRIES_POWERUP 20 490 #endif 491 492 static int power_up_device(struct drxk_state *state) 493 { 494 int status; 495 u8 data = 0; 496 u16 retry_count = 0; 497 498 dprintk(1, "\n"); 499 500 status = i2c_read1(state, state->demod_address, &data); 501 if (status < 0) { 502 do { 503 data = 0; 504 status = i2c_write(state, state->demod_address, 505 &data, 1); 506 usleep_range(10000, 11000); 507 retry_count++; 508 if (status < 0) 509 continue; 510 status = i2c_read1(state, state->demod_address, 511 &data); 512 } while (status < 0 && 513 (retry_count < DRXK_MAX_RETRIES_POWERUP)); 514 if (status < 0 && retry_count >= DRXK_MAX_RETRIES_POWERUP) 515 goto error; 516 } 517 518 /* Make sure all clk domains are active */ 519 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE); 520 if (status < 0) 521 goto error; 522 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); 523 if (status < 0) 524 goto error; 525 /* Enable pll lock tests */ 526 status = write16(state, SIO_CC_PLL_LOCK__A, 1); 527 if (status < 0) 528 goto error; 529 530 state->m_current_power_mode = DRX_POWER_UP; 531 532 error: 533 if (status < 0) 534 pr_err("Error %d on %s\n", status, __func__); 535 536 return status; 537 } 538 539 540 static int init_state(struct drxk_state *state) 541 { 542 /* 543 * FIXME: most (all?) of the values below should be moved into 544 * struct drxk_config, as they are probably board-specific 545 */ 546 u32 ul_vsb_if_agc_mode = DRXK_AGC_CTRL_AUTO; 547 u32 ul_vsb_if_agc_output_level = 0; 548 u32 ul_vsb_if_agc_min_level = 0; 549 u32 ul_vsb_if_agc_max_level = 0x7FFF; 550 u32 ul_vsb_if_agc_speed = 3; 551 552 u32 ul_vsb_rf_agc_mode = DRXK_AGC_CTRL_AUTO; 553 u32 ul_vsb_rf_agc_output_level = 0; 554 u32 ul_vsb_rf_agc_min_level = 0; 555 u32 ul_vsb_rf_agc_max_level = 0x7FFF; 556 u32 ul_vsb_rf_agc_speed = 3; 557 u32 ul_vsb_rf_agc_top = 9500; 558 u32 ul_vsb_rf_agc_cut_off_current = 4000; 559 560 u32 ul_atv_if_agc_mode = DRXK_AGC_CTRL_AUTO; 561 u32 ul_atv_if_agc_output_level = 0; 562 u32 ul_atv_if_agc_min_level = 0; 563 u32 ul_atv_if_agc_max_level = 0; 564 u32 ul_atv_if_agc_speed = 3; 565 566 u32 ul_atv_rf_agc_mode = DRXK_AGC_CTRL_OFF; 567 u32 ul_atv_rf_agc_output_level = 0; 568 u32 ul_atv_rf_agc_min_level = 0; 569 u32 ul_atv_rf_agc_max_level = 0; 570 u32 ul_atv_rf_agc_top = 9500; 571 u32 ul_atv_rf_agc_cut_off_current = 4000; 572 u32 ul_atv_rf_agc_speed = 3; 573 574 u32 ulQual83 = DEFAULT_MER_83; 575 u32 ulQual93 = DEFAULT_MER_93; 576 577 u32 ul_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; 578 u32 ul_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; 579 580 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ 581 /* io_pad_cfg_mode output mode is drive always */ 582 /* io_pad_cfg_drive is set to power 2 (23 mA) */ 583 u32 ul_gpio_cfg = 0x0113; 584 u32 ul_invert_ts_clock = 0; 585 u32 ul_ts_data_strength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH; 586 u32 ul_dvbt_bitrate = 50000000; 587 u32 ul_dvbc_bitrate = DRXK_QAM_SYMBOLRATE_MAX * 8; 588 589 u32 ul_insert_rs_byte = 0; 590 591 u32 ul_rf_mirror = 1; 592 u32 ul_power_down = 0; 593 594 dprintk(1, "\n"); 595 596 state->m_has_lna = false; 597 state->m_has_dvbt = false; 598 state->m_has_dvbc = false; 599 state->m_has_atv = false; 600 state->m_has_oob = false; 601 state->m_has_audio = false; 602 603 if (!state->m_chunk_size) 604 state->m_chunk_size = 124; 605 606 state->m_osc_clock_freq = 0; 607 state->m_smart_ant_inverted = false; 608 state->m_b_p_down_open_bridge = false; 609 610 /* real system clock frequency in kHz */ 611 state->m_sys_clock_freq = 151875; 612 /* Timing div, 250ns/Psys */ 613 /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */ 614 state->m_hi_cfg_timing_div = ((state->m_sys_clock_freq / 1000) * 615 HI_I2C_DELAY) / 1000; 616 /* Clipping */ 617 if (state->m_hi_cfg_timing_div > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M) 618 state->m_hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; 619 state->m_hi_cfg_wake_up_key = (state->demod_address << 1); 620 /* port/bridge/power down ctrl */ 621 state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; 622 623 state->m_b_power_down = (ul_power_down != 0); 624 625 state->m_drxk_a3_patch_code = false; 626 627 /* Init AGC and PGA parameters */ 628 /* VSB IF */ 629 state->m_vsb_if_agc_cfg.ctrl_mode = ul_vsb_if_agc_mode; 630 state->m_vsb_if_agc_cfg.output_level = ul_vsb_if_agc_output_level; 631 state->m_vsb_if_agc_cfg.min_output_level = ul_vsb_if_agc_min_level; 632 state->m_vsb_if_agc_cfg.max_output_level = ul_vsb_if_agc_max_level; 633 state->m_vsb_if_agc_cfg.speed = ul_vsb_if_agc_speed; 634 state->m_vsb_pga_cfg = 140; 635 636 /* VSB RF */ 637 state->m_vsb_rf_agc_cfg.ctrl_mode = ul_vsb_rf_agc_mode; 638 state->m_vsb_rf_agc_cfg.output_level = ul_vsb_rf_agc_output_level; 639 state->m_vsb_rf_agc_cfg.min_output_level = ul_vsb_rf_agc_min_level; 640 state->m_vsb_rf_agc_cfg.max_output_level = ul_vsb_rf_agc_max_level; 641 state->m_vsb_rf_agc_cfg.speed = ul_vsb_rf_agc_speed; 642 state->m_vsb_rf_agc_cfg.top = ul_vsb_rf_agc_top; 643 state->m_vsb_rf_agc_cfg.cut_off_current = ul_vsb_rf_agc_cut_off_current; 644 state->m_vsb_pre_saw_cfg.reference = 0x07; 645 state->m_vsb_pre_saw_cfg.use_pre_saw = true; 646 647 state->m_Quality83percent = DEFAULT_MER_83; 648 state->m_Quality93percent = DEFAULT_MER_93; 649 if (ulQual93 <= 500 && ulQual83 < ulQual93) { 650 state->m_Quality83percent = ulQual83; 651 state->m_Quality93percent = ulQual93; 652 } 653 654 /* ATV IF */ 655 state->m_atv_if_agc_cfg.ctrl_mode = ul_atv_if_agc_mode; 656 state->m_atv_if_agc_cfg.output_level = ul_atv_if_agc_output_level; 657 state->m_atv_if_agc_cfg.min_output_level = ul_atv_if_agc_min_level; 658 state->m_atv_if_agc_cfg.max_output_level = ul_atv_if_agc_max_level; 659 state->m_atv_if_agc_cfg.speed = ul_atv_if_agc_speed; 660 661 /* ATV RF */ 662 state->m_atv_rf_agc_cfg.ctrl_mode = ul_atv_rf_agc_mode; 663 state->m_atv_rf_agc_cfg.output_level = ul_atv_rf_agc_output_level; 664 state->m_atv_rf_agc_cfg.min_output_level = ul_atv_rf_agc_min_level; 665 state->m_atv_rf_agc_cfg.max_output_level = ul_atv_rf_agc_max_level; 666 state->m_atv_rf_agc_cfg.speed = ul_atv_rf_agc_speed; 667 state->m_atv_rf_agc_cfg.top = ul_atv_rf_agc_top; 668 state->m_atv_rf_agc_cfg.cut_off_current = ul_atv_rf_agc_cut_off_current; 669 state->m_atv_pre_saw_cfg.reference = 0x04; 670 state->m_atv_pre_saw_cfg.use_pre_saw = true; 671 672 673 /* DVBT RF */ 674 state->m_dvbt_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF; 675 state->m_dvbt_rf_agc_cfg.output_level = 0; 676 state->m_dvbt_rf_agc_cfg.min_output_level = 0; 677 state->m_dvbt_rf_agc_cfg.max_output_level = 0xFFFF; 678 state->m_dvbt_rf_agc_cfg.top = 0x2100; 679 state->m_dvbt_rf_agc_cfg.cut_off_current = 4000; 680 state->m_dvbt_rf_agc_cfg.speed = 1; 681 682 683 /* DVBT IF */ 684 state->m_dvbt_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO; 685 state->m_dvbt_if_agc_cfg.output_level = 0; 686 state->m_dvbt_if_agc_cfg.min_output_level = 0; 687 state->m_dvbt_if_agc_cfg.max_output_level = 9000; 688 state->m_dvbt_if_agc_cfg.top = 13424; 689 state->m_dvbt_if_agc_cfg.cut_off_current = 0; 690 state->m_dvbt_if_agc_cfg.speed = 3; 691 state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay = 30; 692 state->m_dvbt_if_agc_cfg.ingain_tgt_max = 30000; 693 /* state->m_dvbtPgaCfg = 140; */ 694 695 state->m_dvbt_pre_saw_cfg.reference = 4; 696 state->m_dvbt_pre_saw_cfg.use_pre_saw = false; 697 698 /* QAM RF */ 699 state->m_qam_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF; 700 state->m_qam_rf_agc_cfg.output_level = 0; 701 state->m_qam_rf_agc_cfg.min_output_level = 6023; 702 state->m_qam_rf_agc_cfg.max_output_level = 27000; 703 state->m_qam_rf_agc_cfg.top = 0x2380; 704 state->m_qam_rf_agc_cfg.cut_off_current = 4000; 705 state->m_qam_rf_agc_cfg.speed = 3; 706 707 /* QAM IF */ 708 state->m_qam_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO; 709 state->m_qam_if_agc_cfg.output_level = 0; 710 state->m_qam_if_agc_cfg.min_output_level = 0; 711 state->m_qam_if_agc_cfg.max_output_level = 9000; 712 state->m_qam_if_agc_cfg.top = 0x0511; 713 state->m_qam_if_agc_cfg.cut_off_current = 0; 714 state->m_qam_if_agc_cfg.speed = 3; 715 state->m_qam_if_agc_cfg.ingain_tgt_max = 5119; 716 state->m_qam_if_agc_cfg.fast_clip_ctrl_delay = 50; 717 718 state->m_qam_pga_cfg = 140; 719 state->m_qam_pre_saw_cfg.reference = 4; 720 state->m_qam_pre_saw_cfg.use_pre_saw = false; 721 722 state->m_operation_mode = OM_NONE; 723 state->m_drxk_state = DRXK_UNINITIALIZED; 724 725 /* MPEG output configuration */ 726 state->m_enable_mpeg_output = true; /* If TRUE; enable MPEG ouput */ 727 state->m_insert_rs_byte = false; /* If TRUE; insert RS byte */ 728 state->m_invert_data = false; /* If TRUE; invert DATA signals */ 729 state->m_invert_err = false; /* If TRUE; invert ERR signal */ 730 state->m_invert_str = false; /* If TRUE; invert STR signals */ 731 state->m_invert_val = false; /* If TRUE; invert VAL signals */ 732 state->m_invert_clk = (ul_invert_ts_clock != 0); /* If TRUE; invert CLK signals */ 733 734 /* If TRUE; static MPEG clockrate will be used; 735 otherwise clockrate will adapt to the bitrate of the TS */ 736 737 state->m_dvbt_bitrate = ul_dvbt_bitrate; 738 state->m_dvbc_bitrate = ul_dvbc_bitrate; 739 740 state->m_ts_data_strength = (ul_ts_data_strength & 0x07); 741 742 /* Maximum bitrate in b/s in case static clockrate is selected */ 743 state->m_mpeg_ts_static_bitrate = 19392658; 744 state->m_disable_te_ihandling = false; 745 746 if (ul_insert_rs_byte) 747 state->m_insert_rs_byte = true; 748 749 state->m_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; 750 if (ul_mpeg_lock_time_out < 10000) 751 state->m_mpeg_lock_time_out = ul_mpeg_lock_time_out; 752 state->m_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; 753 if (ul_demod_lock_time_out < 10000) 754 state->m_demod_lock_time_out = ul_demod_lock_time_out; 755 756 /* QAM defaults */ 757 state->m_constellation = DRX_CONSTELLATION_AUTO; 758 state->m_qam_interleave_mode = DRXK_QAM_I12_J17; 759 state->m_fec_rs_plen = 204 * 8; /* fecRsPlen annex A */ 760 state->m_fec_rs_prescale = 1; 761 762 state->m_sqi_speed = DRXK_DVBT_SQI_SPEED_MEDIUM; 763 state->m_agcfast_clip_ctrl_delay = 0; 764 765 state->m_gpio_cfg = ul_gpio_cfg; 766 767 state->m_b_power_down = false; 768 state->m_current_power_mode = DRX_POWER_DOWN; 769 770 state->m_rfmirror = (ul_rf_mirror == 0); 771 state->m_if_agc_pol = false; 772 return 0; 773 } 774 775 static int drxx_open(struct drxk_state *state) 776 { 777 int status = 0; 778 u32 jtag = 0; 779 u16 bid = 0; 780 u16 key = 0; 781 782 dprintk(1, "\n"); 783 /* stop lock indicator process */ 784 status = write16(state, SCU_RAM_GPIO__A, 785 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); 786 if (status < 0) 787 goto error; 788 /* Check device id */ 789 status = read16(state, SIO_TOP_COMM_KEY__A, &key); 790 if (status < 0) 791 goto error; 792 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); 793 if (status < 0) 794 goto error; 795 status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag); 796 if (status < 0) 797 goto error; 798 status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid); 799 if (status < 0) 800 goto error; 801 status = write16(state, SIO_TOP_COMM_KEY__A, key); 802 error: 803 if (status < 0) 804 pr_err("Error %d on %s\n", status, __func__); 805 return status; 806 } 807 808 static int get_device_capabilities(struct drxk_state *state) 809 { 810 u16 sio_pdr_ohw_cfg = 0; 811 u32 sio_top_jtagid_lo = 0; 812 int status; 813 const char *spin = ""; 814 815 dprintk(1, "\n"); 816 817 /* driver 0.9.0 */ 818 /* stop lock indicator process */ 819 status = write16(state, SCU_RAM_GPIO__A, 820 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); 821 if (status < 0) 822 goto error; 823 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); 824 if (status < 0) 825 goto error; 826 status = read16(state, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg); 827 if (status < 0) 828 goto error; 829 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); 830 if (status < 0) 831 goto error; 832 833 switch ((sio_pdr_ohw_cfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) { 834 case 0: 835 /* ignore (bypass ?) */ 836 break; 837 case 1: 838 /* 27 MHz */ 839 state->m_osc_clock_freq = 27000; 840 break; 841 case 2: 842 /* 20.25 MHz */ 843 state->m_osc_clock_freq = 20250; 844 break; 845 case 3: 846 /* 4 MHz */ 847 state->m_osc_clock_freq = 20250; 848 break; 849 default: 850 pr_err("Clock Frequency is unknown\n"); 851 return -EINVAL; 852 } 853 /* 854 Determine device capabilities 855 Based on pinning v14 856 */ 857 status = read32(state, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo); 858 if (status < 0) 859 goto error; 860 861 pr_info("status = 0x%08x\n", sio_top_jtagid_lo); 862 863 /* driver 0.9.0 */ 864 switch ((sio_top_jtagid_lo >> 29) & 0xF) { 865 case 0: 866 state->m_device_spin = DRXK_SPIN_A1; 867 spin = "A1"; 868 break; 869 case 2: 870 state->m_device_spin = DRXK_SPIN_A2; 871 spin = "A2"; 872 break; 873 case 3: 874 state->m_device_spin = DRXK_SPIN_A3; 875 spin = "A3"; 876 break; 877 default: 878 state->m_device_spin = DRXK_SPIN_UNKNOWN; 879 status = -EINVAL; 880 pr_err("Spin %d unknown\n", (sio_top_jtagid_lo >> 29) & 0xF); 881 goto error2; 882 } 883 switch ((sio_top_jtagid_lo >> 12) & 0xFF) { 884 case 0x13: 885 /* typeId = DRX3913K_TYPE_ID */ 886 state->m_has_lna = false; 887 state->m_has_oob = false; 888 state->m_has_atv = false; 889 state->m_has_audio = false; 890 state->m_has_dvbt = true; 891 state->m_has_dvbc = true; 892 state->m_has_sawsw = true; 893 state->m_has_gpio2 = false; 894 state->m_has_gpio1 = false; 895 state->m_has_irqn = false; 896 break; 897 case 0x15: 898 /* typeId = DRX3915K_TYPE_ID */ 899 state->m_has_lna = false; 900 state->m_has_oob = false; 901 state->m_has_atv = true; 902 state->m_has_audio = false; 903 state->m_has_dvbt = true; 904 state->m_has_dvbc = false; 905 state->m_has_sawsw = true; 906 state->m_has_gpio2 = true; 907 state->m_has_gpio1 = true; 908 state->m_has_irqn = false; 909 break; 910 case 0x16: 911 /* typeId = DRX3916K_TYPE_ID */ 912 state->m_has_lna = false; 913 state->m_has_oob = false; 914 state->m_has_atv = true; 915 state->m_has_audio = false; 916 state->m_has_dvbt = true; 917 state->m_has_dvbc = false; 918 state->m_has_sawsw = true; 919 state->m_has_gpio2 = true; 920 state->m_has_gpio1 = true; 921 state->m_has_irqn = false; 922 break; 923 case 0x18: 924 /* typeId = DRX3918K_TYPE_ID */ 925 state->m_has_lna = false; 926 state->m_has_oob = false; 927 state->m_has_atv = true; 928 state->m_has_audio = true; 929 state->m_has_dvbt = true; 930 state->m_has_dvbc = false; 931 state->m_has_sawsw = true; 932 state->m_has_gpio2 = true; 933 state->m_has_gpio1 = true; 934 state->m_has_irqn = false; 935 break; 936 case 0x21: 937 /* typeId = DRX3921K_TYPE_ID */ 938 state->m_has_lna = false; 939 state->m_has_oob = false; 940 state->m_has_atv = true; 941 state->m_has_audio = true; 942 state->m_has_dvbt = true; 943 state->m_has_dvbc = true; 944 state->m_has_sawsw = true; 945 state->m_has_gpio2 = true; 946 state->m_has_gpio1 = true; 947 state->m_has_irqn = false; 948 break; 949 case 0x23: 950 /* typeId = DRX3923K_TYPE_ID */ 951 state->m_has_lna = false; 952 state->m_has_oob = false; 953 state->m_has_atv = true; 954 state->m_has_audio = true; 955 state->m_has_dvbt = true; 956 state->m_has_dvbc = true; 957 state->m_has_sawsw = true; 958 state->m_has_gpio2 = true; 959 state->m_has_gpio1 = true; 960 state->m_has_irqn = false; 961 break; 962 case 0x25: 963 /* typeId = DRX3925K_TYPE_ID */ 964 state->m_has_lna = false; 965 state->m_has_oob = false; 966 state->m_has_atv = true; 967 state->m_has_audio = true; 968 state->m_has_dvbt = true; 969 state->m_has_dvbc = true; 970 state->m_has_sawsw = true; 971 state->m_has_gpio2 = true; 972 state->m_has_gpio1 = true; 973 state->m_has_irqn = false; 974 break; 975 case 0x26: 976 /* typeId = DRX3926K_TYPE_ID */ 977 state->m_has_lna = false; 978 state->m_has_oob = false; 979 state->m_has_atv = true; 980 state->m_has_audio = false; 981 state->m_has_dvbt = true; 982 state->m_has_dvbc = true; 983 state->m_has_sawsw = true; 984 state->m_has_gpio2 = true; 985 state->m_has_gpio1 = true; 986 state->m_has_irqn = false; 987 break; 988 default: 989 pr_err("DeviceID 0x%02x not supported\n", 990 ((sio_top_jtagid_lo >> 12) & 0xFF)); 991 status = -EINVAL; 992 goto error2; 993 } 994 995 pr_info("detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n", 996 ((sio_top_jtagid_lo >> 12) & 0xFF), spin, 997 state->m_osc_clock_freq / 1000, 998 state->m_osc_clock_freq % 1000); 999 1000 error: 1001 if (status < 0) 1002 pr_err("Error %d on %s\n", status, __func__); 1003 1004 error2: 1005 return status; 1006 } 1007 1008 static int hi_command(struct drxk_state *state, u16 cmd, u16 *p_result) 1009 { 1010 int status; 1011 bool powerdown_cmd; 1012 1013 dprintk(1, "\n"); 1014 1015 /* Write command */ 1016 status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd); 1017 if (status < 0) 1018 goto error; 1019 if (cmd == SIO_HI_RA_RAM_CMD_RESET) 1020 usleep_range(1000, 2000); 1021 1022 powerdown_cmd = 1023 (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) && 1024 ((state->m_hi_cfg_ctrl) & 1025 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) == 1026 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ); 1027 if (!powerdown_cmd) { 1028 /* Wait until command rdy */ 1029 u32 retry_count = 0; 1030 u16 wait_cmd; 1031 1032 do { 1033 usleep_range(1000, 2000); 1034 retry_count += 1; 1035 status = read16(state, SIO_HI_RA_RAM_CMD__A, 1036 &wait_cmd); 1037 } while ((status < 0) && (retry_count < DRXK_MAX_RETRIES) 1038 && (wait_cmd != 0)); 1039 if (status < 0) 1040 goto error; 1041 status = read16(state, SIO_HI_RA_RAM_RES__A, p_result); 1042 } 1043 error: 1044 if (status < 0) 1045 pr_err("Error %d on %s\n", status, __func__); 1046 1047 return status; 1048 } 1049 1050 static int hi_cfg_command(struct drxk_state *state) 1051 { 1052 int status; 1053 1054 dprintk(1, "\n"); 1055 1056 mutex_lock(&state->mutex); 1057 1058 status = write16(state, SIO_HI_RA_RAM_PAR_6__A, 1059 state->m_hi_cfg_timeout); 1060 if (status < 0) 1061 goto error; 1062 status = write16(state, SIO_HI_RA_RAM_PAR_5__A, 1063 state->m_hi_cfg_ctrl); 1064 if (status < 0) 1065 goto error; 1066 status = write16(state, SIO_HI_RA_RAM_PAR_4__A, 1067 state->m_hi_cfg_wake_up_key); 1068 if (status < 0) 1069 goto error; 1070 status = write16(state, SIO_HI_RA_RAM_PAR_3__A, 1071 state->m_hi_cfg_bridge_delay); 1072 if (status < 0) 1073 goto error; 1074 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, 1075 state->m_hi_cfg_timing_div); 1076 if (status < 0) 1077 goto error; 1078 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, 1079 SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY); 1080 if (status < 0) 1081 goto error; 1082 status = hi_command(state, SIO_HI_RA_RAM_CMD_CONFIG, NULL); 1083 if (status < 0) 1084 goto error; 1085 1086 state->m_hi_cfg_ctrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; 1087 error: 1088 mutex_unlock(&state->mutex); 1089 if (status < 0) 1090 pr_err("Error %d on %s\n", status, __func__); 1091 return status; 1092 } 1093 1094 static int init_hi(struct drxk_state *state) 1095 { 1096 dprintk(1, "\n"); 1097 1098 state->m_hi_cfg_wake_up_key = (state->demod_address << 1); 1099 state->m_hi_cfg_timeout = 0x96FF; 1100 /* port/bridge/power down ctrl */ 1101 state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; 1102 1103 return hi_cfg_command(state); 1104 } 1105 1106 static int mpegts_configure_pins(struct drxk_state *state, bool mpeg_enable) 1107 { 1108 int status = -1; 1109 u16 sio_pdr_mclk_cfg = 0; 1110 u16 sio_pdr_mdx_cfg = 0; 1111 u16 err_cfg = 0; 1112 1113 dprintk(1, ": mpeg %s, %s mode\n", 1114 mpeg_enable ? "enable" : "disable", 1115 state->m_enable_parallel ? "parallel" : "serial"); 1116 1117 /* stop lock indicator process */ 1118 status = write16(state, SCU_RAM_GPIO__A, 1119 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); 1120 if (status < 0) 1121 goto error; 1122 1123 /* MPEG TS pad configuration */ 1124 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); 1125 if (status < 0) 1126 goto error; 1127 1128 if (!mpeg_enable) { 1129 /* Set MPEG TS pads to inputmode */ 1130 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000); 1131 if (status < 0) 1132 goto error; 1133 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000); 1134 if (status < 0) 1135 goto error; 1136 status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000); 1137 if (status < 0) 1138 goto error; 1139 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000); 1140 if (status < 0) 1141 goto error; 1142 status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000); 1143 if (status < 0) 1144 goto error; 1145 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000); 1146 if (status < 0) 1147 goto error; 1148 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000); 1149 if (status < 0) 1150 goto error; 1151 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000); 1152 if (status < 0) 1153 goto error; 1154 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000); 1155 if (status < 0) 1156 goto error; 1157 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000); 1158 if (status < 0) 1159 goto error; 1160 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000); 1161 if (status < 0) 1162 goto error; 1163 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000); 1164 if (status < 0) 1165 goto error; 1166 } else { 1167 /* Enable MPEG output */ 1168 sio_pdr_mdx_cfg = 1169 ((state->m_ts_data_strength << 1170 SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003); 1171 sio_pdr_mclk_cfg = ((state->m_ts_clockk_strength << 1172 SIO_PDR_MCLK_CFG_DRIVE__B) | 1173 0x0003); 1174 1175 status = write16(state, SIO_PDR_MSTRT_CFG__A, sio_pdr_mdx_cfg); 1176 if (status < 0) 1177 goto error; 1178 1179 if (state->enable_merr_cfg) 1180 err_cfg = sio_pdr_mdx_cfg; 1181 1182 status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg); 1183 if (status < 0) 1184 goto error; 1185 status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg); 1186 if (status < 0) 1187 goto error; 1188 1189 if (state->m_enable_parallel) { 1190 /* parallel -> enable MD1 to MD7 */ 1191 status = write16(state, SIO_PDR_MD1_CFG__A, 1192 sio_pdr_mdx_cfg); 1193 if (status < 0) 1194 goto error; 1195 status = write16(state, SIO_PDR_MD2_CFG__A, 1196 sio_pdr_mdx_cfg); 1197 if (status < 0) 1198 goto error; 1199 status = write16(state, SIO_PDR_MD3_CFG__A, 1200 sio_pdr_mdx_cfg); 1201 if (status < 0) 1202 goto error; 1203 status = write16(state, SIO_PDR_MD4_CFG__A, 1204 sio_pdr_mdx_cfg); 1205 if (status < 0) 1206 goto error; 1207 status = write16(state, SIO_PDR_MD5_CFG__A, 1208 sio_pdr_mdx_cfg); 1209 if (status < 0) 1210 goto error; 1211 status = write16(state, SIO_PDR_MD6_CFG__A, 1212 sio_pdr_mdx_cfg); 1213 if (status < 0) 1214 goto error; 1215 status = write16(state, SIO_PDR_MD7_CFG__A, 1216 sio_pdr_mdx_cfg); 1217 if (status < 0) 1218 goto error; 1219 } else { 1220 sio_pdr_mdx_cfg = ((state->m_ts_data_strength << 1221 SIO_PDR_MD0_CFG_DRIVE__B) 1222 | 0x0003); 1223 /* serial -> disable MD1 to MD7 */ 1224 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000); 1225 if (status < 0) 1226 goto error; 1227 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000); 1228 if (status < 0) 1229 goto error; 1230 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000); 1231 if (status < 0) 1232 goto error; 1233 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000); 1234 if (status < 0) 1235 goto error; 1236 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000); 1237 if (status < 0) 1238 goto error; 1239 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000); 1240 if (status < 0) 1241 goto error; 1242 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000); 1243 if (status < 0) 1244 goto error; 1245 } 1246 status = write16(state, SIO_PDR_MCLK_CFG__A, sio_pdr_mclk_cfg); 1247 if (status < 0) 1248 goto error; 1249 status = write16(state, SIO_PDR_MD0_CFG__A, sio_pdr_mdx_cfg); 1250 if (status < 0) 1251 goto error; 1252 } 1253 /* Enable MB output over MPEG pads and ctl input */ 1254 status = write16(state, SIO_PDR_MON_CFG__A, 0x0000); 1255 if (status < 0) 1256 goto error; 1257 /* Write nomagic word to enable pdr reg write */ 1258 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); 1259 error: 1260 if (status < 0) 1261 pr_err("Error %d on %s\n", status, __func__); 1262 return status; 1263 } 1264 1265 static int mpegts_disable(struct drxk_state *state) 1266 { 1267 dprintk(1, "\n"); 1268 1269 return mpegts_configure_pins(state, false); 1270 } 1271 1272 static int bl_chain_cmd(struct drxk_state *state, 1273 u16 rom_offset, u16 nr_of_elements, u32 time_out) 1274 { 1275 u16 bl_status = 0; 1276 int status; 1277 unsigned long end; 1278 1279 dprintk(1, "\n"); 1280 mutex_lock(&state->mutex); 1281 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN); 1282 if (status < 0) 1283 goto error; 1284 status = write16(state, SIO_BL_CHAIN_ADDR__A, rom_offset); 1285 if (status < 0) 1286 goto error; 1287 status = write16(state, SIO_BL_CHAIN_LEN__A, nr_of_elements); 1288 if (status < 0) 1289 goto error; 1290 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON); 1291 if (status < 0) 1292 goto error; 1293 1294 end = jiffies + msecs_to_jiffies(time_out); 1295 do { 1296 usleep_range(1000, 2000); 1297 status = read16(state, SIO_BL_STATUS__A, &bl_status); 1298 if (status < 0) 1299 goto error; 1300 } while ((bl_status == 0x1) && 1301 ((time_is_after_jiffies(end)))); 1302 1303 if (bl_status == 0x1) { 1304 pr_err("SIO not ready\n"); 1305 status = -EINVAL; 1306 goto error2; 1307 } 1308 error: 1309 if (status < 0) 1310 pr_err("Error %d on %s\n", status, __func__); 1311 error2: 1312 mutex_unlock(&state->mutex); 1313 return status; 1314 } 1315 1316 1317 static int download_microcode(struct drxk_state *state, 1318 const u8 p_mc_image[], u32 length) 1319 { 1320 const u8 *p_src = p_mc_image; 1321 u32 address; 1322 u16 n_blocks; 1323 u16 block_size; 1324 u32 offset = 0; 1325 u32 i; 1326 int status = 0; 1327 1328 dprintk(1, "\n"); 1329 1330 /* down the drain (we don't care about MAGIC_WORD) */ 1331 #if 0 1332 /* For future reference */ 1333 drain = (p_src[0] << 8) | p_src[1]; 1334 #endif 1335 p_src += sizeof(u16); 1336 offset += sizeof(u16); 1337 n_blocks = (p_src[0] << 8) | p_src[1]; 1338 p_src += sizeof(u16); 1339 offset += sizeof(u16); 1340 1341 for (i = 0; i < n_blocks; i += 1) { 1342 address = (p_src[0] << 24) | (p_src[1] << 16) | 1343 (p_src[2] << 8) | p_src[3]; 1344 p_src += sizeof(u32); 1345 offset += sizeof(u32); 1346 1347 block_size = ((p_src[0] << 8) | p_src[1]) * sizeof(u16); 1348 p_src += sizeof(u16); 1349 offset += sizeof(u16); 1350 1351 #if 0 1352 /* For future reference */ 1353 flags = (p_src[0] << 8) | p_src[1]; 1354 #endif 1355 p_src += sizeof(u16); 1356 offset += sizeof(u16); 1357 1358 #if 0 1359 /* For future reference */ 1360 block_crc = (p_src[0] << 8) | p_src[1]; 1361 #endif 1362 p_src += sizeof(u16); 1363 offset += sizeof(u16); 1364 1365 if (offset + block_size > length) { 1366 pr_err("Firmware is corrupted.\n"); 1367 return -EINVAL; 1368 } 1369 1370 status = write_block(state, address, block_size, p_src); 1371 if (status < 0) { 1372 pr_err("Error %d while loading firmware\n", status); 1373 break; 1374 } 1375 p_src += block_size; 1376 offset += block_size; 1377 } 1378 return status; 1379 } 1380 1381 static int dvbt_enable_ofdm_token_ring(struct drxk_state *state, bool enable) 1382 { 1383 int status; 1384 u16 data = 0; 1385 u16 desired_ctrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON; 1386 u16 desired_status = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED; 1387 unsigned long end; 1388 1389 dprintk(1, "\n"); 1390 1391 if (!enable) { 1392 desired_ctrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF; 1393 desired_status = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN; 1394 } 1395 1396 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data); 1397 if (status >= 0 && data == desired_status) { 1398 /* tokenring already has correct status */ 1399 return status; 1400 } 1401 /* Disable/enable dvbt tokenring bridge */ 1402 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desired_ctrl); 1403 1404 end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT); 1405 do { 1406 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data); 1407 if ((status >= 0 && data == desired_status) 1408 || time_is_after_jiffies(end)) 1409 break; 1410 usleep_range(1000, 2000); 1411 } while (1); 1412 if (data != desired_status) { 1413 pr_err("SIO not ready\n"); 1414 return -EINVAL; 1415 } 1416 return status; 1417 } 1418 1419 static int mpegts_stop(struct drxk_state *state) 1420 { 1421 int status = 0; 1422 u16 fec_oc_snc_mode = 0; 1423 u16 fec_oc_ipr_mode = 0; 1424 1425 dprintk(1, "\n"); 1426 1427 /* Graceful shutdown (byte boundaries) */ 1428 status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode); 1429 if (status < 0) 1430 goto error; 1431 fec_oc_snc_mode |= FEC_OC_SNC_MODE_SHUTDOWN__M; 1432 status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode); 1433 if (status < 0) 1434 goto error; 1435 1436 /* Suppress MCLK during absence of data */ 1437 status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode); 1438 if (status < 0) 1439 goto error; 1440 fec_oc_ipr_mode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M; 1441 status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode); 1442 1443 error: 1444 if (status < 0) 1445 pr_err("Error %d on %s\n", status, __func__); 1446 1447 return status; 1448 } 1449 1450 static int scu_command(struct drxk_state *state, 1451 u16 cmd, u8 parameter_len, 1452 u16 *parameter, u8 result_len, u16 *result) 1453 { 1454 #if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15 1455 #error DRXK register mapping no longer compatible with this routine! 1456 #endif 1457 u16 cur_cmd = 0; 1458 int status = -EINVAL; 1459 unsigned long end; 1460 u8 buffer[34]; 1461 int cnt = 0, ii; 1462 const char *p; 1463 char errname[30]; 1464 1465 dprintk(1, "\n"); 1466 1467 if ((cmd == 0) || ((parameter_len > 0) && (parameter == NULL)) || 1468 ((result_len > 0) && (result == NULL))) { 1469 pr_err("Error %d on %s\n", status, __func__); 1470 return status; 1471 } 1472 1473 mutex_lock(&state->mutex); 1474 1475 /* assume that the command register is ready 1476 since it is checked afterwards */ 1477 for (ii = parameter_len - 1; ii >= 0; ii -= 1) { 1478 buffer[cnt++] = (parameter[ii] & 0xFF); 1479 buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF); 1480 } 1481 buffer[cnt++] = (cmd & 0xFF); 1482 buffer[cnt++] = ((cmd >> 8) & 0xFF); 1483 1484 write_block(state, SCU_RAM_PARAM_0__A - 1485 (parameter_len - 1), cnt, buffer); 1486 /* Wait until SCU has processed command */ 1487 end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME); 1488 do { 1489 usleep_range(1000, 2000); 1490 status = read16(state, SCU_RAM_COMMAND__A, &cur_cmd); 1491 if (status < 0) 1492 goto error; 1493 } while (!(cur_cmd == DRX_SCU_READY) && (time_is_after_jiffies(end))); 1494 if (cur_cmd != DRX_SCU_READY) { 1495 pr_err("SCU not ready\n"); 1496 status = -EIO; 1497 goto error2; 1498 } 1499 /* read results */ 1500 if ((result_len > 0) && (result != NULL)) { 1501 s16 err; 1502 int ii; 1503 1504 for (ii = result_len - 1; ii >= 0; ii -= 1) { 1505 status = read16(state, SCU_RAM_PARAM_0__A - ii, 1506 &result[ii]); 1507 if (status < 0) 1508 goto error; 1509 } 1510 1511 /* Check if an error was reported by SCU */ 1512 err = (s16)result[0]; 1513 if (err >= 0) 1514 goto error; 1515 1516 /* check for the known error codes */ 1517 switch (err) { 1518 case SCU_RESULT_UNKCMD: 1519 p = "SCU_RESULT_UNKCMD"; 1520 break; 1521 case SCU_RESULT_UNKSTD: 1522 p = "SCU_RESULT_UNKSTD"; 1523 break; 1524 case SCU_RESULT_SIZE: 1525 p = "SCU_RESULT_SIZE"; 1526 break; 1527 case SCU_RESULT_INVPAR: 1528 p = "SCU_RESULT_INVPAR"; 1529 break; 1530 default: /* Other negative values are errors */ 1531 sprintf(errname, "ERROR: %d\n", err); 1532 p = errname; 1533 } 1534 pr_err("%s while sending cmd 0x%04x with params:", p, cmd); 1535 print_hex_dump_bytes("drxk: ", DUMP_PREFIX_NONE, buffer, cnt); 1536 status = -EINVAL; 1537 goto error2; 1538 } 1539 1540 error: 1541 if (status < 0) 1542 pr_err("Error %d on %s\n", status, __func__); 1543 error2: 1544 mutex_unlock(&state->mutex); 1545 return status; 1546 } 1547 1548 static int set_iqm_af(struct drxk_state *state, bool active) 1549 { 1550 u16 data = 0; 1551 int status; 1552 1553 dprintk(1, "\n"); 1554 1555 /* Configure IQM */ 1556 status = read16(state, IQM_AF_STDBY__A, &data); 1557 if (status < 0) 1558 goto error; 1559 1560 if (!active) { 1561 data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY 1562 | IQM_AF_STDBY_STDBY_AMP_STANDBY 1563 | IQM_AF_STDBY_STDBY_PD_STANDBY 1564 | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY 1565 | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY); 1566 } else { 1567 data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY) 1568 & (~IQM_AF_STDBY_STDBY_AMP_STANDBY) 1569 & (~IQM_AF_STDBY_STDBY_PD_STANDBY) 1570 & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY) 1571 & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY) 1572 ); 1573 } 1574 status = write16(state, IQM_AF_STDBY__A, data); 1575 1576 error: 1577 if (status < 0) 1578 pr_err("Error %d on %s\n", status, __func__); 1579 return status; 1580 } 1581 1582 static int ctrl_power_mode(struct drxk_state *state, enum drx_power_mode *mode) 1583 { 1584 int status = 0; 1585 u16 sio_cc_pwd_mode = 0; 1586 1587 dprintk(1, "\n"); 1588 1589 /* Check arguments */ 1590 if (mode == NULL) 1591 return -EINVAL; 1592 1593 switch (*mode) { 1594 case DRX_POWER_UP: 1595 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_NONE; 1596 break; 1597 case DRXK_POWER_DOWN_OFDM: 1598 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OFDM; 1599 break; 1600 case DRXK_POWER_DOWN_CORE: 1601 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_CLOCK; 1602 break; 1603 case DRXK_POWER_DOWN_PLL: 1604 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_PLL; 1605 break; 1606 case DRX_POWER_DOWN: 1607 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OSC; 1608 break; 1609 default: 1610 /* Unknow sleep mode */ 1611 return -EINVAL; 1612 } 1613 1614 /* If already in requested power mode, do nothing */ 1615 if (state->m_current_power_mode == *mode) 1616 return 0; 1617 1618 /* For next steps make sure to start from DRX_POWER_UP mode */ 1619 if (state->m_current_power_mode != DRX_POWER_UP) { 1620 status = power_up_device(state); 1621 if (status < 0) 1622 goto error; 1623 status = dvbt_enable_ofdm_token_ring(state, true); 1624 if (status < 0) 1625 goto error; 1626 } 1627 1628 if (*mode == DRX_POWER_UP) { 1629 /* Restore analog & pin configuration */ 1630 } else { 1631 /* Power down to requested mode */ 1632 /* Backup some register settings */ 1633 /* Set pins with possible pull-ups connected 1634 to them in input mode */ 1635 /* Analog power down */ 1636 /* ADC power down */ 1637 /* Power down device */ 1638 /* stop all comm_exec */ 1639 /* Stop and power down previous standard */ 1640 switch (state->m_operation_mode) { 1641 case OM_DVBT: 1642 status = mpegts_stop(state); 1643 if (status < 0) 1644 goto error; 1645 status = power_down_dvbt(state, false); 1646 if (status < 0) 1647 goto error; 1648 break; 1649 case OM_QAM_ITU_A: 1650 case OM_QAM_ITU_C: 1651 status = mpegts_stop(state); 1652 if (status < 0) 1653 goto error; 1654 status = power_down_qam(state); 1655 if (status < 0) 1656 goto error; 1657 break; 1658 default: 1659 break; 1660 } 1661 status = dvbt_enable_ofdm_token_ring(state, false); 1662 if (status < 0) 1663 goto error; 1664 status = write16(state, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode); 1665 if (status < 0) 1666 goto error; 1667 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); 1668 if (status < 0) 1669 goto error; 1670 1671 if (*mode != DRXK_POWER_DOWN_OFDM) { 1672 state->m_hi_cfg_ctrl |= 1673 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; 1674 status = hi_cfg_command(state); 1675 if (status < 0) 1676 goto error; 1677 } 1678 } 1679 state->m_current_power_mode = *mode; 1680 1681 error: 1682 if (status < 0) 1683 pr_err("Error %d on %s\n", status, __func__); 1684 1685 return status; 1686 } 1687 1688 static int power_down_dvbt(struct drxk_state *state, bool set_power_mode) 1689 { 1690 enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM; 1691 u16 cmd_result = 0; 1692 u16 data = 0; 1693 int status; 1694 1695 dprintk(1, "\n"); 1696 1697 status = read16(state, SCU_COMM_EXEC__A, &data); 1698 if (status < 0) 1699 goto error; 1700 if (data == SCU_COMM_EXEC_ACTIVE) { 1701 /* Send OFDM stop command */ 1702 status = scu_command(state, 1703 SCU_RAM_COMMAND_STANDARD_OFDM 1704 | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 1705 0, NULL, 1, &cmd_result); 1706 if (status < 0) 1707 goto error; 1708 /* Send OFDM reset command */ 1709 status = scu_command(state, 1710 SCU_RAM_COMMAND_STANDARD_OFDM 1711 | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 1712 0, NULL, 1, &cmd_result); 1713 if (status < 0) 1714 goto error; 1715 } 1716 1717 /* Reset datapath for OFDM, processors first */ 1718 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); 1719 if (status < 0) 1720 goto error; 1721 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); 1722 if (status < 0) 1723 goto error; 1724 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); 1725 if (status < 0) 1726 goto error; 1727 1728 /* powerdown AFE */ 1729 status = set_iqm_af(state, false); 1730 if (status < 0) 1731 goto error; 1732 1733 /* powerdown to OFDM mode */ 1734 if (set_power_mode) { 1735 status = ctrl_power_mode(state, &power_mode); 1736 if (status < 0) 1737 goto error; 1738 } 1739 error: 1740 if (status < 0) 1741 pr_err("Error %d on %s\n", status, __func__); 1742 return status; 1743 } 1744 1745 static int setoperation_mode(struct drxk_state *state, 1746 enum operation_mode o_mode) 1747 { 1748 int status = 0; 1749 1750 dprintk(1, "\n"); 1751 /* 1752 Stop and power down previous standard 1753 TODO investigate total power down instead of partial 1754 power down depending on "previous" standard. 1755 */ 1756 1757 /* disable HW lock indicator */ 1758 status = write16(state, SCU_RAM_GPIO__A, 1759 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); 1760 if (status < 0) 1761 goto error; 1762 1763 /* Device is already at the required mode */ 1764 if (state->m_operation_mode == o_mode) 1765 return 0; 1766 1767 switch (state->m_operation_mode) { 1768 /* OM_NONE was added for start up */ 1769 case OM_NONE: 1770 break; 1771 case OM_DVBT: 1772 status = mpegts_stop(state); 1773 if (status < 0) 1774 goto error; 1775 status = power_down_dvbt(state, true); 1776 if (status < 0) 1777 goto error; 1778 state->m_operation_mode = OM_NONE; 1779 break; 1780 case OM_QAM_ITU_A: /* fallthrough */ 1781 case OM_QAM_ITU_C: 1782 status = mpegts_stop(state); 1783 if (status < 0) 1784 goto error; 1785 status = power_down_qam(state); 1786 if (status < 0) 1787 goto error; 1788 state->m_operation_mode = OM_NONE; 1789 break; 1790 case OM_QAM_ITU_B: 1791 default: 1792 status = -EINVAL; 1793 goto error; 1794 } 1795 1796 /* 1797 Power up new standard 1798 */ 1799 switch (o_mode) { 1800 case OM_DVBT: 1801 dprintk(1, ": DVB-T\n"); 1802 state->m_operation_mode = o_mode; 1803 status = set_dvbt_standard(state, o_mode); 1804 if (status < 0) 1805 goto error; 1806 break; 1807 case OM_QAM_ITU_A: /* fallthrough */ 1808 case OM_QAM_ITU_C: 1809 dprintk(1, ": DVB-C Annex %c\n", 1810 (state->m_operation_mode == OM_QAM_ITU_A) ? 'A' : 'C'); 1811 state->m_operation_mode = o_mode; 1812 status = set_qam_standard(state, o_mode); 1813 if (status < 0) 1814 goto error; 1815 break; 1816 case OM_QAM_ITU_B: 1817 default: 1818 status = -EINVAL; 1819 } 1820 error: 1821 if (status < 0) 1822 pr_err("Error %d on %s\n", status, __func__); 1823 return status; 1824 } 1825 1826 static int start(struct drxk_state *state, s32 offset_freq, 1827 s32 intermediate_frequency) 1828 { 1829 int status = -EINVAL; 1830 1831 u16 i_freqk_hz; 1832 s32 offsetk_hz = offset_freq / 1000; 1833 1834 dprintk(1, "\n"); 1835 if (state->m_drxk_state != DRXK_STOPPED && 1836 state->m_drxk_state != DRXK_DTV_STARTED) 1837 goto error; 1838 1839 state->m_b_mirror_freq_spect = (state->props.inversion == INVERSION_ON); 1840 1841 if (intermediate_frequency < 0) { 1842 state->m_b_mirror_freq_spect = !state->m_b_mirror_freq_spect; 1843 intermediate_frequency = -intermediate_frequency; 1844 } 1845 1846 switch (state->m_operation_mode) { 1847 case OM_QAM_ITU_A: 1848 case OM_QAM_ITU_C: 1849 i_freqk_hz = (intermediate_frequency / 1000); 1850 status = set_qam(state, i_freqk_hz, offsetk_hz); 1851 if (status < 0) 1852 goto error; 1853 state->m_drxk_state = DRXK_DTV_STARTED; 1854 break; 1855 case OM_DVBT: 1856 i_freqk_hz = (intermediate_frequency / 1000); 1857 status = mpegts_stop(state); 1858 if (status < 0) 1859 goto error; 1860 status = set_dvbt(state, i_freqk_hz, offsetk_hz); 1861 if (status < 0) 1862 goto error; 1863 status = dvbt_start(state); 1864 if (status < 0) 1865 goto error; 1866 state->m_drxk_state = DRXK_DTV_STARTED; 1867 break; 1868 default: 1869 break; 1870 } 1871 error: 1872 if (status < 0) 1873 pr_err("Error %d on %s\n", status, __func__); 1874 return status; 1875 } 1876 1877 static int shut_down(struct drxk_state *state) 1878 { 1879 dprintk(1, "\n"); 1880 1881 mpegts_stop(state); 1882 return 0; 1883 } 1884 1885 static int get_lock_status(struct drxk_state *state, u32 *p_lock_status) 1886 { 1887 int status = -EINVAL; 1888 1889 dprintk(1, "\n"); 1890 1891 if (p_lock_status == NULL) 1892 goto error; 1893 1894 *p_lock_status = NOT_LOCKED; 1895 1896 /* define the SCU command code */ 1897 switch (state->m_operation_mode) { 1898 case OM_QAM_ITU_A: 1899 case OM_QAM_ITU_B: 1900 case OM_QAM_ITU_C: 1901 status = get_qam_lock_status(state, p_lock_status); 1902 break; 1903 case OM_DVBT: 1904 status = get_dvbt_lock_status(state, p_lock_status); 1905 break; 1906 default: 1907 break; 1908 } 1909 error: 1910 if (status < 0) 1911 pr_err("Error %d on %s\n", status, __func__); 1912 return status; 1913 } 1914 1915 static int mpegts_start(struct drxk_state *state) 1916 { 1917 int status; 1918 1919 u16 fec_oc_snc_mode = 0; 1920 1921 /* Allow OC to sync again */ 1922 status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode); 1923 if (status < 0) 1924 goto error; 1925 fec_oc_snc_mode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M; 1926 status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode); 1927 if (status < 0) 1928 goto error; 1929 status = write16(state, FEC_OC_SNC_UNLOCK__A, 1); 1930 error: 1931 if (status < 0) 1932 pr_err("Error %d on %s\n", status, __func__); 1933 return status; 1934 } 1935 1936 static int mpegts_dto_init(struct drxk_state *state) 1937 { 1938 int status; 1939 1940 dprintk(1, "\n"); 1941 1942 /* Rate integration settings */ 1943 status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000); 1944 if (status < 0) 1945 goto error; 1946 status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C); 1947 if (status < 0) 1948 goto error; 1949 status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A); 1950 if (status < 0) 1951 goto error; 1952 status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008); 1953 if (status < 0) 1954 goto error; 1955 status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006); 1956 if (status < 0) 1957 goto error; 1958 status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680); 1959 if (status < 0) 1960 goto error; 1961 status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080); 1962 if (status < 0) 1963 goto error; 1964 status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4); 1965 if (status < 0) 1966 goto error; 1967 1968 /* Additional configuration */ 1969 status = write16(state, FEC_OC_OCR_INVERT__A, 0); 1970 if (status < 0) 1971 goto error; 1972 status = write16(state, FEC_OC_SNC_LWM__A, 2); 1973 if (status < 0) 1974 goto error; 1975 status = write16(state, FEC_OC_SNC_HWM__A, 12); 1976 error: 1977 if (status < 0) 1978 pr_err("Error %d on %s\n", status, __func__); 1979 1980 return status; 1981 } 1982 1983 static int mpegts_dto_setup(struct drxk_state *state, 1984 enum operation_mode o_mode) 1985 { 1986 int status; 1987 1988 u16 fec_oc_reg_mode = 0; /* FEC_OC_MODE register value */ 1989 u16 fec_oc_reg_ipr_mode = 0; /* FEC_OC_IPR_MODE register value */ 1990 u16 fec_oc_dto_mode = 0; /* FEC_OC_IPR_INVERT register value */ 1991 u16 fec_oc_fct_mode = 0; /* FEC_OC_IPR_INVERT register value */ 1992 u16 fec_oc_dto_period = 2; /* FEC_OC_IPR_INVERT register value */ 1993 u16 fec_oc_dto_burst_len = 188; /* FEC_OC_IPR_INVERT register value */ 1994 u32 fec_oc_rcn_ctl_rate = 0; /* FEC_OC_IPR_INVERT register value */ 1995 u16 fec_oc_tmd_mode = 0; 1996 u16 fec_oc_tmd_int_upd_rate = 0; 1997 u32 max_bit_rate = 0; 1998 bool static_clk = false; 1999 2000 dprintk(1, "\n"); 2001 2002 /* Check insertion of the Reed-Solomon parity bytes */ 2003 status = read16(state, FEC_OC_MODE__A, &fec_oc_reg_mode); 2004 if (status < 0) 2005 goto error; 2006 status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode); 2007 if (status < 0) 2008 goto error; 2009 fec_oc_reg_mode &= (~FEC_OC_MODE_PARITY__M); 2010 fec_oc_reg_ipr_mode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M); 2011 if (state->m_insert_rs_byte) { 2012 /* enable parity symbol forward */ 2013 fec_oc_reg_mode |= FEC_OC_MODE_PARITY__M; 2014 /* MVAL disable during parity bytes */ 2015 fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M; 2016 /* TS burst length to 204 */ 2017 fec_oc_dto_burst_len = 204; 2018 } 2019 2020 /* Check serial or parallel output */ 2021 fec_oc_reg_ipr_mode &= (~(FEC_OC_IPR_MODE_SERIAL__M)); 2022 if (!state->m_enable_parallel) { 2023 /* MPEG data output is serial -> set ipr_mode[0] */ 2024 fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_SERIAL__M; 2025 } 2026 2027 switch (o_mode) { 2028 case OM_DVBT: 2029 max_bit_rate = state->m_dvbt_bitrate; 2030 fec_oc_tmd_mode = 3; 2031 fec_oc_rcn_ctl_rate = 0xC00000; 2032 static_clk = state->m_dvbt_static_clk; 2033 break; 2034 case OM_QAM_ITU_A: /* fallthrough */ 2035 case OM_QAM_ITU_C: 2036 fec_oc_tmd_mode = 0x0004; 2037 fec_oc_rcn_ctl_rate = 0xD2B4EE; /* good for >63 Mb/s */ 2038 max_bit_rate = state->m_dvbc_bitrate; 2039 static_clk = state->m_dvbc_static_clk; 2040 break; 2041 default: 2042 status = -EINVAL; 2043 } /* switch (standard) */ 2044 if (status < 0) 2045 goto error; 2046 2047 /* Configure DTO's */ 2048 if (static_clk) { 2049 u32 bit_rate = 0; 2050 2051 /* Rational DTO for MCLK source (static MCLK rate), 2052 Dynamic DTO for optimal grouping 2053 (avoid intra-packet gaps), 2054 DTO offset enable to sync TS burst with MSTRT */ 2055 fec_oc_dto_mode = (FEC_OC_DTO_MODE_DYNAMIC__M | 2056 FEC_OC_DTO_MODE_OFFSET_ENABLE__M); 2057 fec_oc_fct_mode = (FEC_OC_FCT_MODE_RAT_ENA__M | 2058 FEC_OC_FCT_MODE_VIRT_ENA__M); 2059 2060 /* Check user defined bitrate */ 2061 bit_rate = max_bit_rate; 2062 if (bit_rate > 75900000UL) { /* max is 75.9 Mb/s */ 2063 bit_rate = 75900000UL; 2064 } 2065 /* Rational DTO period: 2066 dto_period = (Fsys / bitrate) - 2 2067 2068 result should be floored, 2069 to make sure >= requested bitrate 2070 */ 2071 fec_oc_dto_period = (u16) (((state->m_sys_clock_freq) 2072 * 1000) / bit_rate); 2073 if (fec_oc_dto_period <= 2) 2074 fec_oc_dto_period = 0; 2075 else 2076 fec_oc_dto_period -= 2; 2077 fec_oc_tmd_int_upd_rate = 8; 2078 } else { 2079 /* (commonAttr->static_clk == false) => dynamic mode */ 2080 fec_oc_dto_mode = FEC_OC_DTO_MODE_DYNAMIC__M; 2081 fec_oc_fct_mode = FEC_OC_FCT_MODE__PRE; 2082 fec_oc_tmd_int_upd_rate = 5; 2083 } 2084 2085 /* Write appropriate registers with requested configuration */ 2086 status = write16(state, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len); 2087 if (status < 0) 2088 goto error; 2089 status = write16(state, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period); 2090 if (status < 0) 2091 goto error; 2092 status = write16(state, FEC_OC_DTO_MODE__A, fec_oc_dto_mode); 2093 if (status < 0) 2094 goto error; 2095 status = write16(state, FEC_OC_FCT_MODE__A, fec_oc_fct_mode); 2096 if (status < 0) 2097 goto error; 2098 status = write16(state, FEC_OC_MODE__A, fec_oc_reg_mode); 2099 if (status < 0) 2100 goto error; 2101 status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode); 2102 if (status < 0) 2103 goto error; 2104 2105 /* Rate integration settings */ 2106 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fec_oc_rcn_ctl_rate); 2107 if (status < 0) 2108 goto error; 2109 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, 2110 fec_oc_tmd_int_upd_rate); 2111 if (status < 0) 2112 goto error; 2113 status = write16(state, FEC_OC_TMD_MODE__A, fec_oc_tmd_mode); 2114 error: 2115 if (status < 0) 2116 pr_err("Error %d on %s\n", status, __func__); 2117 return status; 2118 } 2119 2120 static int mpegts_configure_polarity(struct drxk_state *state) 2121 { 2122 u16 fec_oc_reg_ipr_invert = 0; 2123 2124 /* Data mask for the output data byte */ 2125 u16 invert_data_mask = 2126 FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M | 2127 FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M | 2128 FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M | 2129 FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M; 2130 2131 dprintk(1, "\n"); 2132 2133 /* Control selective inversion of output bits */ 2134 fec_oc_reg_ipr_invert &= (~(invert_data_mask)); 2135 if (state->m_invert_data) 2136 fec_oc_reg_ipr_invert |= invert_data_mask; 2137 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MERR__M)); 2138 if (state->m_invert_err) 2139 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MERR__M; 2140 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MSTRT__M)); 2141 if (state->m_invert_str) 2142 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MSTRT__M; 2143 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MVAL__M)); 2144 if (state->m_invert_val) 2145 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MVAL__M; 2146 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MCLK__M)); 2147 if (state->m_invert_clk) 2148 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MCLK__M; 2149 2150 return write16(state, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert); 2151 } 2152 2153 #define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000 2154 2155 static int set_agc_rf(struct drxk_state *state, 2156 struct s_cfg_agc *p_agc_cfg, bool is_dtv) 2157 { 2158 int status = -EINVAL; 2159 u16 data = 0; 2160 struct s_cfg_agc *p_if_agc_settings; 2161 2162 dprintk(1, "\n"); 2163 2164 if (p_agc_cfg == NULL) 2165 goto error; 2166 2167 switch (p_agc_cfg->ctrl_mode) { 2168 case DRXK_AGC_CTRL_AUTO: 2169 /* Enable RF AGC DAC */ 2170 status = read16(state, IQM_AF_STDBY__A, &data); 2171 if (status < 0) 2172 goto error; 2173 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; 2174 status = write16(state, IQM_AF_STDBY__A, data); 2175 if (status < 0) 2176 goto error; 2177 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); 2178 if (status < 0) 2179 goto error; 2180 2181 /* Enable SCU RF AGC loop */ 2182 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; 2183 2184 /* Polarity */ 2185 if (state->m_rf_agc_pol) 2186 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; 2187 else 2188 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; 2189 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); 2190 if (status < 0) 2191 goto error; 2192 2193 /* Set speed (using complementary reduction value) */ 2194 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data); 2195 if (status < 0) 2196 goto error; 2197 2198 data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M; 2199 data |= (~(p_agc_cfg->speed << 2200 SCU_RAM_AGC_KI_RED_RAGC_RED__B) 2201 & SCU_RAM_AGC_KI_RED_RAGC_RED__M); 2202 2203 status = write16(state, SCU_RAM_AGC_KI_RED__A, data); 2204 if (status < 0) 2205 goto error; 2206 2207 if (is_dvbt(state)) 2208 p_if_agc_settings = &state->m_dvbt_if_agc_cfg; 2209 else if (is_qam(state)) 2210 p_if_agc_settings = &state->m_qam_if_agc_cfg; 2211 else 2212 p_if_agc_settings = &state->m_atv_if_agc_cfg; 2213 if (p_if_agc_settings == NULL) { 2214 status = -EINVAL; 2215 goto error; 2216 } 2217 2218 /* Set TOP, only if IF-AGC is in AUTO mode */ 2219 if (p_if_agc_settings->ctrl_mode == DRXK_AGC_CTRL_AUTO) { 2220 status = write16(state, 2221 SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 2222 p_agc_cfg->top); 2223 if (status < 0) 2224 goto error; 2225 } 2226 2227 /* Cut-Off current */ 2228 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 2229 p_agc_cfg->cut_off_current); 2230 if (status < 0) 2231 goto error; 2232 2233 /* Max. output level */ 2234 status = write16(state, SCU_RAM_AGC_RF_MAX__A, 2235 p_agc_cfg->max_output_level); 2236 if (status < 0) 2237 goto error; 2238 2239 break; 2240 2241 case DRXK_AGC_CTRL_USER: 2242 /* Enable RF AGC DAC */ 2243 status = read16(state, IQM_AF_STDBY__A, &data); 2244 if (status < 0) 2245 goto error; 2246 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; 2247 status = write16(state, IQM_AF_STDBY__A, data); 2248 if (status < 0) 2249 goto error; 2250 2251 /* Disable SCU RF AGC loop */ 2252 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); 2253 if (status < 0) 2254 goto error; 2255 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; 2256 if (state->m_rf_agc_pol) 2257 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; 2258 else 2259 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; 2260 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); 2261 if (status < 0) 2262 goto error; 2263 2264 /* SCU c.o.c. to 0, enabling full control range */ 2265 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0); 2266 if (status < 0) 2267 goto error; 2268 2269 /* Write value to output pin */ 2270 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 2271 p_agc_cfg->output_level); 2272 if (status < 0) 2273 goto error; 2274 break; 2275 2276 case DRXK_AGC_CTRL_OFF: 2277 /* Disable RF AGC DAC */ 2278 status = read16(state, IQM_AF_STDBY__A, &data); 2279 if (status < 0) 2280 goto error; 2281 data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; 2282 status = write16(state, IQM_AF_STDBY__A, data); 2283 if (status < 0) 2284 goto error; 2285 2286 /* Disable SCU RF AGC loop */ 2287 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); 2288 if (status < 0) 2289 goto error; 2290 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; 2291 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); 2292 if (status < 0) 2293 goto error; 2294 break; 2295 2296 default: 2297 status = -EINVAL; 2298 2299 } 2300 error: 2301 if (status < 0) 2302 pr_err("Error %d on %s\n", status, __func__); 2303 return status; 2304 } 2305 2306 #define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000 2307 2308 static int set_agc_if(struct drxk_state *state, 2309 struct s_cfg_agc *p_agc_cfg, bool is_dtv) 2310 { 2311 u16 data = 0; 2312 int status = 0; 2313 struct s_cfg_agc *p_rf_agc_settings; 2314 2315 dprintk(1, "\n"); 2316 2317 switch (p_agc_cfg->ctrl_mode) { 2318 case DRXK_AGC_CTRL_AUTO: 2319 2320 /* Enable IF AGC DAC */ 2321 status = read16(state, IQM_AF_STDBY__A, &data); 2322 if (status < 0) 2323 goto error; 2324 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; 2325 status = write16(state, IQM_AF_STDBY__A, data); 2326 if (status < 0) 2327 goto error; 2328 2329 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); 2330 if (status < 0) 2331 goto error; 2332 2333 /* Enable SCU IF AGC loop */ 2334 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; 2335 2336 /* Polarity */ 2337 if (state->m_if_agc_pol) 2338 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; 2339 else 2340 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; 2341 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); 2342 if (status < 0) 2343 goto error; 2344 2345 /* Set speed (using complementary reduction value) */ 2346 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data); 2347 if (status < 0) 2348 goto error; 2349 data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M; 2350 data |= (~(p_agc_cfg->speed << 2351 SCU_RAM_AGC_KI_RED_IAGC_RED__B) 2352 & SCU_RAM_AGC_KI_RED_IAGC_RED__M); 2353 2354 status = write16(state, SCU_RAM_AGC_KI_RED__A, data); 2355 if (status < 0) 2356 goto error; 2357 2358 if (is_qam(state)) 2359 p_rf_agc_settings = &state->m_qam_rf_agc_cfg; 2360 else 2361 p_rf_agc_settings = &state->m_atv_rf_agc_cfg; 2362 if (p_rf_agc_settings == NULL) 2363 return -1; 2364 /* Restore TOP */ 2365 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 2366 p_rf_agc_settings->top); 2367 if (status < 0) 2368 goto error; 2369 break; 2370 2371 case DRXK_AGC_CTRL_USER: 2372 2373 /* Enable IF AGC DAC */ 2374 status = read16(state, IQM_AF_STDBY__A, &data); 2375 if (status < 0) 2376 goto error; 2377 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; 2378 status = write16(state, IQM_AF_STDBY__A, data); 2379 if (status < 0) 2380 goto error; 2381 2382 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); 2383 if (status < 0) 2384 goto error; 2385 2386 /* Disable SCU IF AGC loop */ 2387 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; 2388 2389 /* Polarity */ 2390 if (state->m_if_agc_pol) 2391 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; 2392 else 2393 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; 2394 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); 2395 if (status < 0) 2396 goto error; 2397 2398 /* Write value to output pin */ 2399 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 2400 p_agc_cfg->output_level); 2401 if (status < 0) 2402 goto error; 2403 break; 2404 2405 case DRXK_AGC_CTRL_OFF: 2406 2407 /* Disable If AGC DAC */ 2408 status = read16(state, IQM_AF_STDBY__A, &data); 2409 if (status < 0) 2410 goto error; 2411 data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; 2412 status = write16(state, IQM_AF_STDBY__A, data); 2413 if (status < 0) 2414 goto error; 2415 2416 /* Disable SCU IF AGC loop */ 2417 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); 2418 if (status < 0) 2419 goto error; 2420 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; 2421 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); 2422 if (status < 0) 2423 goto error; 2424 break; 2425 } /* switch (agcSettingsIf->ctrl_mode) */ 2426 2427 /* always set the top to support 2428 configurations without if-loop */ 2429 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_cfg->top); 2430 error: 2431 if (status < 0) 2432 pr_err("Error %d on %s\n", status, __func__); 2433 return status; 2434 } 2435 2436 static int get_qam_signal_to_noise(struct drxk_state *state, 2437 s32 *p_signal_to_noise) 2438 { 2439 int status = 0; 2440 u16 qam_sl_err_power = 0; /* accum. error between 2441 raw and sliced symbols */ 2442 u32 qam_sl_sig_power = 0; /* used for MER, depends of 2443 QAM modulation */ 2444 u32 qam_sl_mer = 0; /* QAM MER */ 2445 2446 dprintk(1, "\n"); 2447 2448 /* MER calculation */ 2449 2450 /* get the register value needed for MER */ 2451 status = read16(state, QAM_SL_ERR_POWER__A, &qam_sl_err_power); 2452 if (status < 0) { 2453 pr_err("Error %d on %s\n", status, __func__); 2454 return -EINVAL; 2455 } 2456 2457 switch (state->props.modulation) { 2458 case QAM_16: 2459 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM16 << 2; 2460 break; 2461 case QAM_32: 2462 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM32 << 2; 2463 break; 2464 case QAM_64: 2465 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM64 << 2; 2466 break; 2467 case QAM_128: 2468 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM128 << 2; 2469 break; 2470 default: 2471 case QAM_256: 2472 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM256 << 2; 2473 break; 2474 } 2475 2476 if (qam_sl_err_power > 0) { 2477 qam_sl_mer = log10times100(qam_sl_sig_power) - 2478 log10times100((u32) qam_sl_err_power); 2479 } 2480 *p_signal_to_noise = qam_sl_mer; 2481 2482 return status; 2483 } 2484 2485 static int get_dvbt_signal_to_noise(struct drxk_state *state, 2486 s32 *p_signal_to_noise) 2487 { 2488 int status; 2489 u16 reg_data = 0; 2490 u32 eq_reg_td_sqr_err_i = 0; 2491 u32 eq_reg_td_sqr_err_q = 0; 2492 u16 eq_reg_td_sqr_err_exp = 0; 2493 u16 eq_reg_td_tps_pwr_ofs = 0; 2494 u16 eq_reg_td_req_smb_cnt = 0; 2495 u32 tps_cnt = 0; 2496 u32 sqr_err_iq = 0; 2497 u32 a = 0; 2498 u32 b = 0; 2499 u32 c = 0; 2500 u32 i_mer = 0; 2501 u16 transmission_params = 0; 2502 2503 dprintk(1, "\n"); 2504 2505 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, 2506 &eq_reg_td_tps_pwr_ofs); 2507 if (status < 0) 2508 goto error; 2509 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, 2510 &eq_reg_td_req_smb_cnt); 2511 if (status < 0) 2512 goto error; 2513 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, 2514 &eq_reg_td_sqr_err_exp); 2515 if (status < 0) 2516 goto error; 2517 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, 2518 ®_data); 2519 if (status < 0) 2520 goto error; 2521 /* Extend SQR_ERR_I operational range */ 2522 eq_reg_td_sqr_err_i = (u32) reg_data; 2523 if ((eq_reg_td_sqr_err_exp > 11) && 2524 (eq_reg_td_sqr_err_i < 0x00000FFFUL)) { 2525 eq_reg_td_sqr_err_i += 0x00010000UL; 2526 } 2527 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, ®_data); 2528 if (status < 0) 2529 goto error; 2530 /* Extend SQR_ERR_Q operational range */ 2531 eq_reg_td_sqr_err_q = (u32) reg_data; 2532 if ((eq_reg_td_sqr_err_exp > 11) && 2533 (eq_reg_td_sqr_err_q < 0x00000FFFUL)) 2534 eq_reg_td_sqr_err_q += 0x00010000UL; 2535 2536 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, 2537 &transmission_params); 2538 if (status < 0) 2539 goto error; 2540 2541 /* Check input data for MER */ 2542 2543 /* MER calculation (in 0.1 dB) without math.h */ 2544 if ((eq_reg_td_tps_pwr_ofs == 0) || (eq_reg_td_req_smb_cnt == 0)) 2545 i_mer = 0; 2546 else if ((eq_reg_td_sqr_err_i + eq_reg_td_sqr_err_q) == 0) { 2547 /* No error at all, this must be the HW reset value 2548 * Apparently no first measurement yet 2549 * Set MER to 0.0 */ 2550 i_mer = 0; 2551 } else { 2552 sqr_err_iq = (eq_reg_td_sqr_err_i + eq_reg_td_sqr_err_q) << 2553 eq_reg_td_sqr_err_exp; 2554 if ((transmission_params & 2555 OFDM_SC_RA_RAM_OP_PARAM_MODE__M) 2556 == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K) 2557 tps_cnt = 17; 2558 else 2559 tps_cnt = 68; 2560 2561 /* IMER = 100 * log10 (x) 2562 where x = (eq_reg_td_tps_pwr_ofs^2 * 2563 eq_reg_td_req_smb_cnt * tps_cnt)/sqr_err_iq 2564 2565 => IMER = a + b -c 2566 where a = 100 * log10 (eq_reg_td_tps_pwr_ofs^2) 2567 b = 100 * log10 (eq_reg_td_req_smb_cnt * tps_cnt) 2568 c = 100 * log10 (sqr_err_iq) 2569 */ 2570 2571 /* log(x) x = 9bits * 9bits->18 bits */ 2572 a = log10times100(eq_reg_td_tps_pwr_ofs * 2573 eq_reg_td_tps_pwr_ofs); 2574 /* log(x) x = 16bits * 7bits->23 bits */ 2575 b = log10times100(eq_reg_td_req_smb_cnt * tps_cnt); 2576 /* log(x) x = (16bits + 16bits) << 15 ->32 bits */ 2577 c = log10times100(sqr_err_iq); 2578 2579 i_mer = a + b - c; 2580 } 2581 *p_signal_to_noise = i_mer; 2582 2583 error: 2584 if (status < 0) 2585 pr_err("Error %d on %s\n", status, __func__); 2586 return status; 2587 } 2588 2589 static int get_signal_to_noise(struct drxk_state *state, s32 *p_signal_to_noise) 2590 { 2591 dprintk(1, "\n"); 2592 2593 *p_signal_to_noise = 0; 2594 switch (state->m_operation_mode) { 2595 case OM_DVBT: 2596 return get_dvbt_signal_to_noise(state, p_signal_to_noise); 2597 case OM_QAM_ITU_A: 2598 case OM_QAM_ITU_C: 2599 return get_qam_signal_to_noise(state, p_signal_to_noise); 2600 default: 2601 break; 2602 } 2603 return 0; 2604 } 2605 2606 #if 0 2607 static int get_dvbt_quality(struct drxk_state *state, s32 *p_quality) 2608 { 2609 /* SNR Values for quasi errorfree reception rom Nordig 2.2 */ 2610 int status = 0; 2611 2612 dprintk(1, "\n"); 2613 2614 static s32 QE_SN[] = { 2615 51, /* QPSK 1/2 */ 2616 69, /* QPSK 2/3 */ 2617 79, /* QPSK 3/4 */ 2618 89, /* QPSK 5/6 */ 2619 97, /* QPSK 7/8 */ 2620 108, /* 16-QAM 1/2 */ 2621 131, /* 16-QAM 2/3 */ 2622 146, /* 16-QAM 3/4 */ 2623 156, /* 16-QAM 5/6 */ 2624 160, /* 16-QAM 7/8 */ 2625 165, /* 64-QAM 1/2 */ 2626 187, /* 64-QAM 2/3 */ 2627 202, /* 64-QAM 3/4 */ 2628 216, /* 64-QAM 5/6 */ 2629 225, /* 64-QAM 7/8 */ 2630 }; 2631 2632 *p_quality = 0; 2633 2634 do { 2635 s32 signal_to_noise = 0; 2636 u16 constellation = 0; 2637 u16 code_rate = 0; 2638 u32 signal_to_noise_rel; 2639 u32 ber_quality; 2640 2641 status = get_dvbt_signal_to_noise(state, &signal_to_noise); 2642 if (status < 0) 2643 break; 2644 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A, 2645 &constellation); 2646 if (status < 0) 2647 break; 2648 constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M; 2649 2650 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A, 2651 &code_rate); 2652 if (status < 0) 2653 break; 2654 code_rate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M; 2655 2656 if (constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM || 2657 code_rate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8) 2658 break; 2659 signal_to_noise_rel = signal_to_noise - 2660 QE_SN[constellation * 5 + code_rate]; 2661 ber_quality = 100; 2662 2663 if (signal_to_noise_rel < -70) 2664 *p_quality = 0; 2665 else if (signal_to_noise_rel < 30) 2666 *p_quality = ((signal_to_noise_rel + 70) * 2667 ber_quality) / 100; 2668 else 2669 *p_quality = ber_quality; 2670 } while (0); 2671 return 0; 2672 }; 2673 2674 static int get_dvbc_quality(struct drxk_state *state, s32 *p_quality) 2675 { 2676 int status = 0; 2677 *p_quality = 0; 2678 2679 dprintk(1, "\n"); 2680 2681 do { 2682 u32 signal_to_noise = 0; 2683 u32 ber_quality = 100; 2684 u32 signal_to_noise_rel = 0; 2685 2686 status = get_qam_signal_to_noise(state, &signal_to_noise); 2687 if (status < 0) 2688 break; 2689 2690 switch (state->props.modulation) { 2691 case QAM_16: 2692 signal_to_noise_rel = signal_to_noise - 200; 2693 break; 2694 case QAM_32: 2695 signal_to_noise_rel = signal_to_noise - 230; 2696 break; /* Not in NorDig */ 2697 case QAM_64: 2698 signal_to_noise_rel = signal_to_noise - 260; 2699 break; 2700 case QAM_128: 2701 signal_to_noise_rel = signal_to_noise - 290; 2702 break; 2703 default: 2704 case QAM_256: 2705 signal_to_noise_rel = signal_to_noise - 320; 2706 break; 2707 } 2708 2709 if (signal_to_noise_rel < -70) 2710 *p_quality = 0; 2711 else if (signal_to_noise_rel < 30) 2712 *p_quality = ((signal_to_noise_rel + 70) * 2713 ber_quality) / 100; 2714 else 2715 *p_quality = ber_quality; 2716 } while (0); 2717 2718 return status; 2719 } 2720 2721 static int get_quality(struct drxk_state *state, s32 *p_quality) 2722 { 2723 dprintk(1, "\n"); 2724 2725 switch (state->m_operation_mode) { 2726 case OM_DVBT: 2727 return get_dvbt_quality(state, p_quality); 2728 case OM_QAM_ITU_A: 2729 return get_dvbc_quality(state, p_quality); 2730 default: 2731 break; 2732 } 2733 2734 return 0; 2735 } 2736 #endif 2737 2738 /* Free data ram in SIO HI */ 2739 #define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040 2740 #define SIO_HI_RA_RAM_USR_END__A 0x420060 2741 2742 #define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A) 2743 #define DRXK_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7) 2744 #define DRXK_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 2745 #define DRXK_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 2746 2747 #define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr) >> 22) & 0x3F) 2748 #define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F) 2749 #define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF) 2750 2751 static int ConfigureI2CBridge(struct drxk_state *state, bool b_enable_bridge) 2752 { 2753 int status = -EINVAL; 2754 2755 dprintk(1, "\n"); 2756 2757 if (state->m_drxk_state == DRXK_UNINITIALIZED) 2758 return 0; 2759 if (state->m_drxk_state == DRXK_POWERED_DOWN) 2760 goto error; 2761 2762 if (state->no_i2c_bridge) 2763 return 0; 2764 2765 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, 2766 SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY); 2767 if (status < 0) 2768 goto error; 2769 if (b_enable_bridge) { 2770 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, 2771 SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED); 2772 if (status < 0) 2773 goto error; 2774 } else { 2775 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, 2776 SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN); 2777 if (status < 0) 2778 goto error; 2779 } 2780 2781 status = hi_command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, NULL); 2782 2783 error: 2784 if (status < 0) 2785 pr_err("Error %d on %s\n", status, __func__); 2786 return status; 2787 } 2788 2789 static int set_pre_saw(struct drxk_state *state, 2790 struct s_cfg_pre_saw *p_pre_saw_cfg) 2791 { 2792 int status = -EINVAL; 2793 2794 dprintk(1, "\n"); 2795 2796 if ((p_pre_saw_cfg == NULL) 2797 || (p_pre_saw_cfg->reference > IQM_AF_PDREF__M)) 2798 goto error; 2799 2800 status = write16(state, IQM_AF_PDREF__A, p_pre_saw_cfg->reference); 2801 error: 2802 if (status < 0) 2803 pr_err("Error %d on %s\n", status, __func__); 2804 return status; 2805 } 2806 2807 static int bl_direct_cmd(struct drxk_state *state, u32 target_addr, 2808 u16 rom_offset, u16 nr_of_elements, u32 time_out) 2809 { 2810 u16 bl_status = 0; 2811 u16 offset = (u16) ((target_addr >> 0) & 0x00FFFF); 2812 u16 blockbank = (u16) ((target_addr >> 16) & 0x000FFF); 2813 int status; 2814 unsigned long end; 2815 2816 dprintk(1, "\n"); 2817 2818 mutex_lock(&state->mutex); 2819 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT); 2820 if (status < 0) 2821 goto error; 2822 status = write16(state, SIO_BL_TGT_HDR__A, blockbank); 2823 if (status < 0) 2824 goto error; 2825 status = write16(state, SIO_BL_TGT_ADDR__A, offset); 2826 if (status < 0) 2827 goto error; 2828 status = write16(state, SIO_BL_SRC_ADDR__A, rom_offset); 2829 if (status < 0) 2830 goto error; 2831 status = write16(state, SIO_BL_SRC_LEN__A, nr_of_elements); 2832 if (status < 0) 2833 goto error; 2834 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON); 2835 if (status < 0) 2836 goto error; 2837 2838 end = jiffies + msecs_to_jiffies(time_out); 2839 do { 2840 status = read16(state, SIO_BL_STATUS__A, &bl_status); 2841 if (status < 0) 2842 goto error; 2843 } while ((bl_status == 0x1) && time_is_after_jiffies(end)); 2844 if (bl_status == 0x1) { 2845 pr_err("SIO not ready\n"); 2846 status = -EINVAL; 2847 goto error2; 2848 } 2849 error: 2850 if (status < 0) 2851 pr_err("Error %d on %s\n", status, __func__); 2852 error2: 2853 mutex_unlock(&state->mutex); 2854 return status; 2855 2856 } 2857 2858 static int adc_sync_measurement(struct drxk_state *state, u16 *count) 2859 { 2860 u16 data = 0; 2861 int status; 2862 2863 dprintk(1, "\n"); 2864 2865 /* start measurement */ 2866 status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE); 2867 if (status < 0) 2868 goto error; 2869 status = write16(state, IQM_AF_START_LOCK__A, 1); 2870 if (status < 0) 2871 goto error; 2872 2873 *count = 0; 2874 status = read16(state, IQM_AF_PHASE0__A, &data); 2875 if (status < 0) 2876 goto error; 2877 if (data == 127) 2878 *count = *count + 1; 2879 status = read16(state, IQM_AF_PHASE1__A, &data); 2880 if (status < 0) 2881 goto error; 2882 if (data == 127) 2883 *count = *count + 1; 2884 status = read16(state, IQM_AF_PHASE2__A, &data); 2885 if (status < 0) 2886 goto error; 2887 if (data == 127) 2888 *count = *count + 1; 2889 2890 error: 2891 if (status < 0) 2892 pr_err("Error %d on %s\n", status, __func__); 2893 return status; 2894 } 2895 2896 static int adc_synchronization(struct drxk_state *state) 2897 { 2898 u16 count = 0; 2899 int status; 2900 2901 dprintk(1, "\n"); 2902 2903 status = adc_sync_measurement(state, &count); 2904 if (status < 0) 2905 goto error; 2906 2907 if (count == 1) { 2908 /* Try sampling on a different edge */ 2909 u16 clk_neg = 0; 2910 2911 status = read16(state, IQM_AF_CLKNEG__A, &clk_neg); 2912 if (status < 0) 2913 goto error; 2914 if ((clk_neg & IQM_AF_CLKNEG_CLKNEGDATA__M) == 2915 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) { 2916 clk_neg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M)); 2917 clk_neg |= 2918 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG; 2919 } else { 2920 clk_neg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M)); 2921 clk_neg |= 2922 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS; 2923 } 2924 status = write16(state, IQM_AF_CLKNEG__A, clk_neg); 2925 if (status < 0) 2926 goto error; 2927 status = adc_sync_measurement(state, &count); 2928 if (status < 0) 2929 goto error; 2930 } 2931 2932 if (count < 2) 2933 status = -EINVAL; 2934 error: 2935 if (status < 0) 2936 pr_err("Error %d on %s\n", status, __func__); 2937 return status; 2938 } 2939 2940 static int set_frequency_shifter(struct drxk_state *state, 2941 u16 intermediate_freqk_hz, 2942 s32 tuner_freq_offset, bool is_dtv) 2943 { 2944 bool select_pos_image = false; 2945 u32 rf_freq_residual = tuner_freq_offset; 2946 u32 fm_frequency_shift = 0; 2947 bool tuner_mirror = !state->m_b_mirror_freq_spect; 2948 u32 adc_freq; 2949 bool adc_flip; 2950 int status; 2951 u32 if_freq_actual; 2952 u32 sampling_frequency = (u32) (state->m_sys_clock_freq / 3); 2953 u32 frequency_shift; 2954 bool image_to_select; 2955 2956 dprintk(1, "\n"); 2957 2958 /* 2959 Program frequency shifter 2960 No need to account for mirroring on RF 2961 */ 2962 if (is_dtv) { 2963 if ((state->m_operation_mode == OM_QAM_ITU_A) || 2964 (state->m_operation_mode == OM_QAM_ITU_C) || 2965 (state->m_operation_mode == OM_DVBT)) 2966 select_pos_image = true; 2967 else 2968 select_pos_image = false; 2969 } 2970 if (tuner_mirror) 2971 /* tuner doesn't mirror */ 2972 if_freq_actual = intermediate_freqk_hz + 2973 rf_freq_residual + fm_frequency_shift; 2974 else 2975 /* tuner mirrors */ 2976 if_freq_actual = intermediate_freqk_hz - 2977 rf_freq_residual - fm_frequency_shift; 2978 if (if_freq_actual > sampling_frequency / 2) { 2979 /* adc mirrors */ 2980 adc_freq = sampling_frequency - if_freq_actual; 2981 adc_flip = true; 2982 } else { 2983 /* adc doesn't mirror */ 2984 adc_freq = if_freq_actual; 2985 adc_flip = false; 2986 } 2987 2988 frequency_shift = adc_freq; 2989 image_to_select = state->m_rfmirror ^ tuner_mirror ^ 2990 adc_flip ^ select_pos_image; 2991 state->m_iqm_fs_rate_ofs = 2992 Frac28a((frequency_shift), sampling_frequency); 2993 2994 if (image_to_select) 2995 state->m_iqm_fs_rate_ofs = ~state->m_iqm_fs_rate_ofs + 1; 2996 2997 /* Program frequency shifter with tuner offset compensation */ 2998 /* frequency_shift += tuner_freq_offset; TODO */ 2999 status = write32(state, IQM_FS_RATE_OFS_LO__A, 3000 state->m_iqm_fs_rate_ofs); 3001 if (status < 0) 3002 pr_err("Error %d on %s\n", status, __func__); 3003 return status; 3004 } 3005 3006 static int init_agc(struct drxk_state *state, bool is_dtv) 3007 { 3008 u16 ingain_tgt = 0; 3009 u16 ingain_tgt_min = 0; 3010 u16 ingain_tgt_max = 0; 3011 u16 clp_cyclen = 0; 3012 u16 clp_sum_min = 0; 3013 u16 clp_dir_to = 0; 3014 u16 sns_sum_min = 0; 3015 u16 sns_sum_max = 0; 3016 u16 clp_sum_max = 0; 3017 u16 sns_dir_to = 0; 3018 u16 ki_innergain_min = 0; 3019 u16 if_iaccu_hi_tgt = 0; 3020 u16 if_iaccu_hi_tgt_min = 0; 3021 u16 if_iaccu_hi_tgt_max = 0; 3022 u16 data = 0; 3023 u16 fast_clp_ctrl_delay = 0; 3024 u16 clp_ctrl_mode = 0; 3025 int status = 0; 3026 3027 dprintk(1, "\n"); 3028 3029 /* Common settings */ 3030 sns_sum_max = 1023; 3031 if_iaccu_hi_tgt_min = 2047; 3032 clp_cyclen = 500; 3033 clp_sum_max = 1023; 3034 3035 /* AGCInit() not available for DVBT; init done in microcode */ 3036 if (!is_qam(state)) { 3037 pr_err("%s: mode %d is not DVB-C\n", 3038 __func__, state->m_operation_mode); 3039 return -EINVAL; 3040 } 3041 3042 /* FIXME: Analog TV AGC require different settings */ 3043 3044 /* Standard specific settings */ 3045 clp_sum_min = 8; 3046 clp_dir_to = (u16) -9; 3047 clp_ctrl_mode = 0; 3048 sns_sum_min = 8; 3049 sns_dir_to = (u16) -9; 3050 ki_innergain_min = (u16) -1030; 3051 if_iaccu_hi_tgt_max = 0x2380; 3052 if_iaccu_hi_tgt = 0x2380; 3053 ingain_tgt_min = 0x0511; 3054 ingain_tgt = 0x0511; 3055 ingain_tgt_max = 5119; 3056 fast_clp_ctrl_delay = state->m_qam_if_agc_cfg.fast_clip_ctrl_delay; 3057 3058 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 3059 fast_clp_ctrl_delay); 3060 if (status < 0) 3061 goto error; 3062 3063 status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode); 3064 if (status < 0) 3065 goto error; 3066 status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingain_tgt); 3067 if (status < 0) 3068 goto error; 3069 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingain_tgt_min); 3070 if (status < 0) 3071 goto error; 3072 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max); 3073 if (status < 0) 3074 goto error; 3075 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, 3076 if_iaccu_hi_tgt_min); 3077 if (status < 0) 3078 goto error; 3079 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 3080 if_iaccu_hi_tgt_max); 3081 if (status < 0) 3082 goto error; 3083 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0); 3084 if (status < 0) 3085 goto error; 3086 status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0); 3087 if (status < 0) 3088 goto error; 3089 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0); 3090 if (status < 0) 3091 goto error; 3092 status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0); 3093 if (status < 0) 3094 goto error; 3095 status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max); 3096 if (status < 0) 3097 goto error; 3098 status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max); 3099 if (status < 0) 3100 goto error; 3101 3102 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, 3103 ki_innergain_min); 3104 if (status < 0) 3105 goto error; 3106 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, 3107 if_iaccu_hi_tgt); 3108 if (status < 0) 3109 goto error; 3110 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clp_cyclen); 3111 if (status < 0) 3112 goto error; 3113 3114 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023); 3115 if (status < 0) 3116 goto error; 3117 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023); 3118 if (status < 0) 3119 goto error; 3120 status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50); 3121 if (status < 0) 3122 goto error; 3123 3124 status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20); 3125 if (status < 0) 3126 goto error; 3127 status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clp_sum_min); 3128 if (status < 0) 3129 goto error; 3130 status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, sns_sum_min); 3131 if (status < 0) 3132 goto error; 3133 status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to); 3134 if (status < 0) 3135 goto error; 3136 status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to); 3137 if (status < 0) 3138 goto error; 3139 status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff); 3140 if (status < 0) 3141 goto error; 3142 status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0); 3143 if (status < 0) 3144 goto error; 3145 status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117); 3146 if (status < 0) 3147 goto error; 3148 status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657); 3149 if (status < 0) 3150 goto error; 3151 status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0); 3152 if (status < 0) 3153 goto error; 3154 status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0); 3155 if (status < 0) 3156 goto error; 3157 status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0); 3158 if (status < 0) 3159 goto error; 3160 status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1); 3161 if (status < 0) 3162 goto error; 3163 status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0); 3164 if (status < 0) 3165 goto error; 3166 status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0); 3167 if (status < 0) 3168 goto error; 3169 status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0); 3170 if (status < 0) 3171 goto error; 3172 status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1); 3173 if (status < 0) 3174 goto error; 3175 status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500); 3176 if (status < 0) 3177 goto error; 3178 status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500); 3179 if (status < 0) 3180 goto error; 3181 3182 /* Initialize inner-loop KI gain factors */ 3183 status = read16(state, SCU_RAM_AGC_KI__A, &data); 3184 if (status < 0) 3185 goto error; 3186 3187 data = 0x0657; 3188 data &= ~SCU_RAM_AGC_KI_RF__M; 3189 data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B); 3190 data &= ~SCU_RAM_AGC_KI_IF__M; 3191 data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B); 3192 3193 status = write16(state, SCU_RAM_AGC_KI__A, data); 3194 error: 3195 if (status < 0) 3196 pr_err("Error %d on %s\n", status, __func__); 3197 return status; 3198 } 3199 3200 static int dvbtqam_get_acc_pkt_err(struct drxk_state *state, u16 *packet_err) 3201 { 3202 int status; 3203 3204 dprintk(1, "\n"); 3205 if (packet_err == NULL) 3206 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0); 3207 else 3208 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 3209 packet_err); 3210 if (status < 0) 3211 pr_err("Error %d on %s\n", status, __func__); 3212 return status; 3213 } 3214 3215 static int dvbt_sc_command(struct drxk_state *state, 3216 u16 cmd, u16 subcmd, 3217 u16 param0, u16 param1, u16 param2, 3218 u16 param3, u16 param4) 3219 { 3220 u16 cur_cmd = 0; 3221 u16 err_code = 0; 3222 u16 retry_cnt = 0; 3223 u16 sc_exec = 0; 3224 int status; 3225 3226 dprintk(1, "\n"); 3227 status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_exec); 3228 if (sc_exec != 1) { 3229 /* SC is not running */ 3230 status = -EINVAL; 3231 } 3232 if (status < 0) 3233 goto error; 3234 3235 /* Wait until sc is ready to receive command */ 3236 retry_cnt = 0; 3237 do { 3238 usleep_range(1000, 2000); 3239 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd); 3240 retry_cnt++; 3241 } while ((cur_cmd != 0) && (retry_cnt < DRXK_MAX_RETRIES)); 3242 if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0)) 3243 goto error; 3244 3245 /* Write sub-command */ 3246 switch (cmd) { 3247 /* All commands using sub-cmd */ 3248 case OFDM_SC_RA_RAM_CMD_PROC_START: 3249 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: 3250 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: 3251 status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd); 3252 if (status < 0) 3253 goto error; 3254 break; 3255 default: 3256 /* Do nothing */ 3257 break; 3258 } 3259 3260 /* Write needed parameters and the command */ 3261 status = 0; 3262 switch (cmd) { 3263 /* All commands using 5 parameters */ 3264 /* All commands using 4 parameters */ 3265 /* All commands using 3 parameters */ 3266 /* All commands using 2 parameters */ 3267 case OFDM_SC_RA_RAM_CMD_PROC_START: 3268 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: 3269 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: 3270 status |= write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1); 3271 /* All commands using 1 parameters */ 3272 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING: 3273 case OFDM_SC_RA_RAM_CMD_USER_IO: 3274 status |= write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0); 3275 /* All commands using 0 parameters */ 3276 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM: 3277 case OFDM_SC_RA_RAM_CMD_NULL: 3278 /* Write command */ 3279 status |= write16(state, OFDM_SC_RA_RAM_CMD__A, cmd); 3280 break; 3281 default: 3282 /* Unknown command */ 3283 status = -EINVAL; 3284 } 3285 if (status < 0) 3286 goto error; 3287 3288 /* Wait until sc is ready processing command */ 3289 retry_cnt = 0; 3290 do { 3291 usleep_range(1000, 2000); 3292 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd); 3293 retry_cnt++; 3294 } while ((cur_cmd != 0) && (retry_cnt < DRXK_MAX_RETRIES)); 3295 if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0)) 3296 goto error; 3297 3298 /* Check for illegal cmd */ 3299 status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &err_code); 3300 if (err_code == 0xFFFF) { 3301 /* illegal command */ 3302 status = -EINVAL; 3303 } 3304 if (status < 0) 3305 goto error; 3306 3307 /* Retrieve results parameters from SC */ 3308 switch (cmd) { 3309 /* All commands yielding 5 results */ 3310 /* All commands yielding 4 results */ 3311 /* All commands yielding 3 results */ 3312 /* All commands yielding 2 results */ 3313 /* All commands yielding 1 result */ 3314 case OFDM_SC_RA_RAM_CMD_USER_IO: 3315 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM: 3316 status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0)); 3317 /* All commands yielding 0 results */ 3318 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING: 3319 case OFDM_SC_RA_RAM_CMD_SET_TIMER: 3320 case OFDM_SC_RA_RAM_CMD_PROC_START: 3321 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: 3322 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: 3323 case OFDM_SC_RA_RAM_CMD_NULL: 3324 break; 3325 default: 3326 /* Unknown command */ 3327 status = -EINVAL; 3328 break; 3329 } /* switch (cmd->cmd) */ 3330 error: 3331 if (status < 0) 3332 pr_err("Error %d on %s\n", status, __func__); 3333 return status; 3334 } 3335 3336 static int power_up_dvbt(struct drxk_state *state) 3337 { 3338 enum drx_power_mode power_mode = DRX_POWER_UP; 3339 int status; 3340 3341 dprintk(1, "\n"); 3342 status = ctrl_power_mode(state, &power_mode); 3343 if (status < 0) 3344 pr_err("Error %d on %s\n", status, __func__); 3345 return status; 3346 } 3347 3348 static int dvbt_ctrl_set_inc_enable(struct drxk_state *state, bool *enabled) 3349 { 3350 int status; 3351 3352 dprintk(1, "\n"); 3353 if (*enabled) 3354 status = write16(state, IQM_CF_BYPASSDET__A, 0); 3355 else 3356 status = write16(state, IQM_CF_BYPASSDET__A, 1); 3357 if (status < 0) 3358 pr_err("Error %d on %s\n", status, __func__); 3359 return status; 3360 } 3361 3362 #define DEFAULT_FR_THRES_8K 4000 3363 static int dvbt_ctrl_set_fr_enable(struct drxk_state *state, bool *enabled) 3364 { 3365 3366 int status; 3367 3368 dprintk(1, "\n"); 3369 if (*enabled) { 3370 /* write mask to 1 */ 3371 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 3372 DEFAULT_FR_THRES_8K); 3373 } else { 3374 /* write mask to 0 */ 3375 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0); 3376 } 3377 if (status < 0) 3378 pr_err("Error %d on %s\n", status, __func__); 3379 3380 return status; 3381 } 3382 3383 static int dvbt_ctrl_set_echo_threshold(struct drxk_state *state, 3384 struct drxk_cfg_dvbt_echo_thres_t *echo_thres) 3385 { 3386 u16 data = 0; 3387 int status; 3388 3389 dprintk(1, "\n"); 3390 status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data); 3391 if (status < 0) 3392 goto error; 3393 3394 switch (echo_thres->fft_mode) { 3395 case DRX_FFTMODE_2K: 3396 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M; 3397 data |= ((echo_thres->threshold << 3398 OFDM_SC_RA_RAM_ECHO_THRES_2K__B) 3399 & (OFDM_SC_RA_RAM_ECHO_THRES_2K__M)); 3400 break; 3401 case DRX_FFTMODE_8K: 3402 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M; 3403 data |= ((echo_thres->threshold << 3404 OFDM_SC_RA_RAM_ECHO_THRES_8K__B) 3405 & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M)); 3406 break; 3407 default: 3408 return -EINVAL; 3409 } 3410 3411 status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data); 3412 error: 3413 if (status < 0) 3414 pr_err("Error %d on %s\n", status, __func__); 3415 return status; 3416 } 3417 3418 static int dvbt_ctrl_set_sqi_speed(struct drxk_state *state, 3419 enum drxk_cfg_dvbt_sqi_speed *speed) 3420 { 3421 int status = -EINVAL; 3422 3423 dprintk(1, "\n"); 3424 3425 switch (*speed) { 3426 case DRXK_DVBT_SQI_SPEED_FAST: 3427 case DRXK_DVBT_SQI_SPEED_MEDIUM: 3428 case DRXK_DVBT_SQI_SPEED_SLOW: 3429 break; 3430 default: 3431 goto error; 3432 } 3433 status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A, 3434 (u16) *speed); 3435 error: 3436 if (status < 0) 3437 pr_err("Error %d on %s\n", status, __func__); 3438 return status; 3439 } 3440 3441 /*============================================================================*/ 3442 3443 /** 3444 * \brief Activate DVBT specific presets 3445 * \param demod instance of demodulator. 3446 * \return DRXStatus_t. 3447 * 3448 * Called in DVBTSetStandard 3449 * 3450 */ 3451 static int dvbt_activate_presets(struct drxk_state *state) 3452 { 3453 int status; 3454 bool setincenable = false; 3455 bool setfrenable = true; 3456 3457 struct drxk_cfg_dvbt_echo_thres_t echo_thres2k = { 0, DRX_FFTMODE_2K }; 3458 struct drxk_cfg_dvbt_echo_thres_t echo_thres8k = { 0, DRX_FFTMODE_8K }; 3459 3460 dprintk(1, "\n"); 3461 status = dvbt_ctrl_set_inc_enable(state, &setincenable); 3462 if (status < 0) 3463 goto error; 3464 status = dvbt_ctrl_set_fr_enable(state, &setfrenable); 3465 if (status < 0) 3466 goto error; 3467 status = dvbt_ctrl_set_echo_threshold(state, &echo_thres2k); 3468 if (status < 0) 3469 goto error; 3470 status = dvbt_ctrl_set_echo_threshold(state, &echo_thres8k); 3471 if (status < 0) 3472 goto error; 3473 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, 3474 state->m_dvbt_if_agc_cfg.ingain_tgt_max); 3475 error: 3476 if (status < 0) 3477 pr_err("Error %d on %s\n", status, __func__); 3478 return status; 3479 } 3480 3481 /*============================================================================*/ 3482 3483 /** 3484 * \brief Initialize channelswitch-independent settings for DVBT. 3485 * \param demod instance of demodulator. 3486 * \return DRXStatus_t. 3487 * 3488 * For ROM code channel filter taps are loaded from the bootloader. For microcode 3489 * the DVB-T taps from the drxk_filters.h are used. 3490 */ 3491 static int set_dvbt_standard(struct drxk_state *state, 3492 enum operation_mode o_mode) 3493 { 3494 u16 cmd_result = 0; 3495 u16 data = 0; 3496 int status; 3497 3498 dprintk(1, "\n"); 3499 3500 power_up_dvbt(state); 3501 /* added antenna switch */ 3502 switch_antenna_to_dvbt(state); 3503 /* send OFDM reset command */ 3504 status = scu_command(state, 3505 SCU_RAM_COMMAND_STANDARD_OFDM 3506 | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 3507 0, NULL, 1, &cmd_result); 3508 if (status < 0) 3509 goto error; 3510 3511 /* send OFDM setenv command */ 3512 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM 3513 | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 3514 0, NULL, 1, &cmd_result); 3515 if (status < 0) 3516 goto error; 3517 3518 /* reset datapath for OFDM, processors first */ 3519 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); 3520 if (status < 0) 3521 goto error; 3522 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); 3523 if (status < 0) 3524 goto error; 3525 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); 3526 if (status < 0) 3527 goto error; 3528 3529 /* IQM setup */ 3530 /* synchronize on ofdstate->m_festart */ 3531 status = write16(state, IQM_AF_UPD_SEL__A, 1); 3532 if (status < 0) 3533 goto error; 3534 /* window size for clipping ADC detection */ 3535 status = write16(state, IQM_AF_CLP_LEN__A, 0); 3536 if (status < 0) 3537 goto error; 3538 /* window size for for sense pre-SAW detection */ 3539 status = write16(state, IQM_AF_SNS_LEN__A, 0); 3540 if (status < 0) 3541 goto error; 3542 /* sense threshold for sense pre-SAW detection */ 3543 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC); 3544 if (status < 0) 3545 goto error; 3546 status = set_iqm_af(state, true); 3547 if (status < 0) 3548 goto error; 3549 3550 status = write16(state, IQM_AF_AGC_RF__A, 0); 3551 if (status < 0) 3552 goto error; 3553 3554 /* Impulse noise cruncher setup */ 3555 status = write16(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */ 3556 if (status < 0) 3557 goto error; 3558 status = write16(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */ 3559 if (status < 0) 3560 goto error; 3561 status = write16(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */ 3562 if (status < 0) 3563 goto error; 3564 3565 status = write16(state, IQM_RC_STRETCH__A, 16); 3566 if (status < 0) 3567 goto error; 3568 status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */ 3569 if (status < 0) 3570 goto error; 3571 status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */ 3572 if (status < 0) 3573 goto error; 3574 status = write16(state, IQM_CF_SCALE__A, 1600); 3575 if (status < 0) 3576 goto error; 3577 status = write16(state, IQM_CF_SCALE_SH__A, 0); 3578 if (status < 0) 3579 goto error; 3580 3581 /* virtual clipping threshold for clipping ADC detection */ 3582 status = write16(state, IQM_AF_CLP_TH__A, 448); 3583 if (status < 0) 3584 goto error; 3585 status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */ 3586 if (status < 0) 3587 goto error; 3588 3589 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT, 3590 DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT); 3591 if (status < 0) 3592 goto error; 3593 3594 status = write16(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */ 3595 if (status < 0) 3596 goto error; 3597 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2); 3598 if (status < 0) 3599 goto error; 3600 /* enable power measurement interrupt */ 3601 status = write16(state, IQM_CF_COMM_INT_MSK__A, 1); 3602 if (status < 0) 3603 goto error; 3604 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE); 3605 if (status < 0) 3606 goto error; 3607 3608 /* IQM will not be reset from here, sync ADC and update/init AGC */ 3609 status = adc_synchronization(state); 3610 if (status < 0) 3611 goto error; 3612 status = set_pre_saw(state, &state->m_dvbt_pre_saw_cfg); 3613 if (status < 0) 3614 goto error; 3615 3616 /* Halt SCU to enable safe non-atomic accesses */ 3617 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); 3618 if (status < 0) 3619 goto error; 3620 3621 status = set_agc_rf(state, &state->m_dvbt_rf_agc_cfg, true); 3622 if (status < 0) 3623 goto error; 3624 status = set_agc_if(state, &state->m_dvbt_if_agc_cfg, true); 3625 if (status < 0) 3626 goto error; 3627 3628 /* Set Noise Estimation notch width and enable DC fix */ 3629 status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data); 3630 if (status < 0) 3631 goto error; 3632 data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M; 3633 status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data); 3634 if (status < 0) 3635 goto error; 3636 3637 /* Activate SCU to enable SCU commands */ 3638 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); 3639 if (status < 0) 3640 goto error; 3641 3642 if (!state->m_drxk_a3_rom_code) { 3643 /* AGCInit() is not done for DVBT, so set agcfast_clip_ctrl_delay */ 3644 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 3645 state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay); 3646 if (status < 0) 3647 goto error; 3648 } 3649 3650 /* OFDM_SC setup */ 3651 #ifdef COMPILE_FOR_NONRT 3652 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1); 3653 if (status < 0) 3654 goto error; 3655 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2); 3656 if (status < 0) 3657 goto error; 3658 #endif 3659 3660 /* FEC setup */ 3661 status = write16(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */ 3662 if (status < 0) 3663 goto error; 3664 3665 3666 #ifdef COMPILE_FOR_NONRT 3667 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400); 3668 if (status < 0) 3669 goto error; 3670 #else 3671 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000); 3672 if (status < 0) 3673 goto error; 3674 #endif 3675 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001); 3676 if (status < 0) 3677 goto error; 3678 3679 /* Setup MPEG bus */ 3680 status = mpegts_dto_setup(state, OM_DVBT); 3681 if (status < 0) 3682 goto error; 3683 /* Set DVBT Presets */ 3684 status = dvbt_activate_presets(state); 3685 if (status < 0) 3686 goto error; 3687 3688 error: 3689 if (status < 0) 3690 pr_err("Error %d on %s\n", status, __func__); 3691 return status; 3692 } 3693 3694 /*============================================================================*/ 3695 /** 3696 * \brief start dvbt demodulating for channel. 3697 * \param demod instance of demodulator. 3698 * \return DRXStatus_t. 3699 */ 3700 static int dvbt_start(struct drxk_state *state) 3701 { 3702 u16 param1; 3703 int status; 3704 /* drxk_ofdm_sc_cmd_t scCmd; */ 3705 3706 dprintk(1, "\n"); 3707 /* start correct processes to get in lock */ 3708 /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */ 3709 param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN; 3710 status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, 3711 OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1, 3712 0, 0, 0); 3713 if (status < 0) 3714 goto error; 3715 /* start FEC OC */ 3716 status = mpegts_start(state); 3717 if (status < 0) 3718 goto error; 3719 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); 3720 if (status < 0) 3721 goto error; 3722 error: 3723 if (status < 0) 3724 pr_err("Error %d on %s\n", status, __func__); 3725 return status; 3726 } 3727 3728 3729 /*============================================================================*/ 3730 3731 /** 3732 * \brief Set up dvbt demodulator for channel. 3733 * \param demod instance of demodulator. 3734 * \return DRXStatus_t. 3735 * // original DVBTSetChannel() 3736 */ 3737 static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, 3738 s32 tuner_freq_offset) 3739 { 3740 u16 cmd_result = 0; 3741 u16 transmission_params = 0; 3742 u16 operation_mode = 0; 3743 u32 iqm_rc_rate_ofs = 0; 3744 u32 bandwidth = 0; 3745 u16 param1; 3746 int status; 3747 3748 dprintk(1, "IF =%d, TFO = %d\n", 3749 intermediate_freqk_hz, tuner_freq_offset); 3750 3751 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM 3752 | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 3753 0, NULL, 1, &cmd_result); 3754 if (status < 0) 3755 goto error; 3756 3757 /* Halt SCU to enable safe non-atomic accesses */ 3758 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); 3759 if (status < 0) 3760 goto error; 3761 3762 /* Stop processors */ 3763 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); 3764 if (status < 0) 3765 goto error; 3766 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); 3767 if (status < 0) 3768 goto error; 3769 3770 /* Mandatory fix, always stop CP, required to set spl offset back to 3771 hardware default (is set to 0 by ucode during pilot detection */ 3772 status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP); 3773 if (status < 0) 3774 goto error; 3775 3776 /*== Write channel settings to device ================================*/ 3777 3778 /* mode */ 3779 switch (state->props.transmission_mode) { 3780 case TRANSMISSION_MODE_AUTO: 3781 default: 3782 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M; 3783 /* fall through , try first guess DRX_FFTMODE_8K */ 3784 case TRANSMISSION_MODE_8K: 3785 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K; 3786 break; 3787 case TRANSMISSION_MODE_2K: 3788 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K; 3789 break; 3790 } 3791 3792 /* guard */ 3793 switch (state->props.guard_interval) { 3794 default: 3795 case GUARD_INTERVAL_AUTO: 3796 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M; 3797 /* fall through , try first guess DRX_GUARD_1DIV4 */ 3798 case GUARD_INTERVAL_1_4: 3799 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4; 3800 break; 3801 case GUARD_INTERVAL_1_32: 3802 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32; 3803 break; 3804 case GUARD_INTERVAL_1_16: 3805 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16; 3806 break; 3807 case GUARD_INTERVAL_1_8: 3808 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8; 3809 break; 3810 } 3811 3812 /* hierarchy */ 3813 switch (state->props.hierarchy) { 3814 case HIERARCHY_AUTO: 3815 case HIERARCHY_NONE: 3816 default: 3817 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M; 3818 /* fall through , try first guess SC_RA_RAM_OP_PARAM_HIER_NO */ 3819 /* transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; */ 3820 /* break; */ 3821 case HIERARCHY_1: 3822 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1; 3823 break; 3824 case HIERARCHY_2: 3825 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2; 3826 break; 3827 case HIERARCHY_4: 3828 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4; 3829 break; 3830 } 3831 3832 3833 /* modulation */ 3834 switch (state->props.modulation) { 3835 case QAM_AUTO: 3836 default: 3837 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M; 3838 /* fall through , try first guess DRX_CONSTELLATION_QAM64 */ 3839 case QAM_64: 3840 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64; 3841 break; 3842 case QPSK: 3843 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK; 3844 break; 3845 case QAM_16: 3846 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16; 3847 break; 3848 } 3849 #if 0 3850 /* No hierarchical channels support in BDA */ 3851 /* Priority (only for hierarchical channels) */ 3852 switch (channel->priority) { 3853 case DRX_PRIORITY_LOW: 3854 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO; 3855 WR16(dev_addr, OFDM_EC_SB_PRIOR__A, 3856 OFDM_EC_SB_PRIOR_LO); 3857 break; 3858 case DRX_PRIORITY_HIGH: 3859 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI; 3860 WR16(dev_addr, OFDM_EC_SB_PRIOR__A, 3861 OFDM_EC_SB_PRIOR_HI)); 3862 break; 3863 case DRX_PRIORITY_UNKNOWN: /* fall through */ 3864 default: 3865 status = -EINVAL; 3866 goto error; 3867 } 3868 #else 3869 /* Set Priorty high */ 3870 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI; 3871 status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI); 3872 if (status < 0) 3873 goto error; 3874 #endif 3875 3876 /* coderate */ 3877 switch (state->props.code_rate_HP) { 3878 case FEC_AUTO: 3879 default: 3880 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M; 3881 /* fall through , try first guess DRX_CODERATE_2DIV3 */ 3882 case FEC_2_3: 3883 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3; 3884 break; 3885 case FEC_1_2: 3886 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2; 3887 break; 3888 case FEC_3_4: 3889 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4; 3890 break; 3891 case FEC_5_6: 3892 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6; 3893 break; 3894 case FEC_7_8: 3895 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8; 3896 break; 3897 } 3898 3899 /* 3900 * SAW filter selection: normaly not necesarry, but if wanted 3901 * the application can select a SAW filter via the driver by 3902 * using UIOs 3903 */ 3904 3905 /* First determine real bandwidth (Hz) */ 3906 /* Also set delay for impulse noise cruncher */ 3907 /* 3908 * Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is 3909 * changed by SC for fix for some 8K,1/8 guard but is restored by 3910 * InitEC and ResetEC functions 3911 */ 3912 switch (state->props.bandwidth_hz) { 3913 case 0: 3914 state->props.bandwidth_hz = 8000000; 3915 /* fall though */ 3916 case 8000000: 3917 bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ; 3918 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3919 3052); 3920 if (status < 0) 3921 goto error; 3922 /* cochannel protection for PAL 8 MHz */ 3923 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 3924 7); 3925 if (status < 0) 3926 goto error; 3927 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 3928 7); 3929 if (status < 0) 3930 goto error; 3931 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 3932 7); 3933 if (status < 0) 3934 goto error; 3935 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 3936 1); 3937 if (status < 0) 3938 goto error; 3939 break; 3940 case 7000000: 3941 bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ; 3942 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3943 3491); 3944 if (status < 0) 3945 goto error; 3946 /* cochannel protection for PAL 7 MHz */ 3947 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 3948 8); 3949 if (status < 0) 3950 goto error; 3951 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 3952 8); 3953 if (status < 0) 3954 goto error; 3955 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 3956 4); 3957 if (status < 0) 3958 goto error; 3959 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 3960 1); 3961 if (status < 0) 3962 goto error; 3963 break; 3964 case 6000000: 3965 bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ; 3966 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3967 4073); 3968 if (status < 0) 3969 goto error; 3970 /* cochannel protection for NTSC 6 MHz */ 3971 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 3972 19); 3973 if (status < 0) 3974 goto error; 3975 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 3976 19); 3977 if (status < 0) 3978 goto error; 3979 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 3980 14); 3981 if (status < 0) 3982 goto error; 3983 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 3984 1); 3985 if (status < 0) 3986 goto error; 3987 break; 3988 default: 3989 status = -EINVAL; 3990 goto error; 3991 } 3992 3993 if (iqm_rc_rate_ofs == 0) { 3994 /* Now compute IQM_RC_RATE_OFS 3995 (((SysFreq/BandWidth)/2)/2) -1) * 2^23) 3996 => 3997 ((SysFreq / BandWidth) * (2^21)) - (2^23) 3998 */ 3999 /* (SysFreq / BandWidth) * (2^28) */ 4000 /* 4001 * assert (MAX(sysClk)/MIN(bandwidth) < 16) 4002 * => assert(MAX(sysClk) < 16*MIN(bandwidth)) 4003 * => assert(109714272 > 48000000) = true 4004 * so Frac 28 can be used 4005 */ 4006 iqm_rc_rate_ofs = Frac28a((u32) 4007 ((state->m_sys_clock_freq * 4008 1000) / 3), bandwidth); 4009 /* (SysFreq / BandWidth) * (2^21), rounding before truncating */ 4010 if ((iqm_rc_rate_ofs & 0x7fL) >= 0x40) 4011 iqm_rc_rate_ofs += 0x80L; 4012 iqm_rc_rate_ofs = iqm_rc_rate_ofs >> 7; 4013 /* ((SysFreq / BandWidth) * (2^21)) - (2^23) */ 4014 iqm_rc_rate_ofs = iqm_rc_rate_ofs - (1 << 23); 4015 } 4016 4017 iqm_rc_rate_ofs &= 4018 ((((u32) IQM_RC_RATE_OFS_HI__M) << 4019 IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M); 4020 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate_ofs); 4021 if (status < 0) 4022 goto error; 4023 4024 /* Bandwidth setting done */ 4025 4026 #if 0 4027 status = dvbt_set_frequency_shift(demod, channel, tuner_offset); 4028 if (status < 0) 4029 goto error; 4030 #endif 4031 status = set_frequency_shifter(state, intermediate_freqk_hz, 4032 tuner_freq_offset, true); 4033 if (status < 0) 4034 goto error; 4035 4036 /*== start SC, write channel settings to SC ==========================*/ 4037 4038 /* Activate SCU to enable SCU commands */ 4039 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); 4040 if (status < 0) 4041 goto error; 4042 4043 /* Enable SC after setting all other parameters */ 4044 status = write16(state, OFDM_SC_COMM_STATE__A, 0); 4045 if (status < 0) 4046 goto error; 4047 status = write16(state, OFDM_SC_COMM_EXEC__A, 1); 4048 if (status < 0) 4049 goto error; 4050 4051 4052 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM 4053 | SCU_RAM_COMMAND_CMD_DEMOD_START, 4054 0, NULL, 1, &cmd_result); 4055 if (status < 0) 4056 goto error; 4057 4058 /* Write SC parameter registers, set all AUTO flags in operation mode */ 4059 param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M | 4060 OFDM_SC_RA_RAM_OP_AUTO_GUARD__M | 4061 OFDM_SC_RA_RAM_OP_AUTO_CONST__M | 4062 OFDM_SC_RA_RAM_OP_AUTO_HIER__M | 4063 OFDM_SC_RA_RAM_OP_AUTO_RATE__M); 4064 status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM, 4065 0, transmission_params, param1, 0, 0, 0); 4066 if (status < 0) 4067 goto error; 4068 4069 if (!state->m_drxk_a3_rom_code) 4070 status = dvbt_ctrl_set_sqi_speed(state, &state->m_sqi_speed); 4071 error: 4072 if (status < 0) 4073 pr_err("Error %d on %s\n", status, __func__); 4074 4075 return status; 4076 } 4077 4078 4079 /*============================================================================*/ 4080 4081 /** 4082 * \brief Retrieve lock status . 4083 * \param demod Pointer to demodulator instance. 4084 * \param lockStat Pointer to lock status structure. 4085 * \return DRXStatus_t. 4086 * 4087 */ 4088 static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status) 4089 { 4090 int status; 4091 const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M | 4092 OFDM_SC_RA_RAM_LOCK_FEC__M); 4093 const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M); 4094 const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M; 4095 4096 u16 sc_ra_ram_lock = 0; 4097 u16 sc_comm_exec = 0; 4098 4099 dprintk(1, "\n"); 4100 4101 *p_lock_status = NOT_LOCKED; 4102 /* driver 0.9.0 */ 4103 /* Check if SC is running */ 4104 status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_comm_exec); 4105 if (status < 0) 4106 goto end; 4107 if (sc_comm_exec == OFDM_SC_COMM_EXEC_STOP) 4108 goto end; 4109 4110 status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &sc_ra_ram_lock); 4111 if (status < 0) 4112 goto end; 4113 4114 if ((sc_ra_ram_lock & mpeg_lock_mask) == mpeg_lock_mask) 4115 *p_lock_status = MPEG_LOCK; 4116 else if ((sc_ra_ram_lock & fec_lock_mask) == fec_lock_mask) 4117 *p_lock_status = FEC_LOCK; 4118 else if ((sc_ra_ram_lock & demod_lock_mask) == demod_lock_mask) 4119 *p_lock_status = DEMOD_LOCK; 4120 else if (sc_ra_ram_lock & OFDM_SC_RA_RAM_LOCK_NODVBT__M) 4121 *p_lock_status = NEVER_LOCK; 4122 end: 4123 if (status < 0) 4124 pr_err("Error %d on %s\n", status, __func__); 4125 4126 return status; 4127 } 4128 4129 static int power_up_qam(struct drxk_state *state) 4130 { 4131 enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM; 4132 int status; 4133 4134 dprintk(1, "\n"); 4135 status = ctrl_power_mode(state, &power_mode); 4136 if (status < 0) 4137 pr_err("Error %d on %s\n", status, __func__); 4138 4139 return status; 4140 } 4141 4142 4143 /** Power Down QAM */ 4144 static int power_down_qam(struct drxk_state *state) 4145 { 4146 u16 data = 0; 4147 u16 cmd_result; 4148 int status = 0; 4149 4150 dprintk(1, "\n"); 4151 status = read16(state, SCU_COMM_EXEC__A, &data); 4152 if (status < 0) 4153 goto error; 4154 if (data == SCU_COMM_EXEC_ACTIVE) { 4155 /* 4156 STOP demodulator 4157 QAM and HW blocks 4158 */ 4159 /* stop all comstate->m_exec */ 4160 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); 4161 if (status < 0) 4162 goto error; 4163 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM 4164 | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 4165 0, NULL, 1, &cmd_result); 4166 if (status < 0) 4167 goto error; 4168 } 4169 /* powerdown AFE */ 4170 status = set_iqm_af(state, false); 4171 4172 error: 4173 if (status < 0) 4174 pr_err("Error %d on %s\n", status, __func__); 4175 4176 return status; 4177 } 4178 4179 /*============================================================================*/ 4180 4181 /** 4182 * \brief Setup of the QAM Measurement intervals for signal quality 4183 * \param demod instance of demod. 4184 * \param modulation current modulation. 4185 * \return DRXStatus_t. 4186 * 4187 * NOTE: 4188 * Take into account that for certain settings the errorcounters can overflow. 4189 * The implementation does not check this. 4190 * 4191 */ 4192 static int set_qam_measurement(struct drxk_state *state, 4193 enum e_drxk_constellation modulation, 4194 u32 symbol_rate) 4195 { 4196 u32 fec_bits_desired = 0; /* BER accounting period */ 4197 u32 fec_rs_period_total = 0; /* Total period */ 4198 u16 fec_rs_prescale = 0; /* ReedSolomon Measurement Prescale */ 4199 u16 fec_rs_period = 0; /* Value for corresponding I2C register */ 4200 int status = 0; 4201 4202 dprintk(1, "\n"); 4203 4204 fec_rs_prescale = 1; 4205 /* fec_bits_desired = symbol_rate [kHz] * 4206 FrameLenght [ms] * 4207 (modulation + 1) * 4208 SyncLoss (== 1) * 4209 ViterbiLoss (==1) 4210 */ 4211 switch (modulation) { 4212 case DRX_CONSTELLATION_QAM16: 4213 fec_bits_desired = 4 * symbol_rate; 4214 break; 4215 case DRX_CONSTELLATION_QAM32: 4216 fec_bits_desired = 5 * symbol_rate; 4217 break; 4218 case DRX_CONSTELLATION_QAM64: 4219 fec_bits_desired = 6 * symbol_rate; 4220 break; 4221 case DRX_CONSTELLATION_QAM128: 4222 fec_bits_desired = 7 * symbol_rate; 4223 break; 4224 case DRX_CONSTELLATION_QAM256: 4225 fec_bits_desired = 8 * symbol_rate; 4226 break; 4227 default: 4228 status = -EINVAL; 4229 } 4230 if (status < 0) 4231 goto error; 4232 4233 fec_bits_desired /= 1000; /* symbol_rate [Hz] -> symbol_rate [kHz] */ 4234 fec_bits_desired *= 500; /* meas. period [ms] */ 4235 4236 /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */ 4237 /* fec_rs_period_total = fec_bits_desired / 1632 */ 4238 fec_rs_period_total = (fec_bits_desired / 1632UL) + 1; /* roughly ceil */ 4239 4240 /* fec_rs_period_total = fec_rs_prescale * fec_rs_period */ 4241 fec_rs_prescale = 1 + (u16) (fec_rs_period_total >> 16); 4242 if (fec_rs_prescale == 0) { 4243 /* Divide by zero (though impossible) */ 4244 status = -EINVAL; 4245 if (status < 0) 4246 goto error; 4247 } 4248 fec_rs_period = 4249 ((u16) fec_rs_period_total + 4250 (fec_rs_prescale >> 1)) / fec_rs_prescale; 4251 4252 /* write corresponding registers */ 4253 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fec_rs_period); 4254 if (status < 0) 4255 goto error; 4256 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 4257 fec_rs_prescale); 4258 if (status < 0) 4259 goto error; 4260 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fec_rs_period); 4261 error: 4262 if (status < 0) 4263 pr_err("Error %d on %s\n", status, __func__); 4264 return status; 4265 } 4266 4267 static int set_qam16(struct drxk_state *state) 4268 { 4269 int status = 0; 4270 4271 dprintk(1, "\n"); 4272 /* QAM Equalizer Setup */ 4273 /* Equalizer */ 4274 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517); 4275 if (status < 0) 4276 goto error; 4277 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517); 4278 if (status < 0) 4279 goto error; 4280 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517); 4281 if (status < 0) 4282 goto error; 4283 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517); 4284 if (status < 0) 4285 goto error; 4286 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517); 4287 if (status < 0) 4288 goto error; 4289 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517); 4290 if (status < 0) 4291 goto error; 4292 /* Decision Feedback Equalizer */ 4293 status = write16(state, QAM_DQ_QUAL_FUN0__A, 2); 4294 if (status < 0) 4295 goto error; 4296 status = write16(state, QAM_DQ_QUAL_FUN1__A, 2); 4297 if (status < 0) 4298 goto error; 4299 status = write16(state, QAM_DQ_QUAL_FUN2__A, 2); 4300 if (status < 0) 4301 goto error; 4302 status = write16(state, QAM_DQ_QUAL_FUN3__A, 2); 4303 if (status < 0) 4304 goto error; 4305 status = write16(state, QAM_DQ_QUAL_FUN4__A, 2); 4306 if (status < 0) 4307 goto error; 4308 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); 4309 if (status < 0) 4310 goto error; 4311 4312 status = write16(state, QAM_SY_SYNC_HWM__A, 5); 4313 if (status < 0) 4314 goto error; 4315 status = write16(state, QAM_SY_SYNC_AWM__A, 4); 4316 if (status < 0) 4317 goto error; 4318 status = write16(state, QAM_SY_SYNC_LWM__A, 3); 4319 if (status < 0) 4320 goto error; 4321 4322 /* QAM Slicer Settings */ 4323 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, 4324 DRXK_QAM_SL_SIG_POWER_QAM16); 4325 if (status < 0) 4326 goto error; 4327 4328 /* QAM Loop Controller Coeficients */ 4329 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); 4330 if (status < 0) 4331 goto error; 4332 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); 4333 if (status < 0) 4334 goto error; 4335 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); 4336 if (status < 0) 4337 goto error; 4338 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); 4339 if (status < 0) 4340 goto error; 4341 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); 4342 if (status < 0) 4343 goto error; 4344 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); 4345 if (status < 0) 4346 goto error; 4347 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); 4348 if (status < 0) 4349 goto error; 4350 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); 4351 if (status < 0) 4352 goto error; 4353 4354 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); 4355 if (status < 0) 4356 goto error; 4357 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); 4358 if (status < 0) 4359 goto error; 4360 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80); 4361 if (status < 0) 4362 goto error; 4363 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); 4364 if (status < 0) 4365 goto error; 4366 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20); 4367 if (status < 0) 4368 goto error; 4369 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); 4370 if (status < 0) 4371 goto error; 4372 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); 4373 if (status < 0) 4374 goto error; 4375 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16); 4376 if (status < 0) 4377 goto error; 4378 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32); 4379 if (status < 0) 4380 goto error; 4381 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); 4382 if (status < 0) 4383 goto error; 4384 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); 4385 if (status < 0) 4386 goto error; 4387 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); 4388 if (status < 0) 4389 goto error; 4390 4391 4392 /* QAM State Machine (FSM) Thresholds */ 4393 4394 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140); 4395 if (status < 0) 4396 goto error; 4397 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50); 4398 if (status < 0) 4399 goto error; 4400 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95); 4401 if (status < 0) 4402 goto error; 4403 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120); 4404 if (status < 0) 4405 goto error; 4406 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230); 4407 if (status < 0) 4408 goto error; 4409 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105); 4410 if (status < 0) 4411 goto error; 4412 4413 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); 4414 if (status < 0) 4415 goto error; 4416 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); 4417 if (status < 0) 4418 goto error; 4419 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24); 4420 if (status < 0) 4421 goto error; 4422 4423 4424 /* QAM FSM Tracking Parameters */ 4425 4426 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16); 4427 if (status < 0) 4428 goto error; 4429 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220); 4430 if (status < 0) 4431 goto error; 4432 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25); 4433 if (status < 0) 4434 goto error; 4435 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6); 4436 if (status < 0) 4437 goto error; 4438 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24); 4439 if (status < 0) 4440 goto error; 4441 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65); 4442 if (status < 0) 4443 goto error; 4444 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127); 4445 if (status < 0) 4446 goto error; 4447 4448 error: 4449 if (status < 0) 4450 pr_err("Error %d on %s\n", status, __func__); 4451 return status; 4452 } 4453 4454 /*============================================================================*/ 4455 4456 /** 4457 * \brief QAM32 specific setup 4458 * \param demod instance of demod. 4459 * \return DRXStatus_t. 4460 */ 4461 static int set_qam32(struct drxk_state *state) 4462 { 4463 int status = 0; 4464 4465 dprintk(1, "\n"); 4466 4467 /* QAM Equalizer Setup */ 4468 /* Equalizer */ 4469 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707); 4470 if (status < 0) 4471 goto error; 4472 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707); 4473 if (status < 0) 4474 goto error; 4475 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707); 4476 if (status < 0) 4477 goto error; 4478 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707); 4479 if (status < 0) 4480 goto error; 4481 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707); 4482 if (status < 0) 4483 goto error; 4484 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707); 4485 if (status < 0) 4486 goto error; 4487 4488 /* Decision Feedback Equalizer */ 4489 status = write16(state, QAM_DQ_QUAL_FUN0__A, 3); 4490 if (status < 0) 4491 goto error; 4492 status = write16(state, QAM_DQ_QUAL_FUN1__A, 3); 4493 if (status < 0) 4494 goto error; 4495 status = write16(state, QAM_DQ_QUAL_FUN2__A, 3); 4496 if (status < 0) 4497 goto error; 4498 status = write16(state, QAM_DQ_QUAL_FUN3__A, 3); 4499 if (status < 0) 4500 goto error; 4501 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3); 4502 if (status < 0) 4503 goto error; 4504 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); 4505 if (status < 0) 4506 goto error; 4507 4508 status = write16(state, QAM_SY_SYNC_HWM__A, 6); 4509 if (status < 0) 4510 goto error; 4511 status = write16(state, QAM_SY_SYNC_AWM__A, 5); 4512 if (status < 0) 4513 goto error; 4514 status = write16(state, QAM_SY_SYNC_LWM__A, 3); 4515 if (status < 0) 4516 goto error; 4517 4518 /* QAM Slicer Settings */ 4519 4520 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, 4521 DRXK_QAM_SL_SIG_POWER_QAM32); 4522 if (status < 0) 4523 goto error; 4524 4525 4526 /* QAM Loop Controller Coeficients */ 4527 4528 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); 4529 if (status < 0) 4530 goto error; 4531 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); 4532 if (status < 0) 4533 goto error; 4534 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); 4535 if (status < 0) 4536 goto error; 4537 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); 4538 if (status < 0) 4539 goto error; 4540 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); 4541 if (status < 0) 4542 goto error; 4543 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); 4544 if (status < 0) 4545 goto error; 4546 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); 4547 if (status < 0) 4548 goto error; 4549 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); 4550 if (status < 0) 4551 goto error; 4552 4553 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); 4554 if (status < 0) 4555 goto error; 4556 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); 4557 if (status < 0) 4558 goto error; 4559 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80); 4560 if (status < 0) 4561 goto error; 4562 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); 4563 if (status < 0) 4564 goto error; 4565 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20); 4566 if (status < 0) 4567 goto error; 4568 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); 4569 if (status < 0) 4570 goto error; 4571 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); 4572 if (status < 0) 4573 goto error; 4574 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16); 4575 if (status < 0) 4576 goto error; 4577 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16); 4578 if (status < 0) 4579 goto error; 4580 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); 4581 if (status < 0) 4582 goto error; 4583 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); 4584 if (status < 0) 4585 goto error; 4586 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0); 4587 if (status < 0) 4588 goto error; 4589 4590 4591 /* QAM State Machine (FSM) Thresholds */ 4592 4593 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90); 4594 if (status < 0) 4595 goto error; 4596 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50); 4597 if (status < 0) 4598 goto error; 4599 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); 4600 if (status < 0) 4601 goto error; 4602 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100); 4603 if (status < 0) 4604 goto error; 4605 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170); 4606 if (status < 0) 4607 goto error; 4608 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100); 4609 if (status < 0) 4610 goto error; 4611 4612 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); 4613 if (status < 0) 4614 goto error; 4615 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); 4616 if (status < 0) 4617 goto error; 4618 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10); 4619 if (status < 0) 4620 goto error; 4621 4622 4623 /* QAM FSM Tracking Parameters */ 4624 4625 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12); 4626 if (status < 0) 4627 goto error; 4628 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140); 4629 if (status < 0) 4630 goto error; 4631 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8); 4632 if (status < 0) 4633 goto error; 4634 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16); 4635 if (status < 0) 4636 goto error; 4637 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26); 4638 if (status < 0) 4639 goto error; 4640 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56); 4641 if (status < 0) 4642 goto error; 4643 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86); 4644 error: 4645 if (status < 0) 4646 pr_err("Error %d on %s\n", status, __func__); 4647 return status; 4648 } 4649 4650 /*============================================================================*/ 4651 4652 /** 4653 * \brief QAM64 specific setup 4654 * \param demod instance of demod. 4655 * \return DRXStatus_t. 4656 */ 4657 static int set_qam64(struct drxk_state *state) 4658 { 4659 int status = 0; 4660 4661 dprintk(1, "\n"); 4662 /* QAM Equalizer Setup */ 4663 /* Equalizer */ 4664 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336); 4665 if (status < 0) 4666 goto error; 4667 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618); 4668 if (status < 0) 4669 goto error; 4670 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988); 4671 if (status < 0) 4672 goto error; 4673 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809); 4674 if (status < 0) 4675 goto error; 4676 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809); 4677 if (status < 0) 4678 goto error; 4679 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609); 4680 if (status < 0) 4681 goto error; 4682 4683 /* Decision Feedback Equalizer */ 4684 status = write16(state, QAM_DQ_QUAL_FUN0__A, 4); 4685 if (status < 0) 4686 goto error; 4687 status = write16(state, QAM_DQ_QUAL_FUN1__A, 4); 4688 if (status < 0) 4689 goto error; 4690 status = write16(state, QAM_DQ_QUAL_FUN2__A, 4); 4691 if (status < 0) 4692 goto error; 4693 status = write16(state, QAM_DQ_QUAL_FUN3__A, 4); 4694 if (status < 0) 4695 goto error; 4696 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3); 4697 if (status < 0) 4698 goto error; 4699 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); 4700 if (status < 0) 4701 goto error; 4702 4703 status = write16(state, QAM_SY_SYNC_HWM__A, 5); 4704 if (status < 0) 4705 goto error; 4706 status = write16(state, QAM_SY_SYNC_AWM__A, 4); 4707 if (status < 0) 4708 goto error; 4709 status = write16(state, QAM_SY_SYNC_LWM__A, 3); 4710 if (status < 0) 4711 goto error; 4712 4713 /* QAM Slicer Settings */ 4714 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, 4715 DRXK_QAM_SL_SIG_POWER_QAM64); 4716 if (status < 0) 4717 goto error; 4718 4719 4720 /* QAM Loop Controller Coeficients */ 4721 4722 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); 4723 if (status < 0) 4724 goto error; 4725 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); 4726 if (status < 0) 4727 goto error; 4728 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); 4729 if (status < 0) 4730 goto error; 4731 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); 4732 if (status < 0) 4733 goto error; 4734 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); 4735 if (status < 0) 4736 goto error; 4737 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); 4738 if (status < 0) 4739 goto error; 4740 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); 4741 if (status < 0) 4742 goto error; 4743 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); 4744 if (status < 0) 4745 goto error; 4746 4747 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); 4748 if (status < 0) 4749 goto error; 4750 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30); 4751 if (status < 0) 4752 goto error; 4753 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100); 4754 if (status < 0) 4755 goto error; 4756 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); 4757 if (status < 0) 4758 goto error; 4759 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30); 4760 if (status < 0) 4761 goto error; 4762 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); 4763 if (status < 0) 4764 goto error; 4765 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); 4766 if (status < 0) 4767 goto error; 4768 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); 4769 if (status < 0) 4770 goto error; 4771 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48); 4772 if (status < 0) 4773 goto error; 4774 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); 4775 if (status < 0) 4776 goto error; 4777 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); 4778 if (status < 0) 4779 goto error; 4780 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); 4781 if (status < 0) 4782 goto error; 4783 4784 4785 /* QAM State Machine (FSM) Thresholds */ 4786 4787 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100); 4788 if (status < 0) 4789 goto error; 4790 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60); 4791 if (status < 0) 4792 goto error; 4793 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); 4794 if (status < 0) 4795 goto error; 4796 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110); 4797 if (status < 0) 4798 goto error; 4799 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200); 4800 if (status < 0) 4801 goto error; 4802 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95); 4803 if (status < 0) 4804 goto error; 4805 4806 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); 4807 if (status < 0) 4808 goto error; 4809 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); 4810 if (status < 0) 4811 goto error; 4812 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15); 4813 if (status < 0) 4814 goto error; 4815 4816 4817 /* QAM FSM Tracking Parameters */ 4818 4819 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12); 4820 if (status < 0) 4821 goto error; 4822 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141); 4823 if (status < 0) 4824 goto error; 4825 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7); 4826 if (status < 0) 4827 goto error; 4828 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0); 4829 if (status < 0) 4830 goto error; 4831 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15); 4832 if (status < 0) 4833 goto error; 4834 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45); 4835 if (status < 0) 4836 goto error; 4837 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80); 4838 error: 4839 if (status < 0) 4840 pr_err("Error %d on %s\n", status, __func__); 4841 4842 return status; 4843 } 4844 4845 /*============================================================================*/ 4846 4847 /** 4848 * \brief QAM128 specific setup 4849 * \param demod: instance of demod. 4850 * \return DRXStatus_t. 4851 */ 4852 static int set_qam128(struct drxk_state *state) 4853 { 4854 int status = 0; 4855 4856 dprintk(1, "\n"); 4857 /* QAM Equalizer Setup */ 4858 /* Equalizer */ 4859 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564); 4860 if (status < 0) 4861 goto error; 4862 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598); 4863 if (status < 0) 4864 goto error; 4865 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394); 4866 if (status < 0) 4867 goto error; 4868 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409); 4869 if (status < 0) 4870 goto error; 4871 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656); 4872 if (status < 0) 4873 goto error; 4874 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238); 4875 if (status < 0) 4876 goto error; 4877 4878 /* Decision Feedback Equalizer */ 4879 status = write16(state, QAM_DQ_QUAL_FUN0__A, 6); 4880 if (status < 0) 4881 goto error; 4882 status = write16(state, QAM_DQ_QUAL_FUN1__A, 6); 4883 if (status < 0) 4884 goto error; 4885 status = write16(state, QAM_DQ_QUAL_FUN2__A, 6); 4886 if (status < 0) 4887 goto error; 4888 status = write16(state, QAM_DQ_QUAL_FUN3__A, 6); 4889 if (status < 0) 4890 goto error; 4891 status = write16(state, QAM_DQ_QUAL_FUN4__A, 5); 4892 if (status < 0) 4893 goto error; 4894 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); 4895 if (status < 0) 4896 goto error; 4897 4898 status = write16(state, QAM_SY_SYNC_HWM__A, 6); 4899 if (status < 0) 4900 goto error; 4901 status = write16(state, QAM_SY_SYNC_AWM__A, 5); 4902 if (status < 0) 4903 goto error; 4904 status = write16(state, QAM_SY_SYNC_LWM__A, 3); 4905 if (status < 0) 4906 goto error; 4907 4908 4909 /* QAM Slicer Settings */ 4910 4911 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, 4912 DRXK_QAM_SL_SIG_POWER_QAM128); 4913 if (status < 0) 4914 goto error; 4915 4916 4917 /* QAM Loop Controller Coeficients */ 4918 4919 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); 4920 if (status < 0) 4921 goto error; 4922 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); 4923 if (status < 0) 4924 goto error; 4925 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); 4926 if (status < 0) 4927 goto error; 4928 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); 4929 if (status < 0) 4930 goto error; 4931 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); 4932 if (status < 0) 4933 goto error; 4934 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); 4935 if (status < 0) 4936 goto error; 4937 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); 4938 if (status < 0) 4939 goto error; 4940 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); 4941 if (status < 0) 4942 goto error; 4943 4944 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); 4945 if (status < 0) 4946 goto error; 4947 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40); 4948 if (status < 0) 4949 goto error; 4950 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120); 4951 if (status < 0) 4952 goto error; 4953 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); 4954 if (status < 0) 4955 goto error; 4956 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40); 4957 if (status < 0) 4958 goto error; 4959 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60); 4960 if (status < 0) 4961 goto error; 4962 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); 4963 if (status < 0) 4964 goto error; 4965 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); 4966 if (status < 0) 4967 goto error; 4968 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64); 4969 if (status < 0) 4970 goto error; 4971 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); 4972 if (status < 0) 4973 goto error; 4974 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); 4975 if (status < 0) 4976 goto error; 4977 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0); 4978 if (status < 0) 4979 goto error; 4980 4981 4982 /* QAM State Machine (FSM) Thresholds */ 4983 4984 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50); 4985 if (status < 0) 4986 goto error; 4987 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60); 4988 if (status < 0) 4989 goto error; 4990 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); 4991 if (status < 0) 4992 goto error; 4993 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100); 4994 if (status < 0) 4995 goto error; 4996 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140); 4997 if (status < 0) 4998 goto error; 4999 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100); 5000 if (status < 0) 5001 goto error; 5002 5003 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); 5004 if (status < 0) 5005 goto error; 5006 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5); 5007 if (status < 0) 5008 goto error; 5009 5010 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12); 5011 if (status < 0) 5012 goto error; 5013 5014 /* QAM FSM Tracking Parameters */ 5015 5016 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8); 5017 if (status < 0) 5018 goto error; 5019 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65); 5020 if (status < 0) 5021 goto error; 5022 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5); 5023 if (status < 0) 5024 goto error; 5025 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3); 5026 if (status < 0) 5027 goto error; 5028 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1); 5029 if (status < 0) 5030 goto error; 5031 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12); 5032 if (status < 0) 5033 goto error; 5034 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23); 5035 error: 5036 if (status < 0) 5037 pr_err("Error %d on %s\n", status, __func__); 5038 5039 return status; 5040 } 5041 5042 /*============================================================================*/ 5043 5044 /** 5045 * \brief QAM256 specific setup 5046 * \param demod: instance of demod. 5047 * \return DRXStatus_t. 5048 */ 5049 static int set_qam256(struct drxk_state *state) 5050 { 5051 int status = 0; 5052 5053 dprintk(1, "\n"); 5054 /* QAM Equalizer Setup */ 5055 /* Equalizer */ 5056 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502); 5057 if (status < 0) 5058 goto error; 5059 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084); 5060 if (status < 0) 5061 goto error; 5062 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543); 5063 if (status < 0) 5064 goto error; 5065 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931); 5066 if (status < 0) 5067 goto error; 5068 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629); 5069 if (status < 0) 5070 goto error; 5071 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385); 5072 if (status < 0) 5073 goto error; 5074 5075 /* Decision Feedback Equalizer */ 5076 status = write16(state, QAM_DQ_QUAL_FUN0__A, 8); 5077 if (status < 0) 5078 goto error; 5079 status = write16(state, QAM_DQ_QUAL_FUN1__A, 8); 5080 if (status < 0) 5081 goto error; 5082 status = write16(state, QAM_DQ_QUAL_FUN2__A, 8); 5083 if (status < 0) 5084 goto error; 5085 status = write16(state, QAM_DQ_QUAL_FUN3__A, 8); 5086 if (status < 0) 5087 goto error; 5088 status = write16(state, QAM_DQ_QUAL_FUN4__A, 6); 5089 if (status < 0) 5090 goto error; 5091 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); 5092 if (status < 0) 5093 goto error; 5094 5095 status = write16(state, QAM_SY_SYNC_HWM__A, 5); 5096 if (status < 0) 5097 goto error; 5098 status = write16(state, QAM_SY_SYNC_AWM__A, 4); 5099 if (status < 0) 5100 goto error; 5101 status = write16(state, QAM_SY_SYNC_LWM__A, 3); 5102 if (status < 0) 5103 goto error; 5104 5105 /* QAM Slicer Settings */ 5106 5107 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, 5108 DRXK_QAM_SL_SIG_POWER_QAM256); 5109 if (status < 0) 5110 goto error; 5111 5112 5113 /* QAM Loop Controller Coeficients */ 5114 5115 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); 5116 if (status < 0) 5117 goto error; 5118 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); 5119 if (status < 0) 5120 goto error; 5121 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); 5122 if (status < 0) 5123 goto error; 5124 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); 5125 if (status < 0) 5126 goto error; 5127 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); 5128 if (status < 0) 5129 goto error; 5130 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); 5131 if (status < 0) 5132 goto error; 5133 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); 5134 if (status < 0) 5135 goto error; 5136 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); 5137 if (status < 0) 5138 goto error; 5139 5140 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); 5141 if (status < 0) 5142 goto error; 5143 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50); 5144 if (status < 0) 5145 goto error; 5146 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250); 5147 if (status < 0) 5148 goto error; 5149 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); 5150 if (status < 0) 5151 goto error; 5152 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50); 5153 if (status < 0) 5154 goto error; 5155 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125); 5156 if (status < 0) 5157 goto error; 5158 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); 5159 if (status < 0) 5160 goto error; 5161 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); 5162 if (status < 0) 5163 goto error; 5164 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48); 5165 if (status < 0) 5166 goto error; 5167 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); 5168 if (status < 0) 5169 goto error; 5170 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); 5171 if (status < 0) 5172 goto error; 5173 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); 5174 if (status < 0) 5175 goto error; 5176 5177 5178 /* QAM State Machine (FSM) Thresholds */ 5179 5180 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50); 5181 if (status < 0) 5182 goto error; 5183 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60); 5184 if (status < 0) 5185 goto error; 5186 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); 5187 if (status < 0) 5188 goto error; 5189 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100); 5190 if (status < 0) 5191 goto error; 5192 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150); 5193 if (status < 0) 5194 goto error; 5195 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110); 5196 if (status < 0) 5197 goto error; 5198 5199 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); 5200 if (status < 0) 5201 goto error; 5202 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); 5203 if (status < 0) 5204 goto error; 5205 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12); 5206 if (status < 0) 5207 goto error; 5208 5209 5210 /* QAM FSM Tracking Parameters */ 5211 5212 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8); 5213 if (status < 0) 5214 goto error; 5215 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74); 5216 if (status < 0) 5217 goto error; 5218 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18); 5219 if (status < 0) 5220 goto error; 5221 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13); 5222 if (status < 0) 5223 goto error; 5224 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7); 5225 if (status < 0) 5226 goto error; 5227 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0); 5228 if (status < 0) 5229 goto error; 5230 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8); 5231 error: 5232 if (status < 0) 5233 pr_err("Error %d on %s\n", status, __func__); 5234 return status; 5235 } 5236 5237 5238 /*============================================================================*/ 5239 /** 5240 * \brief Reset QAM block. 5241 * \param demod: instance of demod. 5242 * \param channel: pointer to channel data. 5243 * \return DRXStatus_t. 5244 */ 5245 static int qam_reset_qam(struct drxk_state *state) 5246 { 5247 int status; 5248 u16 cmd_result; 5249 5250 dprintk(1, "\n"); 5251 /* Stop QAM comstate->m_exec */ 5252 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); 5253 if (status < 0) 5254 goto error; 5255 5256 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM 5257 | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 5258 0, NULL, 1, &cmd_result); 5259 error: 5260 if (status < 0) 5261 pr_err("Error %d on %s\n", status, __func__); 5262 return status; 5263 } 5264 5265 /*============================================================================*/ 5266 5267 /** 5268 * \brief Set QAM symbolrate. 5269 * \param demod: instance of demod. 5270 * \param channel: pointer to channel data. 5271 * \return DRXStatus_t. 5272 */ 5273 static int qam_set_symbolrate(struct drxk_state *state) 5274 { 5275 u32 adc_frequency = 0; 5276 u32 symb_freq = 0; 5277 u32 iqm_rc_rate = 0; 5278 u16 ratesel = 0; 5279 u32 lc_symb_rate = 0; 5280 int status; 5281 5282 dprintk(1, "\n"); 5283 /* Select & calculate correct IQM rate */ 5284 adc_frequency = (state->m_sys_clock_freq * 1000) / 3; 5285 ratesel = 0; 5286 /* printk(KERN_DEBUG "drxk: SR %d\n", state->props.symbol_rate); */ 5287 if (state->props.symbol_rate <= 1188750) 5288 ratesel = 3; 5289 else if (state->props.symbol_rate <= 2377500) 5290 ratesel = 2; 5291 else if (state->props.symbol_rate <= 4755000) 5292 ratesel = 1; 5293 status = write16(state, IQM_FD_RATESEL__A, ratesel); 5294 if (status < 0) 5295 goto error; 5296 5297 /* 5298 IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23) 5299 */ 5300 symb_freq = state->props.symbol_rate * (1 << ratesel); 5301 if (symb_freq == 0) { 5302 /* Divide by zero */ 5303 status = -EINVAL; 5304 goto error; 5305 } 5306 iqm_rc_rate = (adc_frequency / symb_freq) * (1 << 21) + 5307 (Frac28a((adc_frequency % symb_freq), symb_freq) >> 7) - 5308 (1 << 23); 5309 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate); 5310 if (status < 0) 5311 goto error; 5312 state->m_iqm_rc_rate = iqm_rc_rate; 5313 /* 5314 LcSymbFreq = round (.125 * symbolrate / adc_freq * (1<<15)) 5315 */ 5316 symb_freq = state->props.symbol_rate; 5317 if (adc_frequency == 0) { 5318 /* Divide by zero */ 5319 status = -EINVAL; 5320 goto error; 5321 } 5322 lc_symb_rate = (symb_freq / adc_frequency) * (1 << 12) + 5323 (Frac28a((symb_freq % adc_frequency), adc_frequency) >> 5324 16); 5325 if (lc_symb_rate > 511) 5326 lc_symb_rate = 511; 5327 status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lc_symb_rate); 5328 5329 error: 5330 if (status < 0) 5331 pr_err("Error %d on %s\n", status, __func__); 5332 return status; 5333 } 5334 5335 /*============================================================================*/ 5336 5337 /** 5338 * \brief Get QAM lock status. 5339 * \param demod: instance of demod. 5340 * \param channel: pointer to channel data. 5341 * \return DRXStatus_t. 5342 */ 5343 5344 static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status) 5345 { 5346 int status; 5347 u16 result[2] = { 0, 0 }; 5348 5349 dprintk(1, "\n"); 5350 *p_lock_status = NOT_LOCKED; 5351 status = scu_command(state, 5352 SCU_RAM_COMMAND_STANDARD_QAM | 5353 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2, 5354 result); 5355 if (status < 0) 5356 pr_err("Error %d on %s\n", status, __func__); 5357 5358 if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) { 5359 /* 0x0000 NOT LOCKED */ 5360 } else if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) { 5361 /* 0x4000 DEMOD LOCKED */ 5362 *p_lock_status = DEMOD_LOCK; 5363 } else if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) { 5364 /* 0x8000 DEMOD + FEC LOCKED (system lock) */ 5365 *p_lock_status = MPEG_LOCK; 5366 } else { 5367 /* 0xC000 NEVER LOCKED */ 5368 /* (system will never be able to lock to the signal) */ 5369 /* 5370 * TODO: check this, intermediate & standard specific lock 5371 * states are not taken into account here 5372 */ 5373 *p_lock_status = NEVER_LOCK; 5374 } 5375 return status; 5376 } 5377 5378 #define QAM_MIRROR__M 0x03 5379 #define QAM_MIRROR_NORMAL 0x00 5380 #define QAM_MIRRORED 0x01 5381 #define QAM_MIRROR_AUTO_ON 0x02 5382 #define QAM_LOCKRANGE__M 0x10 5383 #define QAM_LOCKRANGE_NORMAL 0x10 5384 5385 static int qam_demodulator_command(struct drxk_state *state, 5386 int number_of_parameters) 5387 { 5388 int status; 5389 u16 cmd_result; 5390 u16 set_param_parameters[4] = { 0, 0, 0, 0 }; 5391 5392 set_param_parameters[0] = state->m_constellation; /* modulation */ 5393 set_param_parameters[1] = DRXK_QAM_I12_J17; /* interleave mode */ 5394 5395 if (number_of_parameters == 2) { 5396 u16 set_env_parameters[1] = { 0 }; 5397 5398 if (state->m_operation_mode == OM_QAM_ITU_C) 5399 set_env_parameters[0] = QAM_TOP_ANNEX_C; 5400 else 5401 set_env_parameters[0] = QAM_TOP_ANNEX_A; 5402 5403 status = scu_command(state, 5404 SCU_RAM_COMMAND_STANDARD_QAM 5405 | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 5406 1, set_env_parameters, 1, &cmd_result); 5407 if (status < 0) 5408 goto error; 5409 5410 status = scu_command(state, 5411 SCU_RAM_COMMAND_STANDARD_QAM 5412 | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 5413 number_of_parameters, set_param_parameters, 5414 1, &cmd_result); 5415 } else if (number_of_parameters == 4) { 5416 if (state->m_operation_mode == OM_QAM_ITU_C) 5417 set_param_parameters[2] = QAM_TOP_ANNEX_C; 5418 else 5419 set_param_parameters[2] = QAM_TOP_ANNEX_A; 5420 5421 set_param_parameters[3] |= (QAM_MIRROR_AUTO_ON); 5422 /* Env parameters */ 5423 /* check for LOCKRANGE Extented */ 5424 /* set_param_parameters[3] |= QAM_LOCKRANGE_NORMAL; */ 5425 5426 status = scu_command(state, 5427 SCU_RAM_COMMAND_STANDARD_QAM 5428 | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 5429 number_of_parameters, set_param_parameters, 5430 1, &cmd_result); 5431 } else { 5432 pr_warn("Unknown QAM demodulator parameter count %d\n", 5433 number_of_parameters); 5434 status = -EINVAL; 5435 } 5436 5437 error: 5438 if (status < 0) 5439 pr_warn("Warning %d on %s\n", status, __func__); 5440 return status; 5441 } 5442 5443 static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz, 5444 s32 tuner_freq_offset) 5445 { 5446 int status; 5447 u16 cmd_result; 5448 int qam_demod_param_count = state->qam_demod_parameter_count; 5449 5450 dprintk(1, "\n"); 5451 /* 5452 * STEP 1: reset demodulator 5453 * resets FEC DI and FEC RS 5454 * resets QAM block 5455 * resets SCU variables 5456 */ 5457 status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP); 5458 if (status < 0) 5459 goto error; 5460 status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP); 5461 if (status < 0) 5462 goto error; 5463 status = qam_reset_qam(state); 5464 if (status < 0) 5465 goto error; 5466 5467 /* 5468 * STEP 2: configure demodulator 5469 * -set params; resets IQM,QAM,FEC HW; initializes some 5470 * SCU variables 5471 */ 5472 status = qam_set_symbolrate(state); 5473 if (status < 0) 5474 goto error; 5475 5476 /* Set params */ 5477 switch (state->props.modulation) { 5478 case QAM_256: 5479 state->m_constellation = DRX_CONSTELLATION_QAM256; 5480 break; 5481 case QAM_AUTO: 5482 case QAM_64: 5483 state->m_constellation = DRX_CONSTELLATION_QAM64; 5484 break; 5485 case QAM_16: 5486 state->m_constellation = DRX_CONSTELLATION_QAM16; 5487 break; 5488 case QAM_32: 5489 state->m_constellation = DRX_CONSTELLATION_QAM32; 5490 break; 5491 case QAM_128: 5492 state->m_constellation = DRX_CONSTELLATION_QAM128; 5493 break; 5494 default: 5495 status = -EINVAL; 5496 break; 5497 } 5498 if (status < 0) 5499 goto error; 5500 5501 /* Use the 4-parameter if it's requested or we're probing for 5502 * the correct command. */ 5503 if (state->qam_demod_parameter_count == 4 5504 || !state->qam_demod_parameter_count) { 5505 qam_demod_param_count = 4; 5506 status = qam_demodulator_command(state, qam_demod_param_count); 5507 } 5508 5509 /* Use the 2-parameter command if it was requested or if we're 5510 * probing for the correct command and the 4-parameter command 5511 * failed. */ 5512 if (state->qam_demod_parameter_count == 2 5513 || (!state->qam_demod_parameter_count && status < 0)) { 5514 qam_demod_param_count = 2; 5515 status = qam_demodulator_command(state, qam_demod_param_count); 5516 } 5517 5518 if (status < 0) { 5519 dprintk(1, "Could not set demodulator parameters.\n"); 5520 dprintk(1, 5521 "Make sure qam_demod_parameter_count (%d) is correct for your firmware (%s).\n", 5522 state->qam_demod_parameter_count, 5523 state->microcode_name); 5524 goto error; 5525 } else if (!state->qam_demod_parameter_count) { 5526 dprintk(1, 5527 "Auto-probing the QAM command parameters was successful - using %d parameters.\n", 5528 qam_demod_param_count); 5529 5530 /* 5531 * One of our commands was successful. We don't need to 5532 * auto-probe anymore, now that we got the correct command. 5533 */ 5534 state->qam_demod_parameter_count = qam_demod_param_count; 5535 } 5536 5537 /* 5538 * STEP 3: enable the system in a mode where the ADC provides valid 5539 * signal setup modulation independent registers 5540 */ 5541 #if 0 5542 status = set_frequency(channel, tuner_freq_offset)); 5543 if (status < 0) 5544 goto error; 5545 #endif 5546 status = set_frequency_shifter(state, intermediate_freqk_hz, 5547 tuner_freq_offset, true); 5548 if (status < 0) 5549 goto error; 5550 5551 /* Setup BER measurement */ 5552 status = set_qam_measurement(state, state->m_constellation, 5553 state->props.symbol_rate); 5554 if (status < 0) 5555 goto error; 5556 5557 /* Reset default values */ 5558 status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE); 5559 if (status < 0) 5560 goto error; 5561 status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE); 5562 if (status < 0) 5563 goto error; 5564 5565 /* Reset default LC values */ 5566 status = write16(state, QAM_LC_RATE_LIMIT__A, 3); 5567 if (status < 0) 5568 goto error; 5569 status = write16(state, QAM_LC_LPF_FACTORP__A, 4); 5570 if (status < 0) 5571 goto error; 5572 status = write16(state, QAM_LC_LPF_FACTORI__A, 4); 5573 if (status < 0) 5574 goto error; 5575 status = write16(state, QAM_LC_MODE__A, 7); 5576 if (status < 0) 5577 goto error; 5578 5579 status = write16(state, QAM_LC_QUAL_TAB0__A, 1); 5580 if (status < 0) 5581 goto error; 5582 status = write16(state, QAM_LC_QUAL_TAB1__A, 1); 5583 if (status < 0) 5584 goto error; 5585 status = write16(state, QAM_LC_QUAL_TAB2__A, 1); 5586 if (status < 0) 5587 goto error; 5588 status = write16(state, QAM_LC_QUAL_TAB3__A, 1); 5589 if (status < 0) 5590 goto error; 5591 status = write16(state, QAM_LC_QUAL_TAB4__A, 2); 5592 if (status < 0) 5593 goto error; 5594 status = write16(state, QAM_LC_QUAL_TAB5__A, 2); 5595 if (status < 0) 5596 goto error; 5597 status = write16(state, QAM_LC_QUAL_TAB6__A, 2); 5598 if (status < 0) 5599 goto error; 5600 status = write16(state, QAM_LC_QUAL_TAB8__A, 2); 5601 if (status < 0) 5602 goto error; 5603 status = write16(state, QAM_LC_QUAL_TAB9__A, 2); 5604 if (status < 0) 5605 goto error; 5606 status = write16(state, QAM_LC_QUAL_TAB10__A, 2); 5607 if (status < 0) 5608 goto error; 5609 status = write16(state, QAM_LC_QUAL_TAB12__A, 2); 5610 if (status < 0) 5611 goto error; 5612 status = write16(state, QAM_LC_QUAL_TAB15__A, 3); 5613 if (status < 0) 5614 goto error; 5615 status = write16(state, QAM_LC_QUAL_TAB16__A, 3); 5616 if (status < 0) 5617 goto error; 5618 status = write16(state, QAM_LC_QUAL_TAB20__A, 4); 5619 if (status < 0) 5620 goto error; 5621 status = write16(state, QAM_LC_QUAL_TAB25__A, 4); 5622 if (status < 0) 5623 goto error; 5624 5625 /* Mirroring, QAM-block starting point not inverted */ 5626 status = write16(state, QAM_SY_SP_INV__A, 5627 QAM_SY_SP_INV_SPECTRUM_INV_DIS); 5628 if (status < 0) 5629 goto error; 5630 5631 /* Halt SCU to enable safe non-atomic accesses */ 5632 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); 5633 if (status < 0) 5634 goto error; 5635 5636 /* STEP 4: modulation specific setup */ 5637 switch (state->props.modulation) { 5638 case QAM_16: 5639 status = set_qam16(state); 5640 break; 5641 case QAM_32: 5642 status = set_qam32(state); 5643 break; 5644 case QAM_AUTO: 5645 case QAM_64: 5646 status = set_qam64(state); 5647 break; 5648 case QAM_128: 5649 status = set_qam128(state); 5650 break; 5651 case QAM_256: 5652 status = set_qam256(state); 5653 break; 5654 default: 5655 status = -EINVAL; 5656 break; 5657 } 5658 if (status < 0) 5659 goto error; 5660 5661 /* Activate SCU to enable SCU commands */ 5662 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); 5663 if (status < 0) 5664 goto error; 5665 5666 /* Re-configure MPEG output, requires knowledge of channel bitrate */ 5667 /* extAttr->currentChannel.modulation = channel->modulation; */ 5668 /* extAttr->currentChannel.symbolrate = channel->symbolrate; */ 5669 status = mpegts_dto_setup(state, state->m_operation_mode); 5670 if (status < 0) 5671 goto error; 5672 5673 /* start processes */ 5674 status = mpegts_start(state); 5675 if (status < 0) 5676 goto error; 5677 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); 5678 if (status < 0) 5679 goto error; 5680 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE); 5681 if (status < 0) 5682 goto error; 5683 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE); 5684 if (status < 0) 5685 goto error; 5686 5687 /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */ 5688 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM 5689 | SCU_RAM_COMMAND_CMD_DEMOD_START, 5690 0, NULL, 1, &cmd_result); 5691 if (status < 0) 5692 goto error; 5693 5694 /* update global DRXK data container */ 5695 /*? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */ 5696 5697 error: 5698 if (status < 0) 5699 pr_err("Error %d on %s\n", status, __func__); 5700 return status; 5701 } 5702 5703 static int set_qam_standard(struct drxk_state *state, 5704 enum operation_mode o_mode) 5705 { 5706 int status; 5707 #ifdef DRXK_QAM_TAPS 5708 #define DRXK_QAMA_TAPS_SELECT 5709 #include "drxk_filters.h" 5710 #undef DRXK_QAMA_TAPS_SELECT 5711 #endif 5712 5713 dprintk(1, "\n"); 5714 5715 /* added antenna switch */ 5716 switch_antenna_to_qam(state); 5717 5718 /* Ensure correct power-up mode */ 5719 status = power_up_qam(state); 5720 if (status < 0) 5721 goto error; 5722 /* Reset QAM block */ 5723 status = qam_reset_qam(state); 5724 if (status < 0) 5725 goto error; 5726 5727 /* Setup IQM */ 5728 5729 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); 5730 if (status < 0) 5731 goto error; 5732 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC); 5733 if (status < 0) 5734 goto error; 5735 5736 /* Upload IQM Channel Filter settings by 5737 boot loader from ROM table */ 5738 switch (o_mode) { 5739 case OM_QAM_ITU_A: 5740 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A, 5741 DRXK_BLCC_NR_ELEMENTS_TAPS, 5742 DRXK_BLC_TIMEOUT); 5743 break; 5744 case OM_QAM_ITU_C: 5745 status = bl_direct_cmd(state, IQM_CF_TAP_RE0__A, 5746 DRXK_BL_ROM_OFFSET_TAPS_ITU_C, 5747 DRXK_BLDC_NR_ELEMENTS_TAPS, 5748 DRXK_BLC_TIMEOUT); 5749 if (status < 0) 5750 goto error; 5751 status = bl_direct_cmd(state, 5752 IQM_CF_TAP_IM0__A, 5753 DRXK_BL_ROM_OFFSET_TAPS_ITU_C, 5754 DRXK_BLDC_NR_ELEMENTS_TAPS, 5755 DRXK_BLC_TIMEOUT); 5756 break; 5757 default: 5758 status = -EINVAL; 5759 } 5760 if (status < 0) 5761 goto error; 5762 5763 status = write16(state, IQM_CF_OUT_ENA__A, 1 << IQM_CF_OUT_ENA_QAM__B); 5764 if (status < 0) 5765 goto error; 5766 status = write16(state, IQM_CF_SYMMETRIC__A, 0); 5767 if (status < 0) 5768 goto error; 5769 status = write16(state, IQM_CF_MIDTAP__A, 5770 ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B))); 5771 if (status < 0) 5772 goto error; 5773 5774 status = write16(state, IQM_RC_STRETCH__A, 21); 5775 if (status < 0) 5776 goto error; 5777 status = write16(state, IQM_AF_CLP_LEN__A, 0); 5778 if (status < 0) 5779 goto error; 5780 status = write16(state, IQM_AF_CLP_TH__A, 448); 5781 if (status < 0) 5782 goto error; 5783 status = write16(state, IQM_AF_SNS_LEN__A, 0); 5784 if (status < 0) 5785 goto error; 5786 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0); 5787 if (status < 0) 5788 goto error; 5789 5790 status = write16(state, IQM_FS_ADJ_SEL__A, 1); 5791 if (status < 0) 5792 goto error; 5793 status = write16(state, IQM_RC_ADJ_SEL__A, 1); 5794 if (status < 0) 5795 goto error; 5796 status = write16(state, IQM_CF_ADJ_SEL__A, 1); 5797 if (status < 0) 5798 goto error; 5799 status = write16(state, IQM_AF_UPD_SEL__A, 0); 5800 if (status < 0) 5801 goto error; 5802 5803 /* IQM Impulse Noise Processing Unit */ 5804 status = write16(state, IQM_CF_CLP_VAL__A, 500); 5805 if (status < 0) 5806 goto error; 5807 status = write16(state, IQM_CF_DATATH__A, 1000); 5808 if (status < 0) 5809 goto error; 5810 status = write16(state, IQM_CF_BYPASSDET__A, 1); 5811 if (status < 0) 5812 goto error; 5813 status = write16(state, IQM_CF_DET_LCT__A, 0); 5814 if (status < 0) 5815 goto error; 5816 status = write16(state, IQM_CF_WND_LEN__A, 1); 5817 if (status < 0) 5818 goto error; 5819 status = write16(state, IQM_CF_PKDTH__A, 1); 5820 if (status < 0) 5821 goto error; 5822 status = write16(state, IQM_AF_INC_BYPASS__A, 1); 5823 if (status < 0) 5824 goto error; 5825 5826 /* turn on IQMAF. Must be done before setAgc**() */ 5827 status = set_iqm_af(state, true); 5828 if (status < 0) 5829 goto error; 5830 status = write16(state, IQM_AF_START_LOCK__A, 0x01); 5831 if (status < 0) 5832 goto error; 5833 5834 /* IQM will not be reset from here, sync ADC and update/init AGC */ 5835 status = adc_synchronization(state); 5836 if (status < 0) 5837 goto error; 5838 5839 /* Set the FSM step period */ 5840 status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000); 5841 if (status < 0) 5842 goto error; 5843 5844 /* Halt SCU to enable safe non-atomic accesses */ 5845 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); 5846 if (status < 0) 5847 goto error; 5848 5849 /* No more resets of the IQM, current standard correctly set => 5850 now AGCs can be configured. */ 5851 5852 status = init_agc(state, true); 5853 if (status < 0) 5854 goto error; 5855 status = set_pre_saw(state, &(state->m_qam_pre_saw_cfg)); 5856 if (status < 0) 5857 goto error; 5858 5859 /* Configure AGC's */ 5860 status = set_agc_rf(state, &(state->m_qam_rf_agc_cfg), true); 5861 if (status < 0) 5862 goto error; 5863 status = set_agc_if(state, &(state->m_qam_if_agc_cfg), true); 5864 if (status < 0) 5865 goto error; 5866 5867 /* Activate SCU to enable SCU commands */ 5868 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); 5869 error: 5870 if (status < 0) 5871 pr_err("Error %d on %s\n", status, __func__); 5872 return status; 5873 } 5874 5875 static int write_gpio(struct drxk_state *state) 5876 { 5877 int status; 5878 u16 value = 0; 5879 5880 dprintk(1, "\n"); 5881 /* stop lock indicator process */ 5882 status = write16(state, SCU_RAM_GPIO__A, 5883 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); 5884 if (status < 0) 5885 goto error; 5886 5887 /* Write magic word to enable pdr reg write */ 5888 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); 5889 if (status < 0) 5890 goto error; 5891 5892 if (state->m_has_sawsw) { 5893 if (state->uio_mask & 0x0001) { /* UIO-1 */ 5894 /* write to io pad configuration register - output mode */ 5895 status = write16(state, SIO_PDR_SMA_TX_CFG__A, 5896 state->m_gpio_cfg); 5897 if (status < 0) 5898 goto error; 5899 5900 /* use corresponding bit in io data output registar */ 5901 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); 5902 if (status < 0) 5903 goto error; 5904 if ((state->m_gpio & 0x0001) == 0) 5905 value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */ 5906 else 5907 value |= 0x8000; /* write one to 15th bit - 1st UIO */ 5908 /* write back to io data output register */ 5909 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value); 5910 if (status < 0) 5911 goto error; 5912 } 5913 if (state->uio_mask & 0x0002) { /* UIO-2 */ 5914 /* write to io pad configuration register - output mode */ 5915 status = write16(state, SIO_PDR_SMA_RX_CFG__A, 5916 state->m_gpio_cfg); 5917 if (status < 0) 5918 goto error; 5919 5920 /* use corresponding bit in io data output registar */ 5921 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); 5922 if (status < 0) 5923 goto error; 5924 if ((state->m_gpio & 0x0002) == 0) 5925 value &= 0xBFFF; /* write zero to 14th bit - 2st UIO */ 5926 else 5927 value |= 0x4000; /* write one to 14th bit - 2st UIO */ 5928 /* write back to io data output register */ 5929 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value); 5930 if (status < 0) 5931 goto error; 5932 } 5933 if (state->uio_mask & 0x0004) { /* UIO-3 */ 5934 /* write to io pad configuration register - output mode */ 5935 status = write16(state, SIO_PDR_GPIO_CFG__A, 5936 state->m_gpio_cfg); 5937 if (status < 0) 5938 goto error; 5939 5940 /* use corresponding bit in io data output registar */ 5941 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); 5942 if (status < 0) 5943 goto error; 5944 if ((state->m_gpio & 0x0004) == 0) 5945 value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */ 5946 else 5947 value |= 0x0004; /* write one to 2nd bit - 3rd UIO */ 5948 /* write back to io data output register */ 5949 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value); 5950 if (status < 0) 5951 goto error; 5952 } 5953 } 5954 /* Write magic word to disable pdr reg write */ 5955 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); 5956 error: 5957 if (status < 0) 5958 pr_err("Error %d on %s\n", status, __func__); 5959 return status; 5960 } 5961 5962 static int switch_antenna_to_qam(struct drxk_state *state) 5963 { 5964 int status = 0; 5965 bool gpio_state; 5966 5967 dprintk(1, "\n"); 5968 5969 if (!state->antenna_gpio) 5970 return 0; 5971 5972 gpio_state = state->m_gpio & state->antenna_gpio; 5973 5974 if (state->antenna_dvbt ^ gpio_state) { 5975 /* Antenna is on DVB-T mode. Switch */ 5976 if (state->antenna_dvbt) 5977 state->m_gpio &= ~state->antenna_gpio; 5978 else 5979 state->m_gpio |= state->antenna_gpio; 5980 status = write_gpio(state); 5981 } 5982 if (status < 0) 5983 pr_err("Error %d on %s\n", status, __func__); 5984 return status; 5985 } 5986 5987 static int switch_antenna_to_dvbt(struct drxk_state *state) 5988 { 5989 int status = 0; 5990 bool gpio_state; 5991 5992 dprintk(1, "\n"); 5993 5994 if (!state->antenna_gpio) 5995 return 0; 5996 5997 gpio_state = state->m_gpio & state->antenna_gpio; 5998 5999 if (!(state->antenna_dvbt ^ gpio_state)) { 6000 /* Antenna is on DVB-C mode. Switch */ 6001 if (state->antenna_dvbt) 6002 state->m_gpio |= state->antenna_gpio; 6003 else 6004 state->m_gpio &= ~state->antenna_gpio; 6005 status = write_gpio(state); 6006 } 6007 if (status < 0) 6008 pr_err("Error %d on %s\n", status, __func__); 6009 return status; 6010 } 6011 6012 6013 static int power_down_device(struct drxk_state *state) 6014 { 6015 /* Power down to requested mode */ 6016 /* Backup some register settings */ 6017 /* Set pins with possible pull-ups connected to them in input mode */ 6018 /* Analog power down */ 6019 /* ADC power down */ 6020 /* Power down device */ 6021 int status; 6022 6023 dprintk(1, "\n"); 6024 if (state->m_b_p_down_open_bridge) { 6025 /* Open I2C bridge before power down of DRXK */ 6026 status = ConfigureI2CBridge(state, true); 6027 if (status < 0) 6028 goto error; 6029 } 6030 /* driver 0.9.0 */ 6031 status = dvbt_enable_ofdm_token_ring(state, false); 6032 if (status < 0) 6033 goto error; 6034 6035 status = write16(state, SIO_CC_PWD_MODE__A, 6036 SIO_CC_PWD_MODE_LEVEL_CLOCK); 6037 if (status < 0) 6038 goto error; 6039 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); 6040 if (status < 0) 6041 goto error; 6042 state->m_hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; 6043 status = hi_cfg_command(state); 6044 error: 6045 if (status < 0) 6046 pr_err("Error %d on %s\n", status, __func__); 6047 6048 return status; 6049 } 6050 6051 static int init_drxk(struct drxk_state *state) 6052 { 6053 int status = 0, n = 0; 6054 enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM; 6055 u16 driver_version; 6056 6057 dprintk(1, "\n"); 6058 if ((state->m_drxk_state == DRXK_UNINITIALIZED)) { 6059 drxk_i2c_lock(state); 6060 status = power_up_device(state); 6061 if (status < 0) 6062 goto error; 6063 status = drxx_open(state); 6064 if (status < 0) 6065 goto error; 6066 /* Soft reset of OFDM-, sys- and osc-clockdomain */ 6067 status = write16(state, SIO_CC_SOFT_RST__A, 6068 SIO_CC_SOFT_RST_OFDM__M 6069 | SIO_CC_SOFT_RST_SYS__M 6070 | SIO_CC_SOFT_RST_OSC__M); 6071 if (status < 0) 6072 goto error; 6073 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); 6074 if (status < 0) 6075 goto error; 6076 /* 6077 * TODO is this needed? If yes, how much delay in 6078 * worst case scenario 6079 */ 6080 usleep_range(1000, 2000); 6081 state->m_drxk_a3_patch_code = true; 6082 status = get_device_capabilities(state); 6083 if (status < 0) 6084 goto error; 6085 6086 /* Bridge delay, uses oscilator clock */ 6087 /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */ 6088 /* SDA brdige delay */ 6089 state->m_hi_cfg_bridge_delay = 6090 (u16) ((state->m_osc_clock_freq / 1000) * 6091 HI_I2C_BRIDGE_DELAY) / 1000; 6092 /* Clipping */ 6093 if (state->m_hi_cfg_bridge_delay > 6094 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) { 6095 state->m_hi_cfg_bridge_delay = 6096 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M; 6097 } 6098 /* SCL bridge delay, same as SDA for now */ 6099 state->m_hi_cfg_bridge_delay += 6100 state->m_hi_cfg_bridge_delay << 6101 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B; 6102 6103 status = init_hi(state); 6104 if (status < 0) 6105 goto error; 6106 /* disable various processes */ 6107 #if NOA1ROM 6108 if (!(state->m_DRXK_A1_ROM_CODE) 6109 && !(state->m_DRXK_A2_ROM_CODE)) 6110 #endif 6111 { 6112 status = write16(state, SCU_RAM_GPIO__A, 6113 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); 6114 if (status < 0) 6115 goto error; 6116 } 6117 6118 /* disable MPEG port */ 6119 status = mpegts_disable(state); 6120 if (status < 0) 6121 goto error; 6122 6123 /* Stop AUD and SCU */ 6124 status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP); 6125 if (status < 0) 6126 goto error; 6127 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP); 6128 if (status < 0) 6129 goto error; 6130 6131 /* enable token-ring bus through OFDM block for possible ucode upload */ 6132 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, 6133 SIO_OFDM_SH_OFDM_RING_ENABLE_ON); 6134 if (status < 0) 6135 goto error; 6136 6137 /* include boot loader section */ 6138 status = write16(state, SIO_BL_COMM_EXEC__A, 6139 SIO_BL_COMM_EXEC_ACTIVE); 6140 if (status < 0) 6141 goto error; 6142 status = bl_chain_cmd(state, 0, 6, 100); 6143 if (status < 0) 6144 goto error; 6145 6146 if (state->fw) { 6147 status = download_microcode(state, state->fw->data, 6148 state->fw->size); 6149 if (status < 0) 6150 goto error; 6151 } 6152 6153 /* disable token-ring bus through OFDM block for possible ucode upload */ 6154 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, 6155 SIO_OFDM_SH_OFDM_RING_ENABLE_OFF); 6156 if (status < 0) 6157 goto error; 6158 6159 /* Run SCU for a little while to initialize microcode version numbers */ 6160 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); 6161 if (status < 0) 6162 goto error; 6163 status = drxx_open(state); 6164 if (status < 0) 6165 goto error; 6166 /* added for test */ 6167 msleep(30); 6168 6169 power_mode = DRXK_POWER_DOWN_OFDM; 6170 status = ctrl_power_mode(state, &power_mode); 6171 if (status < 0) 6172 goto error; 6173 6174 /* Stamp driver version number in SCU data RAM in BCD code 6175 Done to enable field application engineers to retrieve drxdriver version 6176 via I2C from SCU RAM. 6177 Not using SCU command interface for SCU register access since no 6178 microcode may be present. 6179 */ 6180 driver_version = 6181 (((DRXK_VERSION_MAJOR / 100) % 10) << 12) + 6182 (((DRXK_VERSION_MAJOR / 10) % 10) << 8) + 6183 ((DRXK_VERSION_MAJOR % 10) << 4) + 6184 (DRXK_VERSION_MINOR % 10); 6185 status = write16(state, SCU_RAM_DRIVER_VER_HI__A, 6186 driver_version); 6187 if (status < 0) 6188 goto error; 6189 driver_version = 6190 (((DRXK_VERSION_PATCH / 1000) % 10) << 12) + 6191 (((DRXK_VERSION_PATCH / 100) % 10) << 8) + 6192 (((DRXK_VERSION_PATCH / 10) % 10) << 4) + 6193 (DRXK_VERSION_PATCH % 10); 6194 status = write16(state, SCU_RAM_DRIVER_VER_LO__A, 6195 driver_version); 6196 if (status < 0) 6197 goto error; 6198 6199 pr_info("DRXK driver version %d.%d.%d\n", 6200 DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR, 6201 DRXK_VERSION_PATCH); 6202 6203 /* 6204 * Dirty fix of default values for ROM/PATCH microcode 6205 * Dirty because this fix makes it impossible to setup 6206 * suitable values before calling DRX_Open. This solution 6207 * requires changes to RF AGC speed to be done via the CTRL 6208 * function after calling DRX_Open 6209 */ 6210 6211 /* m_dvbt_rf_agc_cfg.speed = 3; */ 6212 6213 /* Reset driver debug flags to 0 */ 6214 status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0); 6215 if (status < 0) 6216 goto error; 6217 /* driver 0.9.0 */ 6218 /* Setup FEC OC: 6219 NOTE: No more full FEC resets allowed afterwards!! */ 6220 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP); 6221 if (status < 0) 6222 goto error; 6223 /* MPEGTS functions are still the same */ 6224 status = mpegts_dto_init(state); 6225 if (status < 0) 6226 goto error; 6227 status = mpegts_stop(state); 6228 if (status < 0) 6229 goto error; 6230 status = mpegts_configure_polarity(state); 6231 if (status < 0) 6232 goto error; 6233 status = mpegts_configure_pins(state, state->m_enable_mpeg_output); 6234 if (status < 0) 6235 goto error; 6236 /* added: configure GPIO */ 6237 status = write_gpio(state); 6238 if (status < 0) 6239 goto error; 6240 6241 state->m_drxk_state = DRXK_STOPPED; 6242 6243 if (state->m_b_power_down) { 6244 status = power_down_device(state); 6245 if (status < 0) 6246 goto error; 6247 state->m_drxk_state = DRXK_POWERED_DOWN; 6248 } else 6249 state->m_drxk_state = DRXK_STOPPED; 6250 6251 /* Initialize the supported delivery systems */ 6252 n = 0; 6253 if (state->m_has_dvbc) { 6254 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A; 6255 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C; 6256 strlcat(state->frontend.ops.info.name, " DVB-C", 6257 sizeof(state->frontend.ops.info.name)); 6258 } 6259 if (state->m_has_dvbt) { 6260 state->frontend.ops.delsys[n++] = SYS_DVBT; 6261 strlcat(state->frontend.ops.info.name, " DVB-T", 6262 sizeof(state->frontend.ops.info.name)); 6263 } 6264 drxk_i2c_unlock(state); 6265 } 6266 error: 6267 if (status < 0) { 6268 state->m_drxk_state = DRXK_NO_DEV; 6269 drxk_i2c_unlock(state); 6270 pr_err("Error %d on %s\n", status, __func__); 6271 } 6272 6273 return status; 6274 } 6275 6276 static void load_firmware_cb(const struct firmware *fw, 6277 void *context) 6278 { 6279 struct drxk_state *state = context; 6280 6281 dprintk(1, ": %s\n", fw ? "firmware loaded" : "firmware not loaded"); 6282 if (!fw) { 6283 pr_err("Could not load firmware file %s.\n", 6284 state->microcode_name); 6285 pr_info("Copy %s to your hotplug directory!\n", 6286 state->microcode_name); 6287 state->microcode_name = NULL; 6288 6289 /* 6290 * As firmware is now load asynchronous, it is not possible 6291 * anymore to fail at frontend attach. We might silently 6292 * return here, and hope that the driver won't crash. 6293 * We might also change all DVB callbacks to return -ENODEV 6294 * if the device is not initialized. 6295 * As the DRX-K devices have their own internal firmware, 6296 * let's just hope that it will match a firmware revision 6297 * compatible with this driver and proceed. 6298 */ 6299 } 6300 state->fw = fw; 6301 6302 init_drxk(state); 6303 } 6304 6305 static void drxk_release(struct dvb_frontend *fe) 6306 { 6307 struct drxk_state *state = fe->demodulator_priv; 6308 6309 dprintk(1, "\n"); 6310 release_firmware(state->fw); 6311 6312 kfree(state); 6313 } 6314 6315 static int drxk_sleep(struct dvb_frontend *fe) 6316 { 6317 struct drxk_state *state = fe->demodulator_priv; 6318 6319 dprintk(1, "\n"); 6320 6321 if (state->m_drxk_state == DRXK_NO_DEV) 6322 return -ENODEV; 6323 if (state->m_drxk_state == DRXK_UNINITIALIZED) 6324 return 0; 6325 6326 shut_down(state); 6327 return 0; 6328 } 6329 6330 static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable) 6331 { 6332 struct drxk_state *state = fe->demodulator_priv; 6333 6334 dprintk(1, ": %s\n", enable ? "enable" : "disable"); 6335 6336 if (state->m_drxk_state == DRXK_NO_DEV) 6337 return -ENODEV; 6338 6339 return ConfigureI2CBridge(state, enable ? true : false); 6340 } 6341 6342 static int drxk_set_parameters(struct dvb_frontend *fe) 6343 { 6344 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 6345 u32 delsys = p->delivery_system, old_delsys; 6346 struct drxk_state *state = fe->demodulator_priv; 6347 u32 IF; 6348 6349 dprintk(1, "\n"); 6350 6351 if (state->m_drxk_state == DRXK_NO_DEV) 6352 return -ENODEV; 6353 6354 if (state->m_drxk_state == DRXK_UNINITIALIZED) 6355 return -EAGAIN; 6356 6357 if (!fe->ops.tuner_ops.get_if_frequency) { 6358 pr_err("Error: get_if_frequency() not defined at tuner. Can't work without it!\n"); 6359 return -EINVAL; 6360 } 6361 6362 if (fe->ops.i2c_gate_ctrl) 6363 fe->ops.i2c_gate_ctrl(fe, 1); 6364 if (fe->ops.tuner_ops.set_params) 6365 fe->ops.tuner_ops.set_params(fe); 6366 if (fe->ops.i2c_gate_ctrl) 6367 fe->ops.i2c_gate_ctrl(fe, 0); 6368 6369 old_delsys = state->props.delivery_system; 6370 state->props = *p; 6371 6372 if (old_delsys != delsys) { 6373 shut_down(state); 6374 switch (delsys) { 6375 case SYS_DVBC_ANNEX_A: 6376 case SYS_DVBC_ANNEX_C: 6377 if (!state->m_has_dvbc) 6378 return -EINVAL; 6379 state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ? 6380 true : false; 6381 if (state->m_itut_annex_c) 6382 setoperation_mode(state, OM_QAM_ITU_C); 6383 else 6384 setoperation_mode(state, OM_QAM_ITU_A); 6385 break; 6386 case SYS_DVBT: 6387 if (!state->m_has_dvbt) 6388 return -EINVAL; 6389 setoperation_mode(state, OM_DVBT); 6390 break; 6391 default: 6392 return -EINVAL; 6393 } 6394 } 6395 6396 fe->ops.tuner_ops.get_if_frequency(fe, &IF); 6397 start(state, 0, IF); 6398 6399 /* After set_frontend, stats aren't available */ 6400 p->strength.stat[0].scale = FE_SCALE_RELATIVE; 6401 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6402 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6403 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6404 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6405 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6406 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6407 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6408 6409 /* printk(KERN_DEBUG "drxk: %s IF=%d done\n", __func__, IF); */ 6410 6411 return 0; 6412 } 6413 6414 static int get_strength(struct drxk_state *state, u64 *strength) 6415 { 6416 int status; 6417 struct s_cfg_agc rf_agc, if_agc; 6418 u32 total_gain = 0; 6419 u32 atten = 0; 6420 u32 agc_range = 0; 6421 u16 scu_lvl = 0; 6422 u16 scu_coc = 0; 6423 /* FIXME: those are part of the tuner presets */ 6424 u16 tuner_rf_gain = 50; /* Default value on az6007 driver */ 6425 u16 tuner_if_gain = 40; /* Default value on az6007 driver */ 6426 6427 *strength = 0; 6428 6429 if (is_dvbt(state)) { 6430 rf_agc = state->m_dvbt_rf_agc_cfg; 6431 if_agc = state->m_dvbt_if_agc_cfg; 6432 } else if (is_qam(state)) { 6433 rf_agc = state->m_qam_rf_agc_cfg; 6434 if_agc = state->m_qam_if_agc_cfg; 6435 } else { 6436 rf_agc = state->m_atv_rf_agc_cfg; 6437 if_agc = state->m_atv_if_agc_cfg; 6438 } 6439 6440 if (rf_agc.ctrl_mode == DRXK_AGC_CTRL_AUTO) { 6441 /* SCU output_level */ 6442 status = read16(state, SCU_RAM_AGC_RF_IACCU_HI__A, &scu_lvl); 6443 if (status < 0) 6444 return status; 6445 6446 /* SCU c.o.c. */ 6447 status = read16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, &scu_coc); 6448 if (status < 0) 6449 return status; 6450 6451 if (((u32) scu_lvl + (u32) scu_coc) < 0xffff) 6452 rf_agc.output_level = scu_lvl + scu_coc; 6453 else 6454 rf_agc.output_level = 0xffff; 6455 6456 /* Take RF gain into account */ 6457 total_gain += tuner_rf_gain; 6458 6459 /* clip output value */ 6460 if (rf_agc.output_level < rf_agc.min_output_level) 6461 rf_agc.output_level = rf_agc.min_output_level; 6462 if (rf_agc.output_level > rf_agc.max_output_level) 6463 rf_agc.output_level = rf_agc.max_output_level; 6464 6465 agc_range = (u32) (rf_agc.max_output_level - rf_agc.min_output_level); 6466 if (agc_range > 0) { 6467 atten += 100UL * 6468 ((u32)(tuner_rf_gain)) * 6469 ((u32)(rf_agc.output_level - rf_agc.min_output_level)) 6470 / agc_range; 6471 } 6472 } 6473 6474 if (if_agc.ctrl_mode == DRXK_AGC_CTRL_AUTO) { 6475 status = read16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 6476 &if_agc.output_level); 6477 if (status < 0) 6478 return status; 6479 6480 status = read16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, 6481 &if_agc.top); 6482 if (status < 0) 6483 return status; 6484 6485 /* Take IF gain into account */ 6486 total_gain += (u32) tuner_if_gain; 6487 6488 /* clip output value */ 6489 if (if_agc.output_level < if_agc.min_output_level) 6490 if_agc.output_level = if_agc.min_output_level; 6491 if (if_agc.output_level > if_agc.max_output_level) 6492 if_agc.output_level = if_agc.max_output_level; 6493 6494 agc_range = (u32)(if_agc.max_output_level - if_agc.min_output_level); 6495 if (agc_range > 0) { 6496 atten += 100UL * 6497 ((u32)(tuner_if_gain)) * 6498 ((u32)(if_agc.output_level - if_agc.min_output_level)) 6499 / agc_range; 6500 } 6501 } 6502 6503 /* 6504 * Convert to 0..65535 scale. 6505 * If it can't be measured (AGC is disabled), just show 100%. 6506 */ 6507 if (total_gain > 0) 6508 *strength = (65535UL * atten / total_gain / 100); 6509 else 6510 *strength = 65535; 6511 6512 return 0; 6513 } 6514 6515 static int drxk_get_stats(struct dvb_frontend *fe) 6516 { 6517 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 6518 struct drxk_state *state = fe->demodulator_priv; 6519 int status; 6520 u32 stat; 6521 u16 reg16; 6522 u32 post_bit_count; 6523 u32 post_bit_err_count; 6524 u32 post_bit_error_scale; 6525 u32 pre_bit_err_count; 6526 u32 pre_bit_count; 6527 u32 pkt_count; 6528 u32 pkt_error_count; 6529 s32 cnr; 6530 6531 if (state->m_drxk_state == DRXK_NO_DEV) 6532 return -ENODEV; 6533 if (state->m_drxk_state == DRXK_UNINITIALIZED) 6534 return -EAGAIN; 6535 6536 /* get status */ 6537 state->fe_status = 0; 6538 get_lock_status(state, &stat); 6539 if (stat == MPEG_LOCK) 6540 state->fe_status |= 0x1f; 6541 if (stat == FEC_LOCK) 6542 state->fe_status |= 0x0f; 6543 if (stat == DEMOD_LOCK) 6544 state->fe_status |= 0x07; 6545 6546 /* 6547 * Estimate signal strength from AGC 6548 */ 6549 get_strength(state, &c->strength.stat[0].uvalue); 6550 c->strength.stat[0].scale = FE_SCALE_RELATIVE; 6551 6552 6553 if (stat >= DEMOD_LOCK) { 6554 get_signal_to_noise(state, &cnr); 6555 c->cnr.stat[0].svalue = cnr * 100; 6556 c->cnr.stat[0].scale = FE_SCALE_DECIBEL; 6557 } else { 6558 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6559 } 6560 6561 if (stat < FEC_LOCK) { 6562 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6563 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6564 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6565 c->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6566 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6567 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6568 return 0; 6569 } 6570 6571 /* Get post BER */ 6572 6573 /* BER measurement is valid if at least FEC lock is achieved */ 6574 6575 /* 6576 * OFDM_EC_VD_REQ_SMB_CNT__A and/or OFDM_EC_VD_REQ_BIT_CNT can be 6577 * written to set nr of symbols or bits over which to measure 6578 * EC_VD_REG_ERR_BIT_CNT__A . See CtrlSetCfg(). 6579 */ 6580 6581 /* Read registers for post/preViterbi BER calculation */ 6582 status = read16(state, OFDM_EC_VD_ERR_BIT_CNT__A, ®16); 6583 if (status < 0) 6584 goto error; 6585 pre_bit_err_count = reg16; 6586 6587 status = read16(state, OFDM_EC_VD_IN_BIT_CNT__A , ®16); 6588 if (status < 0) 6589 goto error; 6590 pre_bit_count = reg16; 6591 6592 /* Number of bit-errors */ 6593 status = read16(state, FEC_RS_NR_BIT_ERRORS__A, ®16); 6594 if (status < 0) 6595 goto error; 6596 post_bit_err_count = reg16; 6597 6598 status = read16(state, FEC_RS_MEASUREMENT_PRESCALE__A, ®16); 6599 if (status < 0) 6600 goto error; 6601 post_bit_error_scale = reg16; 6602 6603 status = read16(state, FEC_RS_MEASUREMENT_PERIOD__A, ®16); 6604 if (status < 0) 6605 goto error; 6606 pkt_count = reg16; 6607 6608 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, ®16); 6609 if (status < 0) 6610 goto error; 6611 pkt_error_count = reg16; 6612 write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0); 6613 6614 post_bit_err_count *= post_bit_error_scale; 6615 6616 post_bit_count = pkt_count * 204 * 8; 6617 6618 /* Store the results */ 6619 c->block_error.stat[0].scale = FE_SCALE_COUNTER; 6620 c->block_error.stat[0].uvalue += pkt_error_count; 6621 c->block_count.stat[0].scale = FE_SCALE_COUNTER; 6622 c->block_count.stat[0].uvalue += pkt_count; 6623 6624 c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; 6625 c->pre_bit_error.stat[0].uvalue += pre_bit_err_count; 6626 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; 6627 c->pre_bit_count.stat[0].uvalue += pre_bit_count; 6628 6629 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; 6630 c->post_bit_error.stat[0].uvalue += post_bit_err_count; 6631 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; 6632 c->post_bit_count.stat[0].uvalue += post_bit_count; 6633 6634 error: 6635 return status; 6636 } 6637 6638 6639 static int drxk_read_status(struct dvb_frontend *fe, enum fe_status *status) 6640 { 6641 struct drxk_state *state = fe->demodulator_priv; 6642 int rc; 6643 6644 dprintk(1, "\n"); 6645 6646 rc = drxk_get_stats(fe); 6647 if (rc < 0) 6648 return rc; 6649 6650 *status = state->fe_status; 6651 6652 return 0; 6653 } 6654 6655 static int drxk_read_signal_strength(struct dvb_frontend *fe, 6656 u16 *strength) 6657 { 6658 struct drxk_state *state = fe->demodulator_priv; 6659 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 6660 6661 dprintk(1, "\n"); 6662 6663 if (state->m_drxk_state == DRXK_NO_DEV) 6664 return -ENODEV; 6665 if (state->m_drxk_state == DRXK_UNINITIALIZED) 6666 return -EAGAIN; 6667 6668 *strength = c->strength.stat[0].uvalue; 6669 return 0; 6670 } 6671 6672 static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr) 6673 { 6674 struct drxk_state *state = fe->demodulator_priv; 6675 s32 snr2; 6676 6677 dprintk(1, "\n"); 6678 6679 if (state->m_drxk_state == DRXK_NO_DEV) 6680 return -ENODEV; 6681 if (state->m_drxk_state == DRXK_UNINITIALIZED) 6682 return -EAGAIN; 6683 6684 get_signal_to_noise(state, &snr2); 6685 6686 /* No negative SNR, clip to zero */ 6687 if (snr2 < 0) 6688 snr2 = 0; 6689 *snr = snr2 & 0xffff; 6690 return 0; 6691 } 6692 6693 static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 6694 { 6695 struct drxk_state *state = fe->demodulator_priv; 6696 u16 err; 6697 6698 dprintk(1, "\n"); 6699 6700 if (state->m_drxk_state == DRXK_NO_DEV) 6701 return -ENODEV; 6702 if (state->m_drxk_state == DRXK_UNINITIALIZED) 6703 return -EAGAIN; 6704 6705 dvbtqam_get_acc_pkt_err(state, &err); 6706 *ucblocks = (u32) err; 6707 return 0; 6708 } 6709 6710 static int drxk_get_tune_settings(struct dvb_frontend *fe, 6711 struct dvb_frontend_tune_settings *sets) 6712 { 6713 struct drxk_state *state = fe->demodulator_priv; 6714 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 6715 6716 dprintk(1, "\n"); 6717 6718 if (state->m_drxk_state == DRXK_NO_DEV) 6719 return -ENODEV; 6720 if (state->m_drxk_state == DRXK_UNINITIALIZED) 6721 return -EAGAIN; 6722 6723 switch (p->delivery_system) { 6724 case SYS_DVBC_ANNEX_A: 6725 case SYS_DVBC_ANNEX_C: 6726 case SYS_DVBT: 6727 sets->min_delay_ms = 3000; 6728 sets->max_drift = 0; 6729 sets->step_size = 0; 6730 return 0; 6731 default: 6732 return -EINVAL; 6733 } 6734 } 6735 6736 static const struct dvb_frontend_ops drxk_ops = { 6737 /* .delsys will be filled dynamically */ 6738 .info = { 6739 .name = "DRXK", 6740 .frequency_min = 47000000, 6741 .frequency_max = 865000000, 6742 /* For DVB-C */ 6743 .symbol_rate_min = 870000, 6744 .symbol_rate_max = 11700000, 6745 /* For DVB-T */ 6746 .frequency_stepsize = 166667, 6747 6748 .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | 6749 FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO | 6750 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 6751 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_MUTE_TS | 6752 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER | 6753 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO 6754 }, 6755 6756 .release = drxk_release, 6757 .sleep = drxk_sleep, 6758 .i2c_gate_ctrl = drxk_gate_ctrl, 6759 6760 .set_frontend = drxk_set_parameters, 6761 .get_tune_settings = drxk_get_tune_settings, 6762 6763 .read_status = drxk_read_status, 6764 .read_signal_strength = drxk_read_signal_strength, 6765 .read_snr = drxk_read_snr, 6766 .read_ucblocks = drxk_read_ucblocks, 6767 }; 6768 6769 struct dvb_frontend *drxk_attach(const struct drxk_config *config, 6770 struct i2c_adapter *i2c) 6771 { 6772 struct dtv_frontend_properties *p; 6773 struct drxk_state *state = NULL; 6774 u8 adr = config->adr; 6775 int status; 6776 6777 dprintk(1, "\n"); 6778 state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL); 6779 if (!state) 6780 return NULL; 6781 6782 state->i2c = i2c; 6783 state->demod_address = adr; 6784 state->single_master = config->single_master; 6785 state->microcode_name = config->microcode_name; 6786 state->qam_demod_parameter_count = config->qam_demod_parameter_count; 6787 state->no_i2c_bridge = config->no_i2c_bridge; 6788 state->antenna_gpio = config->antenna_gpio; 6789 state->antenna_dvbt = config->antenna_dvbt; 6790 state->m_chunk_size = config->chunk_size; 6791 state->enable_merr_cfg = config->enable_merr_cfg; 6792 6793 if (config->dynamic_clk) { 6794 state->m_dvbt_static_clk = false; 6795 state->m_dvbc_static_clk = false; 6796 } else { 6797 state->m_dvbt_static_clk = true; 6798 state->m_dvbc_static_clk = true; 6799 } 6800 6801 6802 if (config->mpeg_out_clk_strength) 6803 state->m_ts_clockk_strength = config->mpeg_out_clk_strength & 0x07; 6804 else 6805 state->m_ts_clockk_strength = 0x06; 6806 6807 if (config->parallel_ts) 6808 state->m_enable_parallel = true; 6809 else 6810 state->m_enable_parallel = false; 6811 6812 /* NOTE: as more UIO bits will be used, add them to the mask */ 6813 state->uio_mask = config->antenna_gpio; 6814 6815 /* Default gpio to DVB-C */ 6816 if (!state->antenna_dvbt && state->antenna_gpio) 6817 state->m_gpio |= state->antenna_gpio; 6818 else 6819 state->m_gpio &= ~state->antenna_gpio; 6820 6821 mutex_init(&state->mutex); 6822 6823 memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops)); 6824 state->frontend.demodulator_priv = state; 6825 6826 init_state(state); 6827 6828 /* Load firmware and initialize DRX-K */ 6829 if (state->microcode_name) { 6830 const struct firmware *fw = NULL; 6831 6832 status = request_firmware(&fw, state->microcode_name, 6833 state->i2c->dev.parent); 6834 if (status < 0) 6835 fw = NULL; 6836 load_firmware_cb(fw, state); 6837 } else if (init_drxk(state) < 0) 6838 goto error; 6839 6840 6841 /* Initialize stats */ 6842 p = &state->frontend.dtv_property_cache; 6843 p->strength.len = 1; 6844 p->cnr.len = 1; 6845 p->block_error.len = 1; 6846 p->block_count.len = 1; 6847 p->pre_bit_error.len = 1; 6848 p->pre_bit_count.len = 1; 6849 p->post_bit_error.len = 1; 6850 p->post_bit_count.len = 1; 6851 6852 p->strength.stat[0].scale = FE_SCALE_RELATIVE; 6853 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6854 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6855 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6856 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6857 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6858 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6859 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6860 6861 pr_info("frontend initialized.\n"); 6862 return &state->frontend; 6863 6864 error: 6865 pr_err("not found\n"); 6866 kfree(state); 6867 return NULL; 6868 } 6869 EXPORT_SYMBOL(drxk_attach); 6870 6871 MODULE_DESCRIPTION("DRX-K driver"); 6872 MODULE_AUTHOR("Ralph Metzler"); 6873 MODULE_LICENSE("GPL"); 6874